STD4NS25T4

STD4NS25 N-CHANNEL 250V - 0.9Ω - 4A DPAK/IPAK MESH OVERLAY™ MOSFET ■ ■ ■ ■ TYPE VDSS RDS(on) ID STD4NS25 250 V < 1.1 Ω 4A TYPICAL RDS(on) = 0.9 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED ADD SUFFIX “T4” FOR ORDERING IN TAPE & REEL DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performance. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, makes it suitable in coverters for lighting applications. (s) 3 3 ct 1 DPAK TO-252 u d o r P e 2 1 IPAK TO-251 t e l o bs INTERNAL SCHEMATIC DIAGRAM O ) s ( t c APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SWITH MODE POWER SUPPLIES (SMPS) ■ DC-DC CONVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT u d o r P e t e l o ABSOLUTE MAXIMUM RATINGS s b O Symbol VDS VDGR VGS Value Unit Drain-source Voltage (VGS = 0) Parameter 250 V Drain-gate Voltage (RGS = 20 kΩ) 250 V Gate- source Voltage ± 20 V ID Drain Current (continuos) at TC = 25°C 4 A ID Drain Current (continuos) at TC = 100°C 2.5 A Drain Current (pulsed) 16 A Total Dissipation at TC = 25°C 50 W Derating Factor 0.4 W/°C 5 V/ns –65 to 150 °C 150 °C IDM (●) PTOT dv/dt (1) Tstg Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature (•)Pulse width limited by safe operating area February 2001 (1) ISD≤ 4A, di/dt≤300 A/µs, VDD≤ V (BR)DSS, Tj≤TjMAX 1/9 STD4NS25 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 2.5 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W Rthc-sink Thermal Resistance Case-sink Typ 1.5 °C/W Maximum Lead Temperature For Soldering Purpose 275 °C Tl AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value Unit 4 A 120 mJ ) s ( ct ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating Gate-body Leakage Current (VDS = 0) VGS = ±20V ) (s Parameter VGS(th) Gate Threshold Voltage RDS(on) Static Drain-source On Resistance ID(on) On State Drain Current s b O Test Conditions ct du e t e ol e t e ol Typ. Pr 250 VDS = Max Rating, TC = 125 °C ON (1) Symbol u d o Min. o r P VDS = VGS, ID = 250µA Unit V 1 µA 10 µA ±100 nA Min. Typ. Max. Unit 2 3 4 V 0.9 1.1 Ω VGS = 10V, ID = 2 A VDS > ID(on) x RDS(on)max, VGS = 10V Max. 4 A DYNAMIC bs Symbol O 2/9 gfs (1) Parameter Forward Transconductance Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 2A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 1 3.5 Max. Unit S 355 pF 64 pF 29.5 pF STD4NS25 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) Parameter Test Conditions Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Typ. VDD = 125 V, ID = 2 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) Turn-on Delay Time tr Min. VDD = 200V, ID = 4 A, VGS = 10V Max. 12 ns 18 ns 19 27 Parameter Test Conditions td(Voff) tf Turn-off- Delay Time Fall Time VDD = 125V, ID = 2 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 3) tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time Vclamp = 200V, ID = 4 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) nC 7.5 nC bs ISD Parameter Test Conditions Source-drain Current ISDM (2) Source-drain Current (pulsed) VSD (1) Forward On Voltage ) s ( ct Reverse Recovery Time Qrr Reverse Recovery Charge IRRM Reverse Recovery Current du o r P Max. Pr Min. O ) 13 10 21.5 Typ. ISD = 4 A, VGS = 0 ISD = 4 A, di/dt = 100A/µs VDD = 30V, Tj = 150°C (see test circuit, Figure 5) Unit ns ns u d o s ( t c trr Typ. 70 10.5 e t e ol SOURCE DRAIN DIODE Symbol Min. nC 3.2 SWITCHING OFF Symbol Unit ns ns ns Max. Unit 4 A 16 A 1.5 V 124 ns 0.5 µC 7.2 A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. e t e l Safe Operating Area Thermal Impedance o s b O 3/9 STD4NS25 Output Characteristics Transfer Characteristics ) s ( ct u d o r P e Transconductance Static Drain-source On Resistance t e l o ) (s s b O t c u d o r P e t e l o Gate Charge vs Gate-source Voltage s b O 4/9 Capacitance Variations STD4NS25 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature ) s ( ct u d o r P e Source-drain Diode Forward Characteristics t e l o ) (s s b O t c u d o r P e t e l o s b O 5/9 STD4NS25 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform ) s ( ct u d o r P e Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit t e l o ) (s t c u d o r P e t e l o Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times s b O 6/9 s b O STD4NS25 TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.20 2.40 0.087 0.094 A1 0.90 1.10 0.035 0.043 ) s ( ct A2 0.03 0.23 0.001 B 0.64 0.90 0.025 B2 5.20 5.40 0.204 C 0.45 0.60 0.018 C2 0.48 0.60 0.019 D 6.00 6.20 0.236 E 6.40 6.60 0.252 G 4.40 4.60 H 9.35 10.10 L2 0.8 L4 0.60 V2 0o )- 0.009 0.035 0.213 P e s b O t e l o 0.173 ro du 0.368 0.024 0.024 0.244 0.260 0.181 0.398 0.031 1.00 0.024 0.039 8o 0o 0o s ( t c u d o r P e t e l o s b O P032P_B 7/9 STD4NS25 TO-251 (IPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. 2.4 0.086 MAX. 0.094 0.043 A 2.2 A1 0.9 1.1 0.035 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 ) s ( ct 0.85 B5 0.033 u d o 0.3 0.012 B6 0.95 0.037 C 0.45 0.6 0.017 C2 0.48 0.6 0.019 D 6 6.2 0.236 E 6.4 6.6 G 4.4 4.6 H 15.9 16.3 L 9 9.4 L1 0.8 ) s ( ct L2 0.8 t e l o 0.626 0.641 0.354 0.370 bs 0.260 0.173 0.181 0.031 0.047 1 du 0.023 0.244 0.252 -O 1.2 r P e 0.023 0.031 0.039 H A1 C2 L D = 1 = 2 G = = = E B2 = 3 B B3 L2 B5 s b O B6 e t e ol A3 A C o r P L1 0068771-E 8/9 STD4NS25 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9