STD40P8F6AG

STD40P8F6AG Automotive-grade P-channel -80 V, 18.5 mΩ typ., -40 A STripFET™ F6 Power MOSFET in a DPAK package Datasheet - production data Features  Figure 1: Internal schematic diagram D(2, TAB)     Order code VDSS RDS(on) max. ID STD40P8F6AG -80 V 28 mΩ -40 A Designed for automotive applications and AEC-Q101 qualified Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Applications  Switching applications Description This device is a P-channel Power MOSFET developed using the STripFET™ F6 technology, with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. G(1) S(3) AM11258v1 Table 1: Device summary Order code Marking Package Packing STD40P8F6AG 40P8F6 DPAK Tape and reel July 2016 DocID029583 Rev 1 This is information on a product in full production. 1/16 www.st.com Contents STD40P8F6AG Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/16 4.1 DPAK type A2 package information ................................................ 10 4.2 DPAK packing information .............................................................. 13 Revision history ............................................................................ 15 DocID029583 Rev 1 STD40P8F6AG 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage -80 V VGS Gate-source voltage ±20 V ID Drain current (continuous) at TC = 25 °C -40 A ID Drain current (continuous) at TC = 100 °C -28 A IDM(1) Drain current (pulsed) -160 A PTOT Total dissipation at TC = 25 °C 100 W EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = -40 A, VDD = -60 V) 240 mJ -55 to 175 °C Tstg Storage temperature range Tj Junction temperature range Notes: (1)Pulse width limited by safe operating area. Table 3: Thermal data Symbol Rthj-case Rthj-pcb Parameter Thermal resistance junction-case max Thermal resistance junction-pcb max(1) Value Unit 1.5 °C/W 50 °C/W Notes: (1)When mounted on 1 inch2 FR-4, 2 Oz copper board. DocID029583 Rev 1 3/16 Electrical characteristics 2 STD40P8F6AG Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: Static Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS VGS = 0 V, ID = -1 mA Min. Typ. Max. -80 Unit V VGS = 0 V, VDS = -60 V -1 µA VGS = 0 V, VDS = -60 V, TC = 125 °C(1) -10 µA Gate-body leakage current VDS = 0 V, VGS = ±20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = -250 µA -4 V RDS(on) Static drain-source on-resistance VGS = -10 V, ID = -20 A 18.5 28 mΩ Min. Typ. Max. Unit - 4112 - pF - 366 - pF - 188 - pF - 73 - nC - 17.1 - nC - 18 - nC -2 Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol 4/16 Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = -25 V, f = 1 MHz, VGS = 0 V VDD = -40 V, ID = -40 A, VGS = -10 V (see Figure 14: "Gate charge test circuit") DocID029583 Rev 1 STD40P8F6AG Electrical characteristics Table 6: Switching times Symbol td(on) Parameter Turn-on delay time tr Rise time td(off) Turn-off-delay time tf Fall time Test conditions VDD = -40 V, ID = -20 A, RG = 4.7 Ω, VGS = -10 V (see Figure 13: "Switching times test circuit for resistive load") Min. Typ. Max. Unit - 17.5 - ns - 28.5 - ns - 68.5 - ns - 34.5 - ns Min. Typ. Max. Unit Table 7: Source drain diode Symbol Parameter ISD Source-drain current - -40 A ISDM(1) Source-drain current (pulsed) - -160 A VSD (2) Forward on voltage - -1.2 V trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Test conditions VGS = 0 V, ISD = -40 A ISD = -40 A, di/dt = 100 A/µs, VDD = -64 V, (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 35 ns - 44 nC - -2.5 A Notes: (1)Pulse width limited by safe operating area. (2)Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID029583 Rev 1 5/16 Electrical characteristics 2.1 STD40P8F6AG Electrical characteristics (curves) For the P-channel Power MOSFET, current and voltage polarities are reversed. 6/16 Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID029583 Rev 1 STD40P8F6AG Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized V(BR)DSS vs temperature Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics DocID029583 Rev 1 7/16 Test circuits 3 STD40P8F6AG Test circuits Figure 13: Switching times test circuit for resistive load Figure 14: Gate charge test circuit Figure 15: Test circuit for inductive load switching and diode recovery times 8/16 DocID029583 Rev 1 STD40P8F6AG 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID029583 Rev 1 9/16 Package information 4.1 STD40P8F6AG DPAK type A2 package information Figure 16: DPAK (TO-252) type A2 package outline 0068772_type-A2_rev21 10/16 DocID029583 Rev 1 STD40P8F6AG Package information Table 8: DPAK (TO-252) type A2 mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 5.10 5.25 6.60 1.00 0.20 0° DocID029583 Rev 1 8° 11/16 Package information STD40P8F6AG Figure 17: DPAK (TO-252) recommended footprint (dimensions are in mm) 12/16 DocID029583 Rev 1 STD40P8F6AG 4.2 Package information DPAK packing information Figure 18: DPAK (TO-252) tape outline DocID029583 Rev 1 13/16 Package information STD40P8F6AG Figure 19: DPAK (TO-252) reel outline Table 9: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 B1 14/16 D 1.5 D1 1.5 E 1.65 F 1.6 Min. Max. 330 13.2 D 20.2 G 16.4 1.85 N 50 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID029583 Rev 1 18.4 22.4 STD40P8F6AG 5 Revision history Revision history Table 10: Document revision history Date Revision 19-Jul-2016 1 DocID029583 Rev 1 Changes First release. 15/16 STD40P8F6AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 16/16 DocID029583 Rev 1