STV7801

STV7801S PLASMA DATA POWER SWITCH PRELIMINARY DATA FEATURES s s s s s s s s s s . High Voltage - Low Power Pulse Generator 100V Absolute Maximum Supply High Load Drive Capability (25nF) 5V Compatible Input Logic Very Low Stand-by Current Power Recovery High Current (±7A) Totem Pole High Output Current (±5A) Built-in Timing Control & Thermal Protection BCD Technology Packaging: Multiwatt 15, Power SO20 MULTIWATT 15 (Plastic Package) ORDER CODE: STV7801S DESCRIPTION STV7801 is a monolithic integrated circuit implemented in STMicroelectronics BCD proprietary technology designed as a switched power supply generator for data drivers in a Plasma Display Panel (P.D.P.) application. The high load drive capability of the STV7801 reduces the number of devices necessary to drive a complete PDP (4 to 6 devices for a 42” VGA 16/9 PDP monitor). The STV7801 high current drive capability provides a high power recovery efficiency coefficient superior to 85% on constant capacitive load. To limit the number of external components, the device integrates level shifters driven with 5V CMOS compatible levels. To increase the reliability of the system, the device integrates several protections such as output over-voltage, over-temperature, power-ON protection. Customer samples will be available by september 2000 20 leads POWERSO20 (Plastic Package) ORDER CODE: STV7801SP Revision 3.3 June 2000 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/18 1 STV7801S 1 - PIN CONNECTION Multiwatt 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Vpp Vpp CBoot Out Vssp Vdd DM-LH Vsslog PR DM-HL PR-FPS LH-Tr L-Clmp H-Clmp HL-Tr PowerSO20 Vsssub HL-Tr H-Clmp L-Clmp LH-Tr PR-FPS PR-FPS DM-HL PR Vsssub 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Vsssub Vpp Vpp CBoot Out Vssp Vssp Vdd DM-LH Vsslog 2/18 2 STV7801S 2 - BLOC DIAGRAM MULTIWATT 15 CBoot Vpp 13 Voltage Control Vdd 10 Protection Control 15 14 Bootstrap control H-Clmp 2 H-Clmp Transistor 7 PR LH-Tr 4 Timing Control LH Transistor HL Transistor 12 Out HL-Tr 1 L-Clmp Transistor L-Clmp 3 Vsslog 8 STV7801S 5 6 9 11 Vssp PR-FPS DM-HL DM-LH 3/18 STV7801S 3 - PIN DESCRIPTION Multiwatt 15 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Name HL-Tr H-Clmp L-Clmp LH-Tr PR-FPS DM-HL PR Vsslog DM-LH Vdd Vssp Out CBoot Vpp Vpp Function Input Input Input Input Input Input Output Ground Output Supply Ground Output Input Supply Supply Description Power Recovery High Level/Low Level Transition Main Switch High-Side Clamp Input Main Switch Low-Side Clamp Input Power Recovery Low Level/High Level Transition Power Recovery Floating Supply Current Recirculation- Input Pin - High/Low Transition Power Recirculation Output Stage Logic Ground/Substrate Ground Current Recirculation- Output Pin - Low/High Transition Logic Supply Power Ground Main Switch Output Bootstrap Capacitor Input Pin High Voltage Supply High Voltage Supply PowerSO20 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Name Vssub HL-Tr H-Clmp L-Clmp LH-Tr PR-FPS PR-FPS DM-HL Function Ground Input Input Input Input Input Input Input Output Ground Ground Output Supply Ground Ground Output Input Substrate Ground Description Power Recovery High Level/Low Level Transition Main Switch High-Side Clamp Input Main Switch Low-Side Clamp Input Power Recovery Low Level/High Level Transition Power Recovery Floating Supply Power Recovery Floating Supply Current Recirculation- Input Pin - High/Low Transition Power Recirculation Output Stage Substrate Ground Logic Ground/Substrate Ground Current Recirculation- Output Pin - Low/High Transition Logic Supply Power Ground Power Ground Main Switch Output Bootstrap Capacitor Input Pin PR Vssub Vsslog DM-LH Vdd Vssp Vssp Out CBoot 4/18 STV7801S Pin Number 18 19 20 Pin Name Vpp Vpp Vssub Function Supply Supply Ground High Voltage Supply High Voltage Supply Substrate Ground Description 4 - CIRCUIT DESCRIPTION STV7801 is a monolithic integrated circuit implemented in ST Microelectronics BCD proprietary technology designed as a switched power supply generator for data drivers in a Plasma Display Panel (P.D.P.) application. The high load drive capability of STV7801 reduces the number of devices necessary to drive a complete PDP (4 to 6 devices for a 42" VGA 16/9 PDP monitor). STV7801 high current drive capability provides a high power recovery efficiency coefficient superior to 85% on constant capacitive load. The structure of the output stage is implemented with 2 DMOS transistors to minimise the die size. External components like bootstrap capacitor can also be implemented to increase the performances of the circuit. STV7801 integrates level shifters driven with 5V CMOS compatible levels. This feature reduces the number of discrete components such as voltage translators. STV7801 integrates several protections like output over-voltage, timing control and over-temperature to increase the reliability of the system. Over-voltage protection consists in clamping diodes connected between Vpp, Vssp and critical nodes of the devices. Timing control consists in a monitoring of the output stage control signals to avoid any cross-conduction. Over-temperature protection is activated when junction temperature reaches the threshold values fixed internally and sets the device in tri-state mode. STV7801 can drive several data drivers connected to column electrodes of the panel. The maximum amount of data drivers is given by the Power Recovery Current of the device and then the maximum rise/fall time of the signal. The rise and fall time of the AC supply signal is adjusted by the value of the inductance connected to the panel capacitance through the data drivers. The amount of STV7801 needed to generate the AC supply can be reduced by increasing the rise/fall time of the generated AC supply. 5 - CONTROL SIGNALS TRUTH TABLE HL-Tr L H L X X X H L LH-Tr H L X L X H X L L-Clmp L L L H H H X L H-Clmp L L H L H X H L Device Output Low to High Transition High to Low Transition Comments Power Saving Mode Power Saving Mode Power Supply Clamp Power Ground Clamp Protection Mode Protection Mode Protection Mode Protection Mode Vpp Vssp Tri-State Tri-State Tri-State Tri-State 5/18 STV7801S 6 - POWER ON SEQUENCE If Vpp is switched ON before Vdd, the circuit remains in Tri-State mode until Vdd reaches Vdd threshold. If Vddis switched ON before Vpp, the circuit remains in Tri-State mode until Vpp reaches Vpp threshold. 7 - ABSOLUTE MAXIMUM RATINGS Symbol Vdd Vpp VIn Ih-Out Il-Out Ipr-Hi Ipr-Lo VCBoot-Vout Tjmax Top Tstg Logic Supply Range Driver Supply Range Logic Input Voltage Range Main Switch High Side Current Main Switch Low Side Current Power Recovery Current (note1) Power Recovery current (note1) Difference between Boot voltage and output voltage Maximum Junction Temperature (note2) Operating Temperature Range Storage Temperature Range Parameter Value -0.3,+14 -0.3 , + 100 -0.3, Vdd+0.3 -5 5 -7 7 14 Internally protected -20, +70 -50, +150 Unit V V °C A A A A V °C °C °C Note 1 Peak current as defined in Figure 1 on page 9 Note 2 These parameters are measured during ST’s internal qualification which includes temperature characterization on standard and corner batches of the process. These parameters are not tested on the parts. Remark: ESD susceptibility Human body Model: 100pF, 1.5kΩ Vpp pin (14-15: Multiwatt 15) VESD= 200V DM-LH pin (9: Multiwatt 15) VESD=400V By connecting a 1nF decoupling capacitor, the circuit withstands VESD=2.2kV on all pins. 8 - THERMAL DATA Value Symbol Rth(j-a) Rth(j-c) Parameter Junction - Ambient Thermal Resistance Junction - Case Thermal Resistance PowerSO20 40(note3) +0.6, +2.5 MW15 35 (note4) -0.6, +2.4 Unit °C/W Note 3 Multilayer PCB. Note 4 Package floating in the air. 6/18 STV7801S 9 - ELECTRICAL CHARACTERISTICS (Tamb = 25°C, Vdd=12 V, Vpp=90 V, Vsslog=Vssub=0 V, Vssp=0 V, unless otherwise specified) Symbol SUPPLY Vdd Vpp Idd Ipp Logic Supply Voltage Power Output Supply Voltage Logic Biasing Current without Transition (Stand-by-mode) Power Biasing Current without Transition (Stand-by-mode) Bootstrap supply voltage Boot leakage current Hiz mode Hiz mode Vpp=100V, VCBoot-Vout = 10V HClmp = high Vpp=100V, VCBoot-Vout = 10V -5 0 11 20 12 5 6 13 100 V V mA mA Parameter Test Conditions Min Typ Max Unit BOOTSTRAPPED SUPPLY VOLTAGE VCBoot-Vout Ilkg1Boot 12 5 V µA Ilkg2Boot OUTPUTS Boot leakage current HClmp 15 30 50 µA Output Saturation Voltage (high level) Voltage Drop vs Vpp VsatH iH@-1A iH@-3A iH@-4A Output Saturation Voltage (low level) VsatL iL@1A iL@3A iL@4A Power recirculation - Voltage drop (high to low level) VsatHL iL@1A iL@3A iL@6A Power recirculation - Voltage drop (low to high level) VsatLH iL@-1A iL@-3A iL@-6A Thermal protection temperature threshold Power ON threshold voltage on Vdd Power ON threshold voltage on Vpp Input high level (CMOS compatible) Input low level (CMOS compatible) High level inut current (Vih=Vdd) Low level input current (Vil=0) Vih=Vdd=12V 80 -2 120 0 4 VPR-FPS=Vpp/2 0.8 2.5 5 V V V 1.5 4.5 6.5 V V V 1.5 4.5 6.5 V V V VPR-FPS=Vpp/2 0.8 2 5 V V V PROTECTION Tth Vddthreshold Vppthreshold INPUTS Vih Vil Iih Iil Vdd 0.9 150 +2 V V µA µA 170 7.5 13.3 °C V V 7/18 STV7801S 10 - AC TIME REQUIREMENTS (Tamb = 25°C, Vdd=12 V, Vpp=90 V, Vsslog=Vssub=0 V, Vssp=0 V, unless otherwise specified) Symbol tLH tHL tH tL tHsetup tLsetup tHhold tLhold Parameter Low/High transition high level control pulse High/Low transition high level control pulse Duration of high voltage clamp control pulse at high level Duration of low voltage clamp control pulse at low level Set-up time of Vpp voltage clamp after low to high transition Set-up time of Vssp voltage clamp after high to low transition Hold time Vout low before high voltage clamp control pulse Hold time Vout high before low voltage clamp control pulse Test Conditions Min 10 10 10 10 10 100 TBD TBD Typ Max Unit ns ns ns ns ns ns 11 - AC TIMING CHARACTERISTICS (Tamb = 25°C, Vdd=12 V, Vpp=90 V, Vsslog=Vssub=0 V, Vssp=0 V, unless otherwise specified) Symbol tON-LH tON-HClmp tON-HL tON-LClmp Parameter Delay of power output change after recirculation low to high transition Delay of power output clamp at Vpp after output stage high side ON Delay of power output change after recirculation high to low transition Delay of power output clamp at GND after output stage low side ON Test Conditions Vpp=40V Min Typ 140 160 140 60 Max Unit ns ns ns ns 8/18 STV7801S 12 - AC CHARACTERISTIC WAVEFORMS Figure 1. Power output Current in the inductance Figure 2. tON-HClmp tON-LH Power output HClmp tH LH-tr tLH 9/18 STV7801S Figure 3. ton_HL Power output tON-LClmp L-Clmp tL HL-tr tHL 10/18 STV7801S 13 - APPLICATION DIAGRAM 10K HL-Tr 100pF Vpp 10K H-Clmp 100pF 13 1nF 10K L-Clmp 100pF 3 12 Out 2 CBoot 14 +90V 100µF/160V 1 15 Vpp STV7801 1µH Vssp 11 to Vpp pins of data driver ICs (eg pins 1, 2, 42, 66, 107,108 of STV7610A) 10K LH-Tr 100pF 4 47µF/160V 1µF/160V 5 10 Vdd DM-HL DM-LH 6 9 Vsslog 7 8 PR The diodes for the recirculation current directly impact the device performances. High Voltage diodes with recovery time inferior to 50ns are recommended. Shorter recovery times will improve the power efficiency of the application. The rise and fall time of the output signal is adjusted by the value of the inductance for a given capacitive load. trise (tfall) is calculated by the following formula : = π x L xClo ad rise A 1nF bootstrap capacitor is recommended. The bootstrap capacitor allows the output signal to reach the Vpp value. For a given output level, the power efficiency will be increased. A 47µF capacitor is recommended. The ripple on the tank capacitor is reduced by increasing the tank capacitor value. Decoupling capacitors on the power supplies will minimise the overshoots. t 11/18 STV7801S The timing of the control signals will be adjusted by the trimmers of the RC cells. It is recommended to enable the clamp signals (H-Clmp, L-Clmp) after the rising (falling) edge of the output signal has reached its maximum (minimum) value. 14 - RECOVERY FACTOR MEASUREMENT CONDITIONS An idealised schematic of the Power Recovery application is defined below. The inductance (power saving mode) and the 2 capacitors (load, floating_supply) are external components for the D.P.S. device. Figure 4. DPS Device : Functional Diagram Vpp A S3 Cfloating_supply S1 Inductance (Power Saving Mode) Cload S2 S4 Vssp The Power Recovery Factor (PRF) in % is given by the formula : PRF = 100 x (Pc - Pr) / Pc. – Pc is the theoretical capacitive power dissipated in the switches S1, S2 of the Data Power Switch device when S3, S4 are not activated. Pc is calculated by the formula : P 2 = Cload × V p p xF with F=switching frequency. Cload = equivalent panel capacitance – Pr is the power dissipated in the Data Power Switch device when it is configured in a power recovery mode (S1, S2, S3, S4 activated). Pr is calculated by multiplying the average current given by the current sensor A and the value of the supply voltage Vpp. PRF is affected by the external components of the DPS device such as the inductance and the decoupling capacitors, also the layout of the application. C 12/18 STV7801S 15 - RESULTS OF POWER EFFICIENCY 15.1 Power recovery factor for different inductance values Figure 5. STV7801- Power Recovery Factor, L=1.1µH, T=3.3µs, BYW80-200 diodes 90 85 PRF (in %) 80 75 Cload=4.7nF, Trise=220ns Cload=9.4nF, Trise=310ns Cload=14.1nF, Trise=380ns Cload=18.8nF, Trise=430ns Cload=23.5nF, Trise=480ns 70 30 40 50 60 70 VPP (in V) 80 90 100 110 Figure 6. STV7801- Power Recovery Factor. L=0.66µH, T=3.3µs, BYW80-200 diodes 85 80 PRF (in %) 75 Cload=4.7nF, Trise=170ns Cload=9.4nF, Trise=245ns 70 30 40 50 60 70 Cload=14.1nF, Trise=290ns Cload=18.8nF, Trise=340ns 80 90 100 110 VPP (in V) 13/18 STV7801S Figure 7. STV7801- Power Recovery Factor - L=0.36 µH, T=3.3µs, BYW80-200 diodes 85 80 PRF (in %) 75 70 Cload=4.7nF, Trise=140ns Cload=9.4nF, Trise=200ns Cload=14.1nF, Trise=245ns Cload=18.8nF, Trise=265ns 65 30 40 50 60 70 VPP (in V) 80 90 100 110 15.2 Power recovery factor (PRF) versus time and Cload Figure 8. STV7801- PRF versus rise time and Cload - Vpp=70V, T=3.3µs, BYW80-200 diodes 87 86 85 84 PRF (in %) 83 82 81 80 79 78 150 200 250 300 trise (tfall) in ns 350 400 450 Cload=9.4nF Cload=14.1nF Cload=18.8nF 14/18 STV7801S 15.3 Power recovery factor (PRF) for fixed rise (fall) time Figure 9. PRF versus Cload and L values - Trise (fall) = 260ns, T=3.3 µs, BYW 80-200 diodes 85 84 83 PRF (in %) 82 81 80 79 Cload=18.8nF, L=0.4uH Cload=10.4nF, L=0.66uH Cload=6.7nF , L=1.1uH Cload=17nF, L=0.5uH 78 30 40 50 60 70 Vpp (in V) 80 90 100 110 Figure 10. PRF versus Cload and L values - Trise (fall) = 330ns, T=3.3µs, BYW 80-200 diodes 86 85 84 PRF (in %) 83 82 81 Cload=18.8nF, L=0.66uH Cload=11nF, L=1.0uH Cload=8.7nF , L=1.3uH 80 30 40 50 60 70 Vpp (in V) 80 90 100 110 15/18 STV7801S 16 - PACKAGE MECHANICAL DATA Multiwatt 15 horizontal, shortleads V R R B L5 L2 V E L1 L3 L4 N L7 H2 A C V V F H2 G1 Diam 1 G S H1 MW15HME R1 P S1 Dimensions Min. A B C E F G G1 H1 H2 L1 L2 L3 L4 L5 L7 R S S1 Dia1 Millimeters Typ. 0.49 0.66 1.02 17.53 19.6 19.6 17.8 2.3 17.25 10.3 2.7 2.65 1.9 1.9 3.65 1.27 17.78 18 2.5 17.5 10.7 3 1.5 Max. 5 2.65 1.6 0.55 0.75 1.52 18.03 20.2 20.2 18.2 2.8 17.75 10.9 3.3 2.9 2.6 2.6 3.85 Min. Inches Typ. 0.019 0.026 0.040 0.690 0.772 0.772 0.701 0.091 0.679 0.406 0.106 0.104 0.075 0.075 0.144 0.050 0.700 0.709 0.098 0.689 0.421 0.118 0.059 16/18 3 V Max. 0.197 0.104 0.063 0.022 0.030 0.060 0.709 0.795 0.795 0.717 0.110 0.699 0.429 0.130 0.114 0.102 0.102 0.152 STV7801S PowerSO20 N N a2 A b e DETAIL B lead M a3 20 11 DETAIL B E2 E1 GAGE PLANE 1 s 10 L R DETAIL A e3 H D Dimensions Min. A a1 a2 a3 b c D(1) D1 E e e3 E1(1) E2 E3 G H h L M N R S T 0.20 3.10 0 0.42 0.24 15.85 9.45 14.10 Millimeters Typ. 14.20 1.27 11.43 Max. 3.50 0.275 3.20 0.075 0.50 0.28 15.95 9.75 14.35 Min. 0.008 0.122 0 0.0165 0.009 0.624 0.372 0.555 Inches Typ. 0.559 0.050 0.450 Max. 0.138 0.011 0.126 0.003 0.020 0.011 0.628 0.384 0.565 10.85 5.85 0 15.55 0.85 2.10 0.30 5d. 10.00 11.05 2.85 6.15 0.075 15.85 1.05 2.30 9d. 7d. 0.431 0.230 0 0.612 0.039 0.033 0.083 0.435 0.112 0.242 0.003 0.624 0.041 0.090 9d. 0.012 5d. 0.394 7d. 3d. 3d. Note 5 “D” and “E1” do not include mold flash or protrusions -Mold flash or protrusions shall not exceed 0.15mm (0.006inc.) -Critical dimensions: “E”, “G” and “a3” 17/18 STV7801S Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics ©2000 STMicroelectronics - All Rights Reserved. Purchase of Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. 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