TDA7340G
®
AUDIO SIGNAL PROCESSOR
AUDIOPROCESSOR:
MUTE, SOFT MUTE AND ZERO CROSSING
MUTE
ONE DIFFERENTIAL, TWO STEREO AND
TWO MONO INPUTS
DIFFERENTIAL PHONE INPUT
VOLUME, BASS, TREBLE AND LOUDNESS
CONTROL
FOUR SPEAKER ATTENUATORS WITH INDEPENDENT ATTENUATION CONTROL
STEREODECODER:
ROLL-OFF ADJUSTMENT
ADJUSTMENT FREE INTEGRATED 456KHz
VCO
HIGH CUT CONTROL
STEREO BLEND
NOISE BLANKER:
INTEGRATED HIGH-PASS FILTER
NOISE RECTIFIER OUTPUT FOR QUALITY
DETECTION
PROGRAMMABLE TRIGGER THRESHOLD
DEVIATION AND FIELD STRENGTH DEPENDENT TRIGGER ADJUSTMENT
PAUSE DETECTOR:
PROGRAMMABLE THRESHOLD
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DESCRIPTION
The TDA7340G I2C bus controlled audio signal
processor contains all signal processing blocks of
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ORDERING NUMBER: TDA7340G
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a high performance car radio, including audioprocessor, stereodecoder, noise blanker, pause
detector and different mute functions.
The use of BICMOS technology allows the implementation of several filter functions with switched
capacitor techniques like fully integrated, adjustment free PLL Loop filter, pilot detector with integrator and pilot cancellation.
This minimizes the number of external components.
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained also in the stereodecoder
part. The audioprocessor contains several new
features like softmute, zero-crossing mute and
pause detector.
Very low DC stepping is obtained by use of a
BICMOS technology.
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ALL FUNCTIONS PROGRAMMABLE VIA I2C BUS
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September 1999
1/27
TDA7340G
CONTROLLED
Pause Detector
AUDIO PROCESSOR PART
FEATURES:
Input Multiplexer:
DIFFERENTIAL CD STEREO INPUT
CASSETTE STEREO INPUT
FM STEREO INPUT FROM STEREODECODER
AM INPUT:
MONO OR STEREO MODE (PROGRAMMABLE)
BEEP INPUT (ONLY IN AM MONO MODE)
TELEPHONE DIFFERENTIAL MONO INPUT
GAIN PROGRAMMABLE IN 3 x 3.75dB
STEPS
Loudness:
FULLY PROGRAMMABLE
15 x 1.25dB STEPS
Volume Control:
1.25dB COARSE ATTENUATOR
0.31dB FINE ATTENUATORS
MAX GAIN 20dB
MAX ATTENUATION 59.7dB (PLUS LOUDNESS)
Bass Control
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Speaker Control
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4 INDEPENDENT SPEAKER CONTROL IN
1.25dB STEPS
CONTROL RANGE 37.5dB
INDEPENDENT SPEAKER MUTE
Mute Functions
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DIRECT MUTE
ZERO CROSSING MUTE WITH PROGRAMMABLE THRESHOLD
SOFT MUTE WITH EXTERNAL DEFINED
SLOPE
SOFT MUTE VIA I2C BUS OR EXTERNALLY
2/27
STEREO DECODER PART
FEATURES:
INTERNALLY
ADJUSTABLE
ROLL-OFF
COMPENSATION (I2C BUS CONTROLLED)
INTEGRATED PILOT CANCELLATION
ON CHIP FILTER FOR PILOT DETECTOR
AND PLL
ADJUSTMENT FREE VOLTAGE CONTROLLED OSCILLATOR
AUTOMATIC
PILOT
DEPENDENT
MONO/STEREO SWITCHING
VERY HIGH INTERMODULATION AND INTERFERENCE SUPPRESSION
I2C BUS CONTROLLED (STD OFF, FORCED
MONO, STEREO)
HIGH CUT CONTROL
STEREO BLEND
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NOISE BLANKER PART
FEATURES:
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±7 x 2dB STEPS
2nd ORDER SYMMETRICAL OR NON SYMMETRICAL CUT FREQUENCY RESPONSE
Treble Control
±7 x 2dB STEPS
PROGRAMMABLE THRESHOLD
DELAY TIME DEFINED BY AN EXTERNAL
CAPACITOR
INTERNAL 2nd ORDER HIGH-PASS FILTER
NOISE RECTIFIER OUTPUT FOR SIGNAL
QUALITY DETECTION
PROGRAMMABLE TRIGGER THRESHOLD
TRIGGER THRESHOLD DEPENDENT ON
HIGH FREQUENCY NOISE
BLANKING TIME PROGRAMMABLE BY EXTERNAL CAPACITOR
VERY LOW OFFSET CURRENT DURING
HOLD TIME DUE TO OPAMPS WITH MOS
INPUTS
LEVEL INPUT FOR ADDITIONAL SPIKE DETECTION ON FIELD STRENGTH WITH INTERNAL 1st ORDER + 20KHz HIGH PASS
FILTER
NOISE RECTIFIER OUTPUT FOR QUALITY
DETECTION
CIRCUITS FOR DEVIATION AND FIELD
STRENGTH DEPENDENT TRIGGER ADJUSTMENT
MPX
VCO
PHONE GND
PHONE IN
CASS L
(AM MONO)
AM_L
(BEEP)
CASS R
AM_R
GND
SUPPLY
80KHz
LP
MUX
CREF
CD R+
OUT R
OUT L
PAUSE
C1
47nF
C15
PAUSE
TDA7340G
PLL
456KHz
FM L
FM R
MUTE
field strength
LEVEL
HP
HP
DEMODULATOR
AND
AMPLITUDE ADJ
47nF
C5
LOUD R
+
47nF
C6
CSM
PEAK
DETECTOR
1.4V
-
SOFT
MUTE
19KHz
CANCELLATION
VOLUME +
LOUDNESS
LOUD L
47nF
C4
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BIN L
47nF
C16
PEAK
25KHz
LP
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C7
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IN L
(*) NETWORK TO BE ADAPTED TO THE SPECIFIC REQUESTS FOR STEREO BLEND AND HIGH CUT CONTROL
VS
CD L+
IN R
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1µF
6x
1µF
1µF
C3
4x
100nF
C8
C9
470pF
C17
TBLANK
100K
R3
PULSE
FORMER
VSB
TR L
BOUT R
R5
68K
reflevel
VR
LEVEL
CONTROL
47K
R4
(*)
OUT RR
OUT RF
OUT RR
OUT RF
47K
R6
VHCC
OUT LF
OUT LF
D95AU329A
HC R
HC L
1nF
C14
1nF
C13
DIGGND
SDA
SCL
OUT LR
OUT LR
level
TR R
2.7nF
C12
HIGH
CUT
CONTROL
TREBLE
C11
2.7nF
C10
6.2K
R2
NOISE
BLANKER
I2C BUS
BASS
6.2K
R1
BOUT L
1µF C2
BIN R
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4x
4.7µF
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CD
TDA7340G
BLOCK DIAGRAM
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3/27
TDA7340G
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
Tamb
Tstg
Parameter
Operating Supply Voltage
Operating Temperature Range
Storage Temperature Range
Value
10.5
Unit
V
-40 to 85
-55 to 150
°C
°C
TR R
CASS R
CASS L
AM_R (AM MONO)
AM_L (BEEP)
BOUT L
BIN L
BOUT R
BIN R
OUT R
IN R
PIN CONNECTION
44 43 42 41 40 39 38 37 36 35 34
OUT L
1
33
TR L
IN L
2
32
CD L+
CREF
3
31
CD L-
LOUD L
4
30
CD R-
LOUD R
5
29
CD R+
GND
6
28
PHON IN
DIGGND
7
27
PHON GND
TDA7340P
(PQFP44)
VDD
8
26
OUT LF
CSM
9
25
OUT RF
SCL
10
24
OUT LR
SDA
11
23
OUT RR
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THERMAL DATA
Symbol
Rth j-pins
Parameter
Thermal Resistance Junction-pins
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MPX
VHCC
VR
VSB
HCL
HCR
LEVEL
TBLANK
PEAK
VCO
PAUSE
12 13 14 15 16 17 18 19 20 21 22
D94AU055A
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Value
max 85
Unit
°C/W
ELECTRICAL CHARACTERISTICS (VS = 9V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz;
CREF = 22µF; unless otherwise specified, refer to the Test Circuit.)
Symbol
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SUPPLY
VS
IS
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Parameter
Supply Voltage
Supply Current
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SVR
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Ripple Rejection
Test Condition
Stereo Decoder = ON
Stereo Decoder = OFF
Audioprocessor
Stereo Decoder + Audioprocessor
Min.
Typ.
Max.
Unit
6
10
5
70
9
20
12.5
90
55
10
25
20
V
mA
mA
dB
dB
70
2.1
80
2
-0.75
10.25
2.75
100
2.6
100
130
0
11.25
3.75
2.3
2
3
0.75
12.25
4.75
KΩ
Vrms
dB
KΩ
dB
dB
dB
µV
mV
mV
INPUT SECTION
RI
VCL
SI
RL
GI MIN
GI MAX
GSTEP
eIN
VDC
4/27
Input Resistance
Clipping Level
Input Separation
Output Load Resistance
Minimum Input Gain
Max Input Gain
Step Resolution
Input Noise
Dc Steps
d ≤ 0.3%
Single Ended Input
Adjacent Gain Step
GMIN to GMAX
10
TDA7340G
ELECTRICAL CHARACTERISTICS (continued.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Input selector BIT D6 = 0 (0dB)
Input selector BIT D6 = 1(-6dB)
VCM = 1VRMS ;
f = 1KHz
f = 10KHz
10
14
48
45
15
20
75
70
0.01
5
0
-6
20
30
KΩ
KΩ
dB
dB
%
µV
dB
dB
DIFFERENTIAL CD STEREO INPUT
RI
Input Resistance
CMRR
d
eIN
GDIFF
Common Mode Rejection Ratio
Distortion
Input Noise
Differential Gain
VI = 1VRMS
20Hz to 20KHz; Flat; D6 = 0
D6 = 0
D6 = 1
-1
-7
0.08
1
-5
DIFFERENTIAL TELEPHONE MONO INPUT
RI
CMRR
d
eIN
GDIFF
Input Resistance
Common Mode Rejection Ratio
Distortion
Input Noise
Differential Gain
14
45
-4.75
20
60
0.15
10
-3.75
24
18.75
57.7
0.50
35
20
59.7
1.25
46
21.25
62.7
2.00
KΩ
dB
dB
dB
0.11
0.31
0.51
dB
-1.25
3
0
-3
0.1
0.5
1.25
2
2
3
5
dB
dB
dB
mV
mV
35
0.5
17.5
50
1.25
18.75
65
2.0
20.0
KΩ
dB
dB
20
40
80
160
100
0.3
3
mV
mV
mV
mV
dB
mV
60
1.5
25
2.0
45
dB
ms
ms
1.4
1.6
V
VCM = 1VRMS ; f = 1KHz
VI = 1VRMS
20Hz to 3 KHz; Flat
EA
Input Resistance (INR, INL)
Max Gain
Max Attenuation
Step Resolution Coarse
Attenuation
Step Resolution Fine
Attenuation
Attenuation Set Error
ET
VDC
Tracking Error
DC Steps
ASTEPF
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G = -20 to 20dB
G = -20 to -59.7dB
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Adjacent Attenuation Steps
from 0dB to AMAX
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0.5
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KΩ
dB
%
µV
dB
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-2.75
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VOLUME CONTROL
RI
CMAX
AMAX
ASTEPC
26
LOUDNESS CONTROL (LOUDL, LOUDR)
RI
ASTEP
AMAX
Internal Resistance
Step Resolution
Max Attenuation
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ZERO CROSSING MUTE
VTH
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Zero Crossing Threshold (1)
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AMUTE
VDC
Mute Attenuation
DC Step
WIN = 11
WIN = 10
WIN = 01
WIN = 00
80
0dB to Mute
SOFT MUTE
AMUTE
tD
Mute Attenuation
Delay Time
CEXT = 22nF;
0 to -20dB;
I = IMAX
I = IMIN
45
0.8
15
SOFT MUTE AT PHONE-GND
Vil
Input Low Voltage
(1) WIN represents the MUTE programming bit pair D6,D5 for the zero crossing window threshold
5/27
TDA7340G
ELECTRICAL CHARACTERISTICS (continued.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
BASS CONTROL
CRANGE
Control Range
±11.5
±14
±16
dB
ASTEP
RB
Step Resolution
1
2
3
dB
Internal Feedback Resistance
35
50
65
KΩ
TREBLE CONTROL
CRANGE
Control Range
±13
±14
±15
dB
ASTEP
Step Resolution
1
2
3
dB
SPEAKER ATTENUATORS
CRANGE
Control Range
35.0
37.5
40.0
dB
ASTEP
Step Resolution
0.5
1.25
2.0
dB
AMUTE
EA
Output Mute Attenuation
80
100
VDC
Data Word = 38.75dB
Attenuation Set Error
DC Step
Adjacent Attenuation Steps
dB
0.1
1.50
3
AUDIO OUTPUTS
VCLIP
Clipping Level
RL
ROUT
Output Load Resistance
Output Impedance
d = 0.3%
VDC
DC Voltage Level
Zero Crossing Threshold (1)
WIN = 11
WIN = 10
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WIN = 01
WIN = 00
IDELAY
Pull-up Current
VTHP
Pause Threshold
d
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S/N
d
Signal to Noise Ratio
Distortion
SC
ET
Channel Separation Left/Right
Total Tracking Error
bs
CREF (11)
O
Output Noise
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GENERAL
ENO
od
3.5
PAUSE DETECTOR
VTH
2.6
2
uc
2.1
15
30
3.8
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KΩ
Ω
4.1
V
20
40
mV
mV
80
160
25
mV
mV
µA
35
V
BW = 20Hz to 20KHz, flat
Output Muted
All gains = 0dB
2.5
5
15
All gains 0dB; VO = 1VRMS ;
VI = 1VRMS ;
106
0.01
0.08
AV = 0 to -20dB;
AV = -20 to -60dB;
External Reference Capacitor
VRMS
100
3.0
80
dB
mV
100
0
0
10
1
2
µV
µV
dB
%
dB
dB
dB
µF
BUS INPUT
VIL
VIH
IIN
Input Low Voltage
Input High Voltage
Input Current
VO
Output Voltage SDA
Acknowledge
1
VIN = 0.4V
IO = 1.6mA
(1) WIN represent the MUTE programming bit paIr D6,D5 for the zero crossing window threshold
6/27
3
-5
0.4
5
V
V
µA
0.8
V
TDA7340G
STEREO DECODER PART
ELECTRICAL CHARACTERISTICS (VS = 9V; modulation frequency: 1KHz; de-emphasis time:
T = 50µs; nominal MPX input voltage: VMPX = 0.5VRMS (75KHz deviation); GI = 3.5dB; Tamb = 27°C; unless otherwise specified)
Symbol
VIN
RIN
GMIN
GMAX
GSTEP
SVRR
VO
α
THD
S+N
N
Parameter
MPX Input Level
Input Resistance
Minimum Input Gain
Maximum Input Gain
Step Resolution
Supply Voltage Ripple Rejection
DC Output Voltage (HCL, HCR)
Channel Separation
Total Harmonic distortion
Signal plus noise to noise ratio
Test Condition
Min.
VRIPPLE = 100mV; f = 1KHz
35
2.5
9.5
1.75
50
4.2
VSB - VR = 100mVDC
f = 20Hz to 16KHz; S = 2VRMS
Typ.
0.5
50
3.5
11
2.5
60
4.5
50
0.02
91
Max.
1.25
65
4.5
12.5
3.25
4.8
0.2
CARRIER AND HARMONIC SUPPRESSION AT THE OUTPUT
α19
α38
α57
α76
Pilot Signal f = 19KHz
Subcarrier f = 38KHz
Subcarrier f = 57KHz
Subcarrier f = 76KHz
55
INTERMODULATION (note 1)
α2
α3
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fmod = 10KHz; fspur = 1KHz
fmod = 13KHz; fspur = 1KHz
TRAFFIC RADIO (note 2)
α57
Signal f = 57KHz
75
75
62
90
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VRMS
KΩ
dB
dB
dB
dB
V
dB
%
dB
dB
dB
dB
dB
65
75
dB
dB
70
dB
75
dB
95
84
dB
dB
SCA - SUBSIDIARY COMMUNICATIONS AUTHORIZATION (note 3)
α67
Signal f = 67KHz
)
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ACI - ADJACENT CHANNEL INTERFERENCE (note4)
α114
α190
Signal f = 114KHz
Signal f = 190KHz
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MONO/ STEREO SWITCH
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VINTH
Pilot Threshold Voltage
VINTH
Pilot Threshold Voltage
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for stereo "ON" Pth = 1
Pth = 0
for stereo "OFF" Pth = 1
Pth = 0
11
18
6
13
15
25
12
19
22
34
18
25
mVRMS
mVRMS
mVRMS
mVRMS
-0.31
-0.26
-0.23
V
STEREO BLEND
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VSB-VR
VSB-VR
Control Voltage for Channel
Separation
Control Voltage for Channel
Separation
α = 6dB; VR = 3.6V (note 5)
α = 26dB;
-50
mV
C13, C14 = 1nF; VHCC-VR = 100mV
VHCC-VR = 100mV
VHCC-VR = -1.3V (note 6)
50
50
150
185
µs
KΩ
KΩ
456
1
KHz
%
HIGH CUT CONTROL
τdeemp
RHCC
RHCC
De-Emphasis Time Constant
High Cut Control Resistance
High Cut Control Resistance
115
VCO
fOSC
∆f/f
Oscillator Frequency
Capture and Holding Range
7/27
TDA7340G
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
NOISE INTERFERENCE DETECTOR
VTR
Trigger Threshold 7) 8)
(see pulse slope fig 3)
meas. with
VRECT = 1.2V
meas. with
VRECT = 1.4V
VRECT
TS
IOS
VRECTDEV
VRECTFS
Rectifier Voltage
Suppression Pulse Duration
Input Offset Current During
Suppression Time
Deviation Dependent Rectifier
Voltage 9)
Field strength Controlled Rectifier
Voltage 10)
NTB = 10
NTB = 01
NTB = 10
NTB = 01
NTB = 00
NTB = 11
NTB = 10
NTB = 01
VMPXIN = 0mV
VMPXIN = 50mV;f = 200KHz
VMPXIN = 100mV; f = 200KHz
CBLANK = 470pF
meas. with
VMPX =500mV
(75KHz dev.)
meas. with
VMPX =
0mV,
VSB = VR = 500 mV (Fully
Mono)
)
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NOTES TO THE CHARACTERISTICS
OVD = 11(off)
OVD = 10
OVD = 01
OVD = 00
FSC = 11(off)
FSC = 10
FSC = 01
FSC = 00
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2.0
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VO (signal) (at1KHz)
; fs = (2 x 10KHz) - 19KHz
VO (spurious) (at1KHZ)
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VO (signal) (at1KHz)
α3 =
; fs = (3 x 13KHz) - 38KHz
VO (spurious) (at1KHZ)
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measured with : 91% mono signal; 9% pilot signal; fm=10KHz or 13KHz
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2) TRAFFIC RADIO (V.F.) suppression
α57 (V.W.F.) =
VO
VO(signal) (at1KHz)
(spurious) (at1KHZ ±23Hz)
measured with : 91% stereo signal; 9% pilot signal; fm=1KHz; 5% subcarrier
(f=57KHz, fm = 23Hz AM, m = 60%)
8/27
0.9
1.3
2.3
3.2
0.9
1.2
1.8
2.2
1.3
3.4
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1) INTERMODULATION SUPPRESSION
α2 =
100
130
160
190
150
200
250
300
0.9
1.9
2.9
40
10
mVP
mVP
mVP
mVP
mVP
mVP
mVP
mVP
V
V
V
µs
pA
)
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V
V
V
V
V
V
V
V
TDA7340G
NOTES TO THE CHARACTERISTICS (continued)
3) SCA (SUBSIDIARY COMMUNICATIONS AUTHORIZATION)
α67 =
VO(signal) (at1KHz)
; fs = (2 x 38KHz) - 67KHz
VO (spurious) (at9KHZ)
measured with : 81% mono signal; 9% pilot signal; fm=1KHz;
10% SCA - subcarrier (fs = 67KHz, unmodulated)
4) ACI (ADJACENT CHANNEL INTERFERENCE)
α114 =
VO (signal) (at1KHz)
; fs = 110KHz - (3 x 38KHz)
VO (spurious) (at4KHZ)
α190 =
VO (signal) (at1KHz)
; fs = 186KHz - (5 x 38KHz)
VO (spurious) (at4KHZ)
measured with : 90% mono signal; 9% pilot signal; fm=1KHz; 1% spurious signal
(fs = 110KHz or 186KHz, unmodulated)
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5) Control range typ 11% of VR (see figure 2)
6) Control range typ 30% of VR (see figure 1)
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7) All thresholds are measured by using a pulse with TR = 2µs, THIGH = 2µs and TF = 10µs.
The repetition rate must not increase the PEAK voltage.
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8) NBT represent the STDEC bit pair D6, D5 for the noise blanker trigger threshold
NAT represent the SPKR_LF bit pair D7, D5 for the noise controlled trigger threshold
)
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9) OVD represent the SPKR_LR bit pair D7, D6 for the over deviation detector
10) FSC represent the SPKR_RF bit pair D7, D6 for the field strength control
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11) The TDA7340G has a dedicated internal circuitry providing a soft power-on. The I2C bus data
programmation must start after the reference DC level has reached the target Vs/2 value,
otherwise a pop can be generated. The Cref pin and Out pins rise time at power on are riported
in Figg.4, 5, 6 for Cref values of 4.7uF, 10uF, 22uF.
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e
l
o
12) The CDL- and CDR- can be shortcircuited in applications providing 3 wires CD signal.
s
b
O
L+
CD
∼RL- =
L+
LR-
R+
TDA7340G
R+
D95AU352
13)The AGND and DGND layout wires must be kept separated. A 50Ω resistor is recommend to be put
as far as possible from the device.
9/27
TDA7340G
Figure 1: High Cut Control
Figure 2: Stereo Blend
D94AU056
SEP
(dB)
50
VR=3.6V
40
30
20
10
0
-0.4
-0.3
-0.2
Figure 3
-0.1
c
u
d
VMPX
VTH
e
t
le
DC-LEVEL
Time
D94AU185
TR
THIGH
TF
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
CHIP ADDRESS
bs
O
S
1
0
0
0
1
0
0
R/W
MSB
ACK
X
DATA 1 ... DATA n
LSB
X
T
o
r
P
A subaddress byte
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
SUBADDRESS
LSB
I
A3 A2 A1 A0
MSB
ACK
LSB
DATA
D95AU216
ACK = Acknowledge
S = Start
P = Stop
I = Autoincrement
MAX CLOCK SPEED 500kbits/s
Autoincrement
If bit I in the subaddress byte is set to "1", the autoincrement of subaddress is enabled.
10/27
)
s
t(
o
s
b
O
-
I2C BUS INTERFACE PROTOCOL
The interface protocol comprises:
A start condition (s)
A chip address byte, (the LSB bit determines
read/write transmission).
MSB
VSB-VR(V)
ACK
P
TDA7340G
SUBADDRESS (RECEIVE MODE)
MSB
LSB
X
X
T
T = Testmode
I
A2
0
A1
0
A0
0
0
0
0
1
Loudness
0
0
1
0
Volume
0
0
1
1
Bass, Treble
0
1
0
0
Speaker Attenuator LF
0
1
0
1
Speaker Attenuator LR
0
1
1
0
Speaker Attenuator RF
0
1
1
1
Speaker Attenuator RR
1
0
0
0
Mute
1
0
0
1
Stereodecoder
I = Autoincrement
MSB
LSB
X
X
X
ST
SM
ZM
P
P = Pause (low active)
ZM =Zero Crossing Muted (HIGH = active)
SM = Soft mute activated (HIGH = active)
DATA BYTE SPECIFICATION
X = not relevant; set to "1"during testing
INPUT SELECTOR
MSB
D7
D6
D5
D4
0
1
u
d
o
t
e
l
o
s
b
O
0
1
0
0
1
1
0
1
0
1
0
1
)
s
t(
ST = Stereo (HIGH = active)
X = Not used
The transmitted data is automatically updated after each 9th clock pulse.
Transmission can be repeated without new chipaddress.
c
u
d
e
t
le
o
s
b
O
-
D2
D1
LSB
D0
0
0
0
0
0
1
1
0
1
1
1
0
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
)
s
(
ct
D3
r
P
e
0
Input Selector
X = Not Used
TRANSMITTED DATA (SEND MODE)
X
FUNCTION
A3
0
o
r
P
FUNCTION
Quasi Diff CD
Full Diff CD
Stereo Decoder
Cassette Stereo
AM Mono
Telephone Mono
Beep Mono
AM Stereo
Not allowed
Not allowed
Not allowed
11.25dB gain
7.5dB Gain
3.75dB Gain
0 dB Gain
0dB Differential input Gain (CD Input)
-6dB Differential input Gain (CD Input)
For example to select quasi diff CD input with a gain of 7.5dB the Data Byte is: XXX01000
11/27
TDA7340G
LOUDNESS
MSB
LSB
LOUDNESS
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
0
0
0
0
0
0dB
X
X
X
0
0
0
0
1
-1.25dB
X
X
X
0
0
0
1
0
-2.5dB
X
X
X
0
0
0
1
1
-3.75dB
X
X
X
0
0
1
0
0
-5dB
X
X
X
0
0
1
0
1
-6.25dB
X
X
X
0
0
1
1
0
-7.5dB
X
X
X
X
X
X
0
0
0
1
1
0
1
0
1
0
-8.75dB
-10dB
X
X
X
X
X
X
0
0
1
1
0
0
0
1
1
0
-11.25dB
-12.5dB
X
X
X
X
X
X
0
0
1
1
0
1
1
0
1
0
-13.75dB
-15dB
X
X
X
0
1
1
0
1
-16.25dB
X
X
X
0
1
1
1
0
-17.5dB
X
X
X
0
1
1
1
1
-18.75dB
X
X
X
1
D3
D2
D1
D0
c
u
d
loudness OFF (1)
For example to select -17.5dB loudness the Data Byte is: XXX01110
)
s
t(
o
r
P
Note (1):
If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency response. D0 to D3 determine the
attenuation level
MUTE
MSB
D7
D6
D5
D4
D3
D1
)
s
(
ct
0
1
u
d
o
0
0
1
0
0
t
e
l
o
1
s
b
O
0
1
r
P
e
1
0
1
o
s
b
O
-
D2
1
1
0
e
t
le
LSB
D0
1
Soft Mute On
1
1
Soft Mute with fast slope (I = IMAX)
Soft Mute with slow slope (I = IMIN)
Direct Mute
Zero Crossing Mute ON
ZC Mute OFF (delayed until next zero crossing)
Zero Crossing Mute and Pause Detector Reset(*)
160mV ZC Window Threshold (WIN = 00)
80mV ZC Window Threshold (WIN = 01)
0
40mV ZC Window Threshold (WIN = 10)
1
20mV ZC Window Threshold (WIN = 11)
Nonsymmetrical Bass Cut
Symmetrical Bass Cut
An additional direct mute function is included in the Speaker Attenuators
(*) BIT D4 = 1disables the zero cross mute and pause detector, otherwise always active
12/27
FUNCTION
TDA7340G
SPEAKER ATTENUATORS
MSB
D7
LSB
D6
D5
D4
D3
SPEAKER ATTENUATORS LF, LR, RF, RR
D2
D1
D0
0
0
0
0dB
0
0
1
-1.25dB
0
1
0
-2.5dB
0
1
1
-3.75dB
1
0
0
-5dB
1
0
1
-6.25dB
1
1
0
-7.5dB
1
1
1
-8.75dB
-1.25dB STEPS
10dB STEPS
0
0
0dB
0
1
1
0
-10dB
-20dB
1
1
-30dB
1
1
1
1
1
Speaker Mute
c
u
d
For example an attenuation of 25dB on a selected output is given by: 11110100
Note:
If the speaker attenuator bytes the three MSBs are used for additional Noise blanker Roll off programming
e
t
le
STEREO DECODER
MSB
D7
D6
D5
D4
D3
D2
(s)
t
c
u
d
o
r
P
e
1
0
t
e
l
o
0
1
s
b
O
0
1
o
s
b
O
LSB
1
1
0
)
s
t(
o
r
P
FUNCTION
D1
D0
0
0
11dB Input Gain
0
1
1
0
8.5dB Input Gain
6dB Input Gain
1
1
3.5dB Input Gain
Stereo Decoder Muted
Stereo Decoder Off
0
Forced Mono
Noise Blanker Threshold 1 NBT 35mV
1
0
Noise Blanker Threshold 2 NBT 45mV
Noise Blanker Threshold 3 NBT 55mV
1
Noise Blanker Threshold 4 NBT 65mV
Pilot Threshold High (Pth = 0)
Pilot Threshold Low (Pth = 1)
For example pilot threshold low, noise blanker threshold 3 (NTB = 10), Stereo decoder ON, 6dB input
gain is given by: 11000010.
13/27
TDA7340G
NOISE BLANKER: SPKR LF
MSB
D7
0
0
1
1
D6
D5
D4
D3
D2
D1
LSB
D0
FUNCTION
Noise Contrelled Trigger Adjustment (NAT) *)
at VPEAK = 1.5V
VTHNOISE = 140mV
VTHNOISE = 260mV
VTHNOISE = 220mV
VTHNOISE = 280mV
Noise Blanker Trigger Threshold Fine Adjust
The NBT Threshold is reduced by 5mV
Threshold is as defined above (35, 45, 55, 65mV)
0
1
0
1
0
1
NOISE BLANKER: SPKR LR
MSB
D7
0
0
1
1
D6
D5
D4
D3
D2
D1
LSB
D0
Over Deviation Detector (OVD) *)
( VSB = VR = -1V, fully mono)
VPEAKDEV = 2.8VOP
VPEAKDEV = 2.0VOP
VPEAKDEV = 1.2VOP
off
Noise Blanker Input Mode *)
Internal MPX trigger path is disabled and the
LEVEL pin is directly connected to the trigger
input (bypassing the high pass filter).
Internal MPX trigger path and the LEVEL pin via
the 120KHz high pass are connected (default)
0
1
0
1
c
u
d
0
e
t
le
1
NOISE BLANKER: SPKR RF
MSB
D7
0
0
1
1
D6
D5
D4
D3
D2
)
s
(
ct
0
1
0
1
o
s
b
O
-
D1
LSB
D0
t
e
l
o
o
r
P
FUNCTION
Field Strength Control (FSC) *)
( VSS = VR = -1V, fully mono)
VPEAKFS = 2.4V
VPEAKFS = 1.9V
VPEAKFS = 1.4V
off
u
d
o
r
P
e
0
1
FUNCTION
Blend Mode on
Blend Mode off
NOISE BLANKER: SPKR RR
bs
O
MSB
D7
0
0
0
1
1
1
1
D6
D5
0
1
1
0
0
1
1
1
0
1
0
1
0
1
*) See Noise blanker description
14/27
D4
D3
D2
D1
LSB
D0
FUNCTION
Roll Off Compensation
13.8%
15.6%
17.4%
19.2%
21%
22.8%
24.6%
)
s
t(
TDA7340G
BASS/TREBLE
MSB
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D6
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
D5
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
D4
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
D3
D2
D1
LSB
D0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
TREBLE STEPS
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
0dB
0dB
2dB
4dB
6dB
8dB
10dB
12dB
14dB
BASS STEPS
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
0dB
0dB
2dB
4dB
6dB
8dB
10dB
12dB
14dB
e
t
le
)
s
(
ct
u
d
o
r
P
e
FUNCTION
c
u
d
)
s
t(
o
r
P
o
s
b
O
-
t
e
l
o
For example12dB TREBLE and -8dB BASS give the following Data Byte : 00111001
s
b
O
15/27
TDA7340G
VOLUME
MSB
LSB
D7
D6
D5
D4
D3
D2
FUNCTION
D1
D0
0
0
0
0
1
-0.31dB
1
0
-0.62dB
1
1
-0.94dB
0.31dB FINE ATTENUATION STEPS
1.25dB COARSE ATTENUATION STEPS
0
0
0
0dB
0
0
0
1
1
0
-1.25dB
-2.5dB
0
1
1
-3.75dB
1
0
0
-5dB
1
0
1
-6.25dB
1
1
1
1
0
1
-7.5dB
-8.75dB
10dB GAIN ATTENUATION STEPS
0
0
0
20dB
0
0
1
10dB
0
0
1
1
0
1
0dB
-10dB
1
1
0
0
0
1
-20dB
-30dB
1
1
1
1
0
1
-40dB
-50dB
e
t
le
c
u
d
)
s
t(
o
r
P
o
s
b
O
-
For example to select -47.81dB Volume the Data Byte is: 11011001
STATUS AFTER POWER ON RESET
VOLUME
BASS, TREBLE
SPKRS LF, RF, LR, RR
LOUDNESS
INPUT
STEREODEC
MUTE
u
d
o
r
P
e
t
e
l
o
NOISE BLANKER
)
s
(
ct
-59.69dB
Treble = +2dB, Bass = 0dB, symmetrical
-37.5dB
OFF, -17.5dB
No input selected, GAIN = 0dB, DIFF CD GAIN = -06dB, FULLY DIFF MODE
OFF, FORCED MONO, 6dB GAIN, PILOT THRESHOLD LOW, NOISE BLANKER =11
DIRECTLY MUTED, SOFT OFF, ZEROCROSS RESET, WINDOW THRESHOLD =11
NTB = 11, NAT = 11, OVD = OFF, FSC OFF, BLEND MODE OFF, INTERNAL MPX
PATH ENABLED
s
b
O
DESCRIPTION OF THE NOISE BLANKER
In the normal automotive environment the MPX
signal is disturbed by ignition spikes, motors and
high frequency switches etc.
The aim of the noise blanker part is to cancel the
influence of the spikes produced by these components. Therefore the output of the stereodecoder
is switched off for a time of 40µs (average spike
16/27
duration).
In a first stage the spikes must be detected but to
avoid a wrong triggering on high frequency noise
a complex trigger control is implemented.
Behind the trigger stage a pulse former generates
the 40µs "blanking" pulse.
In the following section all of these circuits are described in their function and their programming,
too (see fig.4).
TDA7340G
1.1 Trigger Path
The incoming MPX signal is highpass-filtered,
amplified and rectified (block RECT-PEAK).
The second order highpass-filter has a corner-frequency of 140KHz.
The rectifier signal, RECT, is used to generate by
peak-rectification a signal called PEAK, which is
available at the PEAK pin.
Also noise with a frequency >100KHz increases
the PEAK voltage. The value of the PEAK voltage
influences the trigger threshold voltage Vth (block
ATC).
Both signals, RECT and PEAK+Vth are fed to a
comparator (block PEAK-COMP) which outputs a
sawtooth-shaped waveform at the TBLANK pin. A
second comparator (block BLANK-COMP) forms
the internal blanking duration of 40µs.
The noise blanker is supplied by his own biasing
circuit (block BIAS-MONO).
1.2 Automatic Noise Controlled Threshold
Control (ATC)
The are two independent possibilities for programming the trigger threshold:
a)the minimum threshold in 8 steps (bits D6, D5
of the STD-byte and bit D5 of the SPKR_LF
byte)
b)and the noise adjusted threshold in 4 steps
(bits D6, D5of the SPKR_LF byte, (see fig.5)
The minimum threshold is used in combination
with a good MPX signal without any noise.
The sensitivity in this operation is high, depending
only on the programmed "minimum trigger threshold", bits NTB of the noise blanker byte 1.
It is independent of the PEAK voltage.
If the MPX signal is noisy (low fieldstrength) the
PEAK signal increases due to the higher noise,
which is also rectified (see part 1.1).
With increasing of the PEAK voltage the trigger
threshold voltage increases, too. This particular
gain is programmable in 4 steps (see fig.2).
)
s
(
ct
r
P
e
1.3 Automatic Threshold Control by the
Stereoblend voltage (ATC-SB)
Besides the noise controlled threshold adjustment
there is an additional possibility for influencing the
trigger. It is controlled by the difference between
Vsb and Vr, similar to the Stereoblend. The reason for implementing such a second control will
be explained in the following:
The point where the MPX signal starts to become
noisy is fixed by the RF part. Therefore also the
starting point of the normal noise controlled trigger adjustment is fixed (fig.6).
O
bs
1.4 Over Deviation Detector (MPX-RECT)
Sometimes when listening to stations with a
higher deviation than 75KHz the noiseblanker
triggers on the high frequency modulation.
To avoid this blanking, which causes noise in the
output signal, the noiseblanker offers a deviationdependent threshold adjustment.
By rectifying the MPX signal a further signal representing the actual deviation is obtained. It is
used to increase the PEAK voltage.
Offset and gain of this circuit are programmable in
3 steps (the first step turns off the detector, see
fig.7).
c
u
d
)
s
t(
o
r
P
1.5 Blend Mode
Another possibility to avoid a disturbing triggering
on modulation is to use the spikes on the fieldstrength signal (LEVEL pin).
But in the range of higher fieldstrength the signal
saturates and no more spike detection is possible. For this reason the TDA7340G offers the
"BLEND MODE". When "BLEND MODE" is activated a smooth transition between the LEVELand the MPX-signal is used to detect the spikes
either on LEVEL or on MPX.
In the lower fieldstrength range mainly the
LEVEL-signal is used whereas in the higher
range mainly the MPX is used. This switching is
controlled also by the normal Stereoblend signal
to avoid additional pins.
With "BLEND MODE OFF" both signals are used
to detect spikes in the whole fieldstrength range.
e
t
le
o
s
b
O
-
u
d
o
t
e
l
o
But in some cases the behaviour of the noiseblanker can be improved by increasing the
threshold even in a region of higher fieldstrength,
for the MPX signal often shows distortion in this
range.
Because of the overlap of this range and the
range of the stereo/mono transition it can be controlled by Vsb and Vr.
This threshold increase is programmable in 3
steps or switched off (see fig.6).
1.6 Input Mode
The NB of TDA7340G offers two input modes.
The first one uses the internal trigger path and
optional the LEVEL input. But the TDA7340G offers also an external trigger mode.
During this mode the internal MPX trigger path is
disabled whereas the high pass at the LEVEL pin
is bypassed.
By using an external highpass at the LEVEL-pin
one can adjust the NB’s behaviour to the desired
one.
17/27
TDA7340G
Figure 4: Block Diagram of the Noise Blanker
LEFT
80KHz LP
SIGNAL PATH
BLANK COMP
PEAK COMP
REF.
+
+
RECT
140KHz HP
MPX IN
AMP
BUF
PEAK
AUTOMATIC
THRESHOLD
CONTROL
ATC
120KHz HP
LEVEL
to OUTPUTS
RIGHT
40µs
PEAK+VTH
5
RECT-PEAK
2
4
I2C-BUS
c
u
d
ADDITIONAL THRESHOLD
CONTROL
(ATC-SB, MPX_RECT)
VR
VSB
RPEAK
82KΩ
CPEAK
47nF
CBLANK
330pF
e
t
le
D95AU330
Figure 5: Trigger Threshold vs. Vpeak
)
s
(
ct
o
r
P
o
s
b
O
-
u
d
o
r
P
e
VTH
t
e
l
o
bs
O
260mV(01)
220mV(10)
180mV(11)
140mV(00)
MIN. TRIG. THRESHOLD
NOISE ADJUSTED
TRIG. THRESHOLD
65mV
8 STEPS
30mV
0.9V
18/27
D95AU331
1.5V
VPEAK(V)
)
s
t(
TDA7340G
Figure 6: Behaviour of the Field Strength Controlled Threshold Adjustment
VPEAK
MONO
STEREO
≈3V
2.2V(00)
1.8V(01)
1.2V(10)
TRIG. THRESHOLD
NOISE
0.9V
ATC_SB OFF (11)
noisy signal
good signal
D95AU333A
E'
c
u
d
Figure 7: Behaviour of the Deviation Dependent Threshold Adiust (Over Deviation Detector)
VPEAK
(V)
e
t
le
)
s
t(
o
r
P
OVM=00
so
3.2
2.3
)
s
(
ct
1.3
0.9
u
d
o
D95AU332A
r
P
e
20
32.5
b
O
-
OVM=10
DETECTOR OFF (11)
45
MUTE & PAUSE FEATURES
The TDA7340G provides three types of mute,
controlled via I2C bus (see pag.12, MUTE BYTE
register).
t
e
l
o
s
b
O
OVM=01
SOFT MUTE
Bit D0=1 → Soft Mute ON
Bit D0=0 →Soft Mute OFF
It allows an automatic soft muting and unmuting
of the signal.
The time constant is fixed by an external capacitor Csm inserted between pin Csm and ground.
Once fixed the external capacitor, two different
slopes (time constant) are selectable by programmation of bit D1.
75
DEVIATION(KHz)
Bit D1=1 → fast slope (I=Imax)
Bit D1=0 → slow slope (I=Imin)
The soft mute generates a gradual signal decreasing avoiding big click noise of an immediate
high attenuation, without necessity to program a
sequence of decreasing volume levels. A response example is reported in Fig.12 (mute) and
Fig.13 (unmute). The final attenuation obtained
with soft mute ON is 60dB typical.
The used reference parameter is the delay time
taken to reach 20dB attenuation (no matter what
the signal level is).
Using a capacitor Csm=22nF this delay is:
d = 1. 8ms when selected Fast slope mode (bit D1=1)
d = 25 ms when selected Slow slope mode (bit D1=0)
19/27
TDA7340G
In application, the soft mute ON programmation
should be followed by programmation of DIRECT
MUTE ON (see later) in order to achieve a final
100dB attenuation.
Beside the I2C bus programmation, the Soft Mute
ON can be generated in a fast way by forcing a
LOW level at pin phone GND, controlled by the
µP through a transistor. This approach is recommended for fast RDS AF switching.
The Soft Mute status can be detected via I2C
bus, reading the Transmitted Byte, bit SM (see
data sheet pag.11).
read bit SM = 1 soft mute status ON
read bit SM = 0 soft mute status OFF
DIRECT MUTE
bit D3 = 1 Direct mute ON
bit D3 = 0 Direct nute OFF
The direct mute bit forces an internal immediate
signal connection to ground.
It is located just before the Volume/Loudness
stage, and gives a typical 100dB attenuation.
SPEAKERS MUTE
An additional direct mute function is included in
the speakers attenuators stage.
The four output LF, RF, LR, RR can be separately
muted by setting the speaker attenuator byte to
the value 11111111 binary.
Typical attenuation level 100dB. This mute is useful for fader and balance functions. It should not
be applied for system mute/unmute, because it
can generate noise due to the offset of previous
stages (bass / treble).
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PAUSE FUNCTION
On chip is implemented a pause detector block.
It uses the same 4 windows threshold selectable
for the zero crossing mute, bit D6,D5 byte MUTE
(see above). The detector can be put in OFF by
forcing bit D4=1, otherwise it is active.
The Pause detector info is available at PAUSE
pin. A capacitor must be connected between
PAUSE pin and Ground.
When the incoming signal is detected to be outside the selected window, the external capacitor
is discharged. When the signal is inside the window, the capacitor is integrating up (see Figg.16
and 17).
The pause status can be detected in two ways:
a)by reading directly the Pause pin level.
The ON/OFF voltage threshold is 3.0V typical.
Pause OFF = level low (< 3.0V)
Pause ON = level high ( ; 3.0V)
b)by reading via I2C bus the Transmitted Byte, bit P
P = 0 pause active.
P = 1 no pause detected.
The external capacitor value fixes the time constant.
The pull up current is 25uV typical
With input signal
Vin = 1Vrm --; Vdc pin pause = 15mV
Vin = 0Vrms --; Vdc pin pause = 5.62V
For example choosing Cpause = 100nF the
charge up constant is about 22ms. Instead with
Cpause = 15nF the charge up constant is about
360us.
The Pause detection is useful in applications like
RDS, to perform noiseless tuning frequeny jumps
avoiding to mute the signal.
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ZEROCROSSING MUTE
bit D2=1 D4=0 zero crossing mute ON
bit D2=0 D4=0 zero crossing mute OFF
The mute activation/deactivation is delayed until
the signal waveform crosses the DC zero level
(Vref level).
The detection works separately for the left and
the right channels (see Figg. 14, 15). Four different windows threshold are software selectable by
two dedicated bits.
bit D6 bit D5 WINDOW
0
0 Vref DC +/-160mV
0
1 Vref DC +/-80mV
1
0 Vref DC +/-40mV
1
1 Vref DC +/-20mV
The zero crossing mute activation/deactivation
starts when the AC signal level falls inside the selected window (internal comparator).
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The ZEROCROSS Mute (and Pause) detector is
always active. It can be disabled, if the feature is
not used, by forcing the bit D4=1 Zero crossing
and Pause detector reset.
In this way the internal comparator logic is
stopped, eliminating its switching noise.
The zero cross mute status is detected reading
the Transmitted Byte bit ZM.
bit ZM = 1 zero cross mute status ON
bit ZM = 0 zero cross mute status OFF
NO SYMMETRICAL BASS CUT RESPONSE
bit D7=0 No symmetrical
bit D7=1 Symmetrical
The Bass stage has the option to generate an
unsymmetrical response, for cut mode settings
(bass level from -2db to - 14dB)
For example using a T-type band pass external
TDA7340G
filter, the bass cut response becomes a low pass
filter, while the response in bass boost condition
is unchanged.
The feature is useful for human ear equalization
in noisy enviroments like cars etc.
See examples in Fig. 18 (symmetrical response)
and Fig. 19 (unsymmetrical response).
TRANSMITTED DATA (SEND MODE)
bit P = 0
bit P = 1
Pause active
No pause detected
bit ZM = 1
bit ZM = 0
Zero cross mute ON
Zero cross mute OFF
bit SM = 1
bit SM = 0
Soft mute ON
Soft mute OFF
bit ST = 1
bit ST = 0
Stereo signal detected (input MPX)
Mono signal detected (input MPX)
The TDA7340G allows the reading of four info
bits.
The type (Stereo/Mono) of received broadcasting
signal is easily checked and displayed by using
the ST bit.
The P bit check is useful in tuning jumps without
signal muting.
The SM soft mute status becomes active immediately, when bit D0 is set to 1 (soft mute ON,
MUTE byte) and not when the signal level has
reached the 60 dB final attenuation.
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WARNING
The TDA7340G always needs to receive a STOP
condition, before beginning a new START condition. The device doesn’t recognize a START condition if a previously active communication was
not ended by a STOP condition.
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TDA7340G I2C BUS PROTOCOL
The protocol is standard I2C, using subaddress
byte plus data bytes (see pagg.11 to 16).
The optional Autoincrement mode allows to refresh all the bytes registers with transmission of a
single subaddress, reducing drastically the total
transmission time.
Without autoincrement, subaddress bit I = 0, to
refresh all the bytes registers (10), it is necessary
to transmit 10 times the chip address, the subaddress and the data byte.
Working with a 100Kb/s clock speed the total time
would be :
[(9*3+2)*10]bits*10us=2.9ms
Instead using autoincrement mode, subaddress
bit I=1, the total time will be:
(9*12+2)*10us=1.1ms.
The autoincrement mode is useful also to refresh
partially the data. For example to refresh the 4
speakers attenuators it is possible to program the
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subaddress Spkr LF (code XX010100), followed
by the data byte of SPKR LF, LR, RF, RR in sequence.
Note:
that the autoincrement mode has a module 16
counter, whereas the total used register bytes are
10.
It is not correct to refresh all the 10 bytes starting
from a subaddress different than XX010000.
For example using subaddress XX010010 (volume) the registers from Volume to Stereodecoder (see pag.11) are correctly updated but the
next two transmitted bytes instead to refer to the
wanted Input selector and Loudness are discharged. (the solution in this case is to send two
separated pattern in autoinc mode, the first composed by address, subaddress XX010010, 8 data
bytes, and the second composed by address,
subaddress XX010000, 2 data bytes).
With autoincrement disabled, the protocol allows
the transmission in sequence of N data bytes of a
specific register, without necessity to resend each
time the address and subaddress bytes.
This feature can be implemented, for example, if
a gradual Volume change has to be performed (
the MCU has not to send the STOP condition,
keeping active the TDA7340G communication).
I2C BUS READ MODE
The TDA7340G gives to the master a 1 byte
"TRANSMITTED INFO" via I2C bus in read
mode. The read mode is Master activated by
sending the chip address with LSB set to 1, followed by acknowledge bit.
The TDA7340G recognizes the request. At the
following master generated clocks bits, the
TDA7340G issues the TRANSMITTED INFO
byte on the SDA data bus line (MSB transmitted
first).
At the nineth clock bit the MCU master can:
- acknowledge the reception, starting in this
way the transmission of another byte from
the TDA7340G.
- no acknowledge, stopping the read mode
communication.
LOUDNESS STAGE
The previous STMicroelectronics audioprocessors
were implementing a fixed loudness response,
only ON/OFF sw programmable.
21/27
TDA7340G
No possibility to change the loud boost rate at a
certain volume level.
The TDA7340G implements a fully programmable
loudness control in 15 steps of 1.25dB.
It allows a customized loudness response for
each application.
The external network connected to the loudness
pins LOUD_L and LOUD_R fixes the type of loudness response
1) Simple Capacitor
The loudness effect is only a boost of low frequencies. (see Fig.20)
2)Second order Loudness (boost of low and
high frequencies).
3)Second order decreased type Loudness
(lower boost of low and high frequencies).
4)Second order modified type Loudness (higher
boost of low and high frequencies).
BASS FILTER
Several bass filter types can be implemented.
Normally it is used the basic T-type Bandpass Filter.
Starting from the filter component values (R1 internal and R2, C1, C2 external), the centre frequency Fc, the gain Av at max bass boost and
the filter Q factor are computed as follows:
Fc =
Av =
1
(R1 ⋅ R2 ⋅ C1 ⋅ C2)
2⋅Π⋅√
R2⋅ C2 + R2 ⋅ C1 + R1 ⋅ C1
R2 ⋅ C1 + R2 ⋅ C2
)
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Viceversa fixed Fc, Av, and R1 = 50KΩ (internal
typ.+/-30%), the external component values are:
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C2 =
Av − 1
2 ⋅ Π ⋅ R1 ⋅ Q
Q ⋅ Q ⋅ C1
Av − 1 − Q ⋅ Q
Av − 1 − Q ⋅ Q
2 ⋅ Π ⋅ C1 ⋅ Fc ⋅ (Av − 1) ⋅ Q
TREBLE STAGE
The Treble stage is a simple high pass filter which
time constant is fixed by internal resistor (50Kohm
typ) and an external capacitor connected between
pins TREB_R/TREB_L and Ground.
IN-OUT PINS
The multiplexer output is available at OUT_R and
OUT_L pins for optional connection of external
graphic equalizer (TDA7316/TDA7317), surround
chip (TDA7346) etc.
The signal is fed in again at pins IN_L and IN-R.
In case of application without external devices the
pins OUT_L/OUT_R and IN_L/IN_R cannot be
short circuited, but must be decoupled via capacitor, necessary to avoid signal DC jumps, generating "Clicking" output noise.
The input impedance of the next volume stage is
35Kohm typical (minimum 24Kohm). A capacitor
no lower than 1uF should be used.
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INPUT SELECTOR
The multiplexer selector can choose one of the
following inputs:
- a differential CD stereo input.
- an FM stereo input coming from the on chipstereo decoder.
- a Cassette stereo input.
- a Telephone Differential mono input.
- an AM stereo input or alternatively (sw programmable) an AM mono + BEEP mono.
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√
(R1 ⋅ R2 ⋅ C1 ⋅ C2)
Q=
R2 ⋅ C1 + R2 ⋅ C2
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R2 =
The signal fed to the input pins must be decoupled via series capacitors. The minimum allowed
value depends on the correspondent input impedance.
For the CD diff input (Zi=10Kohm worst case ) a
Cin=4.7uF is recommended.
For the other inputs (70Kohm worst case, except
PHONE 14Kohm worst case but speech audio
band) a Cin=1uF is recommended.
TDA7340G
Figure 8: Power on Time Constant vs Cref
Capacitor CREF =4.7µF
V
(1V/div)
Figure 9: Power on Time Constant vs Cref
Capacitor CREF =10µF
V
(1V/div)
D95AU380
2
OUT LF
1
CREF
BWL
2
OUT LF
1
CREF
0.5s/DIV TIME
Figure 10: Power on Time Constant vs Cref Capacitor CREF =22µF
D95AU381
BWL
Figure 12: Soft Mute ON
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V
(1V)
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0.5s/DIV
TIME
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SOFT MUTE=ON SLOPE=FAST Vout=500mVrms
D95AU384
b
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-
Main Menu
2
OUT LF
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1
CREF
BWL
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1s/DIV
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TIME
V
Figure 11: SVRR vs. Frequency
SVRR
(dB)
-40
-50
D95AU383
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Chan 2
1ms 0.2V
Vout
Chan 3
1ms 2V
4.7µF
µF
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Pin Csm
-60
µ
10
CH1 9V DC
F
47µF
SOFT MUTE
-70
x
CH1 0.5V 10
~
TIME
CH2 20mV10x ~
CH3 0.2V10x =
x
CH4 20mV 10
= T/div 1ms
-80
VS=8V
Ripple=0.2VRMS
AV=-15dB
-90
-100
10
100
1K
10K
Freq(Hz)
23/27
TDA7340G
Figure 14: Zero Crossing Mute ON
Figure 13: Soft Mute ON
ZERO CROSSING MUTE = ON
D95AU389
V
Panel
STATUS
Memory
x Chan 2
0.5ms 0.2V
Save
PANEL
Recall
Auxiliary
Setups
Memory
Card
SOFT MUTE=OFF SLOPE=FAST Vout=500mVrms
V
x Chan 1
0.5ms 0.2V
LEFT
D95AU387
Main Menu
X-Y mode
Persistance
mode
TIME
CH2 528mV DC
RIGHT
Return
Pin Csm
Figure 15: Zero Crossing Mute OFF
V
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ZERO CROSSING MUTE = OFF
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V
Vout
Chan 2
1ms 0.2V
P
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let
Main Menu
Chan 1
1ms 2V
Multi Zoom
off
TIME
CH1 9V DC
SOFT MUTE
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Figure 16: Pause Detector
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LEFT
D95AU390
x Chan 2
0.2ms 1V
RIGHT
x Chan 1
0.2ms 0.5V
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2ms
CH1 2.7V DC
TIME
Figure 17: Pause Detector
PAUSE DETECTOR ZCW=160mV Cpause=100nF
PAUSE DETECTOR ZCW=160mV Cpause=100nF
D95AU391
V
Vout
D95AU392
Vout
Main Menu
Main Menu
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Chan 1
20ms 0.2V
Chan 2
20ms 2V
CH2 4.12V DC
24/27
TIME
Chan 2
20ms 2V
Chan 3
20ms 0.2V
CH2 4.08V DC
CH1 20mV10x ~
x
BWL CH2 0.2V 10x=
CH3 20mV 10 ~
x
CH4 5mV 10
~ T/div 20ms
TDA7340G
Figure 19: Non_Sym _Bass
Figure 18: Sym _Bass
D95AU393
(dB)
ATT
(dB)
D95AU394
10
10
5
5
0
0
-5
-5
-10
-15
-10
-20
-15
10
100
1K
10K
Freq(Hz)
-25
10
100
1K
Figure 20: Loudness
10K
ATT
(dB)
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14
12
10
8
6
4
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0
10
100
1K
10K
Freq(Hz)
)
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Freq(Hz)
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25/27
TDA7340G
mm
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
2.45
A1
0.25
A2
1.95
B
0.096
0.010
2.10
0.077
0.30
0.45
0.012
0.018
c
0.13
0.23
0.005
0.009
D
12.95
13.20
13.45
0.51
0.52
0.53
D1
9.90
10.00
10.10
0.390
0.394
0.398
2.00
0.079
D3
8.00
0.315
e
0.80
0.031
0.083
E
12.95
13.20
13.45
0.510
0.520
0.530
E1
9.90
10.00
10.10
0.390
0.394
0.398
E3
8.00
L
0.65
L1
OUTLINE AND
MECHANICAL DATA
MAX.
0.80
0.95
0.026
0.031
1.60
K
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0.315
0.037
0.063
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0°(min.), 7°(max.)
D
D1
D3
)
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A
A2
A1
22
0.10mm
.004
Seating Plane
44
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E1
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B
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E3
34
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12
11
1
C
L
L1
e
K
PQFP44
26/27
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23
33
)
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PQFP44 (10 x 10)
B
DIM.
TDA7340G
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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27/27
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