TS4985EKIJT

TS4985 2 X 1.2W Stereo Audio Power Amplifier with Dedicated Standby Pins ■ ■ ■ ■ ■ ■ ■ Operating from VCC=2.2V to 5.5V 1.2W output power per channel @ VCC=5V, THD+N=1%, RL=8Ω 10nA standby current 62dB PSRR @ 217Hz with grounded inputs High SNR: 106dB(A) typ. Near zero pop & click Lead-free 15 bumps, flip-chip package Flip-chip - 15 bumps Pin Connection (top view) VCC2 IN+R Description The TS4985 has been designed for top-class stereo audio applications. Thanks to its compact and power-dissipation efficient flip-chip package, it suits various applications. With a BTL configuration, this audio power amplifier is capable of delivering 1.2W per channel of continuous RMS output power into an 8Ω load @ 5V. Each output channel (left and right), has an external controlled standby mode pin (STDBYL & STDBYR) to reduce the supply current to less than 10nA per channel. The device also features an internal thermal shutdown protection. The gain of each channel can be configured by external gain setting resistors. ■ ■ ■ ■ VCC1 STDBYL IN-R VO+L VO-L BYPASS VO+R VO-R IN+L GND2 IN-L STDBYR GND1 Applications Cellular mobile phones Notebook & PDA computers LCD monitors & TVs Portable audio devices Order Codes Part Number TS4985EIJT TS4985EKIJT -40, +85°C Temperature Range Package Lead free flip-chip Lead free flip-chip + back coating Packaging Tape & Reel Marking A85 May 2005 Rev 2 1/29 www.st.com 29 Typical Application Schematic TS4985 1 Typical Application Schematic Figure 1 shows a typical application schematic for the TS4985. Figure 1. Application schematic Cfeed-L Rfeed-L 22k VCC + Cs 1u A5 VCC1 VCC2 B6 Input L GND Cin-L 100n VCC Rin-L 22k A1 IN-L VO-L A3 B2 IN+L + 1 2 3 C5 Standby L Bias AV = -1 C3 + Neg. Output L VO+L B4 Pos. Output L Bypass + Cb 1u D6 Cin-R Input R GND 100n 22k IN+R + VO-R E3 Rin-R E5 IN-R - VCC AV = -1 C1 Standby R + VO+R D4 Neg. Output R Pos. Output R 1 2 3 GND1 GND2 TS4985 D2 E1 Cfeed-R Rfeed-R 22k Table 1. External component descriptions Components Functional Description RIN L,R Inverting input resistors which sets the closed loop gain in conjunction with Rfeed. These resistors also form a high pass filter with CIN (fc = 1 / (2 x Pi x RIN x CIN)) Input coupling capacitors which blocks the DC voltage at the amplifier input terminal Feedback resistors which sets the closed loop gain in conjunction with RIN Supply Bypass capacitor which provides power supply filtering Bypass pin capacitor which provides half supply filtering Closed loop gain in BTL configuration = 2 x (RFEED / RIN) on each channel CIN L,R R FEED L,R CS CB AV L, R 2/29 TS4985 Absolute Maximum Ratings 2 Absolute Maximum Ratings Table 2. Symbol VCC Vi Toper Tstg Tj Rthja Pd ESD ESD Supply voltage (1) Input Voltage (2) Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Flip-chip Thermal Resistance Junction to Ambient Power Dissipation Human Body Model (3) Machine Model Latch-up Immunity 1. All voltages values are measured with respect to the ground pin. 2. The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V 3. All voltage values are measured from each pin with respect to supplies. Key parameters and their absolute maximum ratings Parameter Value 6 GND to VCC -40 to + 85 -65 to +150 150 180 Internally Limited 2 200 200 kV V mA Unit V V °C °C °C °C/W Table 3. Symbol VCC VICM VSTB RL ROUTGND TSD RTHJA 1. Operating conditions Parameter Supply Voltage Common Mode Input Voltage Range Standby Voltage Input: Device ON Device OFF Load Resistor Resistor Output to GND (VSTB = GND) Thermal Shutdown Temperature Flip-chip Thermal Resistance Junction to Ambient (1) Value 2.2 to 5.5 1.2V to VCC 1.35 ≤ V STB ≤ VCC GND ≤ VSTB ≤ 0.4 ≥4 ≥1 150 110 Unit V V V Ω MΩ °C °C/W When mounted on a 4-layer PCB. 3/29 Electrical Characteristics TS4985 3 Electrical Characteristics Table 4. Symbol ICC ISTANDBY Voo Po THD + N VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Supply Current No input signal, no load Standby Current (1) No input signal, Vstdby = GND, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, F = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 1Wrms, Av = 2, 20Hz ≤ F ≤ 20kHz, RL = 8Ω Power Supply Rejection Ratio(2) RL = 8Ω, Av = 2, Vripple = 200mVpp, Input Grounded F = 217Hz F = 1kHz Channel Separation, RL = 8Ω F = 1kHz F = 20Hz to 20kHz Wake-Up Time (Cb = 1µF) Standby Time (Cb = 1µF) Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain RL = 8Ω, CL = 500pF Gain Margin RL = 8Ω, C L = 500pF Gain Bandwidth Product RL = 8Ω 65 15 1.5 0.9 Min. Typ. 7.4 10 Max. 12 1000 Unit mA nA mV W % 1 1.2 0.2 10 PSRR 55 55 62 64 -107 -82 90 10 1.3 0.4 130 dB Crosstalk TWU TSTDB VSTDBH VSTDBL ΦM GM GBP dB ms µs V V Degrees dB MHz 1. Standby mode is activated when Vstdby is tied to Gnd. 2. All PSRR data limits are guaranteed by production sapling tests. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc 4/29 TS4985 Table 5. Symbol ICC ISTANDBY Voo Po THD + N Electrical Characteristics VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Supply Current No input signal, no load Standby Current (1) No input signal, Vstdby = GND, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, F = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 400mWrms, Av = 2, 20Hz ≤ F ≤ 20kHz, RL = 8Ω Power Supply Rejection Ratio(2) RL = 8Ω, Av = 2, Vripple = 200mVpp, Input Grounded F = 217Hz F = 1kHz Channel Separation, RL = 8Ω F = 1kHz F = 20Hz to 20kHz Wake-Up Time (Cb = 1µF) Standby Time (Cb = 1µF) Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain RL = 8Ω, CL = 500pF Gain Margin RL = 8Ω, C L = 500pF Gain Bandwidth Product RL = 8Ω Gain Bandwidth Product RL = 8Ω 65 15 1.5 1.5 375 Min. Typ. 6.6 10 Max. 12 1000 Unit mA nA mV mW % 1 500 0.1 10 PSRR 55 55 61 63 -107 -82 110 10 1.2 0.4 140 dB Crosstalk TWU TSTDB VSTDBH VSTDBL ΦM GM GBP GBP dB ms µs V V Degrees dB MHz MHz 1. Standby mode is activated when Vstdby is tied to Gnd. 2. All PSRR data limits are guaranteed by production sampling tests. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc 5/29 Electrical Characteristics Table 6. Symbol ICC ISTANDBY Voo Po THD + N TS4985 VCC = +2.6V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Supply Current No input signal, no load Standby Current (1) No input signal, Vstdby = GND, RL = 8Ω Output Offset Voltage No input signal, RL = 8Ω Output Power THD = 1% Max, F = 1kHz, RL = 8Ω Total Harmonic Distortion + Noise Po = 200mWrms, Av = 2, 20Hz ≤ F ≤ 20kHz, RL = 8Ω Power Supply Rejection Ratio(2) RL = 8Ω, Av = 2, Vripple = 200mVpp, Input Grounded F = 217Hz F = 1kHz Channel Separation, RL = 8Ω F = 1kHz F = 20Hz to 20kHz Wake-Up Time (Cb = 1µF) Standby Time (Cb = 1µF) Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain RL = 8Ω, CL = 500pF Gain Margin RL = 8Ω, C L = 500pF Gain Bandwidth Product RL = 8Ω 65 15 1.5 220 Min. Typ. 6.2 10 Max. 12 1000 Unit mA nA mV mW % 1 300 0.1 10 PSRR 55 55 60 62 -107 -82 125 10 1.2 0.4 150 dB Crosstalk TWU TSTDB VSTDBH VSTDBL ΦM GM GBP dB ms µs V V Degrees dB MHz 1. Standby mode is activated when Vstdby is tied to Gnd. 2. All PSRR data limits are guaranteed by production sampling tests. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon Vcc 6/29 TS4985 Table 7. Index of graphics Description Open Loop Frequency Response Power Supply Rejection Ratio (PSRR) vs. Frequency Power Supply Rejection Ratio (PSRR) vs. DC Output Voltage Power Supply Rejection Ratio (PSRR) at F=217Hz vs. Bypass Capacitor Output Power vs. Power Supply Voltage Output Power vs. Load Resistor Power Dissipation vs. Output Power Clipping Voltage vs. Power Supply Voltage and Load Resistor Current Consumption vs. Power Supply Voltage Current Consumption vs. Standby Voltage Output Noise Voltage, Device ON Output Noise Voltage, Device in Standby THD+N vs. Output Power THD+N vs. Frequency Crosstalk vs. Frequency SIgnal to Noise Ratio vs. Power Supply with Unweighted Filter (20Hz to 20kHz) SIgnal to Noise Ratio vs. Power Supply with A-weighted Filter Power Derating Curves Electrical Characteristics Figure Page Figure 2 to 7 Figure 8 to 13 Figure 14 to 22 Figure 23 Figure 24 to 26 Figure 27 to 29 Figure 30 to 32 Figure 33, Figure 34 Figure 35 Figure 36 to 38 Figure 39 Figure 40 Figure 41 to 49 Figure 50 to 52 Figure 53 to 55 Figure 56, Figure 57 Figure 58, Figure 59 Figure 60 page 8 page 9 page 10 to page 11 page 11 page 11 to page 12 page 12 page 12 to page 13 page 13 page 13 page 13 to page 14 page 14 page 14 page 14 to page 15 page 16 page 16 page 17 page 17 page 17 7/29 Electrical Characteristics Figure 2. Open loop frequency response Figure 3. TS4985 Open loop frequency response 60 Gain 40 20 Gain (dB) 0 60 Gain 40 20 Gain (dB) 0 -40 Phase (°) -40 Phase Phase (°) Phase -80 -80 0 -120 -20 -40 -60 0.1 Vcc = 2.6V RL = 8Ω Tamb = 25°C 1 10 100 1000 -160 0 -120 -20 -40 -60 0.1 Vcc = 3.3V RL = 8Ω Tamb = 25°C 1 10 100 1000 -160 -200 10000 -200 10000 Frequency (kHz) Frequency (kHz) Figure 4. Open loop frequency response Figure 5. Open loop frequency response 60 40 20 Gain (dB) 0 Gain -40 Phase (°) 100 80 60 Gain (dB) 0 Gain -40 Phase (°) Phase (°) Phase -80 40 Phase 20 0 -80 0 -120 -20 -40 -60 0.1 Vcc = 5V RL = 8Ω Tamb = 25°C 1 10 100 1000 -160 -120 -20 -200 10000 -40 0.1 Vcc = 2.6V CL = 560pF Tamb = 25°C 1 10 100 1000 -160 -200 10000 Frequency (kHz) Frequency (kHz) Figure 6. Open loop frequency response Figure 7. Open loop frequency response 100 80 60 Gain (dB) 0 Gain 100 80 Gain 0 -40 60 Gain (dB) Phase (°) -40 40 Phase 20 0 -20 -40 0.1 Vcc = 3.3V CL = 560pF Tamb = 25°C 1 10 100 1000 -80 40 Phase 20 0 -80 -120 -120 -160 -20 -200 10000 -40 0.1 Vcc = 5V CL = 560pF Tamb = 25°C 1 10 100 1000 -160 -200 10000 Frequency (kHz) Frequency (kHz) 8/29 TS4985 Figure 8. Power supply rejection ratio (PSRR) Figure 9. vs. frequency Electrical Characteristics Power supply rejection ratio (PSRR) vs. frequency 0 -10 -20 PSRR (dB) 0 Vripple = 200mVpp Rfeed = 22kΩ Input = Floating Cb = 0.1µF RL >= 4Ω Tamb = 25°C Vcc = 2.2, 2.6, 3.3, 5V -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -30 -40 -50 -60 -70 Vripple = 200mVpp Rfeed = 22kΩ Input = Floating Cb = 1µF RL >= 4Ω Tamb = 25°C Vcc = 2.2, 2.6, 3.3, 5V 100 1000 10000 Frequency (Hz) 100000 -80 100 1000 10000 Frequency (Hz) 100000 Figure 10. Power supply rejection ratio (PSRR) Figure 11. Power supply rejection ratio (PSRR) vs. frequency vs. frequency 0 -10 -20 -30 -40 -50 -60 Vripple = 200mVpp Av = 2 Input = Grounded Cb = 0.1µF, Cin = 1µF RL >= 4Ω Tamb = 25°C 0 -10 -20 PSRR (dB) PSRR (dB) -30 -40 -50 -60 -70 Vripple = 200mVpp Av = 2 Input = Grounded Cb = Cin = 1µF RL >= 4Ω Tamb = 25°C Vcc : 2.2V 2.6V 3.3V 5V Vcc = 5, 3.3, 2.5 & 2.2V 100 1000 10000 Frequency (Hz) 100000 100 1000 10000 Frequency (Hz) 100000 Figure 12. Power supply rejection ratio (PSRR) Figure 13. Power supply rejection ratio (PSRR) vs. frequency vs. frequency 0 -10 -20 -30 -40 -50 Vripple = 200mVpp Av = 2 Input = Grounded Cb = 0.1µF, Cin = 1µF RL >= 4Ω Tamb = 25°C 0 Vripple = 200mVpp Av = 10 Input = Grounded Cb = Cin = 1µF RL >= 4Ω Tamb = 25°C Vcc : 2.2V 2.6V 3.3V 5V -10 PSRR (dB) PSRR (dB) -20 -30 Vcc = 5, 3.3, 2.5 & 2.2V -40 -50 -60 100 1000 10000 Frequency (Hz) 100000 100 1000 10000 Frequency (Hz) 100000 9/29 Electrical Characteristics TS4985 Figure 14. Power supply rejection ratio (PSRR) Figure 15. Power supply rejection ratio (PSRR) vs. DC output voltage vs. DC output voltage 0 -10 -20 Vcc = 2.6V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 2 Tamb = 25°C 0 -10 -20 -30 -40 -50 -60 -2.5 -2.0 -1.5 -1.0 -0.5 Vcc = 2.6V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 5 Tamb = 25°C PSRR (dB) -30 -40 -50 -60 -70 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 PSRR (dB) 0.0 0.5 1.0 1.5 2.0 2.5 Differential DC Output Voltage (V) Differential DC Output Voltage (V) Figure 16. Power supply rejection ratio (PSRR) Figure 17. Power supply rejection ratio (PSRR) vs. DC output voltage vs. DC output voltage 0 Vcc = 2.6V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 10 Tamb = 25°C 0 -10 -20 Vcc = 3.3V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 2 Tamb = 25°C -10 PSRR (dB) -20 PSRR (dB) 0.5 1.0 1.5 2.0 2.5 -30 -40 -50 -30 -40 -60 -50 -2.5 -2.0 -1.5 -1.0 -0.5 -70 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Differential DC Output Voltage (V) 0.0 Differential DC Output Voltage (V) Figure 18. Power supply rejection ratio (PSRR) Figure 19. Power supply rejection ratio (PSRR) vs. DC output voltage vs. DC output voltage 0 Vcc = 2.6V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 10 Tamb = 25°C 0 Vcc = 3.3V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 10 Tamb = 25°C -10 -10 PSRR (dB) PSRR (dB) -20 -20 -30 -30 -40 -40 -50 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 -50 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Differential DC Output Voltage (V) Differential DC Output Voltage (V) 10/29 TS4985 Electrical Characteristics Figure 20. Power supply rejection ratio (PSRR) Figure 21. Power supply rejection ratio (PSRR) vs. DC output voltage vs. DC output voltage 0 -10 -20 PSRR (dB) 0 Vcc = 5V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 2 Tamb = 25°C -10 -20 -30 -40 -50 -60 -5 Vcc = 5V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 5 Tamb = 25°C -30 -40 -50 -60 -70 -5 -4 -3 -2 -1 0 1 2 3 Differential DC Output Voltage (V) 4 5 PSRR (dB) -4 -3 -2 -1 0 1 2 3 Differential DC Output Voltage (V) 4 5 Figure 22. Power supply rejection ratio (PSRR) Figure 23. Power supply rejection ratio (PSRR) vs. DC output voltage at f=217Hz vs. bypass capacitor 0 Vcc = 5V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 10 Tamb = 25°C -30 PSRR at 217Hz (dB) -10 -40 Av=10 Vcc: 2.6V 3.3V 5V PSRR (dB) -20 -50 Av=2 Vcc: 2.6V 3.3V 5V -30 -60 -40 -70 Av=5 Vcc: 2.6V 3.3V 5V 1 Bypass Capacitor Cb ( F) Tamb=25°C -50 -5 -4 -3 -2 -1 0 1 2 3 Differential DC Output Voltage (V) 4 5 -80 0.1 Figure 24. Output power vs. power supply voltage Figure 25. Output power vs. power supply voltage 11/29 Electrical Characteristics Figure 26. Output power vs. power supply voltage TS4985 Figure 27. Output power vs. load resistor Figure 28. Output power vs. load resistor Figure 29. Output power vs. load resistor Figure 30. Power dissipation vs. output power Figure 31. Power dissipation vs. output power per channel per channel 12/29 TS4985 Electrical Characteristics Figure 32. Power dissipation vs. output power Figure 33. Clipping voltage vs. power supply per channel voltage and load resistor Figure 34. Clipping voltage vs. power supply voltage and load resistor Figure 35. Current consumption vs. power supply voltage 8 No Loads Tamb=25 C 6 Both channels active 4 Icc (mA) 2 Only One channel active 0 0 1 2 3 Vcc (V) 4 5 Figure 36. Current consumption vs. power supply voltage Figure 37. Current consumption vs. standby voltage 6 5 4 Icc (mA) Vcc = 2.6V No Loads Tamb=25 C Both channels active 6 5 4 Icc (mA) Vcc = 3.3V No Loads Tamb=25 C Both channels active 3 2 Only one channel active 1 0 0.0 3 2 1 0 0.0 Only one channel active 0.5 1.0 1.5 Vstdb (V) 2.0 2.5 0.5 1.0 1.5 2.0 Vstdb (V) 2.5 3.0 13/29 Electrical Characteristics Figure 38. Current consumption vs. standby voltage TS4985 Figure 39. Output noise voltage device ON 8 7 6 5 Both channels active Only one channel active Icc (mA) 4 3 2 1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Vstdb (V) 3.5 Vcc = 5V No Loads Tamb=25 C 4.0 4.5 5.0 Figure 40. Output noise voltage device in Standby Figure 41. THD + N vs. output power Figure 42. THD + N vs. output power Figure 43. THD + N vs. output power 14/29 TS4985 Figure 44. THD + N vs. output power Electrical Characteristics Figure 45. THD + N vs. output power Figure 46. THD + N vs. output power Figure 47. THD + N vs. output power Figure 48. THD + N vs. output power Figure 49. THD + N vs. output power 15/29 Electrical Characteristics Figure 50. THD + N vs. frequency Figure 51. THD + N vs. frequency TS4985 Figure 52. THD + N vs. frequency Figure 53. Crosstalk vs. frequency Figure 54. Crosstalk vs. frequency Figure 55. Crosstalk vs. frequency 16/29 TS4985 Electrical Characteristics Figure 56. Signal to noise ratio vs. power Figure 57. Signal to noise ratio vs. power supply with unweighted filter (20Hz supply with unweighted filter (20Hz to 20kHz) to 20kHz) Figure 58. Signal to noise ratio vs. power Figure 59. Signal to noise ratio vs. power supply with unweighted filter (20Hz supply with A weighted filter (20Hz to 20kHz) to 20kHz) Figure 60. Power derating curves 17/29 Application Information TS4985 4 Application Information The TS4985 integrates two monolithic power amplifiers with a BTL (Bridge Tied Load) output type (explained in more detail in Section 4.1). For this discussion, only the left-channel amplifier will be referred to. Referring to the schematic in Figure 61, we assign the following variables and values: Vin = IN-L Vout1 = VO-L Vout2 = VO+R Rin = Rin-L, Rfeed = Rfeed-L Cfeed = Cfeed-L Figure 61. Typical application schematic - left channel Cfeed = Cfeed-L VCC + Rfeed = Rfeed-L Cs 1u TS4985 VCC1 Input L Cin = Cin-L Vin- = IN-L Rin = Rin-L GND Vin+= IN+L + RL Bias AV = -1 Bypass + - VCC2 Vout 1= VO-L Vout 2 = VO+L + Cb 1u 4.1 BTL configuration principle BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended output amplifiers. Thus, we have: Single-ended output 1 = Vout1 = Vout (V), Single-ended output 2 = Vout2 = -Vout (V), Vout1 - Vout2 = 2Vout (V) The output power is: 2 ( 2V outRMS ) P out = ----------------------------------RL For the same power supply voltage, the output power in a BTL configuration is four times higher than the output power in a single-ended configuration. 18/29 TS4985 Application Information 4.2 Gain in typical application schematic The typical application schematic (Figure 61) is shown on page 18. In the flat region (no Cin effect), the output voltage of the first stage is: R feed V out 1 = ( – V in ) ------------R in (V) For the second stage: Vout2 = -Vout1 (V) The differential output voltage is: R fee d V out 2 – V out1 = 2V in ------------Ri n (V) The differential gain, referred to as Gv for greater convenience, is: G v R feed V out2 – Vout 1 = ---------------------------------- = 2 ------------Vin R in Vout2 is in phase with Vin and Vout1 is phased 180° with Vin. This means that the positive terminal of the loudspeaker should be connected to Vout2 and the negative to Vout1. 4.3 Low and high frequency response In the low frequency region, Cin starts to have an effect. Cin forms with Rin a high-pass filter with a -3dB cut-off frequency: 1 F CL = ------------------------2 π Ri n Ci n (Hz) In the high frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in parallel with Rfeed. It forms a low-pass filter with a -3dB cut-off frequency. FCH is in Hz. 1 F CH = -----------------------------------2 π R feed C fe ed (Hz) The following graph (Figure 62) shows an example of Cin and Cfeed influence. Figure 62. Frequency response gain versus Cin & Cfeed 10 5 0 Gain (dB) Cfeed = 330pF Cfeed = 680pF Cin = 470nF Cin = 22nF Cin = 82nF Rin = Rfeed = 22kΩ Tamb = 25°C 10000 Cfeed = 2.2nF -5 -10 -15 -20 -25 10 100 1000 Frequency (Hz) 19/29 Application Information TS4985 4.4 Power dissipation and efficiency Hypotheses: ● ● Voltage and current in the load are sinusoidal (Vout and Iout). Supply voltage is a pure DC source (Vcc). Vout = V PEAK sin ω t Regarding the load we have: (V) and Vout Iout = ------------RL (A) and V PEA K 2 P out = -----------------------2R L (W) Therefore, the average current delivered by the supply voltage is: I CCAVG V PEAK = 2 -------------------π RL ( A) The power delivered by the supply voltage is: P supply = V CC ⋅ ICC AVG (W) Then, the power dissipated by each amplifier is: P diss = P supply – P out 2 2V CC = ---------------------- ⋅ Pout – P out π RL ( W) P diss ( W) and the maximum value is obtained when: ∂ Pdiss --------------------- = 0 ∂ P out and its value is: 2 2V cc P dissma x = -------------π2 R L (W) Note: This maximum value is only depending on power supply voltage and load values. The efficiency, η, is the ratio between the output power and the power supply: Pout π VPEAK η = ------------------- = -----------------------P supply 4V CC The maximum theoretical value is reached when VPEAK = VCC, so that: π ---- = 78.5% 4 20/29 TS4985 Application Information The TS4985 has two independent power amplifiers, and each amplifier produces heat due to its power dissipation. Therefore, the maximum die temperature is the sum of the each amplifier’s maximum power dissipation. It is calculated as follows: Pdiss L = Power dissipation due to the left channel power amplifier Pdiss R = Power dissipation due to the right channel power amplifier Total Pdiss = Pdiss L + Pdiss R (W) In most cases, Pdiss L = Pdiss R, giving: Total P diss = 2P dis sL (W) or, stated differently: 4 2VCC Total P diss = ---------------------- Pout – 2P out π RL (W ) 4.5 Decoupling the circuit Two capacitors are needed to correctly bypass the TS4985. A power supply bypass capacitor CS and a bias voltage bypass capacitor CB. CS has particular influence on the THD+N in the high frequency region (above 7kHz) and an indirect influence on power supply disturbances. With a value for CS of 1µF, you can expect similar THD+N performances to those shown in the datasheet. For example: ● ● In the high frequency region, if CS is lower than 1µF, it increases THD+N and disturbances on the power supply rail are less filtered. On the other hand, if C S is higher than µF, those disturbances on the power supply rail are more filtered. Cb has an influence on THD+N at lower frequencies, but its function is critical to the final result of PSRR (with input grounded and in the lower frequency region), in the following manner: ● If Cb is lower than 1µF, THD+N increases at lower frequencies and PSRR worsens. ● If Cb is higher than 1µF, the benefit on THD+N at lower frequencies is small, but the benefit to PSRR is substantial. Note that Cin has a non-negligible effect on PSRR at lower frequencies. The lower the value of Cin, the higher the PSRR. 4.6 Wake-up time, TWU When the standby is released to put the device ON, the bypass capacitor Cb will not be charged immediately. As Cb is directly linked to the bias of the amplifier, the bias will not work properly until the Cb voltage is correct. The time to reach this voltage is called wake-up time or TWU and specified in electrical characteristics table with Cb = 1µF. If Cb has a value other than 1µF, please refer to the graph in Figure 63 to establish the wake-up time value. 21/29 Application Information TS4985 D ue to process tolerances, the maximum value of wake-up time could be establish by the graph in Figure 64. Figure 63. Typical wake-up time vs. Cb 600 500 Startup Time (ms) Figure 64. Maximum wake-up time vs. C b Tamb=25°C Vcc=3.3V Tamb=25°C Vcc=3.3V 600 Max. Startup Time (ms) 500 Vcc=2.6V 400 300 200 Vcc=5V 100 0 0.1 400 300 200 Vcc=2.6V Vcc=5V 100 0 0.1 1 2 3 Bypass Capacitor Cb ( F) 4 4.7 1 2 3 Bypass Capacitor Cb ( F) 4 4.7 Note: Bypass capacitor Cb as also a tolerance of typically +/-20%. To calculate the wake-up time with this tolerance, refer to the previous graph (considering for example for Cb = 1µF in the range of 0.8µF ≤ 1µF ≤ 1.2µF). 4.7 Shutdown time When the standby command is set, the time required to put the two output stages in high impedance and the internal circuitry in shutdown mode is a few microseconds. Note: In shutdown mode, Bypass pin and Vin- pin are short-circuited to ground by internal switches. This allows for the quick discharge of the Cb and Cin capacitors. 4.8 Pop performance Pop performance is intimately linked with the size of the input capacitor C in and the bias voltage bypass capacitor Cb. The size of Cin is dependent on the lower cut-off frequency and PSRR values requested. The size of Cb is dependent on THD+N and PSRR values requested at lower frequencies. Moreover, Cb determines the speed with which the amplifier turns ON. In order to reach near zero pop and click, the equivalent input constant time is: τin = (Rin + 2kΩ) x Cin (s) with Rin ≥ 5kΩ must not reach the τin maximum value as indicated in the graph below in Figure 65. 22/29 TS4985 Figure 65. τin max. versus bypass capacitor 160 Tamb=25°C Vcc=3.3V 120 in max. (ms) Application Information Vcc=2.6V 80 40 Vcc=5V 0 1 2 3 Bypass Capacitor Cb ( F) 4 By following previous rules, the TS4985 can reach near zero pop and click even with high gains such as 20dB. Example calculation: With Rin = 22kΩ and a 20Hz, -3db low cut-off frequency, Cin = 361nF. So, Cin =390nF with standard value which gives a lower cut-off frequency equal to 18.5Hz. In this case, (Rin + 2kΩ) x Cin = 9.36ms. When referring to the previous graph, if Cb =1µF and Vcc = 5V, we read 20ms max. This value is twice as high as our current value, thus we can state that pop and click will be reduced to its lowest value. Minimizing both Cin and the gain benefits both the pop phenomena, and the cost and size of the application. 4.9 Dedicated standby control TS4985 has two standby control inputs to allow to put each channel in standby mode independently. In case a channel is active and another one in standby mode It’s very important to be in line with a following recommendation to reach near zero pop. When left (right) channel is active and right (left) channel is in standby mode it's necessary to put active channel in standby mode first and then immediately (with regard to Standby time) activate right (left) channel or both channels together in at the same moment. 4.10 Application example: differential-input BTL power stereo amplifier The schematic in Figure 65 shows how to design the TS4985 to work in differential-input mode. For this discussion, only the left-channel amplifier will be referred to. Let: R1R = R2L = R1, R 2R = R2L = R2 CinR = C inL = Cin The gain of the amplifier is: R2 Gvdif = 2 × -----R1 23/29 Application Information TS4985 In order to reach the optimal performance of the differential function, R1 and R2 should be matched at 1% maximum. Figure 66. Differential input amplifier configuration R2L Neg. Input LEFT VCC + CinL R1L VCC1 VCC2 Cs IN-L Pos. Input LEFT VO-L CinL R1L IN+L + R2L StandBy L LEFT Speaker StandBy L Control Bias Bypass AV = -1 + VO+L 8 Ohms R2R Pos. Input RIGHT CinR R1R IN+R + VO-R IN-R Neg. Input RIGHT - CinR R1R RIGHT Speaker AV = -1 StandBy R Control + 8 Ohms VO+R StandBy R Cb + GND1 GND2 U1 TS4985 R2R The value of the input capacitor CIN can be calculated with the following formula, using the -3dB lower frequency required (where FL is the lower frequency required): C IN ≈ 1 (F ) 2 π R 1 FL Note: This formula is true only if: FCB = 1 (Hz ) 2 π (R 1 + R 2 ) C B is 5 times lower than FL. The following bill of materials (Table 8) is provided as an example of a differential amplifier with a gain of 2 and a -3dB lower cut-off frequency of about 80Hz. Table 8. Example of a bill of materials Designator R1L = R1R R2L = R2R CinR = CinL C b=C S U1 Part Type 20k Ω / 1% 20k Ω / 1% 100nF 1µF TS4985 24/29 TS4985 Application Information 4.11 Demoboard A demoboard for the TS4985 in flip-chip package is available. For more information about this demoboard, please refer to Application Note AN2152, which can be found on www.st.com. Figure 67 shows the schematic of the demoboard. Figure 68, Figure 69 and Figure 70 show the component locations, top layer and bottom layer respectively. Figure 67. Demoboard schematic C2 1 2 1 R2 22K 2 Cn9 Vcc GND VCC 1 1 C7 1uF 2 2 C8 100nF 1 2 2 1 U1 TS4985_FC_ADAPTER Cn1 neg GND InputL pos. GND Cn3 C1 1 2 1 2 1 2 100nF C3 1 2 1 R1 22K 1 R3 2 6 IN-L VO-L 4 2 5 IN+L + Jumper J1 Cn7 VCC 1 2 3 StandByL Cn8 VCC 1 2 3 StandByR VCC1 VCC2 15 STDBYL Bias AV = -1 + VO+L 3 2 1 Cn2 neg. pos. OUTL Jumper J2 8 STDBYR Cn4 neg. GND InputR pos. GND Cn6 C4 1 2 1 2 1 2 100nF C6 1 2 1 R4 22K 1 R6 2 13 IN-R VO-R 11 2 1 Cn5 neg. pos. OUTR 2 14 IN+R + 2 1 R7 1 2 R8 7 AV = -1 Bypass + VO+R 12 1 C9 1uF 2 GND1 10 1 R5 22K C5 1 2 2 9 GND2 25/29 Application Information Figure 68. Component locations TS4985 Figure 69. Top layer Figure 70. Bottom layer 26/29 TS4985 Package Mechanical Data 5 Package Mechanical Data Figure 71. Pinout (top view) 6 5 4 3 2 1 IN-L VCC1 VCC2 IN+R STDBYL IN-R VO+L VO-L BYPASS VO+R VO-R IN+L GND2 STDBYR GND1 Note: Balls are underneath A B C D E Figure 72. Marking (top view) E Marking shows: ■ ■ ST Logo Product & assembly code: XXX - A85 from Tours - 858 from Singapore - 85K from Shenzhen 3-digit datecode: YWW “E” lead-free symbol The dot marks position of pin A1 XXX YWW ■ ■ ■ 27/29 Package Mechanical Data Figure 73. Package mechanical data for 15-bump flip-chip 2.40 mm ■ ■ 0.25m m 0.5mm TS4985 Die size: 2.40 x 1.90 mm ±30µm Die height (including bumps): 600µm Back coating height (optional): 60µm Bump diameter: 315µm ±50µm Bump diameter before reflow: 300µm ±10µm Bump height: 250µm ±40µm Die height: 350µm ±20µm Pitch: 500µm ±50µm Coplanarity: 60µm max. ■ ■ ■ 1.90 mm ∅ 0.3mm 0.86mm ■ ■ 60 µm Back coating * ■ ■ 600 µm * Optional Figure 74. Tape & Reel specification (top view) 4 1.5 1 A A Die size Y + 70µm 1 8 Die size X + 70µm 4 All dimensions are in mm User direction of feed 28/29 TS4985 Revision History 6 Revision History Date November 2004 May 2005 Revision 1 2 Changes First Release corresponding to the product preview version Product in full production Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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