TSX920, TSX921
TSX922, TSX923
Datasheet
10 MHz rail-to-rail CMOS 16 V operational amplifiers
Features
SOT23-5 (TSX921)
SOT23-6 (TSX920)
MiniSO8 (TSX922)
SO8 (TSX922)
DFN8 2x2 (TSX922)
MiniSO10 (TSX923)
•
•
•
•
•
•
•
•
•
Applications
•
•
•
Maturity status link
TSX920, TSX921, TSV922, TSV923
Related products
TSX5
Series for low-power
features
TSX6
Series for micro-power
features
TSX929
Series for higher speeds
TSV9
Series for lower voltages
Rail-to-rail input and output
Wide supply voltage: 4 V - 16 V
Gain bandwidth product: 10 MHz typ at 16 V
Low power consumption: 2.8 mA typ per amplifier at 16 V
Unity gain stable
Low input bias current: 10 pA typ
High tolerance to ESD: 4 kV HBM
Extended temperature range: -40 °C to 125 °C
Automotive qualification
Communications
Process control
Test equipment
Description
The TSX92x single and dual operational amplifiers (op amps) offer excellent AC
characteristics such as 10 MHz gain bandwidth, 17 V/ms slew rate, and 0.0003
% THD+N. These features make the TSX92x family particularly well-adapted for
communications, I/V amplifiers for ADCs, and active filtering applications.
Their rail-to-rail input and output capability, while operating on a wide supply voltage
range of 4 V to 16 V, allows these devices to be used in a wide range of applications.
Automotive qualification is available as these devices can be used in this market
segment.
Shutdown mode is available on the single (TSX920) and dual (TSV923) versions
enabling an important current consumption reduction while this function is active.
The TSX92x family is available in SMD packages featuring a high level of integration.
The DFN8 package, used in the TSV922, with a typical size of 2x2 mm and a
maximum height of 0.8 mm offers even greater package size reduction.
DS9502 - Rev 5 - October 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
TSX920, TSX921, TSX922, TSX923
Package pin connections
1
Package pin connections
Figure 1. Pin connections (top view)
OUT
VCC-
1
5
VCC+
2
1
OUT
6
2
VCC-
5
+
IN+
3
IN-
4
IN+
SOT23-5 (TSX921)
VCC+
3
SHDN
-
IN-
4
SOT23-6 (TSX920)
OUT1
VCC+
OUT1
1
8
VCC+
IN1-
OUT2
IN1-
2
7
OUT2
IN1+
IN2-
IN1+
3
6
IN2-
VCC-
IN2+
VCC-
4
5
IN2+
MiniSO8/SO8 (TSX922)
DFN8 2x2 (TSX922)
OUT1
1
10
VCC+
IN1-
2
9
OUT2
IN1+
3
8
IN2-
VCC-
4
7
IN2+
5
6
SHDN
MiniSO10 (TSX923)
DS9502 - Rev 5
page 2/29
TSX920, TSX921, TSX922, TSX923
Absolute maximum ratings and operating conditions
2
Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol
Parameter
VCC
Supply voltage (1)
Vid
Differential input voltage (2)
Vin
Input voltage
Iin
Tstg
Tj
Rthja
Input current
Unit
18
V
±VCC
mV
(VCC-)- 0.2 to (VCC+) + 0.2
V
10
mA
(3)
Storage temperature
-65 to 150
Maximum junction temperature
150
Thermal resistance junction to ambient (4) (5)
HBM: human body model
ESD
Value
MM: machine model
SOT23-5
250
SOT23-6
240
MiniSO8
190
SO8
125
DFN8 2x2
57
MiniSO10
113
(6)
°C/W
4000
(7)
100
CDM: charged device model
°C
(8)
V
1500
Latch-up immunity
200
mA
1. All voltage values, except the differential voltage are with respect to network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
3. Input current must be limited by a resistor in series with the inputs.
4. Rth are typical values.
5. Short-circuits can cause excessive heating and destructive dissipation.
6. According to JEDEC standard JESD22-A114F
7. According to JEDEC standard JESD22-A115A
8. According to ANSI/ESD STM5.3.1
Table 2. Operating conditions
Symbol
DS9502 - Rev 5
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
4 to 16
(VCC-) - 0.1 to (VCC+) + 0.1
-40 to 125
Unit
V
°C
page 3/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristics
3
Electrical characteristics
Table 3. Electrical characteristics at VCC+ = 4.5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL = 10 kΩ connected
to VCC/2 (unless otherwise specified)
Symbol
Vio
Parameter
Input offset voltage
Conditions
Min.
Typ.
Vicm = 2 V (all order codes except TSX922IYST and
TSX922IYDT)
4
Tmin < Top < Tmax
5
Vicm = 2 V (TSX922IYST, TSX922IYDT order codes
only)
5
Tmin < Top < Tmax
∆Vio/∆T Input offset voltage drift
∆Vio
Iib
Iio
Long-term input offset voltage drift (1) (2)
Input bias current
Input offset current
Max.
Unit
mV
6.5
All order codes except TSX922IYST and
TSX922IYDT
2
10
TSX922IYST and TSX922IYDT order codes only
2
15
TSX920/TSX921
6
TSX922/TSX923
9
Vout = VCC/2
10
Tmin < Top < Tmax
nV/√month
100
200
Vout = VCC/2
10
Tmin < Top < Tmax
μV/°C
100
pA
200
RIN
Input resistance
1
TΩ
CIN
Input capacitance
8
pF
CMRR
Avd
Common mode rejection ratio 20 log
(ΔVic/ΔVio)
Large signal voltage gain
Vicm = -0.1 V to 2 V, VOUT = VCC/2
61
Tmin < Top < Tmax
59
Vicm = -0.1 V to 4.6 V, VOUT = VCC/2
59
Tmin < Top < Tmax
57
RL= 2 kΩ, Vout = 0.3 V to 4.2 V
100
Tmin < Top < Tmax
90
RL= 10 kΩ, Vout = 0.2 V to 4.3 V
100
Tmin < Top < Tmax
90
RL= 2 kΩ tο VCC/2
VOH
High level output voltage
82
72
112
50
Tmin < Top < Tmax
RL= 10 kΩ tο VCC/2
10
16
mV from VCC+
20
RL= 2 kΩ tο VCC/2
Low level output voltage
80
100
Tmin < Top < Tmax
VOL
dB
108
42
Tmin < Top < Tmax
80
100
RL= 10 kΩ tο VCC/2
9
Tmin < Top < Tmax
16
mV
20
Empty
Iout
Isink
DS9502 - Rev 5
Vout = 4.5 V
16
Tmin < Top < Tmax
13
21
mA
page 4/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristics
Symbol
Iout
ICC
GBP
Parameter
Conditions
Isource
Min.
Typ.
Vout = 0 V
16
21
Tmin < Top < Tmax
13
No load, Vout = VCC/2
Supply current (per amplifier)
RL = 10 kΩ, CL = 20 pF, G = 20 dB
9
Unity gain frequency
ɸm
Phase margin
Gm
Gain margin
SR+
Positive slew rate
Av = 1, Vout = 0.5 to 4.0 V, measured between 10 %
to 90 %
14.7
Negative slew rate
Av = 1, Vout = 4.0 to 0.5 V, measured between 90 %
to 10 %
17.2
f = 10 kHz
17.9
f = 100 kHz
12.9
SR-
3.4
3.5
FU
MHz
9.3
RL = 10 kΩ, CL = 20 pF
en
Equivalent input noise voltage
∫en
Low-frequency peak-to-peak input noise Bandwidth: f = 0.1 to 10 Hz
f = 1 kHz, Av = 1, RL = 10 kΩ, Vout = 2 Vrms
THD+N Total harmonic distortion + noise
Unit
mA
2.9
Tmin < Top < Tmax
Gain bandwidth product
Max.
60
Degrees
6.7
dB
V/μs
nV√Hz
8.1
µVpp
0.002
%
Shutdown characteristics (TSX920 and TSX923 only)
ICC_shdn
Supply current in shutdown mode (per
amplifier)
SHDN = VCC-
7
Tmin < Top < Tmax
15
20
ton
Amplifier turn-on time
9
toff
Amplifier turn-off time
0.7
µΑ
µs
1. Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an
activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 5.5 Long term input offset voltage
drift).
2. When used in comparator mode, with high differential input voltage, during a long period of time with VCC close to 16 V and Vicm>VCC/2, Vio
can experience a permanent drift of a few mV drift. This phenomenon is notably worse at low temperatures.
DS9502 - Rev 5
page 5/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristics
Table 4. Electrical characteristics at VCC+ = 10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL = 10 kΩ connected
to VCC/2 (unless otherwise specified)
Symbol
Vio
Parameter
Input offset voltage
Conditions
Min.
Typ.
Vicm = 2 V (all order codes except TSX922IYST and
TSX922IYDT)
4
Tmin < Top < Tmax
5
Vicm = 2 V (TSX922IYST and TSX922IYDT order
codes only)
5
Tmin < Top < Tmax
∆Vio/∆T Input offset voltage drift
∆Vio
Iib
Iio
Long-term input offset voltage drift (1) (2)
Input bias current
Input offset current
Max.
Unit
mV
6.5
All order codes except TSX922IYST and
TSX922IYDT
2
10
TSX922IYST and TSX922IYDT order codes only
2
15
TSX920/TSX921
92
TSX922/TSX923
128
Vout = VCC/2
10
Tmin < Top < Tmax
nV/√month
100
200
Vout = VCC/2
10
Tmin < Top < Tmax
μV/°C
100
pA
200
RIN
Input resistance
1
TΩ
CIN
Input capacitance
8
pF
CMRR
Avd
Common mode rejection ratio 20 log
(ΔVic/ΔVio)
Large signal voltage gain
Vicm = -0.1 V to 7 V, VOUT = VCC/2
72
Tmin < Top < Tmax
70
Vicm = -0.1 V to 10.1 V, VOUT = VCC/2
64
Tmin < Top < Tmax
62
RL= 2 kΩ, Vout = 0.3 V to 9.7 V
100
Tmin < Top < Tmax
90
RL= 10 kΩ, Vout = 0.2 V to 9.8 V
100
Tmin < Top < Tmax
90
RL= 2 kΩ tο VCC/2
VOH
High-level output voltage
85
75
117
94
Tmin < Top < Tmax
RL= 10 kΩ tο VCC/2
31
80
Tmin < Top < Tmax
Iout
Isource
ICC
Supply current (per amplifier)
RL= 10 kΩ tο VCC/2
14
DS9502 - Rev 5
40
mV
50
Vout = 10 V
50
Tmin < Top < Tmax
42
Vout = 0 V
75
Tmin < Top < Tmax
70
No load, Vout = VCC/2
mV from VCC+
110
130
Tmin < Top < Tmax
Isink
40
50
RL= 2 kΩ tο VCC/2
Low-level output voltage
110
130
Tmin < Top < Tmax
VOL
dB
107
55
mA
82
3.1
3.6
mA
page 6/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristics
Symbol
ICC
GBP
Parameter
Conditions
Supply current (per amplifier)
Tmin < Top < Tmax
Gain bandwidth product
RL = 10 kΩ, CL = 20 pF, G = 20 dB
Min.
Typ.
Unit
3.6
mA
10
FU
Unity gain frequency
ɸm
Phase margin
Gm
Gain margin
SR+
Positive slew rate
Av = 1, Vout = 0.5 to 9.5 V, measured between 10 %
to 90 %
17.7
Negative slew rate
Av = 1, Vout = 9.5 to 0.5 V, measured between 90 %
to 10 %
19.6
f = 10 kHz
16.8
f = 100 kHz
12
SR-
Max.
MHz
11.2
RL = 10 kΩ, CL = 20 pF
en
Equivalent input noise voltage
∫en
Low-frequency peak-to-peak input
noise
Bandwidth: f = 0.1 to 10 Hz
f = 1 kHz, Av = 1, RL = 10 kΩ, Vout = 2 Vrms
THD+N Total harmonic distortion + noise
56
Degrees
6
dB
V/μs
nV√Hz
8.64
µVpp
0.0006
%
Shutdown characteristics (TSX920 and TSX923 only)
ICC_shdn
Supply current in shutdown mode (per
amplifier)
SHDN = VCC-
7
Tmin < Top < Tmax
15
20
ton
Amplifier turn-on time
2.4
toff
Amplifier turn-off time
0.35
µΑ
µs
1. Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an
activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 5.5 Long term input offset voltage
drift).
2. When used in comparator mode, with high differential input voltage, during a long period of time with VCC close to 16 V and Vicm>VCC/2, Vio
can experience a permanent drift of a few mV drift. This phenomenon is notably worse at low temperatures.
DS9502 - Rev 5
page 7/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristics
Table 5. Electrical characteristics at VCC+ = 16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL = 10 kΩ connected
to VCC/2 (unless otherwise specified)
Symbol
Vio
Parameter
Input offset voltage
Conditions
Min.
Typ.
Vicm = 2 V (all order codes except TSX922IYST and
TSX922IYDT)
4
Tmin < Top < Tmax
5
Vicm = 2 V (TSX922IYST and TSX922IYDT order
codes only)
5
Tmin < Top < Tmax
∆Vio/∆T Input offset voltage drift
∆Vio
Iib
Iio
Long-term input offset voltage drift (1)
(2)
Input bias current
Input offset current
Max.
Unit
mV
6.5
All order codes except TSX922IYST and
TSX922IYDT
2
10
TSX922IYST and TSX922IYDT order codes only
2
15
TSX920/TSX921
1.73
TSX922/TSX923
2.26
Vout = VCC/2
10
Tmin < Top < Tmax
nV/√month
100
200
Vout = VCC/2
10
Tmin < Top < Tmax
μV/°C
100
pA
200
RIN
Input resistance
1
TΩ
CIN
Input capacitance
8
pF
CMRR
SVRR
Avd
Common mode rejection ratio 20 log
(ΔVic/ΔVio)
Supply voltage rejection ratio
Large signal voltage gain
Vicm = -0.1 V to 13 V, VOUT = VCC/2
73
Tmin < Top < Tmax
71
Vicm = -0.1 V to 16.1 V, VOUT = VCC/2
67
Tmin < Top < Tmax
65
VCC = 4.5 V tο 16 V
73
Tmin < Top < Tmax
71
RL= 2 kΩ, Vout = 0.3 V to 15.7 V
100
Tmin < Top < Tmax
90
RL= 10 kΩ, Vout = 0.2 V to 15.8 V
100
Tmin < Top < Tmax
90
RL= 2 kΩ tο VCC/2
VOH
High-level output voltage
85
76
85
105
113
150
Tmin < Top < Tmax
RL= 10 kΩ tο VCC/2
43
50
mV from VCC+
70
RL= 2 kΩ tο VCC/2
Low-level output voltage
200
230
Tmin < Top < Tmax
VOL
dB
140
Tmin < Top < Tmax
200
230
RL= 10 kΩ tο VCC/2
30
Tmin < Top < Tmax
50
mV
70
Empty
Iout
Isink
DS9502 - Rev 5
Vout = 16 V
45
Tmin < Top < Tmax
40
50
mA
page 8/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristics
Symbol
Iout
ICC
GBP
Parameter
Conditions
Isource
Min.
Typ.
Vout = 0 V
65
74
Tmin < Top < Tmax
60
No load, Vout = VCC/2
Supply current (per amplifier)
RL = 10 kΩ, CL = 20 pF, G = 20 dB
Unit
mA
2.8
Tmin < Top < Tmax
Gain bandwidth product
Max.
3.4
3.4
10
MHz
FU
Unity gain frequency
ɸm
Phase margin
Gm
Gain margin
SR+
Positive slew rate
Av = 1, Vout = 0.5 to 15.5 V, measured between 10 %
to 90 %
16.2
Negative slew rate
Av = 1, Vout = 15.5 to 0.5 V, measured between 90 %
to 10 %
17.2
f = 10 kHz
16.5
f = 100 kHz
11.8
Bandwidth: f = 0.1 to 10 Hz
8.58
µVpp
0.0003
%
SR-
12
RL = 10 kΩ, CL = 20 pF
en
Equivalent input noise voltage
∫en
Low-frequency peak-to-peak input
noise
THD+N Total harmonic distortion + noise
tS
Setting time
f = 1 kHz, Av = 1, RL = 10 kΩ, Vout = 4 Vrms
55
Degrees
5.9
dB
V/μs
Gain = 1, 100 mV input voltage, 0.1 % of final value
245
Gain = 1, 100 mV input voltage, 1 % of final value
178
nV√Hz
ns
Shutdown characteristics (TSX920 and TSX923 only)
ICC_shdn
SHDN = VCCSupply current in shutdown mode (per
amplifier)
Tmin < Top < Tmax
7
15
20
ton
Amplifier turn-on time
1.5
toff
Amplifier turn-off time
0.2
µΑ
µs
1. Typical value is based on the Vio drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an
activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 5.5 Long term input offset voltage
drift).
2. When used in comparator mode, with high differential input voltage, during a long period of time with VCC close to 16 V and Vicm>VCC/2, Vio
can experience a permanent drift of a few mV drift. This phenomenon is notably worse at low temperatures.
DS9502 - Rev 5
page 9/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristic curves
4
Electrical characteristic curves
Figure 3. Distribution of input offset voltage at VCC = 4.5 V
Figure 2. Supply current vs.supply voltage
30
Distribution of Vio
Vcc=4.5V, Vicm=2.25V
Population %
25
20
15
10
5
0
-3
-2
-1
0
1
2
3
Input Offset Voltage(mV)
Figure 4. Distribution of input offset voltage at VCC = 10 V
Figure 5. Distribution of input offset voltage at VCC = 16 V
30
30
Distribution of Vio
Vcc=10V, Vicm=5V
Distribution of Vio
Vcc=16V, Vicm=8V
25
20
Population %
Population %
25
15
10
5
20
15
10
5
0
0
-3
-2
-1
0
1
2
-3
3
-2
Figure 6. Input offset voltage vs. temperature at VCC = 16
V
1
2
3
25
ΔVio/ΔT
Vcc=16V, Vicm=8V
20
3
Population %
Input offset voltage (mV)
0
Figure 7. Distribution of input offset voltage drift over
temperature
Vcc=16V, Vicm=8V
5
-1
Input offset voltage (mV)
Input offset voltage (mV)
0
15
10
-3
5
-5
-40
DS9502 - Rev 5
0
-20
0
20
40
60
80
Temperature (°C)
100 120
-7
-6
-5
-4
-3
-2
-1
0
ΔVio/ΔT (µV/°C)
page 10/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristic curves
Vcc=4V
T=-40°C
0.0 0.3 0.5 0.8 1.0 1.3 1.5 1.8 2.0 2.3 2.5 2.8 3.0 3.3 3.5 3.8 4.0
-75
4.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Output Voltage (V)
Figure 12. Output current vs. output voltage at VCC = 16 V
T=25°C
T=125°C
0
-25
Vcc=16V
-50
Source
Vid=1V
-75
0.0
DS9502 - Rev 5
2.5
5.0
7.5
10.0
Output Voltage (V)
12.5
15.0
16.0
15.9
15.8
15.7
15.6
15.5
15.4
0.5
0.4
0.3
0.2
0.1
0.0
0.0
25
T=-40°C
Output voltage (V)
Output Current (mA)
Sink
50 Vid=-1V
Figure 13. Output rail linearity
Rl=2kΩ
Vcc=16V
Follower configuration
T=25°C
Rl=10kΩ
16.0
3.5
15.9
1.5 2.0 2.5 3.0
Output Voltage (V)
Source
Vid=1V
15.8
1.0
-50
15.7
0.5
Vcc=10V
15.6
-30
0.0
-25
15.5
Source
Vid=1V
0
0.5
-10
T=125°C
T=25°C
15.4
Vcc=4V
25
0.4
T=125°C
0
T=-40°C
0.3
T=25°C
Output Current (mA)
Output Current (mA)
Sink
50 Vid=-1V
T=-40°C
-20
T=125°C
Figure 11. Output current vs. output voltage at VCC = 10 V
30
10
T=25°C
Common mode voltage(V)
Figure 10. Output current vs. output voltage at VCC = 4 V
20
T=-40°C
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
10.011.012.0
12.013.014.0
14.015.016.0
16.0
Common mode voltage(V)
Sink
Vid=-1V
Vcc=16V
0.2
T=125°C
T=25°C
1.0
0.8
0.5
0.3
0.0
-0.3
-0.5
-0.8
-1.0
-1.3
-1.5
-1.8
-2.0
0.1
1.0
0.8
0.5
0.3
0.0
-0.3
-0.5
-0.8
-1.0
-1.3
-1.5
-1.8
-2.0
Figure 9. Input offset voltage vs. common-mode voltage
at VCC = 16 V
Input offset voltage (mV)
Input offset voltage (mV)
Figure 8. Input offset voltage vs. common-mode voltage
at VCC = 4 V
Input voltage (V)
page 11/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristic curves
Figure 15. Bode diagram vs. temperature for VCC = 4 V
120
Gain
60
40
20
Phase
0
-20
Vcc=16V, Vicm=8V,
Rl=10kΩ , Cl=20pF; VRl=Vcc/2
-40
0.01
0.1
1
10
100
1000
200
T=25°C
20
T=125°C
0
0
T=-40°C
-20
-150
Vcc=4V, Vicm=2V, G=100
Rl=10kΩ, Cl=20pF, VRl=Vcc/2
-200
-250
1
10
100
1000
10000
Frequency (kHz)
Figure 17. Bode diagram vs. temperature for VCC = 16 V
250
250
200
Gain
40
200
Gain
150
Gain (dB)
150
100
0
-50
T=-40°C
-20
Phase (°)
50
T=125°C
-100
Phase
T=25°C
20
Gain (dB)
T=25°C
0
Vcc=10V, Vicm=5V, G=100
Rl=10kΩ, Cl=20pF, VRl=Vcc/2
T=125°C
0
T=-40°C
-20
-50
-100
Phase
-150
10
100
1000
Vcc=16V, Vicm=8V, G=100
Rl=10kΩ, Cl=20pF, VRl=Vcc/2
-40
-200
-200
-250
-250
1
100
50
0
-150
-40
-50
-100
Phase
-40
10000
Figure 16. Bode diagram vs. temperature for VCC = 10 V
20
100
50
Frequency (kHz)
40
150
Phase (°)
80
Phase (°)
Gain (dB)
100
250
Gain
40
Phase (°)
360
320
280
240
200
160
120
80
40
0
-40
-80
-120
-160
-200
-240
-280
-320
-360
140
Gain (dB)
Figure 14. Open loop gain vs. frequency
1
10000
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
Figure 18. Bode diagram at VCC = 16 V with low common- Figure 19. Bode diagram at VCC = 16 V with high commonmode voltage
mode voltage
250
Gain (dB)
T=-40°C
100
50
0
0
-50
-20
150
T=25°C
20
-100
Phase
200
Gain
150
100
T=-40°C
T=125°C
0
0
-50
-20
-100
Phase
-150
Vcc=16V, Vicm=0.5V, G=100
Rl=10kΩ, Cl=20pF, VRl=Vcc/2
-40
-200
-150
Vcc=16V, Vicm=15.5V, G=100
Rl=10kΩ, Cl=20pF, VRl=Vcc/2
-40
-200
-250
-250
1
10
100
1000
Frequency (kHz)
DS9502 - Rev 5
10000
50
Phase (°)
T=25°C
T=125°C
40
Gain (dB)
Gain
20
250
200
Phase (°)
40
1
10
100
1000
10000
Frequency (kHz)
page 12/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristic curves
Figure 20. Bode diagram at VCC = 16 V and RL = 10 kΩ, CL
= 47 pF
Figure 21. Bode diagram at VCC = 16 V and RL = 10 kΩ, CL
= 120 pF
250
250
40
200
Gain
200
Gain
150
150
T=25°C
T=125°C
0
-50
T=-40°C
-20
-100
Phase
T=125°C
Gain (dB)
50
0
T=25°C
20
100
Phase (°)
Gain (dB)
20
50
0
0
T=-40°C
-20
-50
-100
Phase
-150
-150
Vcc=16V, Vicm=8V, G=100
Rl=10kΩ, Cl=47pF, VRl=Vcc/2
-40
-200
10
100
1000
Vcc=16V, Vicm=8V, G=100
Rl=10kΩ, Cl=120pF, VRl=Vcc/2
-40
1
10000
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
Figure 22. Bode diagram at VCC = 16 V and RL = 2.2 kΩ, CL
= 20 pF
Figure 23. Slew rate vs. supply voltage and temperature
30
250
40
-200
-250
-250
1
100
Phase (°)
40
200
Gain
20
T=125°C
SR positive
50
0
0
T=-40°C
-20
-50
Phase (°)
Gain (dB)
100
T=125°C
-100
Phase
Slew Rate (V/µs)
150
T=25°C
20
10
100
1000
10000
SR negative
Figure 25. Closed loop gain vs. frequency with different
gain resistors
20
Rf=Rg=1kΩ
10
Gain (dB)
Overshoot (%)
Figure 24. Overshoot vs. capacitive load without feedback
capacitor
DS9502 - Rev 5
Vicm=VRl=Vcc/2
Rl=10kΩ, Cl=20pF
Vin from 0.5V to Vcc-0.5V
-30
4.0 5.0 6.0 7.0 8.0 9.0 10.0
10.011.012.0
12.013.014.0
14.015.016.0
16.0
Vcc (V)
Frequency (kHz)
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10
-10
T=-40°C
-200
-250
1
0
T=25°C
-20
-150
Vcc=16V, Vicm=8V, G=100
Rl=2.2kΩ, Cl=20pF, VRl=Vcc/2
-40
10
G=1
G=-1
Vcc=16V,
100mVpp,
Rl=10kΩ
100
Load capacitance (pF)
1000
Rf=Rg=100kΩ
0
-10
-20
-30
1k
Vcc=16V
Vicm=Vcc/2
Gain=-1
Cf=0pF
Rl=10kΩ
Cl=20pF
10k
Rf=Rg=30kΩ
Rf=Rg=10kΩ
100k
1M
10M
Frequency (Hz)
page 13/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristic curves
Figure 26. Large step response
Figure 27. Small step response
5.00
Output Voltage (V)
3.00
2.00
1.00
0.05
0.03
0.00
-1.00
-2.00
0.01
0.00
-0.01
-0.02
-0.03
-4.00
-0.04
-0.05
-1.0µ
0.0
1.0µ
Time (s)
2.0µ
20.0µ
3.0µ
Figure 28. Small step response with feedback capacitor
CF
0.10
Output Impedance (Ω)
Cf=2pF
0.03
Cf=3pF
0.00
Vcc = 16V
Rl=10kΩ
Cl=20pF
G=-1
Rf=Rg=10kΩ
T=25°C
-0.03
-0.05
-0.08
-0.10
-500.0n
0.0
500.0n
Time (s)
1.0µ
1.5µ
100
10
1
0.1
0.01
0.1
1
500
6
Vicm=15.5V
300
Tamb=25°C
200
Vicm=0.5V
10000
Noise 0.1Hz_10Hz
8.58 µVpp
5
400
10
100
1000
Frequency (kHz)
Figure 31. 0.1 to 10 Hz noise
Output Voltage (µV)
Equivalent Input Voltage Noise (nV/VHz)
20.8µ
Vcc=4V to 16V
Osc level=30mVRMS
G=1
Ta=25° C
Figure 30. Noise vs. frequency with 16 V supply voltage
4
3
2
1
0
-1
100
DS9502 - Rev 5
20.6µ
1000
0.05
0
20.2µ
20.4µ
Time (s)
Figure 29. Output impedance vs. frequency in closed loop
configuration
No Cf
0.08
Output Voltage (V)
0.02
-3.00
-5.00
Vcc = 16V
Rl=10kΩ
Cl=20pF
G=1
T=25°C
0.04
Vcc = 16V
Rl=10kΩ
Cl=20pF
G=1
T=25°C
Output Voltage (V)
4.00
Vicm=8V
100m
-2
1
10
100
Frequency (kHz)
1k
10k
-3
2
Time (s)
3
page 14/29
TSX920, TSX921, TSX922, TSX923
Electrical characteristic curves
Figure 32. THD+N vs. frequency at VCC = 16 V
Figure 33. THD+N vs. output voltage at VCC = 16 V
1
Vin=2Vrms
Gain=1
BW=80kHz
Vcc=16V
Vicm=Vcc/2
0.01
Rl=600Ω
f=1kHz
Gain=1
BW=22kHz
Vcc=16V
Vicm=Vcc/2
0.1
THD + N (%)
THD + N (%)
0.1
0.01
Rl=600Ω
1E-3
Rl=10kΩ
Rl=10kΩ
1E-3
Rl=2kΩ
1E-4
100
1000
Rl=2kΩ
10000
1E-4
0.01
100000
0.1
Frequency (Hz)
1
Output Voltage (Vrms)
Figure 34. Power supply rejection ratio (PSRR) vs.
frequency
Figure 35. Crosstalk vs. frequency between operators on
TSX922 at VCC = 16 V
-120
0
+PSRR
-20
Vcc=16V
Vicm=Vcc/2
Rl=10kΩ
Cl=20pF
Vout=3.5Vrms
-100
Crosstalk (dB)
PSRR (dB)
-40
-80
-PSRR
-60
-40
-60
-80
-100
Ch1 to Ch2
-120
-140
-20
0
10
Vcc=16V, Vicm=8V, G=1
Rl=10kΩ, Cl=20pF, Vripple=100mVpp
100
1000
10000
100000
Ch2 to Ch1
-160
-180
1k
1000000
10k
Frequency (Hz)
Figure 36. Startup time after standby released for VCC = 4
V
17.50
Standby
3.00
Output -40°C
2.00
Vcc = 4V
Rl=10kΩ
1.00 Cl=20pF
G=1
Output 25°C
Output 125°C
0.00
Output Voltage (V)
Output Voltage (V)
10M
20.00
4.00
DS9502 - Rev 5
1M
Figure 37. Startup time after standby released for VCC =
16 V
5.00
-1.00
-20.0µ
100k
Frequency (Hz)
15.00
Standby
12.50
Output -40°C
10.00
Output 25°C
7.50
5.00
2.50
Vcc = 16V
Rl=10kΩ
Cl=20pF
G=1
Output 125°C
0.00
-10.0µ
0.0
10.0µ
Time (s)
20.0µ
30.0µ
-2.0µ
0.0
2.0µ
Time (s)
4.0µ
6.0µ
page 15/29
TSX920, TSX921, TSX922, TSX923
Application information
5
Application information
5.1
Operating voltages
The TSX92x operational amplifiers can operate from 4 V to 16 V. The parameters are fully specified at 4.5 V,
10 V, and 16 V power supplies. However, parameters are very stable in the full VCC range. Additionally, main
specifications are guaranteed in the extended temperature range from -40 to 125 °C.
5.2
Rail-to-rail input
The TSX92x series is designed with two complementary PMOS and NMOS input differential pairs. The device has
a rail-to-rail input and the input common mode range is extended from (VCC-) - 0.1 V to (VCC+) + 0.1 V. However,
the performance of this device is clearly optimized for the PMOS differential pairs (which means from (VCC-) - 0.1
V to (VCC+) - 2 V).
Beyond (VCC+) - 2 V, the operational amplifier is still functional but with downgraded performances (see
Figure 19). Performances are still suitable for a large number of applications requiring the rail-to-rail input feature.
The TSX92x operational amplifiers are designed to prevent phase reversal.
5.3
Input pin voltage range
The TSX92x operational amplifiers have internal ESD diode protections on the inputs. These diodes are
connected between the input and each supply rail to protect MOSFETs inputs from electrostatic discharges.
Thus, if the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and
excessive current could flow through them. To prevent any permanent damage, this current must be limited to 10
mA. This can be done by adding a resistor in series with the input pin (Figure 38). The resistor value has to be
calculated for a 10 mA current limitation on the input pins.
Figure 38. Limiting input current with a series resistor
TSX921
16 V
R
Vin
5.4
-
+
+
-
Vout
Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset variation related to offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1 .
Equation 1
∆V io
V ( T ) – V io ( 25 °C)
= ma x io
∆T
T – 25 °C
with T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a Cpk
(process capability index) greater than 2.
5.5
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
DS9502 - Rev 5
Voltage acceleration, by changing the applied voltage
page 16/29
TSX920, TSX921, TSX922, TSX923
Long term input offset voltage drift
•
Temperature acceleration, by changing the die temperature (below the maximum junction temperature
allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2.
Equation 2
A FV = e
β . ( VS – VU )
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3.
Equation 3
A FT = e
E
1
1
-----a- .
–
k
TU TS
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die undertemperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor (Equation 4).
Equation 4
A F = A FT × A FV
AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can
then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress
duration.
Equation 5
Months = A F × 1000 h × 12 months / ( 24 h × 365.25 days )
To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the
maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement
conditions (see Equation 6).
Equation 6
V CC = maxV op with V icm = V CC / 2
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the
ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation
7).
Equation 7
∆V io =
V io dr ift
( month s )
Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
DS9502 - Rev 5
page 17/29
TSX920, TSX921, TSX922, TSX923
Capacitive load
5.6
Capacitive load
Driving a large capacitive load can cause stability issues. Increasing the load capacitance produces gain peaking
in the frequency response, with overshooting and ringing in the step response. It is usually considered that with
a gain peaking higher than 2.3 dB the op amp might become unstable. Generally, the unity gain configuration is
the worst configuration for stability and the ability to drive large capacitive loads. Figure 39. Stability criteria with a
serial resistor shows the serial resistor (Riso) that must be added to the output, to make the system stable.
Figure 39. Stability criteria with a serial resistor
Serial Resistor (Ohm)
Vcc=16V, Vicm=8V, T=25°C, Rload = 10 kΩ
100 follower configuration
Stable
Unstable
10
0.01
0.1
1
10
Capacitive Load (nF)
100
Figure 40. Test configuration for Riso
+8 V
Riso
VIN
+
5.7
10 kΩ
Cload
-8 V
High-side current sensing
TSX92x rail to rail input devices can be used to measure a small differential voltage on a high side shunt resistor
and translate it into a ground referenced output voltage. The gain is fixed by external resistance.
Figure 41. High-side current sensing configuration
C1
load
Rg1
Rf1
I
In
Rshunt
Rg2
12 V
DS9502 - Rev 5
Ip
12 V
- +
+ -
VOUT
TSX921
Rf2
page 18/29
TSX920, TSX921, TSX922, TSX923
High-speed photodiode
Vout can be expressed as follows:
Equation 8
V ou t = R shun t × I 1 –
R g2
R g2 + R f2
1+
R g2 × R f2
R f1
R f1
R f1
+ Ip
– l n × R f1 – V io 1 +
× 1+
R g2 + R f2
R g1
R g1
R g1
Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 8 can be simplified as follows:
Equation 9
V out = R shunt × I
Rf
Rf
– V io 1 +
+ R f × I io
Rg
Rg
With the TSX92x operational amplifiers, the high side current measurement must be made by respecting the
common mode voltage of the amplifier: (VCC-) - 0.1 V to (VCC+) + 0.1 V. If the application requires a higher
common voltage please refer to the TSC high side current sensing family.
5.8
High-speed photodiode
The TSX92x series is an excellent choice for current to voltage (I-V) conversions. Due to the CMOS technology,
the input bias currents are extremely low. Moreover, the low noise and high unity-gain bandwidth of the TSX92x
operational amplifiers make them particularly suitable for high-speed photodiode preamplifier applications.
The photodiode is considered as a capacitive current source. The input capacitance, CIN, includes the parasitic
input Common mode capacitance, CCM (3 pF), and the input differential mode capacitance, CDIFF (8 pF). CIN acts
in parallel with the intrinsic capacitance of the photodiode, CD. At higher frequencies, the capacitors affect the
circuit response. The output capacitance of a current sensor has a strong effect on the stability of the op amp
feedback loop.
CF stabilizes the gain and limits the transimpedance bandwidth. To ensure good stability and to obtain good noise
performance, CF can be set as shown in Equation 10.
Equation 10
C IN + C D
C F > ---------------------------------------------- – C SMR
2 ⋅ π ⋅ R F ⋅ F GBP
where,
•
CIN = CCM + CDIFF = 11 pF
•
CDIFF is the differential input capacitance: 8 pF typical
•
CCM is the Common mode input capacitance: 3 pF typical
•
CD is the intrinsic capacitance of the photodiode
•
CSMR is the parasitic capacitance of the surface mount RF resistor: 0.2 pF typical
•
FGBP is the gain bandwidth product: 10 MHz at 16 V
RF fixes the gain as shown in Equation 11.
Equation 11
VOUT = RF x ID
Figure 42. High-speed photodiode
CF
RF
+VCC
Photodiode
I
D
CD
Cin
VOUT
+
-VCC
DS9502 - Rev 5
page 19/29
TSX920, TSX921, TSX922, TSX923
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
DS9502 - Rev 5
page 20/29
TSX920, TSX921, TSX922, TSX923
SOT23-5 package information
6.1
SOT23-5 package information
Figure 43. SOT23-5 package outline
Table 6. SOT23-5 mechanical data
Dimensions
Millimeters
Ref.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
0.90
1.20
1.45
0.035
0.047
0.057
A1
DS9502 - Rev 5
Inches
0.15
0.006
A2
0.90
1.05
1.30
0.035
0.041
0.051
B
0.35
0.40
0.50
0.014
0.016
0.020
C
0.09
0.15
0.20
0.004
0.006
0.008
D
2.80
2.90
3.00
0.110
0.114
0.118
D1
1.90
0.075
e
0.95
0.037
E
2.60
2.80
3.00
0.102
0.110
0.118
F
1.50
1.60
1.75
0.059
0.063
0.069
L
0.10
0.35
0.60
0.004
0.014
0.024
K
0 degrees
10 degrees
0 degrees
10 degrees
page 21/29
TSX920, TSX921, TSX922, TSX923
SOT23-6 package information
6.2
SOT23-6 package information
Figure 44. SOT23-6 package outline
Table 7. SOT23-6 mechanical data
Dimensions
Millimeters
Ref.
Min.
A
Typ.
0.90
A1
Max.
Min.
1.45
0.035
Typ.
Max.
0.057
0.10
0.004
A2
0.90
1.30
0.035
0.051
b
0.35
0.50
0.013
0.019
c
0.09
0.20
0.003
0.008
D
2.80
3.05
0.110
0.120
E
1.50
1.75
0.060
0.069
e
DS9502 - Rev 5
Inches
0.95
0.037
H
2.60
3.00
0.102
0.118
L
0.10
0.60
0.004
0.024
θ
0°
10 °
0°
10 °
page 22/29
TSX920, TSX921, TSX922, TSX923
MiniSO8 package information
6.3
MiniSO8 package information
Figure 45. MiniSO8 package outline
Table 8. MiniSO8 package mechanical data
Dimensions
Millimeters
Ref.
Min.
Typ.
A
Max.
Min.
Typ.
1.1
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.030
0.22
0.40
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.80
3.00
3.20
0.11
0.118
0.126
E
4.65
4.90
5.15
0.183
0.193
0.203
E1
2.80
3.00
3.10
0.11
0.118
0.122
e
L
0.85
0.65
0.40
0.60
0.0006
0.033
0.80
0.016
0.024
0.95
0.037
L2
0.25
0.010
ccc
0°
0.037
0.026
L1
k
DS9502 - Rev 5
Inches
8°
0.10
0°
0.031
8°
0.004
page 23/29
TSX920, TSX921, TSX922, TSX923
SO8 package information
6.4
SO8 package information
Figure 46. SO8 package outline
Table 9. SO8 package mechanical data
Dimensions
Millimeters
Ref.
Min.
Typ.
A
Max.
Min.
Typ.
1.75
0.25
Max.
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.010
D
4.80
4.90
5.00
0.189
0.193
0.197
E
5.80
6.00
6.20
0.228
0.236
0.244
E1
3.80
3.90
4.00
0.150
0.154
0.157
e
0.004
0.010
0.049
1.27
0.050
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
L1
k
ccc
DS9502 - Rev 5
Inches
1.04
0°
0.040
8°
0.10
0°
8°
0.004
page 24/29
TSX920, TSX921, TSX922, TSX923
DFN8 2x2 package information
6.5
DFN8 2x2 package information
Figure 47. DFN8 2x2 package outline
D
A
B
0.10 C 2x
E
PIN 1 INDEX AREA
0.10 C 2x
TOP VIEW
A
A1
0.10 C
C
SEATING
PLANE
SIDE VIEW
0.08 C
e
b (8 plcs)
PIN 1 INDEX AREA
1
0.10
4
C A B
L
Pin#1 ID
5
8
BOTTOM VIEW
Table 10. DFN8 2x2 mechanical data
Dimensions
Millimeters
Ref.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.15
0.20
0.25
0.006
0.008
0.010
D
2.00
0.079
E
2.00
0.079
e
0.50
0.020
L
DS9502 - Rev 5
Inches
0.045
0.55
0.65
0.018
0.022
0.026
page 25/29
TSX920, TSX921, TSX922, TSX923
MiniSO10 package information
6.6
MiniSO10 package information
aaa
Figure 48. MiniSO10 package outline
Table 11. MiniSO10 mechanical data
Dimensions
Millimeters
Ref.
Min.
Typ.
A
Max.
Min.
Typ.
1.10
Max.
0.043
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.78
0.86
0.94
0.031
0.034
0.037
b
0.15
0.23
0.30
0.006
0.009
0.012
c
0.13
0.18
0.23
0.005
0.007
0.009
D
2.90
3.00
3.10
0.114
0.118
0.122
E
4.75
4.90
5.05
0.187
0.193
0.199
E1
2.90
3.00
3.10
0.114
0.118
0.122
e
L
0.50
0.40
L1
k
aaa
DS9502 - Rev 5
Inches
0.55
0.020
0.70
0.016
0.95
0°
3°
0.022
0.028
0.037
6°
0.10
0°
3°
6°
0.004
page 26/29
TSX920, TSX921, TSX922, TSX923
Ordering information
7
Ordering information
Table 12. Order codes
Order code
Temperature range
TSX920ILT
TSX922IDT
K305
TSX922I
SO8
-40 °C to 125 °C
MiniSO8
Marking
K304
SΟΤ23-5
TSX921IYLT (1)
TSX922IST
Packing
SOT23-6
TSX921ILT
TSX922IYDT (1)
Package
Tape and reel
SX922IY
K305
TSX922IQ2T
DFN8 2x2
K26
TSX922IYST (1)
MiniSO8 (automotive grade)
K312
TSX922IYDT (1)
SO8 (automotive grade)
SX922IY
TSX923IST
MiniSO10
K305
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 &
Q 002 or equivalent.
DS9502 - Rev 5
page 27/29
TSX920, TSX921, TSX922, TSX923
Revision history
Table 13. Document revision history
Date
Revision
12-Apr-2013
1
Changes
Initial release
Added TSX920,TSX922, TSX923 devices.
Added packages for TSX920,TSX922, and TSX923.
27-Jun-2013
2
Added shutdown characteristics in Table 4, Table 5, and Table 6.
Added Figure 35, Figure 36, and Figure 37.
Updated Table 13 for new order codes.
Added long-term input offset voltage drift parameter in Table 4, Table 5, and
Table 6.
10-Dec-2013
3
Added Section 5.4: Input offset voltage drift over temperature in Section 5:
Application information.
Added Section 5.5: Long-term input offset voltage drift section in Section 5:
Application information.
Updated document layout
Table 4, Table 5, and Table 6: updated Vio and DVio/DT parameters
14-Jan-2016
4
Table 7: updated inches dimension "B" (typ) and "L" (typ and max) to align
with rounded-off values of POA.
Table 10: updated minimum mm dimensions for "k"
Table 13: "Order codes": added order codes TSX922IYST and TSX922IYDT.
07-Oct-2022
DS9502 - Rev 5
5
Updated b and c dimensions in Table 11.
page 28/29
TSX920, TSX921, TSX922, TSX923
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DS9502 - Rev 5
page 29/29
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