UPSD33xx
Turbo series
fast 8032 MCU with programmable logic
Features
■
■
■
■
Fast 8-bit Turbo 8032 MCU, 40 MHz
– Advanced core, 4-clocks per instruction
– 10 MIPs, peak performance at 40 MHz
(5 V)
– JTAG debug and in-system programming
– Branch cache and6 instruction prefetch
queue
– Dual XDATA pointers with auto increment
and decrement
– Compatible with 3rd party 8051 tools
LQFP52 (T) 52-lead, thin, quad, Flat
LQFP80 (U) 80-lead, thin, quad, flat
Dual Flash memories with memory
management
– Place either memory into 8032 program
address space or data address space
– Read-while-write operation for inapplication programming and EEPROM
emulation
– Single voltage program and erase
– 100K guaranteed erase cycles, 15-year
retention
Clock, reset, and supply management
– Flexible 8-level CPU clock divider register
– Normal, Idle, and Power-down modes
– Power-on and low voltage reset supervisor
– Programmable watchdog timer
Programmable logic, general purpose
– 16 macrocells
– Create shifters, state machines, chipselects, glue-logic to keypads, panels,
LCDs, others
Table 1.
■
Packages are ECOPACK®
■
Communication interfaces
– I2C master/slave controller, 833 kHz
– SPI master controller, 10 MHz
– Two UARTs with independent baud rate
– IrDA protocol support up to 115 Kbaud
– Up to 46 I/O, 5 V tolerant on 3.3 V
UPSD33xxV
■
A/D converter
– Eight channels, 10-bit resolution, 6 µs
■
Timers and interrupts
– Three 8032 standard 16-bit timers
– Programmable counter array (PCA), six 16bit modules for PWM/CAPCOM/timers
– 8/10/16-bit PWM operation
– 11 interrupt sources with two external
interrupt pins
■
Operating voltage source (±10%)
– 5 V devices use both 5.0 V and 3.3 V
– 3.3 V devices use only 3.3 V source
Device summary
Reference
Part number
UPSD3312D, UPSD3333D, UPSD3334D, UPSD3354D
UPSD33xx
UPSD3312DV, UPSD3333DV, UPSD3334DV, UPSD3354DV
May 2009
Doc ID 9685 Rev 7
1/272
www.st.com
1
Contents
UPSD33xx
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
UPSD33xx hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1
4.2
5
Internal memory (MCU, standard 8032 memory: DATA, IDATA, SFR) . . . 29
4.1.1
DATA memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.2
IDATA memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.3
SFR memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
External memory (PSD module: program memory, data memory) . . . . . 29
4.2.1
Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.2
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.3
Memory placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8032 MCU core performance enhancements . . . . . . . . . . . . . . . . . . . . 32
5.1
Pre-Fetch Queue (PFQ) and Branch Cache (BC) . . . . . . . . . . . . . . . . . . 33
5.2
PFQ example, multi-cycle instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3
Aggregate performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
MCU module description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
8032 MCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/272
7.1
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2
Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4
Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5
B register (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.6
General purpose registers (R0 - R7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7
Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7.1
Carry flag (CY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7.2
Auxiliary Carry flag (AC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7.3
General purpose flag (F0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 9685 Rev 7
UPSD33xx
Contents
7.7.4
Register bank select flags (RS1, RS0) . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7.5
Overflow flag (OV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.7.6
Parity flag (P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8
Special function registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9
8032 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1
Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2
Direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.3
Register indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.4
Immediate addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.5
External direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.6
External indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.7
Indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.8
Relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.9
Absolute addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.10
Long addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.11
Bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10
UPSD33xx instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11
Dual data pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.1
Data Pointer Control register, DPTC (85h) . . . . . . . . . . . . . . . . . . . . . . . . 56
11.2
Data Pointer Mode register, DPTM (86h) . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.2.1
Firmware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12
Debug unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
13
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.1
Individual interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.1.1
External interrupts Int0 and Int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.1.2
Timer 0 and 1 overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.1.3
Timer 2 overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.1.4
UART0 and UART1 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.1.5
SPI interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.1.6
I2C interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Doc ID 9685 Rev 7
3/272
Contents
14
UPSD33xx
13.1.7
ADC interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13.1.8
PCA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MCU clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.1
MCU_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.2
PERIPH_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.2.1
15
JTAG interface clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
15.1
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
15.2
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
15.3
Reduced frequency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16
Oscillator and external components . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
17
I/O ports of MCU module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
17.1
18
19
MCU port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
17.1.1
GPIO function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
17.1.2
GPIO output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
17.1.3
GPIO input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
17.1.4
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
18.1
Bus read cycles (PSEN or RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
18.2
Bus write cycles (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
18.3
Controlling the PFQ and BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Supervisory functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
19.1
External reset input pin, RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
19.2
Low VCC voltage detect, LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
19.3
Power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
19.4
JTAG debug Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
19.5
Watchdog timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
19.5.1
20
4/272
Firmware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Standard 8032 timer/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Doc ID 9685 Rev 7
UPSD33xx
Contents
20.1
Standard timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
20.2
Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
20.3
SFR, TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
20.4
SFR, TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
20.5
Timer 0 and Timer 1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
20.6
21
20.5.2
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
20.5.3
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
20.5.4
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.6.1
Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.6.2
Auto-reload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.6.3
Baud rate generator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
UART operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21.1.1
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21.1.2
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21.1.3
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
21.1.4
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
21.1.5
Multiprocessor communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
21.2
Serial port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
21.3
UART baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
21.3.1
Using Timer 1 to generate baud rates . . . . . . . . . . . . . . . . . . . . . . . . . 110
21.3.2
Using Timer/Counter 2 to generate baud rates . . . . . . . . . . . . . . . . . . 111
21.4
More about UART mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
21.5
More about UART mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
21.6
More about UART modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
IrDA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
22.1
23
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Serial UART interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21.1
22
20.5.1
Pulse width selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
23.1
I2C interface main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
23.2
Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
23.3
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Doc ID 9685 Rev 7
5/272
Contents
UPSD33xx
23.4
Bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
23.5
Clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
23.5.1
Clock synchronization during arbitration . . . . . . . . . . . . . . . . . . . . . . . 125
23.5.2
Clock sync during handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
23.6
General call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
23.7
Serial I/O engine (SIOE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
23.8
I2C Interface Control register (S1CON) . . . . . . . . . . . . . . . . . . . . . . . . . 128
23.9
I2C Interface Status register (S1STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
23.9.1
Interrupt conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
23.10 I2C Data Shift register (S1DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
23.10.1 Bus Wait condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
23.11 I2C Address register (S1ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
23.12 I2C START sample setting (S1SETUP) . . . . . . . . . . . . . . . . . . . . . . . . . 132
23.13 I2C operating sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
23.13.1 Interrupt Service Routine (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
24
25
Synchronous peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . 141
24.1
SPI bus features and communication flow . . . . . . . . . . . . . . . . . . . . . . . 142
24.2
Full-duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
24.3
Bus-level activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
24.4
SPI SFR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
24.5
SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
24.6
Dynamic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
25.1
26
6/272
Port 1 ADC channel selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Programmable counter array (PCA) with PWM . . . . . . . . . . . . . . . . . 153
26.1
PCA block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
26.2
PCA clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
26.3
Operation of TCM modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
26.4
Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
26.5
Timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
26.6
Toggle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
26.7
PWM mode - (x8), fixed frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Doc ID 9685 Rev 7
UPSD33xx
Contents
26.8
PWM mode - (x8), programmable frequency . . . . . . . . . . . . . . . . . . . . . 157
26.9
PWM mode - fixed frequency, 16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
26.10 PWM mode - fixed frequency, 10-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
26.11 Writing to capture/compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
26.12 Control register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
26.13 TCM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
27
PSD module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
27.1
PSD module functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
27.1.1
8032 address/data/control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
27.1.2
Dual Flash memories and IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
27.1.3
Main Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
27.1.4
Secondary Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
27.1.5
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
27.1.6
Runtime Control registers, CSIOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
27.1.7
Memory page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
27.1.8
Programmable logic (PLDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
27.1.9
PLD #1, Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
27.1.10 PLD #2, General PLD (GPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
27.1.11 OMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
27.1.12 OMC allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
27.1.13 IMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
27.1.14 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
27.1.15 JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
27.1.16 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
27.1.17 Security and NVM sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . 170
27.2
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
27.2.1
8032 program address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
27.2.2
8032 data address space (XDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
27.2.3
Specifying the memory map with PSDsoft Express . . . . . . . . . . . . . . . 172
27.2.4
EEPROM emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
27.2.5
Alternative mapping schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
27.2.6
Memory sector select rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
27.2.7
The VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
27.3
Runtime control register definitions (CSIOP) . . . . . . . . . . . . . . . . . . . . . 180
27.4
PSD module detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Doc ID 9685 Rev 7
7/272
Contents
UPSD33xx
27.4.1
Flash memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
27.4.2
Flash memory instruction sequences . . . . . . . . . . . . . . . . . . . . . . . . . 183
27.4.3
Reading Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
27.4.4
Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
27.4.5
Reading the erase/program status bits . . . . . . . . . . . . . . . . . . . . . . . . 185
27.4.6
Data polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
27.4.7
Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
27.4.8
Erase timeout flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
27.4.9
Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
27.4.10 Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
27.4.11 Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
27.4.12 Ready/Busy (PC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
27.4.13 Bypassed Unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
27.4.14 Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
27.4.15 Flash bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
27.4.16 Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
27.4.17 Suspend sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
27.4.18 Resume sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
27.4.19 Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
27.4.20 Reset signal applied to Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 192
27.4.21 Flash memory sector protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
27.4.22 Flash memory protection during power-up . . . . . . . . . . . . . . . . . . . . . 192
27.4.23 PSD module security bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
27.4.24 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
27.4.25 Turbo Bit and PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
27.4.26 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
27.4.27 General PLD (GPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
27.4.28 Output macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
27.4.29 OMC allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
27.4.30 Product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
27.4.31 Loading and reading OMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
27.4.32 OMC Mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
27.4.33 Input Macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
27.4.34 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
27.4.35 General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
27.4.36 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
27.4.37 MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
8/272
Doc ID 9685 Rev 7
UPSD33xx
Contents
27.4.38 PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
27.4.39 Latched address output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
27.4.40 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
27.4.41 JTAG ISP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
27.4.42 Other port capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
27.4.43 Port pin drive options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
27.4.44 Drive select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
27.4.45 Enable Out registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
27.4.46 Individual port structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
27.4.47 Port A structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
27.4.48 Port B structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
27.4.49 Port C structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
27.4.50 Port D structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
27.4.51 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
27.4.52 Automatic Power-down (APD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
27.4.53 Forced Power-down (FDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
27.4.54 Chip Select Input (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
27.4.55 PLD non-turbo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
27.4.56 PLD current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
27.4.57 Turbo mode current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
27.4.58 Non-turbo mode current consumption . . . . . . . . . . . . . . . . . . . . . . . . . 231
27.4.59 PLD blocking bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
27.4.60 Blocking 8032 bus control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
27.4.61 Blocking common clock, CLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
27.5
PSD module reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
27.5.1
JTAG ISP and JTAG debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
27.5.2
JTAG chaining inside the package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
27.5.3
In-system programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
27.5.4
4-pin JTAG ISP (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
27.5.5
6-pin JTAG ISP (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
27.5.6
Recommended JTAG connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
27.5.7
Chaining UPSD33xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
27.5.8
Debugging the 8032 MCU module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
27.5.9
JTAG security setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
27.5.10 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
28
AC/DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Doc ID 9685 Rev 7
9/272
Contents
UPSD33xx
29
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
30
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
31
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
32
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
33
Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
34
10/272
33.1
PORT 1 not 5 V I/O tolerant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
33.2
9th received data bit corrupted in UART modes 2 and 3 . . . . . . . . . . . . 270
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Doc ID 9685 Rev 7
UPSD33xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Port type and voltage source combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Register bank select addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SFR memory map with direct address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Arithmetic instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Logical instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Data transfer instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Boolean variable manipulation instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Program branching instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Miscellaneous instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Notes on instruction set and addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DPTC: Data Pointer Control register (SFR 85h, reset value 00h) . . . . . . . . . . . . . . . . . . . 56
DPTC register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DPTM: Data Pointer Mode register (SFR 86h, reset value 00h). . . . . . . . . . . . . . . . . . . . . 57
DPTM register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8051 assembly code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
IE: Interrupt Enable register (SFR A8h, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
IE register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
IEA: Interrupt Enable Addition register (SFR A7h, reset value 00h) . . . . . . . . . . . . . . . . . . 65
IEA register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
IP: Interrupt Priority register (SFR B8h, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . 66
IP register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h) . . . . . . . . . . . . . . . . . . 66
IPA register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
CCON0: Clock Control register (SFR F9h, reset value 10h) . . . . . . . . . . . . . . . . . . . . . . . 69
CCON0 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
MCU module port and peripheral status during reduced power modes . . . . . . . . . . . . . . . 72
State of 8032 MCU bus Signals during Power-down and Idle modes . . . . . . . . . . . . . . . . 72
PCON: Power Control register (SFR 87h, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . . 72
PCON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
P1: I/O Port 1 register (SFR 90h, reset value FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
P1 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
P3: I/O Port 3 register (SFR B0h, reset value FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
P3 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
P4: I/O Port 4 register (SFR C0h, reset value FFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
P4 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
P3SFS: Port 3 Special Function Select register (SFR 91h, reset value 00h) . . . . . . . . . . . 83
P3SFS register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
P1SFS0: Port 1 Special Function Select 0 register (SFR 8Eh, reset value 00h) . . . . . . . . 83
P1SFS1: Port 1 Special Function Select 1 register (SFR 8Fh, reset value 00h) . . . . . . . . 83
P1SFS0 and P1SFS1 details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
P4SFS0: Port 4 Special Function Select 0 register (SFR 92h, reset value 00h) . . . . . . . . 84
P4SFS1: Port 4 Special Function Select 1 register (SFR 93h, reset value 00h) . . . . . . . . 84
P4SFS0 and P4SFS1 details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
BUSCON: Bus Control register (SFR 9Dh, reset value EBh) . . . . . . . . . . . . . . . . . . . . . . . 87
BUSCON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Doc ID 9685 Rev 7
11/272
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
12/272
UPSD33xx
Number of MCU_CLK periods required to optimize bus transfer rate . . . . . . . . . . . . . . . . 88
WDKEY: Watchdog Timer Key register (SFR AEh, reset value 55h) . . . . . . . . . . . . . . . . . 92
WDKEY register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
WDRST: Watchdog Timer Reset Counter register (SFR A6h, reset value 00h). . . . . . . . . 92
WDRST register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
TCON: Timer Control register (SFR 88h, reset value 00h). . . . . . . . . . . . . . . . . . . . . . . . . 95
TCON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TMOD: Timer Mode register (SFR 89h, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TMOD register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
T2CON: Timer 2 Control register (SFR C8h, reset value 00h) . . . . . . . . . . . . . . . . . . . . . 100
T2CON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Timer/counter 2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Commonly used baud rates generated from Timer 2 (T2CON = 34h) . . . . . . . . . . . . . . . 103
UART operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SCON0: Serial Port UART0 Control register (SFR 98h, reset value 00h) . . . . . . . . . . . . 108
SCON0 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SCON1: Serial Port UART1 Control register (SFR D8h, reset value 00h) . . . . . . . . . . . . 109
SCON1 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Commonly used baud rates generated from Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
IRDACON register (SFR CEh, Reset Value 0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
RDACON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Recommended CDIV[4:0] values to generate SIRClk
(default CDIV[4:0] = 0Fh, 15 decimal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Serial Control register S1CON (SFR DCh, Reset Value 00h) . . . . . . . . . . . . . . . . . . . . . 128
S1CON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Selection of the SCL frequency in Master mode based on fOSC examples . . . . . . . . . . . 129
S1STA: I2C Interface Status register (SFR DDh, reset value 00h). . . . . . . . . . . . . . . . . . 130
S1STA register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
S1DAT: I2C Data Shift register (SFR DEh, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . 131
S1DAT register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
S1ADR: I2C Address register (SFR DFh, reset value 00h) . . . . . . . . . . . . . . . . . . . . . . . 131
S1ADR register bit definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
S1SETUP: I2C START Condition Sample Setup register (SFR DBh, reset value 00h) . . 132
S1SETUP register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Number of I2C bus samples taken after 1-to-0 transition on SDA (START condition) . . . 133
Start condition hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
S1SETUP examples for various I2C bus speeds and oscillator frequencies . . . . . . . . . . 134
SPICON0: Control register 0 (SFR D6h, Reset Value 00h) . . . . . . . . . . . . . . . . . . . . . . . 147
SPICON0 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SPICON1: SPI Interface Control register 1 (SFR D7h, Reset Value 00h) . . . . . . . . . . . . 148
SPICON1 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SPICLKD: SPI Prescaler (Clock Divider) register (SFR D2h, Reset Value 04h) . . . . . . . 148
SPICLKD register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SPISTAT: SPI Interface Status register (SFR D3h, Reset Value 02h) . . . . . . . . . . . . . . . 149
SPISTAT register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
ACON register (SFR 97h, Reset Value 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
ACON register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
ADCPS register bit definition (SFR 94h, Reset Value 00h) . . . . . . . . . . . . . . . . . . . . . . . 152
ADAT0 register (SFR 95H, Reset Value 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
ADAT1 register (SFR 96h, Reset Value 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
PCA0 and PCA1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
CCON2 register (SFR 0FBh, Reset Value 10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Doc ID 9685 Rev 7
UPSD33xx
List of tables
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
CCON2 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
CCON3 register (SFR 0FCh, Reset Value 10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
CCON3 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
PCA0 Control register PCACON0 (SFR 0A4h, Reset Value 00h) . . . . . . . . . . . . . . . . . . 159
PCACON0 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
PCA1 Control register PCACON1 (SFR 0BCh, Reset Value 00h) . . . . . . . . . . . . . . . . . . 160
PCACON1 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
PCA Status register PCASTA (SFR 0A5h, Reset Value 00h) . . . . . . . . . . . . . . . . . . . . . 161
PCASTA register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
TCMMODE0 - TCMMODE5 (6 registers, Reset Value 00h). . . . . . . . . . . . . . . . . . . . . . . 162
TCMMODEx register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
TCMMODE register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
UPSD33xx memory configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
General I/O pins on PSD module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
HDL statement example generated from PSDsoft for memory map. . . . . . . . . . . . . . . . . 172
VM register (address = csiop + offset E2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
CSIOP registers and their Offsets (in hexadecimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Flash memory instruction sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Flash Memory Status bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Main Flash Memory Protection register definition (address = csiop + offset C0h) . . . . . . 193
Secondary Flash Memory Protection/Security register Definition (csiop+offset C2h) . . . 193
DPLD and GPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
OMC port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Output Macrocell MCELLAB (address = csiop + offset 20h) . . . . . . . . . . . . . . . . . . . . . . 204
Output Macrocell MCELLAC (address = csiop + offset 21h) . . . . . . . . . . . . . . . . . . . . . . 204
Output Macrocell MCELLAB Mask register (address = csiop + offset 22h) . . . . . . . . . . . 204
Output Macrocell MCELLBC Mask register (address = csiop + offset 23h) . . . . . . . . . . . 204
Input Macrocell Port A (address = csiop + offset 0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Input Macrocell Port B (address = csiop + offset 0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Input Macrocell Port C (address = csiop + offset 18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Port configuration setting requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
MCU I/O Mode Port A Data In register (address = csiop + offset 00h). . . . . . . . . . . . . . . 210
MCU I/O Mode Port B Data In register (address = csiop + offset 01h). . . . . . . . . . . . . . . 210
MCU I/O Mode Port C Data In register (address = csiop + offset 10h). . . . . . . . . . . . . . . 210
MCU I/O Mode Port D Data Inregister (address = csiop + offset 11h) . . . . . . . . . . . . . . . 210
MCU I/O Mode Port A Data Out register (address =csiop+offset 04h) . . . . . . . . . . . . . . . 210
MCU I/O Mode Port B Data Out register (address = csiop + offset 05h) . . . . . . . . . . . . . 210
MCU I/O Mode Port C Data Out register (address = csiop + offset 12h) . . . . . . . . . . . . . 211
MCU I/O Mode Port D Data Out register (address = csiop + offset 13h) . . . . . . . . . . . . . 211
MCU I/O Mode Port A Direction register (address=csiop+offset 06h) . . . . . . . . . . . . . . . 211
MCU I/O Mode Port B Direction Inregister (address=csiop+offset 07h) . . . . . . . . . . . . . . 211
MCU I/O Mode Port C Direction register (address = csiop + offset 14h) . . . . . . . . . . . . . 211
MCU I/O Mode Port DDirection register (address = csiop + offset 15h) . . . . . . . . . . . . . . 211
Latched Address output, Port A Control register (address = csiop+offset 02h) . . . . . . . . 214
Latched Address output, Port B Control register (address = csiop+offset 03h) . . . . . . . . 215
Port A Pin Drive Select register (address = csiop + offset 08h) . . . . . . . . . . . . . . . . . . . . 217
Port B Pin Drive Select register (address = csiop + offset 09h) . . . . . . . . . . . . . . . . . . . . 217
Port C Pin Drive Select register (address = csiop + offset 16h) . . . . . . . . . . . . . . . . . . . . 217
Port D Pin Drive Select register (address = csiop + offset 17h) . . . . . . . . . . . . . . . . . . . . 217
Port A Enable Out register (address = csiop + offset 0Ch). . . . . . . . . . . . . . . . . . . . . . . . 217
Port B Enable Out register (address = csiop + offset 0Dh). . . . . . . . . . . . . . . . . . . . . . . . 218
Doc ID 9685 Rev 7
13/272
List of tables
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
14/272
UPSD33xx
Port C Enable Out register (address = csiop + offset 1Ah). . . . . . . . . . . . . . . . . . . . . . . . 218
Port D Enable Out register (address = csiop + offset 1Bh). . . . . . . . . . . . . . . . . . . . . . . . 218
Power Management Mode register PMMR0 (address = csiop + offset B0h) . . . . . . . . . . 225
Power Management Mode register PMMR2 (address = csiop + offset B4h) . . . . . . . . . . 226
Power Management Mode register PMMR3 (address = csiop + offset C7h) . . . . . . . . . . 226
Forced Power-down example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Function status during Power-up Reset, Warm Reset, Power-down mode . . . . . . . . . . . 233
PSD module example, typ. power calculation at VCC = 5.0 V (Turbo mode Off) . . . . . . . 243
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Operating conditions (5 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Operating conditions (3.3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
AC signal letters for timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
AC signal behavior symbols for timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Major parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Preliminary MCU module DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
PSD module DC characteristics (with 5 V VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
PSD module DC characteristics (with 3.3 V VDD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
External PSEN or READ cycle AC Characteristics (3 V or 5 V device) . . . . . . . . . . . . . . 252
n, m, and x, y values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
External WRITE cycle AC characteristics (3 V or 5 V device) . . . . . . . . . . . . . . . . . . . . . 253
External clock drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
A/D analog specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
CPLD combinatorial timing (5 V PSD module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
CPLD combinatorial timing (3 V PSD module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
CPLD macrocell synchronous Clock mode timing (5 V PSD module) . . . . . . . . . . . . . . . 256
CPLD macrocell synchronous Clock mode timing (3 V PSD module) . . . . . . . . . . . . . . . 257
CPLD macrocell asynchronous Clock mode timing (5 V PSD module) . . . . . . . . . . . . . . 258
CPLD macrocell asynchronous Clock mode timing (3timeV PSD module) . . . . . . . . . . . 258
Input macrocell timing (5 V PSD module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Input macrocell timing (3V PSD module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Program, WRITE and Erase times (5 V, 3 V PSD modules) . . . . . . . . . . . . . . . . . . . . . . 260
Port A peripheral data mode READ timing (5 V PSD module) . . . . . . . . . . . . . . . . . . . . . 261
Port A peripheral data mode READ Timing (3 V PSD module) . . . . . . . . . . . . . . . . . . . . 261
Port A peripheral data mode WRITE Timing (5 V PSD module). . . . . . . . . . . . . . . . . . . . 262
Port A peripheral data mode WRITE Timing (3 V PSD module). . . . . . . . . . . . . . . . . . . . 262
Supervisor Reset and LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
ISC timing (5 V PSD module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
ISC timing (3 V PSD module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
I/O pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
LQFP52 – 52-lead plastic thin, quad, flat package mechanical data . . . . . . . . . . . . . . . . 267
LQFP80 – 80-lead plastic thin, quad, flat package mechanical data . . . . . . . . . . . . . . . . 268
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Doc ID 9685 Rev 7
UPSD33xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
LQFP52 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LQFP80 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
UPSD33xx functional modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
UPSD33xx memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Comparison of UPSD33xx with standard 8032 performance . . . . . . . . . . . . . . . . . . . . . . . 32
Instruction pre-fetch queue and branch cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PFQ operation on multi-cycle instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
UPSD33xx multi-cycle instructions compared to standard 8032 . . . . . . . . . . . . . . . . . . . . 35
8032 MCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Program Status Word (PSW) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Enabling and polling Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Clock generation logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Oscillator and clock connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MCU module port pin function routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
MCU I/O cell block diagram for Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
MCU I/O cell block diagram for Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
MCU I/O cell block diagram for Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Supervisor Reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Watchdog counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Timer/Counter Mode 0: 13-bit counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Timer/Counter Mode 2: 8-bit Auto-reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Timer/Counter mode 3: Two 8-bit counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Timer 2 in Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Timer 2 in Auto-Reload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Timer 2 in baud rate generator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART mode 0, block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
UART mode 0, timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
UART mode 1, block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART mode 1, timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART mode 2, block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
UART mode 2, timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
UART mode 3, block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
UART mode 3, timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
IrDA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Pulse shaping by the IrDA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Typical I2C bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Data transfer on an I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
I2C interface SIOE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
SPI device connection examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SPI full-duplex data exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SPI Receive operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SPI Transmit operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SPI Interface, Master mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
10-Bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
PCA0 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Timer mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
PWM mode - (x8), fixed frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Doc ID 9685 Rev 7
15/272
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
Figure 100.
16/272
UPSD33xx
PWM mode - (x8) programmable frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
PSD module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Memory Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Typical system memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
PSDsoft Express memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Mapping: split second Flash in half. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Mapping: all Flash in code space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Mapping: small code / big data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
PSD module memory priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
VM register control of memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
VM register example corresponding to memory map example of Figure 32 . . . . . . . . . . 180
Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Data Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
DPLD and GPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
DPLD logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
GPLD: one OMC, one IMC, and one I/O Port (typical pin, Port A, B, or C) . . . . . . . . . . . 199
Detail of a Single OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
OMC allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Detail of a single IMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Detail of a single I/O port (typical of Ports A, B, C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Simple PLD logic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Pin declarations in PSDsoft Express for simple PLD example . . . . . . . . . . . . . . . . . . . . . 213
Using the Design Assistant in PSDsoft Express for simple PLD example . . . . . . . . . . . . 214
Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Port A structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Port B structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Port C structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Port D structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Automatic Power-down (APD) unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Power-down mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
JTAG chain in UPSD33xx package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Recommended 4-pin JTAG connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Recommended 6-pin JTAG connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Recommended JTAG connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Example of chaining UPSD33xx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
PLD ICC /frequency consumption (5 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
PLD ICC /frequency consumption (3 V range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Switching waveforms – key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
External PSEN/READ cycle (80-pin device only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
External WRITE cycle (80-pin device only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Input to output disable / enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Synchronous Clock mode timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Asynchronous RESET / Preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Asynchronous Clock mode timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Peripheral I/O READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Peripheral I/O WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
MCU module AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
PSD module AC float I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
External clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
PSD module AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Doc ID 9685 Rev 7
UPSD33xx
List of figures
Figure 101. PSD module AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 102. LQFP52 – 52-lead plastic thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 103. LQFP80 – 80-lead plastic thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . . . . 268
Doc ID 9685 Rev 7
17/272
Description
1
UPSD33xx
Description
The Turbo UPSD33xx series combines a powerful 8051-based microcontroller with a flexible
memory structure, programmable logic, and a rich peripheral mix to form an ideal
embedded controller. At its core is a fast 4-cycle 8032 MCU with a 6-byte instruction
prefetch queue (PFQ) and a 4-entry fully associative branching cache (BC) to maximize
MCU performance, enabling loops of code in smaller localities to execute extremely fast.
Code development is easily managed without a hardware in-circuit emulator by using the
serial JTAG debug interface. JTAG is also used for in-system programming (ISP) in as little
as 10 seconds, perfect for manufacturing and lab development. The 8032 core is coupled to
programmable system device (PSD) architecture to optimize the 8032 memory structure,
offering two independent banks of Flash memory that can be placed at virtually any address
within 8032 program or data address space, and easily paged beyond 64 Kbytes using onchip programmable decode logic. Dual Flash memory banks provide a robust solution for
remote product updates in the field through in-application programming (IAP). Dual Flash
banks also support EEPROM emulation, eliminating the need for external EEPROM chips.
General purpose programmable logic (PLD) is included to build an endless variety of gluelogic, saving external logic devices. The PLD is configured using the software development
tool, PSDsoft™ Express, available from the web at www.st.com, at no charge. The
UPSD33xx also includes supervisor functions such as a programmable watchdog timer and
low-voltage reset.
18/272
Doc ID 9685 Rev 7
UPSD33xx
Figure 1.
Description
Block diagram
UPSD33xx
(3) 16-bit
Timer/
Counters
(2)
External
Interrupts
P3.0:7
Turbo
8032
Core
PFQ
&
BC
Programmable
Decode and
Page Logic
I2C
1st Flash Memory:
64K, 128K,
or 256K Bytes
2nd Flash Memory:
16K or 32K Bytes
SRAM:
2K, 8K, or 32K Bytes
UART0
P1.0:7
(8) GPIO, Port 1
(8) 10-bit ADC
Optional IrDA
Encoder/Decoder
P4.0:7
SYSTEM BUS
(8) GPIO, Port 3
General
Purpose
Programmable
Logic,
16 Macrocells
(8) GPIO, Port A
(80-pin only)
PA0:7
(8) GPIO, Port B
PB0:7
(2) GPIO, Port D
PD1:2
(4) GPIO, Port C
PC0:7
UART1
JTAG ICE and ISP
SPI
8032 Address/Data/Control Bus
(80-pin device only)
16-bit PCA
(6) PWM, CAPCOM, TIMER
Supervisor:
Watchdog and Low-Voltage Reset
(8) GPIO, Port 4
VCC, VDD, GND, Reset, Crystal In
MCU
Bus
Dedicated
Pins
AI08875b
Doc ID 9685 Rev 7
19/272
40 P1.6/SPITXD(2)/ADC6
41 P1.7/SPISEL(2)/ADC7
42 PB7
43 PB6
44 RESET_IN
45 GND
46 PB5
47 AVCC/AVREF(3)
LQFP52 connections
50 PB2
Figure 2.
51 PB1
Pin descriptions
52 PB0
2
48 PB4
UPSD33xx
49 PB3
Pin descriptions
PD1/CLKIN 1
39 P1.5/SPIRXD(2)/ADC5
PC7 2
38 P1.4/SPICLK(2)/ADC4
JTAG TDO 3
37 P1.3/TXD1(IrDA)(2)/ADC3
JTAG TDI 4
36 P1.2/RXD1(IrDA)(2)/ADC2
35 P1.1/T2X(2)/ADC1
DEBUG 5
34 P1.0/T2(2)/ADC0
3.3V V CC 6
33 V DD(1)
PC4/TERR 7
VDD(1)
8
32 XTAL2
GND 9
31 XTAL1
PC3/TSTAT 10
30 P3.7/SCL
11
29 P3.6/SDA
PC2
EXTINT1/TG1/P3.3 26
EXTINT0/TG0/P3.2 25
TXD0/P3.1 24
RXD0/P3.0 23
T2(2)/TCM0/P4.0 22
20
T2X(2)/TCM1/P4.1 21
GND 19
RXD1(IrDA)(2)/TCM2/P4.2
18
TXD1(IrDA)(2)/PCACLK0/P4.3
SPICLK(2)/TCM3/P4.4 17
SPIRXD(2)/TCM4/P4.5 16
27 P3.4/C0
SPITXD(2)/TCM5/P4.6 15
28 P3.5/C1
JTAG TMS 13
SPISEL(2)/PCACLK1/P4.7 14
JTAG TCK 12
AI07822b
1. For 5 V applications, VDD must be connected to a 5.0 V source. For 3.3 V applications, VDD must be connected to a 3.3 V
source.
2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1.
3. AVREF and 3.3 V AVCC are shared in the 52-pin package only. ADC channels must use AVCC as AVREF for the 52-pin
package.
20/272
Doc ID 9685 Rev 7
UPSD33xx
61 P1.6/SPITXD(2)/ADC6
62 WR
63 PSEN
64 P1.7/SPISEL(2)/ADC7
65 RD
66 PB7
67 PB6
68 RESET_IN
69 GND
70 AVREF
71 PB5
72 AVCC
73 PB4
74 PB3
75 P3.0/RXD0
76 PB2
77 P3.1/TXD0
78 PB1
79 P3.2/EXINT0/TG0
LQFP80 connections
80 PB0
Figure 3.
Pin descriptions
PD2/CSI 1
60 P1.5/SPIRXD(2)/ADC5
P3.3/TG1/EXINT1 2
59 P1.4/SPICLK(2)/ADC4
58 P1.3/TXD1(IrDA)(2)/ADC3
PD1/CLKIN 3
ALE 4
57 MCU A11
PC7 5
56 P1.2/RXD1(IrDA)(2)/ADC2
55 MCU A10
JTAG TDO 6
54 P1.1/T2X(2)/ADC1
JTAG TDI 7
53 MCU A9
DEBUG 8
52 P1.0/T2(2)/ADC0
PC4/TERR 9
51 MCU A8
3.3V V CC 10
50 V DD(1)
NC 11
VDD(1)
12
49 XTAL2
GND 13
48 XTAL1
PC3/TSTAT 14
47 MCU AD7
PC2 15
46 P3.7/SCL
JTAG TCK 16
45 MCU AD6
NC 17
44 P3.6/SDA
SPISEL(2)/PCACLK1/P4.7 18
43 MCU AD5
SPITXD(2)/TCM5/P4.6 19
42 P3.5/C1
41 MCU AD4
P3.4/C0 40
MCU AD3 39
MCU AD2 38
MCU AD1 37
MCU AD0 36
PA0 35
PA1 34
T2(2)/TCM0/P4.0 33
PA2 32
T2X(2)/TCM1/P4.1 31
RXD1(IrDA)(2)/TCM2/P4.2 30
GND 29
PA3 28
TXD1(IrDA)(2)/PCACLK0/P4.3 27
PA4 26
SPICLK(2)/TCM3/P4.4 25
PA5 24
SPIRXD(2)/TCM4/P4.5 23
PA6 22
PA7 21
JTAG TMS 20
AI07823b
1. For 5 V applications, VDD must be connected to a 5.0 V source. For 3.3 V applications, VDD must be connected to a 3.3 V
source.
2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1.
3. NC = Not Connected
Doc ID 9685 Rev 7
21/272
Pin descriptions
Table 2.
Port pin
UPSD33xx
Pin definitions
Signal
name
80-Pin 52-Pin
num. num.(1)
Function
In/Out
Basic
Alternate 1
Alternate 2
MCUAD0
AD0
36
N/A
I/O
External bus
Multiplexed
address/data bus
A0/D0
MCUAD1
AD1
37
N/A
I/O
Multiplexed
address/data bus
A1/D1
MCUAD2
AD2
38
N/A
I/O
Multiplexed
address/data bus
A2/D2
MCUAD3
AD3
39
N/A
I/O
Multiplexed
address/data bus
A3/D3
MCUAD4
AD4
41
N/A
I/O
Multiplexed
address/data bus
A4/D4
MCUAD5
AD5
43
N/A
I/O
Multiplexed
address/data bus
A5/D5
MCUAD6
AD6
45
N/A
I/O
Multiplexed
address/data bus
A6/D6
MCUAD7
AD7
47
N/A
I/O
Multiplexed
address/data bus
A7/D7
MCUA8
A8
51
N/A
O
External bus, Addr
A8
MCUA9
A9
53
N/A
O
External bus, Addr
A9
MCUA10
A10
55
N/A
O
External bus, Addr
A10
MCUA11
A11
57
N/A
O
External bus, Addr
A11
P1.0
T2
ADC0
52
34
I/O
General I/O port
pin
Timer 2 Count
input (T2)
ADC Channel 0
input (ADC0)
P1.1
T2X
ADC1
54
35
I/O
General I/O port
pin
Timer 2 Trigger
input (T2X)
ADC Channel 1
input (ADC1)
P1.2
RxD1
ADC2
56
36
I/O
General I/O port
pin
UART1 or IrDA
Receive (RxD1)
ADC Channel 2
input (ADC2)
P1.3
TXD1
ADC3
58
37
I/O
General I/O port
pin
UART or IrDA
Transmit (TxD1)
ADC Channel 3
input (ADC3)
22/272
Doc ID 9685 Rev 7
UPSD33xx
Table 2.
Port pin
Pin descriptions
Pin definitions (continued)
Signal
name
80-Pin 52-Pin
num. num.(1)
Function
In/Out
Basic
Alternate 1
Alternate 2
P1.4
SPICLK
ADC4
59
38
I/O
General I/O port
pin
SPI Clock Out
(SPICLK)
ADC Channel 4
input (ADC4)
P1.5
SPIRxD
ADC6
60
39
I/O
General I/O port
pin
SPI Receive
(SPIRxD)
ADC Channel 5
input (ADC5)
P1.6
SPITXD
ADC6
61
40
I/O
General I/O port
pin
SPI Transmit
(SPITxD)
ADC Channel 6
input (ADC6)
P1.7
SPISEL
ADC7
64
41
I/O
General I/O port
pin
SPI Slave Select
(SPISEL)
ADC Channel 7
input (ADC7)
P3.0
RxD0
75
23
I/O
General I/O port
pin
UART0 Receive
(RxD0)
P3.1
TXD0
77
24
I/O
General I/O port
pin
UART0 Transmit
(TxD0)
P3.2
EXINT0
TGO
79
25
I/O
General I/O port
pin
Interrupt 0 input
(EXTINT0)/Timer 0
gate control (TG0)
P3.3
INT1
2
26
I/O
General I/O port
pin
Interrupt 1 input
(EXTINT1)/Timer 1
gate control (TG1)
P3.4
C0
40
27
I/O
General I/O port
pin
Counter 0 input
(C0)
P3.5
C1
42
28
I/O
General I/O port
pin
Counter 1 input
(C1)
P3.6
SDA
44
29
I/O
General I/O port
pin
I2C Bus serial data
(I2CSDA)
P3.7
SCL
46
30
I/O
General I/O port
pin
I2C Bus clock
(I2CSCL)
P4.0
T2
TCM0
33
22
I/O
General I/O port
pin
Program Counter
Array0 PCA0TCM0
Timer 2 Count
input (T2)
P4.1
T2X
TCM1
31
21
I/O
General I/O port
pin
PCA0-TCM1
Timer 2 Trigger
input (T2X)
P4.2
RXD1
TCM2
30
20
I/O
General I/O port
pin
PCA0-TCM2
UART1 or IrDA
Receive (RxD1)
P4.3
TXD1
PCACL
K0
27
18
I/O
General I/O port
pin
PCACLK0
UART1 or IrDA
Transmit (TxD1)
P4.4
SPICLK
TCM3
25
17
I/O
General I/O port
pin
Program Counter
Array1 PCA1TCM3
SPI Clock Out
(SPICLK)
P4.5
SPIRXD
TCM4
23
16
I/O
General I/O port
pin
PCA1-TCM4
SPI Receive
(SPIRxD)
Doc ID 9685 Rev 7
23/272
Pin descriptions
Table 2.
Port pin
UPSD33xx
Pin definitions (continued)
Signal
name
80-Pin 52-Pin
num. num.(1)
Function
In/Out
Basic
Alternate 1
Alternate 2
P4.6
SPITXD
TCM5
19
15
I/O
General I/O port
pin
PCA1-TCM5
SPI Transmit
(SPITxD)
P4.7
SPISEL
PCACL
K1
18
14
I/O
General I/O port
pin
PCACLK1
SPI Slave Select
(SPISEL)
AVREF
70
N/A
I
Reference voltage
input for ADC.
Connect AVREF to
VCC if the ADC is
not used.
RD
65
N/A
O
READ Signal,
external bus
WR
62
N/A
O
WRITE Signal,
external bus
PSEN
63
N/A
O
PSEN Signal,
external bus
ALE
4
N/A
O
Address Latch
signal, external bus
RESET_IN
68
44
I
Active low reset
input
XTAL1
48
31
I
Oscillator input pin
for system clock
XTAL2
49
32
O
Oscillator output
pin for system clock
DEBUG
8
5
I/O
I/O to the MCU
debug unit
24/272
Doc ID 9685 Rev 7
UPSD33xx
Table 2.
Port pin
Pin descriptions
Pin definitions (continued)
Signal
name
80-Pin 52-Pin
num. num.(1)
Function
In/Out
Basic
PA0
35
N/A
I/O
General I/O port
pin
PA1
34
N/A
I/O
General I/O port
pin
PA2
32
N/A
I/O
General I/O port
pin
PA3
28
N/A
I/O
General I/O port
pin
PA4
26
N/A
I/O
General I/O port
pin
PA5
24
N/A
I/O
General I/O port
pin
PA6
22
N/A
I/O
General I/O port
pin
PA7
21
N/A
I/O
General I/O port
pin
Alternate 1
Alternate 2
All Port A pins
support:
– PLD Macro-cell
outputs, or
– PLD inputs, or
– Latched Address
Out (A0-A7), or
– Peripheral I/O
mode
1. N/A = Signal Not Available on 52-pin package.
Doc ID 9685 Rev 7
25/272
UPSD33xx hardware description
3
UPSD33xx
UPSD33xx hardware description
The UPSD33xx has a modular architecture built from a stacked die process. There are two
die, one is designated “MCU module” in this document, and the other is designated “PSD
module” (see Figure 4 on page 27). In all cases, the MCU module die operates at 3.3 V with
5 V tolerant I/O. The PSD module is either a 3.3 V die or a 5 V die, depending on the
UPSD33xx device as described below.
The MCU module consists of a fast 8032 core, that operates with 4 clocks per instruction
cycle, and has many peripheral and system supervisor functions. The PSD module provides
the 8032 with multiple memories (two Flash and one SRAM) for program and data,
programmable logic for address decoding and for general-purpose logic, and additional I/O.
The MCU module communicates with the PSD module through internal address and data
busses (A8 – A15, AD0 – AD7) and control signals (RD, WR, PSEN, ALE, RESET).
There are slightly different I/O characteristics for each module. I/Os for the MCU module are
designated as Ports 1, 3, and 4. I/Os for the PSD module are designated as Ports A, B, C,
and D.
For all 5 V UPSD33xx devices, a 3.3 V MCU module is stacked with a 5 V PSD module. In
this case, a 5 V UPSD33xx device must be supplied with 3.3 VCC for the MCU module and
5.0VDD for the PSD module. Ports 3 and 4 of the MCU module are 3.3 V ports with tolerance
to 5 V devices (they can be directly driven by external 5 V devices and they can directly
drive external 5 V devices while producing a VOH of 2.4 V min and VCC max). Ports A, B, C,
and D of the PSD module are true 5 V ports.
For all 3.3 V UPSD33xxV devices, a 3.3 V MCU module is stacked with a 3.3 V PSD
module. In this case, a 3.3 V UPSD33xx device needs to be supplied with a single 3.3 V
voltage source at both VCC and VDD. I/O pins on Ports 3 and 4 are 5 V tolerant and can be
connected to external 5 V peripherals devices if desired. Ports A, B, C, and D of the PSD
module are 3.3 V ports, which are not tolerant to external 5 V devices.
Refer to Table 3 on page 27 for port type and voltage source requirements.
80-pin UPSD33xx devices provide access to 8032 address, data, and control signals on
external pins to connect external peripheral and memory devices. 52-pin UPSD33xx
devices do not provide access to the 8032 system bus.
All non-volatile memory and configuration portions of the UPSD33xx device are
programmed through the JTAG interface and no special programming voltage is needed.
This same JTAG port is also used for debugging of the 8032 core at runtime providing
breakpoint, single-step, display, and trace features. A non-volatile security bit may be
programmed to block all access via JTAG interface for security. The security bit is defeated
only by erasing the entire device, leaving the device blank and ready to use again.
26/272
Doc ID 9685 Rev 7
UPSD33xx
UPSD33xx hardware description
Table 3.
Port type and voltage source combinations
VCC for MCU
module
VDD for PSD
module
Ports 3 and 4 on
MCU module
Ports A, B, C, and D
on PSD module
5 V:
UPSD33xx
3.3 V
5.0 V
3.3 V but 5 V tolerant
5V
3.3 V:
UPSD33xxV
3.3 V
3.3 V
3.3 V but 5 V tolerant
3.3 V. NOT 5 V tolerant
Device Type
Figure 4.
UPSD33xx functional modules
Port 3 - UART0,
Intr, Timers
Port 3
I2C
Port 4 - PCA,
PWM, UART1
Port 1 - Timer, ADC, SPI
MCU Module
Port 3
XTAL
Clock Unit
Port 1
Turbo 8032 Core
Dual
UARTs
3 Timer /
Counters
Interrupt
256 Byte SRAM
Dedicated Memory
Interface Prefetch,
Branch Cache
10-bit
ADC
SPI
Ext.
Bus
Reset Input
Reset
Pin
LVD
JTAG
DEBUG
Internal
Reset
Enhanced MCU Interface
Decode PLD
VCC Pins
3.3V
I2C
Unit
8032 Internal Bus
8-Bit Die-to-Die Bus
PSD Page Register
PCA
PWM
Counters
Main Flash
Secondary
Flash
Reset Logic
WDT
PSD
Reset
SRAM
PSD Module
PSD Internal Bus
JTAG ISP
UPSD33XX
Port C
JTAG and
GPIO
VDD Pins
3.3V or 5V
CPLD - 16 MACROCELLS
Port A,B,C PLD
I/O and GPIO
Port D
GPIO
AI07842b
Doc ID 9685 Rev 7
27/272
Memory organization
4
UPSD33xx
Memory organization
The 8032 MCU core views memory on the MCU module as “internal” memory and it views
memory on the PSD module as “external” memory, see Figure 5
Internal memory on the MCU module consists of DATA, IDATA, and SFRs. These standard
8032 memories reside in 384 bytes of SRAM located at a fixed address space starting at
address 0x0000.
External memory on the PSD module consists of four types: main Flash (64, 128, or
256 Kbytes), a smaller secondary Flash (16 or 32 Kbytes), SRAM (2, 8, or 32 Kbytes), and a
block of PSD module control registers called CSIOP (256 bytes). These external memories
reside at programmable address ranges, specified using the software tool PSDsoft Express.
See the Section 27: PSD module on page 164 of this document for more details on these
memories.
External memory is accessed by the 8032 in two separate 64 Kbyte address spaces. One
address space is for program memory and the other address space is for data memory.
Program memory is accessed using the 8032 signal, PSEN. Data memory is accessed
using the 8032 signals, RD and WR. If the 8032 needs to access more than 64 Kbytes of
external program or data memory, it must use paging (or banking) techniques provided by
the Page register in the PSD module.
Note:
When referencing program and data memory spaces, it has nothing to do with 8032 internal
SRAM areas of DATA, IDATA, and SFR on the MCU module. Program and data memory
spaces only relate to the external memories on the PSD module.
External memory on the PSD module can overlap the internal SRAM memory on the MCU
module in the same physical address range (starting at 0x0000) without interference
because the 8032 core does not assert the RD or WR signals when accessing internal
SRAM.
Figure 5.
UPSD33xx memories
Internal SRAM on
MCU Module
Main
Flash
Fixed
Addresses
FF
External Memory on
PSD Module
384 Bytes SRAM
Indirect
Addressing
• External memories may be placed at virtually
any address using software tool PSDsoft Express.
• The SRAM and Flash memories may be placed
in 8032 Program Space or Data Space using
PSDsoft Express.
128 Bytes
• Any memory in 8032 Data Space is XDATA.
SFR
IDATA
Direct
Addressing
80 128 Bytes
7F
64KB,
128KB,
or
256KB
128 Bytes
16KB
or
32KB
DATA
0
Secondary
Flash
SRAM
2KB,
8KB,
or
32KB
CSIOP
256 Bytes
Direct or Indirect Addressing
AI07843
28/272
Doc ID 9685 Rev 7
UPSD33xx
Memory organization
4.1
Internal memory (MCU, standard 8032 memory: DATA, IDATA,
SFR)
4.1.1
DATA memory
The first 128 bytes of internal SRAM ranging from address 0x0000 to 0x007F are called
DATA, which can be accessed using 8032 direct or indirect addressing schemes and are
typically used to store variables and stack.
Four register banks, each with 8 registers (R0 – R7), occupy addresses 0x0000 to 0x001F.
Only one of these four banks may be enabled at a time. The next 16 locations at 0x0020 to
0x002F contain 128 directly addressable bit locations that can be used as software flags.
SRAM locations 0x0030 and above may be used for variables and stack.
4.1.2
IDATA memory
The next 128 bytes of internal SRAM are named IDATA and range from address 0x0080 to
0x00FF. IDATA can be accessed only through 8032 indirect addressing and is typically
used to hold the MCU stack as well as data variables. The stack can reside in both DATA
and IDATA memories and reach a size limited only by the available space in the combined
256 bytes of these two memories (since stack accesses are always done using indirect
addressing, the boundary between DATA and IDATA does not exist with regard to the stack).
4.1.3
SFR memory
Special function registers (Table 5 on page 41) occupy a separate physical memory, but
they logically overlap the same 128 bytes as IDATA, ranging from address 0x0080 to
0x00FF. SFRs are accessed only using direct addressing. There 86 active registers used
for many functions: changing the operating mode of the 8032 MCU core, controlling 8032
peripherals, controlling I/O, and managing interrupt functions. The remaining unused SFRs
are reserved and should not be accessed.
16 of the SFRs are both byte- and bit-addressable. Bit-addressable SFRs are those whose
address ends in “0” or “8” hex.
4.2
External memory (PSD module: program memory, data
memory)
The PSD module has four memories: main Flash, secondary Flash, SRAM, and CSIOP.
Section 27: PSD module on page 164 for more detailed information on these memories.
Memory mapping in the PSD module is implemented with the Decode PLD (DPLD) and
optionally the Page register. The user specifies decode equations for individual segments of
each of the memories using the software tool PSDsoft Express. This is a very easy pointand-click process allowing total flexibility in mapping memories. Additionally, each of the
memories may be placed in various combinations of 8032 program address space or 8032
data address space by using the software tool PSDsoft Express.
Doc ID 9685 Rev 7
29/272
Memory organization
4.2.1
UPSD33xx
Program memory
External program memory is addressed by the 8032 using its 16-bit Program Counter (PC)
and is accessed with the 8032 signal, PSEN. Program memory can be present at any
address in program space between 0x0000 and 0xFFFF.
After a power-up or reset, the 8032 begins program execution from location 0x0000 where
the reset vector is stored, causing a jump to an initialization routine in firmware. At address
0x0003, just following the reset vector are the interrupt service locations. Each interrupt is
assigned a fixed interrupt service location in program memory. An interrupt causes the 8032
to jump to that service location, where it commences execution of the service routine.
External Interrupt 0 (EXINT0), for example, is assigned to service location 0x0003. If
EXINT0 is going to be used, its service routine must begin at location 0x0003. Interrupt
service locations are spaced at 8-byte intervals: 0x0003 for EXINT0, 0x000B for Timer 0,
0x0013 for EXINT1, and so forth. If an interrupt service routine is short enough, it can reside
entirely within the 8-byte interval. Longer service routines can use a jump instruction to
somewhere else in program memory.
4.2.2
Data memory
External data is referred to as XDATA and is addressed by the 8032 using Indirect
Addressing via its 16-bit Data Pointer register (DPTR) and is accessed by the 8032 signals,
RD and WR. XDATA can be present at any address in data space between 0x0000 and
0xFFFF.
Note:
The UPSD33xx has dual data pointers (source and destination) making XDATA transfers
much more efficient.
4.2.3
Memory placement
PSD module architecture allows the placement of its external memories into different
combinations of program memory and data memory spaces. This means the main Flash,
the secondary Flash, and the SRAM can be viewed by the 8032 MCU in various
combinations of program memory or data memory as defined by PSDsoft Express.
As an example of this flexibility, for applications that require a great deal of Flash memory in
data space (large lookup tables or extended data recording), the larger main Flash memory
can be placed in data space and the smaller secondary Flash memory can be placed in
program space. The opposite can be realized for a different application if more Flash
memory is needed for code and less Flash memory for data.
By default, the SRAM and CSIOP memories on the PSD module must always reside in data
memory space and they are treated by the 8032 as XDATA. However, the SRAM may
optionally reside in program space in addition to data space if it is desired to execute code
from SRAM. The main Flash and secondary Flash memories may reside in program space,
data space, or both.
These memory placement choices specified by PSDsoft Express are programmed into nonvolatile sections of the UPSD33xx, and are active at power-up and after reset. It is possible
to override these initial settings during runtime for in-application programming (IAP).
30/272
Doc ID 9685 Rev 7
UPSD33xx
Memory organization
Standard 8032 MCU architecture cannot write to its own program memory space to prevent
accidental corruption of firmware. However, this becomes an obstacle in typical 8032
systems when a remote update to firmware in Flash memory is required using IAP. The PSD
module provides a solution for remote updates by allowing 8032 firmware to temporarily
“reclassify” Flash memory to reside in data space during a remote update, then returning
Flash memory back to program space when finished. See the VM register (Table 115 on
page 178) in the PSD module section of this document for more details.
Doc ID 9685 Rev 7
31/272
8032 MCU core performance enhancements
5
UPSD33xx
8032 MCU core performance enhancements
Before describing performance features of the UPSD33xx, let us first look at standard 8032
architecture. The clock source for the 8032 MCU creates a basic unit of timing called a
machine-cycle, which is a period of 12 clocks for standard 8032 MCUs. The instruction set
for traditional 8032 MCUs consists of 1, 2, and 3 byte instructions that execute in different
combinations of 1, 2, or 4 machine-cycles. For example, there are one-byte instructions that
execute in one machine-cycle (12 clocks), one-byte instructions that execute in four
machine-cycles (48 clocks), two-byte, two-cycle instructions (24 clocks), and so on. In
addition, standard 8032 architecture will fetch two bytes from program memory on almost
every machine-cycle, regardless if it needs them or not (dummy fetch). This means for onebyte, one-cycle instructions, the second byte is ignored. These one-byte, one-cycle
instructions account for half of the 8032's instructions (126 out of 255 opcodes). There are
inefficiencies due to wasted bus cycles and idle bus times that can be eliminated.
The UPSD33xx 8032 MCU core offers increased performance in a number of ways, while
keeping the exact same instruction set as the standard 8032 (all opcodes, the number of
bytes per instruction, and the native number a machine-cycles per instruction are identical to
the original 8032). The first way performance is boosted is by reducing the machine-cycle
period to just 4 MCU clocks as compared to 12 MCU clocks in a standard 8032. This
shortened machine-cycle improves the instruction rate for one-byte, one-cycle instructions
by a factor of three (Figure 6) compared to standard 8051 architectures, and significantly
improves performance of multiple-cycle instruction types.
The example in Figure 6 shows a continuous execution stream of one-byte, one-cycle
instructions. The 5 V UPSD33xx will yield 10 MIPS peak performance in this case while
operating at 40 MHz clock rate. In a typical application however, the effective performance
will be lower since programs do not use only one-cycle instructions, but special techniques
are implemented in the UPSD33xx to keep the effective MIPS rate as close as possible to
the peak MIPS rate at all times. This is accomplished with an instruction Pre-Fetch Queue
(PFQ) and a Branch Cache (BC) as shown in Figure 7 on page 33.
Figure 6.
Comparison of UPSD33xx with standard 8032 performance
1-byte, 1-Cycle Instructions
Turbo UPSD33XX
Instruction A
Instruction B
Execute Instruction and
Pre-Fetch Next Instruction
Execute Instruction and
Pre-Fetch Next Instruction
Execute Instruction and
Pre-Fetch Next Instruction
Instruction C
4 clocks (one machine cycle)
one machine cycle
one machine cycle
MCU Clock
12 clocks (one machine cycle)
Instruction A
Standard 8032
Fetch Byte for Instruction A
Execute Instruction A
and Fetch a Second Dummy Byte
Dummy Byte is Ignored (wasted bus access)
Turbo UPSD33XX executes instructions A, B, and C in the same
amount of time that a standard 8032 executes only instruction A.
AI08808b
32/272
Doc ID 9685 Rev 7
UPSD33xx
Figure 7.
8032 MCU core performance enhancements
Instruction pre-fetch queue and branch cache
Branch 4
Code
Branch 4
Code
Branch 4
Code
Branch 4
Code
Branch 4
Code
Branch 4
Code
Previous
Branch 4
Branch 3 Branch 3 Branch 3 Branch 3 Branch 3 Branch 3
Previous
Code
Code
Code
Code
Code
Code
Branch 3
Branch 2 Branch 2 Branch 2 Branch 2 Branch 2 Branch 2
Previous
Code
Branch 2
Code
Code
Code
Code
Code
Branch
Cache
(BC)
Branch 1
Code
Branch 1
Code
Branch 1
Code
Branch 1
Code
Branch 1
Code
Branch 1
Code
Compare
Previous
Branch 1
Address
Load on Branch Address Match
Current
Branch
Address
Instruction
Byte
Program
Memory on
PSD Module
Instruction
Byte
8
Address
8
6 Bytes of Instruction
16
Wait
8032
MCU
Address
16
Instruction Pre-Fetch Queue (PFQ)
Stall
AI08809
5.1
Pre-Fetch Queue (PFQ) and Branch Cache (BC)
The PFQ is always working to minimize the idle bus time inherent to 8032 MCU architecture,
to eliminate wasted memory fetches, and to maximize memory bandwidth to the MCU. The
PFQ does this by running asynchronously in relation to the MCU, looking ahead to pre-fetch
code from program memory during any idle bus periods. Only necessary bytes will be
fetched (no dummy fetches like standard 8032). The PFQ will queue up to six code bytes in
advance of execution, which significantly optimizes sequential program performance.
However, when program execution becomes non-sequential (program branch), a typical prefetch queue will empty itself and reload new code, causing the MCU to stall. The Turbo
UPSD33xx diminishes this problem by using a Branch Cache with the PFQ. The BC is a
four-way, fully associative cache, meaning that when a program branch occurs, it's branch
destination address is compared simultaneously with four recent previous branch
destinations stored in the BC. Each of the four cache entries contain up to six bytes of code
related to a branch. If there is a hit (a match), then all six code bytes of the matching
program branch are transferred immediately and simultaneously from the BC to the PFQ,
and execution on that branch continues with minimal delay. This greatly reduces the chance
that the MCU will stall from an empty PFQ, and improves performance in embedded control
systems where it is quite common to branch and loop in relatively small code localities.
By default, the PFQ and BC are enabled after power-up or reset. The 8032 can disable the
PFQ and BC at runtime if desired by writing to a specific SFR (BUSCON).
The memory in the PSD module operates with variable wait states depending on the value
specified in the SFR named BUSCON. For example, a 5 V UPSD33xx device operating at a
40 MHz crystal frequency requires four memory wait states (equal to four MCU clocks). In
this example, once the PFQ has one or more bytes of code, the wait states become
Doc ID 9685 Rev 7
33/272
8032 MCU core performance enhancements
UPSD33xx
transparent and a full 10 MIPS is achieved when the program stream consists of sequential
one-byte, one machine-cycle instructions as shown in Figure 6 on page 32 (transparent
because a machine-cycle is four MCU clocks which equals the memory pre-fetch wait time
that is also four MCU clocks). But it is also important to understand PFQ operation on multicycle instructions.
5.2
PFQ example, multi-cycle instructions
Let us look at a string of two-byte, two-cycle instructions in Figure 8. There are three
instructions executed sequentially in this example, instructions A, B, and C. Each of the time
divisions in the figure is one machine-cycle of four clocks, and there are six phases to
reference in this discussion. Each instruction is pre-fetched into the PFQ in advance of
execution by the MCU. Prior to Phase 1, the PFQ has pre-fetched the two instruction bytes
(A1 and A2) of instruction A. During Phase one, both bytes are loaded into the MCU
execution unit. Also in Phase 1, the PFQ is pre-fetching the first byte (B1) of instruction B
from program memory. In Phase 2, the MCU is processing instruction A internally while the
PFQ is pre-fetching the second byte (B2) of instruction B. In Phase 3, both bytes of
instruction B are loaded into the MCU execution unit and the PFQ begins to pre-fetch bytes
for the third instruction C. In Phase 4 instruction B is processed and the pre-fetching
continues, eliminating idle bus cycles and feeding a continuous flow of operands and
opcodes to the MCU execution unit.
The UPSD33xx MCU instructions are an exact 1/3 scale of all standard 8032 instructions
with regard to number of cycles per instruction. Figure 9 on page 35 shows the equivalent
instruction sequence from the example above on a standard 8032 for comparison.
5.3
Aggregate performance
The stream of two-byte, two-cycle instructions in Figure 8, running on a 40 MHz, 5 V,
UPSD33xx will yield 5 MIPs. And we saw the stream of one-byte, one-cycle instructions in
Figure 6 on page 32, on the same MCU yield 10 MIPs. Effective performance will depend on
a number of things: the MCU clock frequency; the mixture of instructions types (bytes and
cycles) in the application; the amount of time an empty PFQ stalls the MCU (mix of
instruction types and misses on Branch Cache); and the operating voltage. A 5 V
UPSD33xx device operates with four memory wait states, but a 3.3 V device operates with
five memory wait states yielding 8 MIPS peak compared to 10 MIPs peak for 5 V device.
The same number of wait states will apply to both program fetches and to data
READ/WRITEs unless otherwise specified in the SFR named BUSCON.
In general, a 3X aggregate performance increase is expected over any standard 8032
application running at the same clock frequency.
34/272
Doc ID 9685 Rev 7
UPSD33xx
Figure 8.
8032 MCU core performance enhancements
PFQ operation on multi-cycle instructions
Three 2-byte, 2-cycle Instructions on UPSD33XX
Pre-Fetch Inst A
PFQ
Pre-Fetch Inst B
Pre-Fetch Inst C
Inst A, Byte 1 Inst A, Byte 2 Inst B, Byte 1 Inst B, Byte 2 Inst C, Byte 1 Inst C, Byte 2
Continue to Pre-Fetch
4-clock
Macine Cycle
Previous Instruction
MCU
Execution
Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
A1
Process A
B1
Process B
C1
Process C
A2
B2
Instruction A
Instruction B
C2
Next Inst
Instruction C
AI08810b
Figure 9.
UPSD33xx multi-cycle instructions compared to standard 8032
Three 2-byte, 2-cycle Instructions, UPSD33XX vs. Standard 8032b
24 Clocks Total (4 clocks per cycle)
UPSD33XX
A1
A2
Inst A
B1
B2
Inst B
C1 C2
Inst C
1 Cycle
72 Clocks (12 clocks per cycle)
Std 8032
Byte 1
Byte 2
Process Inst A
Byte 1
Byte 2
Process Inst B
Byte 1
Byte 2
Process Inst C
1 Cycle
AI08811b
Doc ID 9685 Rev 7
35/272
MCU module description
6
UPSD33xx
MCU module description
This section provides a detail description of the MCU module system functions and
peripherals, including:
Note:
36/272
●
8032 MCU registers
●
Special function registers
●
8032 addressing modes
●
UPSD33xx instruction set summary
●
Dual data pointers
●
Debug unit
●
Interrupt system
●
MCU clock generation
●
Power saving modes
●
Oscillator and external components
●
I/O ports
●
MCU bus interface
●
Supervisory functions
●
Standard 8032 timer/counters
●
Serial UART interfaces
●
IrDA interface
●
I2C interface
●
SPI interface
●
Analog-to-digital converter
●
Programmable counter array (PCA)
A full description of the 8032 instruction set may be found in the UPSD33xx programmers
guide.
Doc ID 9685 Rev 7
UPSD33xx
7
8032 MCU registers
8032 MCU registers
The UPSD33xx has the following 8032 MCU core registers, also shown in Figure 10.
Figure 10. 8032 MCU registers
A
Accumulator
B
B Register
SP
PCH
PCL
Program Counter
PSW
Program Status Word
General Purpose
Register (Bank0-3)
Data Pointer Register
R0-R7
DPTR(DPH)
Stack Pointer
DPTR(DPL)
AI06636
7.1
Stack Pointer (SP)
The SP is an 8-bit register which holds the current location of the top of the stack. It is
incremented before a value is pushed onto the stack, and decremented after a value is
popped off the stack. The SP is initialized to 07h after reset. This causes the stack to begin
at location 08h (top of stack). To avoid overlapping conflicts, the user must initialize the top
of the stack to 20h if all four banks of registers R0 - R7 are used, and the user must initialize
the top of stack to 30h if all of the 8032 bit memory locations are used.
7.2
Data Pointer (DPTR)
DPTR is a 16-bit register consisting of two 8-bit registers, DPL and DPH. The DPTR register
is used as a base register to create an address for indirect jumps, table look-up operations,
and for external data transfers (XDATA). When not used for addressing, the DPTR register
can be used as a general purpose 16-bit data register.
Very frequently, the DPTR register is used to access XDATA using the External Direct
addressing mode. The UPSD33xx has a special set of SFR registers (DPTC, DPTM) to
control a secondary DPTR register to speed memory-to-memory XDATA transfers. Having
dual DPTR registers allows rapid switching between source and destination addresses (see
details in Section 11: Dual data pointers on page 56).
7.3
Program Counter (PC)
The PC is a 16-bit register consisting of two 8-bit registers, PCL and PCH. This counter
indicates the address of the next instruction in program memory to be fetched and executed.
A reset forces the PC to location 0000h, which is where the reset jump vector is stored.
Doc ID 9685 Rev 7
37/272
8032 MCU registers
7.4
UPSD33xx
Accumulator (ACC)
This is an 8-bit general purpose register which holds a source operand and receives the
result of arithmetic operations. The ACC register can also be the source or destination of
logic and data movement operations. For MUL and DIV instructions, ACC is combined with
the B register to hold 16-bit operands. The ACC is referred to as “A” in the MCU instruction
set.
7.5
B register (B)
The B register is a general purpose 8-bit register for temporary data storage and also used
as a 16-bit register when concatenated with the ACC register for use with MUL and DIV
instructions.
7.6
General purpose registers (R0 - R7)
There are four banks of eight general purpose 8-bit registers (R0 - R7), but only one bank of
eight registers is active at any given time depending on the setting in the PSW word
(described next). R0 - R7 are generally used to assist in manipulating values and moving
data from one memory location to another. These register banks physically reside in the first
32 locations of 8032 internal DATA SRAM, starting at address 00h. At reset, only the first
bank of eight registers is active (addresses 00h to 07h), and the stack begins at address
08h.
7.7
Program Status Word (PSW)
The PSW is an 8-bit register which stores several important bits, or flags, that are set and
cleared by many 8032 instructions, reflecting the current state of the MCU core. Figure 11
on page 39 shows the individual flags.
7.7.1
Carry flag (CY)
This flag is set when the last arithmetic operation that was executed results in a carry
(addition) or borrow (subtraction). It is cleared by all other arithmetic operations. The CY flag
is also affected by Shift and Rotate instructions.
7.7.2
Auxiliary Carry flag (AC)
This flag is set when the last arithmetic operation that was executed results in a carry into
(addition) or borrow from (subtraction) the high-order nibble. It is cleared by all other
arithmetic operations.
7.7.3
General purpose flag (F0)
This is a bit-addressable, general-purpose flag for use under software control.
7.7.4
Register bank select flags (RS1, RS0)
These bits select which bank of eight registers is used during R0 - R7 register accesses
(see Table 4 on page 39)
38/272
Doc ID 9685 Rev 7
UPSD33xx
7.7.5
8032 MCU registers
Overflow flag (OV)
The OV flag is set when: an ADD, ADDC, or SUBB instruction causes a sign change; a MUL
instruction results in an overflow (result greater than 255); a DIV instruction causes a divideby-zero condition. The OV flag is cleared by the ADD, ADDC, SUBB, MUL, and DIV
instructions in all other cases. The CLRV instruction will clear the OV flag at any time.
7.7.6
Parity flag (P)
The P flag is set if the sum of the eight bits in the Accumulator is odd, and P is cleared if the
sum is even.
Table 4.
Register bank select addresses
RS1
RS0
Register bank
8032 internal DATA address
0
0
0
00h - 07h
0
1
1
08h - 0Fh
1
0
2
10h - 17h
1
1
3
18h - 1Fh
Figure 11. Program Status Word (PSW) register
LSB
MSB
PSW
CY AC FO RS1 RS0 OV
P
Reset Value 00h
Parity Flag
Carry Flag
Auxillary Carry Flag
Bit not assigned
General Purpose Flag
Overflow Flag
Register Bank Select Flags
(to select Bank0-3)
AI06639
Doc ID 9685 Rev 7
39/272
Special function registers (SFR)
8
UPSD33xx
Special function registers (SFR)
A group of registers designated as Special Function register (SFR) is shown in Table 5 on
page 41. SFRs control the operating modes of the MCU core and also control the peripheral
interfaces and I/O pins on the MCU module. The SFRs can be accessed only by using the
Direct Addressing method within the address range from 80h to FFh of internal 8032 SRAM.
Sixteen addresses in SFR address space are both byte- and bit-addressable. The bitaddressable SFRs are noted in Table 5.
86 of a possible 128 SFR addresses are occupied. The remaining unoccupied SFR
addresses (designated as “RESERVED” in Table 5) should not be written. Reading
unoccupied locations will return an undefined value.
Note:
There is a separate set of control registers for the PSD module, designated as csiop, and
they are described in the Section 27: PSD module on page 164. The I/O pins, PLD, and
other functions on the PSD module are NOT controlled by SFRs.
SFRs are categorized as follows:
●
MCU core registers: IP, A, B, PSW, SP, DPTL, DPTH, DPTC, DPTM
●
MCU module I/O port registers: P1, P3, P4, P1SFS0, P1SFS1, P3SFS, P4SFS0,
P4SFS1
●
Standard 8032 timer registers: TCON, TMOD, T2CON, TH0, TH1, TH2, TL0, TL1, TL2,
RCAP2L, RCAP2H
●
Standard serial interfaces (UART): SCON0, SBUF0, SCON1, SBUF1
●
Power, clock, and bus timing registers: PCON, CCON0, BUSCON
●
Hardware watchdog timer registers: WDKEY, WDRST
●
Interrupt system registers: IP, IPA, IE, IEA
●
Program counter array (PCA) control registers: PCACL0, PCACH0, PCACON0,
PCASTA, PCACL1, PCACH1, PCACON1, CCON2, CCON3
●
PCA capture/compare and PWM registers
CAPCOML0, CAPCOMH0, TCMMODE0, CAPCOML1, CAPCOMH1, TCMMODE2,
CAPCOML2, CAPCOMH2, TCMMODE2, CAPCOML3, CAPCOMH3, TCMMODE3,
CAPCOML4, CAPCOMH4, TCMMODE4, CAPCOML5, CAPCOMH5, TCMMODE5,
PWMF0, PMWF1
40/272
●
SPI interface registers: SPICLKD, SPISTAT, SPITDR, SPIRDR, SPICON0, SPICON1
●
I2C interface registers: S1SETUP, S1CON, S1STA, S1DAT, S1ADR
●
Analog-to-digital converter registers: ACON, ADCPS, ADAT0, ADAT1
●
IrDA interface register: IRDACON
Doc ID 9685 Rev 7
UPSD33xx
Table 5.
SFR
addr
(hex)
Special function registers (SFR)
SFR memory map with direct address and reset value
SFR
name
Bit name and
7
6
5
4
80
3
2
1
0
Reset
value
(hex)
Reg. descr.
with link
Section 7.1
on page 37
RESERVED
81
SP
SP[7:0]
07
82
DPL
DPL[7:0]
00
83
DPH
DPH[7:0]
00
84
Section 7.2
on page 37
RESERVED
Table 13 on
page 56
00
Table 15 on
page 57
IDLE
00
Table 31 on
page 72
IE0
IT0
00
Table 54 on
page 95
M1
M0
00
Table 56 on
page 97
DPTC
–
AT
–
–
86
DPTM
–
–
–
–
87
PCON
SMOD0
SMOD1
–
POR
RCLK1
TCLK1
PD
88(1)
TCON
TF1
TR1
TF0
TR0
IE1
IT1
89
TMOD
GATE
C/T
M1
M0
GATE
C/T
8A
TL0
TL0[7:0]
00
8B
TL1
TL1[7:0]
00
8C
TH0
TH0[7:0]
00
8D
TH1
TH1[7:0]
00
8E
P1SFS0
P1SFS0[7:0]
00
Table 41 on
page 83
8F
P1SFS1
P1SFS1[7:0]
00
Table 42 on
page 83
90(1)
P1
FF
Table 33 on
page 80
91
P3SFS
P3SFS[7:0]
00
Table 39 on
page 83
92
P4SFS0
P4SFS0[7:0]
00
Table 44 on
page 84
93
P4SFS1
P4SFS1[7:0]
00
Table 45 on
page 84
94
ADCPS
00
Table 95 on
page 152
95
ADAT0
00
Table 96 on
page 152
96
ADAT1
–
–
–
00
Table 97 on
page 152
97
ACON
AINTF
AINTEN
ADEN
98(1)
SCON0
SM0
SM1
SM2
99
SBUF0
P1.7
–
P1.6
–
P1.5
–
–
00
85
DPSEL[2:0]
MD1[1:0]
P1.4
P1.3
–
MD0[1:0]
P1.2
ADCCE
P1.1
P1.0
ADCPS[2:0]
ADATA[7:0]
–
–
–
ADS[2:0]
REN
TB8
SBUF0[7:0]
9A
RESERVED
9B
RESERVED
Doc ID 9685 Rev 7
RB8
ADATA[9:8]
Section 20.1
on page 94
ADST
ADSF
00
Table 93 on
page 151
TI
RI
00
Table 63 on
page 108
00
Figure 24 on
page 104
41/272
Special function registers (SFR)
Table 5.
SFR
addr
(hex)
UPSD33xx
SFR memory map with direct address and reset value (continued)
SFR
name
Bit name and
7
6
5
4
9C
9D
3
2
1
0
Reset
value
(hex)
RDW0
CW1
CW0
EB
Table 47 on
page 87
Reg. descr.
with link
RESERVED
BUSCON
EPFQ
EBC
WRW1
WRW0
RDW1
9E
RESERVED
9F
RESERVED
A0
RESERVED
A1
RESERVED
A2
PCACL0
PCACL0[7:0]
00
Table 98 on
page 154
A3
PCACH0
PCACH0[7:0]
00
Table 98 on
page 154
A4
PCACON0
EN_ALL
EN_PCA
EOVF1
PCA_IDL
–
–
00
Table 103 on
page 159
A5
PCASTA
OVF1
INTF5
INTF4
INTF3
OVF0
INTF2
00
Table 107 on
page 161
A6
WDTRST
00
Table 52 on
page 92
A7
IEA
EADC
ESPI
EPCA
ES1
–
–
EI2C
–
00
Table 21 on
page 65
A8(1)
IE
EA
–
ET2
ES0
ET1
EX1
ET0
EX0
00
Table 19 on
page 65
A9
TCMMODE
0
EINTF
E_COMP
CAP_PE
CAP_NE
MATCH
TOGGLE
PWM[1:0]
00
AA
TCMMODE
1
EINTF
E_COMP
CAP_PE
CAP_NE
MATCH
TOGGLE
PWM[1:0]
00
AB
TCMMODE
2
EINTF
E_COMP
CAP_PE
CAP_NE
MATCH
TOGGLE
PWM[1:0]
00
AC
CAPCOML
0
CAPCOML0[7:0]
AD
CAPCOMH
0
CAPCOMH0[7:0]
00
AE
WDKEY
WDKEY[7:0]
55
Table 50 on
page 92
AF
CAPCOML
1
CAPCOML1[7:0]
00
Table 98 on
page 154
B0(1)
P3
FF
Table 35 on
page 81
B1
CAPCOMH
1
CAPCOMH1[7:0]
00
B2
CAPCOML
2
CAPCOML2[7:0]
00
B3
CAPCOMH
2
CAPCOMH2[7:0]
00
B4
PWMF0
PWMF0[7:0]
00
INTF1
INTF0
WDTRST[7:0]
Table 109 on
page 162
00
Table 98 on
page 154
P3.7
P3.6
P3.5
P3.4
P3.3
B5
RESERVED
B6
RESERVED
42/272
CLK_SEL[1:0]
Doc ID 9685 Rev 7
P3.2
P3.1
P3.0
Table 98 on
page 154
UPSD33xx
Table 5.
Special function registers (SFR)
SFR memory map with direct address and reset value (continued)
SFR
addr
(hex)
SFR
name
B7
B8(1)
Bit name and
7
6
5
4
3
2
1
0
Reset
value
(hex)
IPA
PADC
PSPI
PPCA
PS1
–
–
PI2C
–
00
Table 25 on
page 66
IP
–
–
PT2
PS0
PT1
PX1
PT0
PX0
00
Table 23 on
page 66
B9
Reg. descr.
with link
RESERVED
BA
PCACL1
PCACL1[7:0]
00
BB
PCACH1
PCACH1[7:0]
00
BC
PCACON1
–
EN_PCA
EOVF1
PCA_IDL
–
–
CLK_SEL[1:0]
00
BD
TCMMODE
3
EINTF
E_COMP
CAP_PE
CAP_NE
MATCH
TOGGLE
PWM[1:0]
00
BE
TCMMODE
4
EINTF
E_COMP
CAP_PE
CAP_NE
MATCH
TOGGLE
PWM[1:0]
00
BF
TCMMODE
5
EINTF
E_COMP
CAP_PE
CAP_NE
MATCH
TOGGLE
PWM[1:0]
00
C0(1)
P4
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
C1
CAPCOML
3
CAPCOML3[7:0]
00
C2
CAPCOMH
3
CAPCOMH3[7:0]
00
C3
CAPCOML
4
CAPCOML4[7:0]
00
C4
CAPCOMH
4
CAPCOMH4[7:0]
00
C5
CAPCOML
5
CAPCOML5[7:0]
00
C6
CAPCOMH
5
CAPCOMH5[7:0]
00
C7
PWMF1
PWMF1[7:0]
00
C8(1)
T2CON
TF2
EXF2
RCLK
TCLK
C9
EXEN2
TR2
P4.1
C/T2
P4.0
CP/RL
2
FF
00
Table 98 on
page 154
Table 105 on
page 160
Table 109 on
page 162
Table 37 on
page 81
Table 98 on
page 154
Table 58 on
page 100
RESERVED
CA
RCAP2L
RCAP2L[7:0]
00
CB
RCAP2H
RCAP2H[7:0]
00
CC
TL2
TL2[7:0]
00
CD
TH2
TH2[7:0]
00
CE
IRDACON
–
IRDA_EN
BIT_PULS
D0(1)
PSW
CY
AC
F0
CDIV4
CDIV3
RS[1:0]
D1
Section 20.1
on page 94
CDIV2
CDIV1
CDIV0
0F
Table 68 on
page 120
OV
–
P
00
Section 7.7
on page 38
–
–
04
Table 89 on
page 148
TISF
RISF
02
Table 91 on
page 149
RESERVED
D2
SPICLKD
D3
SPISTAT
SPICLKD[5:0]
–
–
–
BUSY
TEISF
Doc ID 9685 Rev 7
RORISF
43/272
Special function registers (SFR)
Table 5.
UPSD33xx
SFR memory map with direct address and reset value (continued)
Bit name and
SFR
addr
(hex)
SFR
name
D4
SPITDR
SPITDR[7:0]
00
D5
SPIRDR
SPIRDR[7:0]
00
D6
SPICON0
–
TE
RE
SPIEN
SSEL
FLSB
SPO
–
00
Table 85 on
page 147
D7
SPICON1
–
–
–
–
TEIE
RORIE
TIE
RIE
00
Table 87 on
page 148
D8(1)
SCON1
SM0
工商网监
湘ICP备2023018690号
