VIPer50A-E
VIPer50ASP-E
SMPS PRIMARY I.C.
General Features
In
VDSS
Type
RDS(on)
10
VIPer50A-E/ASP-E
700V
5.7Ω
1.5A
1
■
ADJUSTABLE SWITCHING FREQUENCY UP
TO 200 kHz
■
CURRENT MODE CONTROL
■
SOFT START AND SHUTDOWN CONTROL
■
AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
“BLUE ANGEL” NORM ( -------------------V DD hyst
IDD is the consumption current on the VDD pin when switching. Refer to specified I DD1 and IDD2
values.
tSS is the start up time of the converter when the device begins to switch. Worst case is
generally at full load.
12/31
VIPer50A-E/ASP-E
5 Operation Description
VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).
The soft start feature can be implemented on the COMP pin through a simple capacitor which
will be also used as the compensation network. In this case, the regulation loop bandwidth is
rather low, because of the large value of this capacitor. In case a large regulation loop
bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high
performance compensation network together with a separate high value soft start capacitor.
Both soft start time and regulation loop bandwidth can be adjusted separately.
If the device is intentionally shut down by tying the COMP pin to ground, the device is also
performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff.
This voltage can be used for supplying external functions, provided that their consumption does
not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched
shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state
until the input voltage is removed.
5.4
Transconductance Error Amplifier
The VIPer50A-E/ASP-E includes a transconductance error amplifier. Transconductance Gm is
the change in output current (ICOMP) versus change in input voltage (VDD). Thus:
∂l COMP
G m = ------------------∂V DD
The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as:
V
V
∂ CO MP
1
∂ COMP
- = -------- × ------------------------Z CO MP = -------------------I
G
∂V DD
m
∂ COMP
This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP:
AVOL = Gm x ZCOMP
where Gm value for VIPer50A-E/ASP-E is 1.5 mA/V typically.
Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances.
An impedance Z can be connected between the COMP pin and ground in order to define the
transfer function F of the error amplifier more accurately, according to the following equation
(very similar to the one above):
F(S) = Gm x Z(S)
The error amplifier frequency response is reported in Figure 10. for different values of a simple
resistance connected on the COMP pin. The unloaded transconductance error amplifier shows
an internal ZCOMP of about 330KΩ. More complex impedance can be connected on the COMP
pin to achieve different compensation level. A capacitor will provide an integrator function, thus
eliminating the DC static error, and a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This configuration is illustrated in Figure 20
As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to
avoid any high frequency interference.
Is also possible to implement a slope compensation when working in continuous mode with
duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the
classical compensation network, and Q1 is injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
13/31
5 Operation Description
5.5
VIPer50A-E/ASP-E
External Clock Synchronization:
The OSC pin provides a synchronisation capability when connected to an external frequency
source. Figure 21 shows one possible schematic to be adapted, depending the specific needs.
If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is
sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through
the optotransistor.
5.6
Primary Peak Current Limitation
The primary IDPEAK current and, consequently, the output power can be limited using the
simple circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clamps the voltage on
the COMP pin in order to limit the primary peak current of the device to a value:
V COMP – 0.5
I D PEAK = -------------------------------H ID
where:
R1 + R 2
V COMP = 0.6 × ------------------R2
The suggested value for R1+R2 is in the range of 220KΩ.
5.7
Over-Temperature Protection
Over-temperature protection is based on chip temperature sensing. The minimum junction
temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is
170ºC. The device is automatically restarted when the junction temperature decreases to the
restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 13)
14/31
VIPer50A-E/ASP-E
5.8
5 Operation Description
Operation Pictures
Figure 5.
VDD Regulation Point
ICOMP
Figure 6.
Undervoltage Lockout
IDD
Slope =
Gmin mA/V
ICOMPHI
IDD0
VDD
0
VDDhyst
ICOMPLO
VDDoff
VD S= 35 V
Fsw = 0
VDDon VDD
IDDch
VDDreg
FC00170
FC00150
Figure 7.
Transition Time
Figure 8.
Shutdown Action
VOSC
ID
t
VCOMP
tDISsu
10% Ipeak
t
VDS
VCOMPth
90% VD
t
ID
10% VD
t
tf
tr
t
FC00160
ENABLE
ENABLE
DISABLE
FC00060
Figure 9.
Breakdown Voltage vs. Temperature Figure 10. Typical Frequency Variation
FC00190
FC00180
1.15
(%)
BVDSS
1
0
(Normalized)
1.1
-1
-2
1.05
-3
1
0.95
-4
-5
0
20
40 60 80 100 120
Temperature (°C)
0
20
40 60 80 100 120 140
Temperature (°C)
15/31
VIPer50A-E/ASP-E
5 Operation Description
Figure 11. Behaviour of the high voltage current source at start-up
VDD
2 mA
VDDon
VDDoff
15 mA
3 mA
VDD
1 mA
DRAIN
15 mA
CVDD
Ref.
t
Auxiliary primary
winding
UNDERVOLTAGE
LOCK OUT LOGIC
VIPer50
Start up duty cycle ~ 12%
Figure 12. Start-Up Waveforms
16/31
SOURCE
FC00320
VIPer50A-E/ASP-E
5 Operation Description
Figure 13. Over-temperature Protection
T
T ts c J
T t s d -T h y s t
Vdd
V dd on
V dd off
Id
V
co m p
0000 00 0 0 0 0 0 0 00000000000000000000000000 00 00
0000 0 0 0 0
00 0 00 0 00 00 00 00 00 00 0 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0000
000000
00 0
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t
00 00 0 0 0 0 0 0 0 0 0 0 0 0 0
0000000000000000
00000000 00 00 00 00 00 00 00 00 00 00 000000 00 0 0 0 00 00 00 00 00 00 000000 00 0 0 0
00
00 00 00 00 0 0 00 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0t
00 00 00 00 00 00 00 00 00 00 00 00 00 0 0
00 00 00 00 00
0
0
00 00 00 00 00 00 00 00 00 00 00 00 00
0 0000000000000000000000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 t
00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
00 0 0 0 0 0 0 0 0 0 0 0 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 0
00
00 0 0 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 t
SC 1 0 1 9 1
17/31
VIPer50A-E/ASP-E
5 Operation Description
Figure 14. Oscillator
For R t > 1.2kΩ and Ct ≤ 40KHz
VDD
Rt
O SC
550
2.3
F SW = ----------- ⋅ ⎛ 1 – --------------------⎞
R t – 150⎠
RtCt ⎝
Ct
~360Ω
CLK
FC 00050
Ct
Forbidden area
880
Ct(nF) =
22nF
Fsw(kHz)
15nF
Forbidden area
40kHz
Fsw
Oscillator frequency vs Rt and Ct
FC00030
1,000
Ct = 1.5 nF
500
Frequency (kHz)
Ct = 2.7 nF
300
Ct = 4.7 nF
200
Ct = 10 nF
100
50
30
1
2
3
5
Rt (kΩ)
18/31
10
20
30
50
VIPer50A-E/ASP-E
5 Operation Description
Figure 15. Error Amplifier frequency Response
FC00200
60
RCOMP = +∞
Voltage Gain (dB)
RCOMP = 270k
40
RCOMP = 82k
RCOMP = 27k
20
RCOMP = 12k
0
(20)
0.001
0.01
0.1
1
10
Frequency (kHz)
100
1,000
Figure 16. Error Amplifier Phase Response
FC00210
200
RCOMP = +∞
150
RCOMP = 270k
Phase (°)
RCOMP = 82k
RCOMP = 27k
100
RCOMP = 12k
50
0
(50)
0.001
0.01
0.1
1
10
Frequency (kHz)
100
1,000
19/31
VIPer50A-E/ASP-E
5 Operation Description
Figure 17. Mixed Soft Start and Compensation Figure 18. Latched Shut Down
D2
D3
VIPer50
VDD
VIPer50
R1
DRAIN
OSC
13V
VDD
R3
+
-
OSC
COMP SOURCE
13V
D1
AUXILIARY
WINDING
+
COMP SOURCE
R3
R2
R1
C4
R2
+ C3
DRAIN
Q2
R4
+ C2
C1
Shutdown
D1
Q1
FC00331
FC00340
Figure 19. Typical Compensation Network
Figure 20. Slope Compensation
VIPer50
VDD
DRAIN
-
OSC
13V
R2
R1
VIPer5 0
+
COMP
VD D
SOURCE
D RAIN
OS C
13V
+
C OM P
C2
R1
SO UR CE
C2
C1
Q1
C1
C3
R3
FC00351
FC 00361
Figure 21. External Clock Synchronization
Figure 22. Current Limitation Circuit Example
VIPer50
VDD
VIPer50
VDD
OSC
DRAIN
DRAIN
13V
+
COMP
-
OSC
13V
SOURCE
+
COMP SOURCE
10 kΩ
R1
Q1
R2
FC00370
FC00380
20/31
VIPer50A-E/ASP-E
6 Electrical Over Stress
6
Electrical Over Stress
6.1
Electrical Over Stress Ruggedness
The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or
lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages
most of the time. However in some cases, the voltage surges coupled through the transformer
auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events
may trigger the VDD internal protection circuitry which could be damaged by the strong
discharge current of the VDD bulk capacitor. The simple RC filter shown in Figure 23 can be
implemented to improve the application immunity to such surges.
Figure 23. Input Voltage Surges Protection
R1
D1
(Optional)
R2
39R
Auxilliary winding
C1
Bulk capacitor
VDD
C2
22nF
DRAIN
OSC
13V
VIPerXX0
+
COMP SOURCE
21/31
VIPer50A-E/ASP-E
7 Layout
7
Layout
7.1
Layout Considerations
Some simple rules insure a correct running of switching power supplies. They may be
classified into two categories:
–
Minimizing power loops: The switched power current must be carefully analysed and
the corresponding paths must be as small an inner loop area as possible. This avoids
radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a
better efficiency by eliminating parasitic inductances, especially on secondary side.
–
Using different tracks for low level and power signals: Interference due to mixing of
signal and power may result in instabilities and/or anomalous behavior of the device
in case of violent power surge (Input overvoltages, output short circuits...).
In case of VIPer, these rules apply as shown on (see Figure 24).
–
Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized.
–
C6 must be as close as possible to T1.
–
Signal components C2, ISO1, C3, and C4 are using a dedicated track connected
directly to the power source of the device.
Figure 24. Recommended Layout
T1
D1
C7
D2
R1
VDD
DRAIN
-
C1
OSC
13V
From input
diodes bridge
C5
+
COMP
SOURCE
U1
VIPerXX0
R2
C6
C2
C3
ISO1
C4
FC00500
22/31
To secondary
filtering and load
VIPer50A-E/ASP-E
8
8 Package Mechanical Data
Package Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second Level Interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com.
23/31
VIPer50A-E/ASP-E
8 Package Mechanical Data
Pentawatt HV Mechanical Data
mm.
inch
Dim
Min.
Typ.
Maw.
Min.
Typ.
A
4.30
4.80
0.169
0.189
C
1.17
1.37
0.046
0.054
D
2.40
2.80
0.094
0.11
E
0.35
0.55
0.014
0.022
F
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
0.382
H2
10.40
0.409
H3
10.05
10.40
L
15.60
17.30
6.14
0.681
L1
14.60
15.22
0.575
0.599
L2
21.20
21.85
0.835
0.860
L3
22.20
22.82
0.874
0.898
L5
2.60
3
0.102
0.118
L6
15.10
15.80
0.594
0.622
L7
6
6.60
0.236
0.260
M
2.50
3.10
0.098
0.122
M1
4.50
5.60
0.177
0.220
R
0.50
Diam
0.396
0.409
0.02
90°
V4
3.65
3.85
0.144
0.152
P023H3
24/31
Max.
VIPer50A-E/ASP-E
8 Package Mechanical Data
Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data
mm.
inch
Dim
Min.
Typ.
Maw.
Min.
Typ.
Max.
A
4.30
4.80
0.169
0.189
C
1.17
1.37
0.046
0.054
D
2.40
2.80
0.094
0.110
E
0.35
0.55
0.014
0.022
F
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
0.382
H2
10.40
0.409
H3
10.05
10.40
0.396
0.409
L
16.42
17.42
0.646
0.686
L1
14.60
15.22
0.575
0.599
L3
20.52
21.52
0.808
0.847
L5
2.60
3.00
0.102
0.118
L6
15.10
15.80
0.594
0.622
L7
6.00
6.60
0.236
0.260
M
2.50
3.10
0.098
0.122
M1
5.00
5.70
0.197
0.224
R
0.50
V4
90°
Diam
0.02
0.020
90°
3.65
3.85
0.144
0.154
L
L1
E
A
M
M1
C
D
R
Resin between
leads
L6
L7
V4
H2
H3
H1
G1
G2
F
DIA
L5
L3
25/31
VIPer50A-E/ASP-E
8 Package Mechanical Data
Figure 25. Pentawatt HV Tube Shipment ( no suffix )
Base Q.ty
50
Bulk Q.ty
1000
Tube length ( ± 0.5 )
532
A
18
B
33.1
C ( ± 0.1)
1
All dimensions are in mm.
26/31
VIPer50A-E/ASP-E
8 Package Mechanical Data
PowerSO-10 MECHANICAL DATA
mm
DIM.
MIN.
inch
MAX.
MIN.
A
3.35
TYP.
3.65
0.132
0.144
A1
0.00
0.10
0.000
0.004
B
0.40
0.60
0.016
0.024
C
0.35
0.55
0.013
0.022
D
9.40
9.60
0.370
0.378
D1
7.40
7.60
0.291
e
1.27
TYP.
MAX.
0.300
0.050
E
9.30
9.50
0.366
0.374
E1
7.20
7.40
0.283
0.291
E2
7.20
7.60
0.283
0.300
E3
6.10
6.35
0.240
0.250
E4
5.90
6.10
0.232
0.240
F
1.25
1.35
0.049
h
0.50
0.053
0.002
H
13.80
14.40
0.543
0.567
L
1.20
1.80
0.047
0.071
q
1.70
0.067
0o
α
8o
B
0.10 A B
10
=
E4
=
=
=
E1
=
E3
=
E2
=
E
=
=
=
H
6
=
=
1
5
B
e
0.25
SEATING
PLANE
DETAIL "A"
A
C
M
Q
D
h
= D1 =
=
=
SEATING
PLANE
A
F
A1
A1
L
DETAIL "A"
α
0068039-C
27/31
VIPer50A-E/ASP-E
8 Package Mechanical Data
PowerSO-10™ SUGGESTED PAD LAYOUT
TUBE SHIPMENT (no suffix)
14.6 - 14.9
CASABLANCA
B
10.8 - 11
MUAR
C
6.30
C
A
A
0.67 - 0.73
1
9.5
2
3
4
5
10
9
B
0.54 - 0.6
All dimensions are in mm.
8
7
1.27
Base Q.ty Bulk Q.ty Tube length (± 0.5)
6
Casablanca
Muar
50
50
1000
1000
532
532
A
B
C (± 0.1)
10.4 16.4
4.9 17.2
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
600
600
330
1.5
13
20.2
24.4
60
30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
24
4
24
1.5
1.5
11.5
6.5
2
All dimensions are in mm.
End
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
28/31
500mm min
0.8
0.8
VIPer50A-E/ASP-E
9
9 Order Codes
Order Codes
PENTAWATT HV
PENTAWATT HV (022Y)
PowerSO-10
VIPer50A-E
VIPer50A-22-E
VIPer50ASP-E
29/31
VIPer50A-E/ASP-E
10 Revision history
10
Revision history
Date
Revision
26-Sep-2005
1
30/31
Changes
Initial release.
VIPer50A-E/ASP-E
10 Revision history
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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www.st.com
31/31
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