VIPER50-E

VIPer50-E SMPS PRIMARY I.C. General Features Type VDSS In RDS(on) VIPer50-E 620V 1.5A 5Ω ■ ADJUSTABLE SWITCHING FREQUENCY UP TO 200 kHz ■ CURRENT MODE CONTROL ■ SOFT START AND SHUTDOWN CONTROL ■ AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET “BLUE ANGEL” NORM ( -------------------V DD hyst IDD is the consumption current on the VDD pin when switching. Refer to specified I DD1 and IDD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. 12/29 VIPer50-E 5 Operation Description VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value). The soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. If the device is intentionally shut down by tying the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff. This voltage can be used for supplying external functions, provided that their consumption does not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state until the input voltage is removed. 5.4 Transconductance Error Amplifier ) s t( The VIPer50-E includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP) versus change in input voltage (V DD). Thus: c u d ∂l COMP G m = ------------------∂V DD o r P The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: V e t le V ∂ CO MP 1 ∂ COMP - = -------- × ------------------------Z CO MP = -------------------I G ∂V DD m ∂ COMP o s b O - This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: AVOL = Gm x ZCOMP ) s ( ct where Gm value for VIPer50-E is 1.5 mA/V typically. Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define the transfer function F of the error amplifier more accurately, according to the following equation (very similar to the one above): u d o r P e F(S) = Gm x Z(S) The error amplifier frequency response is reported in Figure 10. for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330KΩ. More complex impedance can be connected on the COMP pin to achieve different compensation level. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated in Figure 20 s b O t e l o As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to avoid any high frequency interference. Is also possible to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. 13/29 VIPer50-E 5 Operation Description 5.5 External Clock Synchronization: The OSC pin provides a synchronisation capability when connected to an external frequency source. Figure 21 shows one possible schematic to be adapted, depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor. 5.6 Primary Peak Current Limitation The primary IDPEAK current and, consequently, the output power can be limited using the simple circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clamps the voltage on the COMP pin in order to limit the primary peak current of the device to a value: V COMP – 0.5 I D PEAK = -------------------------------H ID where: c u d R1 + R 2 V COMP = 0.6 × ------------------R2 The suggested value for R1+R2 is in the range of 220KΩ. 5.7 e t le Over-Temperature Protection o s b O - ) s t( o r P Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is 170ºC. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 13) ) s ( ct u d o r P e t e l o s b O 14/29 VIPer50-E 5.8 5 Operation Description Operation Pictures Figure 5. VDD Regulation Point ICOMP Figure 6. Undervoltage Lockout IDD Slope = Gmin mA/V ICOMPHI IDD0 VDD 0 VDDhyst ICOMPLO VDDoff VD S= 35 V Fsw = 0 VDDon VDD IDDch VDDreg FC00170 FC00150 Figure 7. Transition Time Figure 8. c u d Shutdown Action VOSC ID e t le VCOMP 10% Ipeak t VDS so VCOMPth 90% VD 10% VD t tf ) s ( ct tr FC00160 Figure 9. u d o r P e BVDSS tDISsu t ID t ENABLE ENABLE DISABLE FC00060 1.1 FC00190 FC00180 t e l o (Normalized) O b O - t Breakdown Voltage vs. Temperature Figure 10. Typical Frequency Variation 1.15 bs o r P ) s t( (%) 1 0 -1 -2 1.05 -3 1 0.95 -4 -5 0 20 40 60 80 100 120 Temperature (°C) 0 20 40 60 80 100 120 140 Temperature (°C) 15/29 VIPer50-E 5 Operation Description Figure 11. Behaviour of the high voltage current source at start-up VDD 2 mA VDDon VDDoff 15 mA DRAIN 3 mA VDD 1 mA 15 mA CVDD Ref. t Auxiliary primary winding UNDERVOLTAGE LOCK OUT LOGIC VIPer50 SOURCE Start up duty cycle ~ 12% FC00320 c u d Figure 12. Start-Up Waveforms e t le ) s ( ct u d o r P e t e l o s b O 16/29 o s b O - o r P ) s t( VIPer50-E 5 Operation Description Figure 13. Over-temperature Protection T T ts c J T t s d -T h y s t Vdd V dd on V dd off Id V co m p 0000 00 0 0 0 0 0 0 00000000000000000000000000 00 00 0000 0 0 0 0 00 0 00 0 00 00 00 00 00 00 0 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0000 000000 00 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0000000000000000 00000000 00 00 00 00 00 00 00 00 00 00 000000 00 0 0 0 00 00 00 00 00 00 000000 00 0 0 0 00 00 00 00 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0t 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 00 00 00 00 00 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0000000000000000000000000 ) s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 t t( 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 00 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 0 odu 00 00 0 0 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Pr 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e 00 00 00 00t00 00e00 00 00 00 00 00 00 00 00 t l ) s ( ct o s b O - SC 1 0 1 9 1 u d o r P e t e l o s b O 17/29 VIPer50-E 5 Operation Description Figure 14. Oscillator For R t > 1.2kΩ and Ct ≤ 40KHz VDD Rt O SC 550 2.3 F SW = ----------- ⋅ ⎛ 1 – --------------------⎞ R t – 150⎠ RtCt ⎝ ~360Ω CLK Ct FC 00050 Ct c u d Forbidden area 880 Ct(nF) = 22nF Fsw(kHz) e t le 15nF o s b O - Forbidden area ) s ( ct o r P e 1,000 s b O 40kHz Fsw Oscillator frequency vs Rt and Ct FC00030 Ct = 1.5 nF 500 Frequency (kHz) t e l o du Ct = 2.7 nF 300 Ct = 4.7 nF 200 Ct = 10 nF 100 50 30 1 2 3 5 Rt (kΩ) 18/29 o r P 10 20 30 50 ) s t( VIPer50-E 5 Operation Description Figure 15. Error Amplifier frequency Response FC00200 60 RCOMP = +∞ Voltage Gain (dB) RCOMP = 270k 40 RCOMP = 82k RCOMP = 27k 20 RCOMP = 12k 0 (20) 0.001 0.01 0.1 1 10 Frequency (kHz) Figure 16. Error Amplifier Phase Response 200 s b O t e l o Phase (°) o r P e du e t le o s b O - ct 150 100 (s) 100 1,000 c u d ) s t( o r P FC00210 RCOMP = +∞ RCOMP = 270k RCOMP = 82k RCOMP = 27k RCOMP = 12k 50 0 (50) 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1,000 19/29 VIPer50-E 5 Operation Description Figure 17. Mixed Soft Start and Compensation Figure 18. Latched Shut Down D2 D3 VIPer50 VDD VIPer50 R1 DRAIN VDD OSC 13V DRAIN Q2 R3 + - OSC + 13V COMP SOURCE D1 COMP SOURCE AUXILIARY WINDING R3 R2 R1 C4 R2 + C3 R4 Shutdown + C2 C1 D1 Q1 FC00340 FC00331 Figure 19. Typical Compensation Network Figure 20. Slope Compensation VIPer50 VDD DRAIN - OSC 13V R2 c u d R1 VIPer5 0 + COMP VD D SOURCE D RAIN o r P - OS C 13V + C OM P e t le R1 C2 C1 o s b O C1 (s) FC00351 ct Figure 21. External Clock Sinchronisation o r P e t e l o bs O du SO UR CE C2 Q1 C3 R3 FC 00361 Figure 22. Current Limitation Circuit Example VIPer50 VDD 13V DRAIN DRAIN - OSC VIPer50 VDD + COMP - SOURCE OSC 13V + COMP SOURCE 10 kΩ R1 Q1 R2 FC00370 FC00380 20/29 ) s t( VIPer50-E 6 Electrical Over Stress 6 Electrical Over Stress 6.1 Electrical Over Stress Ruggedness The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages most of the time. However in some cases, the voltage surges coupled through the transformer auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events may trigger the VDD internal protection circuitry which could be damaged by the strong discharge current of the VDD bulk capacitor. The simple RC filter shown in Figure 23 can be implemented to improve the application immunity to such surges. Figure 23. Input Voltage Surges Protection D1 R1 (Optional) c u d R2 39R ) s t( ro Auxilliary winding VDD C1 Bulk capacitor C2 P e let DRAIN - 22nF OSC 13V VIPerXX0 ) s ( ct + o s b O - COMP SOURCE u d o r P e t e l o s b O 21/29 VIPer50-E 7 Layout 7 Layout 7.1 Layout Considerations Some simple rules insure a correct running of switching power supplies. They may be classified into two categories: – Minimizing power loops: The switched power current must be carefully analysed and the corresponding paths must be as small an inner loop area as possible. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. – Using different tracks for low level and power signals: Interference due to mixing of signal and power may result in instabilities and/or anomalous behaviour of the device in case of violent power surge (Input overvoltages, output short circuits...). In case of VIPer, these rules apply as shown on (see Figure 24). – Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized. – C6 must be as close as possible to T1. – Signal components C2, ISO1, C3, and C4 are using a dedicated track connected directly to the power source of the device. c u d Figure 24. Recommended Layout e t le T1 D1 o s b O - C7 D2 R1 (s) VDD - C1 ct OSC 13V From input diodes bridge u d o U1 VIPerXX0 r P e t e l o s b O 22/29 + COMP R2 o r P DRAIN C5 SOURCE C6 C2 C3 ISO1 C4 FC00500 To secondary filtering and load ) s t( VIPer50-E 8 8 Package Mechanical Data Package Mechanical Data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 23/29 VIPer50-E 8 Package Mechanical Data Pentawatt HV Mechanical Data mm. inch Dim Min. Typ. Maw. Min. Typ. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.11 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 H2 10.40 10.05 10.40 L 15.60 17.30 6.14 L1 14.60 15.22 0.575 L2 21.20 21.85 L3 22.20 22.82 L5 2.60 3 L6 15.10 15.80 P e let L7 6 M 2.50 M1 4.50 R 0.50 o r P e Diam 3.65 (s) 0.396 ro c u d 0.835 0.409 0.681 0.599 0.860 0.874 0.898 0.102 0.118 0.594 0.622 6.60 0.236 0.260 3.10 0.098 0.122 5.60 0.177 0.220 o s b O - ct du ) s t( 0.409 H3 V4 0.02 90° 3.85 0.144 0.152 t e l o s b O P023H3 24/29 Max. VIPer50-E 8 Package Mechanical Data Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data mm. inch Dim Min. Typ. Maw. Min. Typ. Max. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.110 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 H2 10.40 H3 10.05 10.40 0.396 L 16.42 17.42 0.646 L1 14.60 15.22 0.575 L3 20.52 21.52 L5 2.60 3.00 L6 15.10 15.80 L7 6.00 6.60 P e let M 2.50 M1 5.00 R 0.50 V4 90° Diam 3.65 c u d ro 0.409 0.686 0.599 0.847 0.102 0.118 0.594 0.622 0.236 0.260 3.10 0.098 0.122 5.70 0.197 0.224 0.02 0.020 90° 3.85 0.144 0.154 L o r P e ct du 0.808 o s b O - (s) ) s t( 0.409 L1 t e l o E A M M1 C D R s b O Resin between leads L6 L7 V4 H2 H3 H1 G1 G2 F DIA L5 L3 25/29 VIPer50-E 8 Package Mechanical Data Figure 25. Pentawatt HV Tube Shipment ( no suffix ) Base Q.ty 50 Bulk Q.ty 1000 Tube length ( ± 0.5 ) 532 A 18 B 33.1 C ( ± 0.1) 1 All dimensions are in mm. c u d e t le ) s ( ct u d o r P e t e l o s b O 26/29 o s b O - o r P ) s t( VIPer50-E 9 9 Order Codes Order Codes PENTAWATT HV PENTAWATT HV (022Y) VIPer50-E VIPer50-22-E c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 27/29 VIPer50-E 10 Revision history 10 Revision history Date Revision 26-Sep-2005 1 Changes Initial release. c u d e t le ) s ( ct u d o r P e t e l o s b O 28/29 o s b O - o r P ) s t( VIPer50-E 10 Revision history c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. t e l o s b O The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 29/29