VIPer50/SP
- VIPer50A/ASP
®
SMPS PRIMARY I.C.
TYPE
VIPer50/SP
VIPer50A/ASP
VDSS
620V
700V
■ ADJUSTABLE
In
1.5 A
1.5 A
RDS(on)
5Ω
5.7 Ω
SWITCHING FREQUENCY UP
TO 200 kHz
■ CURRENT MODE CONTROL
■ SOFT START AND SHUT DOWN CONTROL
■ AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
“BLUE ANGEL” NORM (1.2KΩ
and
Ct ≥ 15nF if FSW ≤ 40KHz
VDD
Rt
OSC
2.3
550
F SW = ------------ ⋅ 1 – ----------------------
R t Ct
Rt – 150
Ct
~360Ω
CLK
FC00050
Ct
c
u
d
Forbidden area
880
e
t
le
Ct(nF) =
22nF
15nF
Forbidden area
(s)
t
c
u
od
s
b
O
t
e
l
o
Frequency (kHz)
r
P
e
1,000
Fsw(kHz)
o
s
b
O
40kHz
)
s
t(
o
r
P
Fsw
Oscillator frequency vs Rt and Ct
FC00030
Ct = 1.5 nF
500
Ct = 2.7 nF
300
Ct = 4.7 nF
200
Ct = 10 nF
100
50
30
1
2
3
5
10
20
30
50
Rt (kΩ)
8/23
1
VIPer50/SP - VIPer50A/ASP
Figure 10: Error Amplifier Frequency Response
FC00200
60
RCOMP = +∞
Voltage Gain (dB)
RCOMP = 270k
40
RCOMP = 82k
RCOMP = 27k
20
RCOMP = 12k
0
(20)
0.001
0.01
0.1
1
10
Frequency (kHz)
e
t
le
Figure 11: Error Amplifier Phase Response
)
s
(
ct
200
150
t
e
l
o
s
b
O
Phase (°)
o
r
P
e
100
100
o
s
b
O
-
du
c
u
d
)
s
t(
o
r
P
1,000
FC00210
RCOMP = +∞
RCOMP = 270k
RCOMP = 82k
RCOMP = 27k
RCOMP = 12k
50
0
(50)
0.001
0.01
0.1
1
10
Frequency (kHz)
100
1,000
9/23
1
VIPer50/SP - VIPer50A/ASP
Figure 12: Avalanche Test Circuit
L1
1mH
2
VDD
1
3
DRAIN
OSC
13V
BT1
0 to 20V
+
COMP
BT2
12V
C1
47uF
16V
Q1
2 x STHV102FI in parallel
R1
47
SOURCE
5
4
GENERATOR INPUT
500us PULSE
U1
VIPer100
R2
1k
c
u
d
R3
100
)
s
t(
o
r
P
FC00195
e
t
le
)
s
(
ct
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
10/23
1
VIPer50/SP - VIPer50A/ASP
Figure 13: Off Line Power Supply With Auxiliary Supply Feedback
F1
C1
BR1
TR2
TR1
D2
AC IN
L2
+Vcc
D1
R9
C2
C7
C9
R1
C3
GND
D3
C10
R7
C4
R2
VDD
DRAIN
OSC
+
13V
c
u
d
VIPer50
COMP SOURCE
C5
C6
C11
R3
o
s
b
O
-
Figure 14: Off Line Power Supply With Optocoupler Feedback
F1
BR1
TR2
C1
TR 1
AC IN
R9
(t s)
C2
uc
o
r
P
FC00301
D2
L2
+V cc
D1
C7
C9
R1
C3
GND
D3
od
r
P
e
e
t
le
)
s
t(
C1 0
R7
C4
R2
s
b
O
t
e
l
o
V DD
DR AIN
O SC
13V
V IP er50
+
COMP
C5
C 11
S O UR C E
C6
R6
IS O 1
R3
R4
C8
U2
R5
F C 0 0311
11/23
1
VIPer50/SP - VIPer50A/ASP
OPERATION DESCRIPTION:
CURRENT MODE TOPOLOGY
The current mode control method, like the one
integrated in the VIPer50/50A uses two control
loops - an inner current control loop and an outer
loop for voltage control. When the Power
MOSFET output transistor is on, the inductor
current (primary side of the transformer) is
monitored with a SenseFET technique and
converted into a voltage VS proportional to this
current. When VS reaches VCOMP (the amplified
output voltage error) the power switch is switched
off. Thus, the outer voltage control loop defines
the level at which the inner loop regulates peak
current through the power switch and the primary
winding of the transformer.
Excellent D.C. open loop and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation, instantaneous correction to line
changes and better stability for the voltage
regulation loop.
Current mode topology also ensures good
limitation in the case of short circuit. During the
first phase the output current increases slowly
following the dynamic of the regulation loop. Then
it reaches the maximum limitation current
internally set and finally stops because the power
supply on VDD is no longer correct. For specific
applications the maximum peak current internally
set can be overridden by limiting the voltage
excursion externally on the COMP pin. An
integrated blanking filter inhibits the PWM
comparator output for a short time after the
integrated Power MOSFET is switched on. This
function prevents anomalous or premature
termination of the switching pulse in the case of
current spikes caused by primary side capacitance
or secondary side rectifier reverse recovery time.
)
s
(
ct
t
e
l
o
STAND-BY MODE
Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary side.
The transition from normal operation to burst
mode operation happens for a power PSTBY given
by:
O
bs
2
1
P STBY = --- L I STBY F
SW
2 P
Where:
LP is the primary inductance of the transformer.
tb + td is the sum of the blanking time and of the
propagation time of the internal current sense and
comparator, and roughly represents the minimum
on time of the device. Note that PSTBY may be
affected by the efficiency of the converter at low
load, and must include the power drawn on the
primary auxiliary voltage.
As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (VCOMP < VCOMPth). This situation leads to
the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as VDD gets
back to the regulation level and the VCOMPth
threshold is reached, the device operates again.
The above cycle repeats itself indefinitely,
providing a burst mode of which the effective duty
cycle is much lower than the minimum one when in
normal operation. The equivalent switching
frequency is also lower than the normal one,
leading to a reduced consumption on the input
mains lines. This mode of operation allows the
VIPer50/50A to meet the new German "Blue
Angel" Norm with less than 1W total power
consumption for the system when working in
stand-by. The output voltage remains regulated
around the normal level, with a low frequency
ripple corresponding to the burst mode. The
amplitude of this ripple is low, because of the
output capacitors and because of the low output
current drawn in such conditions. The normal
operation resumes automatically when the power
gets back levels which are higher than PSTBY.
c
u
d
e
t
le
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
FSW is the normal switching frequency.
ISTBY is the minimum controllable current,
corresponding to the minimum on time that the
device is able to provide in normal operation. This
current can be computed as:
( t b + td )V IN
I STBY = -------------------------------L
P
HIGH
VOLTAGE
START-UP
CURRENT
SOURCE
An integrated high voltage current source provides
a bias current from the DRAIN pin during the startup phase. This current is partially absorbed by
internal control circuits which are placed into a
standby mode with reduced consumption and are
also provided to the external capacitor connected
to the VDD pin. As soon as the voltage on this pin
reaches the high voltage threshold VDDon of the
12/23
VIPer50/SP - VIPer50A/ASP
where:
IDD is the consumption current on the VDD pin
when switching. Refer to specified IDD1 and IDD2
values.
tSS is the start up time of the converter when the
device begins to switch. Worst case is generally at
full load.
VDDhyst is the voltage hysteresis of the UVLO
logic. Refer to the minimum specified value.
Soft start feature can be implemented on the
COMP pin through a simple capacitor which will
also be used as the compensation network. In this
case, the regulation loop bandwidth is rather low,
because of the large value of this capacitor. In
case of a large regulation loop bandwidth is
mandatory, the schematics in figure 16 can be
used. It mixes a high performance compensation
network together with a separate high value soft
start capacitor. Both soft start time and regulation
loop bandwidth can be adjusted separately.
If the device is intentionally shut down by putting
the COMP pin to ground, the device is also
performing start-up cycles, and the VDD voltage is
oscillating between VDDon and VDDoff.
This voltage can be used for supplying external
functions, provided that their consumption doesn’t
exceed 0.5mA. Figure 17 shows a typical
application of this function, with a latched shut
down. Once the "Shutdown" signal has been
activated, the device remains in the off state until
the input voltage is removed.
UVLO logic, the device turns into active mode and
starts switching.
The start up current generator is switched off, and
the converter should normally provide the needed
current on the VDD pin through the auxiliary
winding of the transformer, as shown on figure 15.
In case of abnormal condition where the auxiliary
winding is unable to provide the low voltage supply
current to the VDD pin (i.e. short circuit on the
output of the converter), the external capacitor
discharges itself down to the low threshold voltage
VDDoff of the UVLO logic, and the device gets back
to the inactive state where the internal circuits are
in standby mode and the start up current source is
activated. The converter enters an endless start
up cycle, with a start-up duty cycle defined by the
ratio of charging current towards discharging when
the VIPer50/50A tries to start. This ratio is fixed by
design from 2 to 15, which gives a 12% start up
duty cycle while the power dissipation at start up is
approximately 0.6 W, for a 230 Vrms input voltage.
This low value of start-up duty cycle prevents the
stress of the output rectifiers and of the
transformer when in short circuit.
The external capacitor CVDD on the VDD pin must
be sized according to the time needed by the
converter to start up, when the device starts
switching. This time tSS depends on many
parameters, among which transformer design,
output capacitors, soft start feature and
compensation network implemented on the COMP
pin. The following formula can be used for defining
the minimum capacitor needed:
I DD tSS
CVDD > -------------------------V DDhyst
)
s
(
ct
c
u
d
e
t
le
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
Figure 15: Behavior of the high voltage current source at start-up
r
P
e
VDD
2 mA
t
e
l
o
VDDon
VDDoff
O
bs
15 mA
3 mA
VDD
1 mA
DRAIN
15 mA
CVDD
Ref.
t
Auxiliary primary
winding
UNDERVOLTAGE
LOCK OUT LOGIC
VIPer50
Start up duty cycle ~ 12%
SOURCE
FC00320
13/23
VIPer50/SP - VIPer50A/ASP
TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer50/50A includes a transconductance
error amplifier. Transconductance Gm is the
change in output current (ICOMP) versus change in
input voltage (VDD). Thus:
G
∂I COMP
-----------------------=
m
∂V DD
The output impedance ZCOMP at the output of this
amplifier (COMP pin) can be defined as:
∂V COMP
∂V COMP
1
Z COMP = --------------------------- = --------- × --------------------------G
∂V DD
∂I COMP
m
This last equation shows that the open loop gain
AVOL can be related to Gm and ZCOMP:
AVOL = Gm x ZCOMP
where Gm value for VIPer50/50A is 1.5 mA/V
typically.
Gmis well defined by specification, but ZCOMP and
therefore AVOL are subject to large tolerances. An
impedance Z can be connected between the
COMP pin and ground in order to define more
accurately the transfer function F of the error
amplifier, according to the following equation, very
similar to the one above:
F(S) = Gm x Z(S)
The error amplifier frequency response is reported
in figure 10 for different values of a simple
resistance connected on the COMP pin. The
unloaded transconductance error amplifier shows
an internal ZCOMP of about 330 KΩ. More complex
impedance can be connected on the COMP pin to
)
s
(
ct
u
d
o
t
e
l
o
VDD
s
b
O
+ C3
As shown in figure 18 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
any high frequency interference.
It can also be interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50%. Figure 19 shows
such a configuration. Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
EXTERNAL CLOCK SYNCHRONIZATION
The OSC pin provides a synchronisation
capability, when connected to an external
frequency source. Figure 20 shows one possible
schematic to be adapted depending on the
specific needs. If the proposed schematic is used,
the pulse duration must be kept at a low value
(500ns is sufficient) for minimizing consumption.
The optocoupler must be able to provide 20mA
through the optotransistor.
c
u
d
e
t
le
o
r
P
PRIMARY PEAK CURRENT LIMITATION
The primary IDPEAK current and, as resulting
effect, the output power can be limited using the
simple circuit shown in figure 21. The circuit based
on Q1, R1 and R2 clamps the voltage on the
Figure 17: Latched Shut Down
D2
D3
VIPer50
VIPer50
R1
DRAIN
VDD
-
OSC
13V
)
s
t(
o
s
b
O
-
Figure 16: Mixed Soft Start and Compensation
r
P
e
achieve different compensation laws. A capacitor
will provide an integrator function, thus eliminating
the DC static error, and a resistance in series
leads to a flat gain at higher frequency, insuring a
correct phase margin. This configuration is
illustrated in figure 18.
Q2
R3
+
13V
COMP SOURCE
D1
DRAIN
-
OSC
+
COMP SOURCE
AUXILIARY
WINDING
R3
R2
R1
C4
R2
C1
R4
Shutdown
+ C2
FC00331
Q1
D1
FC00340
14/23
VIPer50/SP - VIPer50A/ASP
COMP pin in order to limit the primary peak current
of the device to a value:
– 0.5
V
COMP
IDPEAK = ------------------------------------H ID
where:
R1 + R2
V COMP = 0.6 × ---------------------R2
OVER-TEMPERATURE PROTECTION:
Over-temperature protection is based on chip
temperature sensing. The minimum junction
temperature at which over-temperature cut-out
occurs is 140ºC while the typical value is 170ºC.
The device is automatically restarted when the
junction temperature decreases to the restart
temperature threshold that is typically 40ºC below
the shutdown value (see figure 8).
The suggested value for R1+R2 is in the range of
220KΩ.
Figure 18: Typical Compensation Network
Figure 19: Slope Compensation
c
u
d
VIPer50
VDD
DRAIN
R2
R1
-
OSC
13V
o
r
P
)
s
t(
V IP er50
VD D
+
COMP
SOURCE
e
t
le
O SC
R1
C2
C1
o
s
b
O
C1
)
s
(
ct
DRAIN
-
13V
+
COM P
SO U RCE
C2
Q1
C3
R3
FC00351
u
d
o
Figure 20: External Clock Synchronization
Figure 21: Current Limitation Circuit Example
r
P
e
s
b
O
t
e
l
o
FC 00361
VIPer50
VDD
13V
VIPer50
VDD
DRAIN
-
OSC
+
COMP
SOURCE
DRAIN
OSC
13V
+
COMP SOURCE
R1
10 kΩ
Q1
R2
FC00370
FC00380
15/23
VIPer50/SP - VIPer50A/ASP
Figure 22: Input Voltage Surges Protection
D1
R1
(Optional)
R2
39R
Auxilliary winding
VDD
C1
Bulk capacitor
C2
DRAIN
OSC
22nF
13V
+
COMP SOURCE
VIPerXX0
c
u
d
e
t
le
ELECTRICAL OVER STRESS RUGGEDNESS
The VIPer may be submitted to electrical over
stress caused by violent input voltage surges or
lightning. Following the enclosed Layout
Considerations chapter rules is the most of the
time sufficient to prevent catastrophic damages,
however in some cases the voltage surges
coupled through the transformer auxiliary winding
)
s
(
ct
)
s
t(
o
r
P
can overpass the VDD pin absolute maximum
rating voltage value. Such events may trigger the
VDD internal protection circuitry which could be
damaged by the strong discharge current of the
VDD bulk capacitor. The simple RC filter shown in
figure 22 can be implemented to improve the
application immunity to such surges.
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
16/23
VIPer50/SP - VIPer50A/ASP
Figure 23: Recommended Layout
T1
D1
C7
D2
R1
2
7RVHFRQGDU\
ILOWHULQJDQGORDG
3
VDD
DRAIN
-
C1
1 OSC
13V
)URPLQSXW
C5
+
COMP
GLRGHVEULGJH
SOURCE
5
U1
VIPerXX0
4
R2
C6
C2
C3
ISO1
c
u
d
C4
)
s
t(
FC00500
LAYOUT CONSIDERATIONS
Some simple rules insure a correct running of
switching power supplies. They may be classified
into two categories:
- To minimize power loops: the way the switched
power current must be carefully analyzed and
the corresponding paths must present the
smallest possible inner loop area. This avoids
radiated EMC noises, conducted EMC noises
by magnetic coupling, and provides a better
efficiency by eliminating parasitic inductances,
especially on secondary side.
)
s
(
ct
u
d
o
e
t
le
o
r
P
- To use different tracks for low level signals and
power ones. The interferences due to a mixing
of signal and power may result in instabilities
and/or anomalous behavior of the device in
case of violent power surge (Input overvoltages,
output short circuits...).
In case of VIPer, these rules apply as shown in
figure 23. The loops C1-T1-U1, C5-D2-T1, C7-D1T1 must be minimized. C6 must be as close as
possible to T1. The signal components C2, ISO1,
C3 and C4 use a dedicated track to be connected
directly to the source of the device.
o
s
b
O
-
r
P
e
t
e
l
o
s
b
O
17/23
1
VIPer50/SP - VIPer50A/ASP
PowerSO-10™ MECHANICAL DATA
mm.
DIM.
MIN.
A
A (*)
A1
B
B (*)
C
C (*)
D
D1
E
E2
E2 (*)
E4
E4 (*)
e
F
F (*)
H
H (*)
h
L
L (*)
α
α (*)
inch
TYP
3.35
3.4
0.00
0.40
0.37
0.35
0.23
9.40
7.40
9.30
7.20
7.30
5.90
5.90
MIN.
3.65
3.6
0.10
0.60
0.53
0.55
0.32
9.60
7.60
9.50
7.60
7.50
6.10
6.30
0.132
0.134
0.000
0.016
0.014
0.013
0.009
0.370
0.291
0.366
0.283
0.287
0.232
0.232
1.35
1.40
14.40
14.35
0.049
0.047
0.543
0.545
1.80
1.10
8º
8º
0.047
0.031
0º
2º
TYP.
e
t
le
0.50
H
E
r
P
e
t
e
l
o
(s)
o
s
b
O
-
0.053
0.055
0.567
0.565
0.002
0.070
0.043
8º
8º
0.10 A B
E2
E4
1
SEATING
PLANE
e
B
DETAIL "A"
A
C
0.25
h
o
r
P
)
s
t(
B
ct
u
d
o
c
u
d
0.050
1.20
0.80
0º
2º
10
MAX.
0.144
0.142
0.004
0.024
0.021
0.022
0.0126
0.378
0.300
0.374
300
0.295
0.240
0.248
1.27
1.25
1.20
13.80
13.85
(*) Muar only POA P013P
s
b
O
MAX.
D
= D1 =
=
=
SEATING
PLANE
A
F
A1
A1
L
DETAIL "A"
α
P095A
18/23
VIPer50/SP - VIPer50A/ASP
PENTAWATT HV MECHANICAL DATA
mm.
DIM.
MIN.
TYP
inch
MAX.
MIN.
TYP.
MAX.
A
4.30
4.80
0.169
0.189
C
1.17
1.37
0.046
0.054
D
2.40
2.80
0.094
0.11
E
0.35
0.55
0.014
0.022
F
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
H2
0.382
10.40
10.05
H3
0.409
10.40
0.396
L
15.60
17.30
6.14
L1
14.60
15.22
0.575
L2
21.20
21.85
0.835
L3
22.20
22.82
0.874
)
s
t(
0.409
0.681
uc
0.599
Pr
od
0.860
0.898
L5
2.60
3
0.102
L6
15.10
15.80
0.594
L7
6
6.60
0.236
0.098
0.122
0.177
0.220
M
2.50
3.10
M1
4.50
5.60
R
0.50
V4
e
t
le
so
b
O
-
0.118
0.622
0.260
0.02
Diam
90° (typ)
3.65
)
s
(
ct
3.85
0.144
0.152
u
d
o
r
P
e
t
e
l
o
s
b
O
P023H3
19/23
1
VIPer50/SP - VIPer50A/ASP
PENTAWATT HV 022Y (VERTICAL HIGH PITCH) MECHANICAL DATA
mm.
DIM.
MIN.
inch
TYP
MAX.
MIN.
TYP.
MAX.
A
4.30
4.80
0.169
0.189
C
1.17
1.37
0.046
0.054
D
2.40
2.80
0.094
0.110
E
0.35
0.55
0.014
0.022
F
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
0.382
H3
10.05
10.40
0.396
L
16.42
17.42
0.646
L1
14.60
15.22
0.575
L3
20.52
21.52
0.808
H2
10.40
)
s
t(
0.409
0.409
uc
0.686
Pr
od
0.599
0.847
L5
2.60
3.00
0.102
L6
15.10
15.80
0.594
L7
6.00
6.60
0.236
M
2.50
3.10
0.098
0.122
M1
5.00
5.70
0.197
0.224
R
0.50
V4
90°
Diam.
3.70
90°
3.90
0.146
0.154
L1
A
C
D
R
t
e
l
o
0.020
M
M1
r
P
e
b
O
-
E
u
d
o
so
0.260
L
)
s
(
ct
e
t
le
0.118
0.622
Resin between
leads
L6
s
b
O
L7
V4
H2
H3
H1
G1
G2
F
DIA
L5
L3
20/23
1
VIPer50/SP - VIPer50A/ASP
PowerSO-10™ SUGGESTED PAD LAYOUT
TUBE SHIPMENT (no suffix)
14.6 - 14.9
CASABLANCA
B
10.8- 11
MUAR
C
6.30
C
A
A
0.67 - 0.73
10
9
1
9.5
2
3
B
0.54 - 0.6
All dimensions are in mm.
8
7
4
5
1.27
Base Q.ty Bulk Q.ty Tube length (± 0.5)
6
Casablanca
Muar
50
50
1000
1000
532
532
A
B
C (± 0.1)
10.4 16.4
4.9 17.2
0.8
0.8
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
e
t
le
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
u
d
o
r
P
e
t
e
l
o
All dimensions are in mm.
bs
)
s
(
ct
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
o
s
b
O
-
600
600
330
1.5
13
20.2
24.4
60
30.4
o
r
P
c
u
d
)
s
t(
All dimensions are in mm.
24
4
24
1.5
1.5
11.5
6.5
2
End
O
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
21/23
1
VIPer50/SP - VIPer50A/ASP
PENTAWATT HV TUBE SHIPMENT (no suffix)
B
C
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
50
1000
532
18
33.1
1
c
u
d
All dimensions are in mm.
A
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
22/23
1
VIPer50/SP - VIPer50A/ASP
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
s
b
O
2003 STMicroelectronics - Printed in ITALY- All Rights Reserved.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
23/23
1