VIPER53SP-E

VIPer53 - E OFF-line primary switch General features Type DIP-8 PowerSO-10TM European (195 - 265Vac) 50W 65W US / Wide range (85 - 265 Vac) 30W 40W PowerSO-10 DIP-8 Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Switching frequency up to 300kHz Current limitation Current mode control with adjustable limitation Soft start and shut-down control Automatic burst mode in standby condition (“Blue Angel“ compliant ) Undervoltage lockout with Hysteresis HIgh voltage star-tup current source Overtemperature protection Overload and short-circuit control Description The VIPer53-E combines an enhanced current mode PWM controller with a high voltage MDMesh Power Mosfet in the same package. Typical applications cover offline power supplies with a secondary power capability ranging up to 30W in wide range input voltage, or 50W in single European voltage range and DIP-8 package, with the following benefits: ■ ■ ■ Overload and short circuit controlled by feedback monitoring and delayed device reset. Efficient standby mode by enhanced pulse skipping. Primary regulation or secondary loop failure protection through high gain error amplifier. DRAIN Block diagram OSC ON/OFF OSCILLAT OR PW M LATCH OVERT EMP. DET ECT OR R1 S FF Q R2 R3 R4 R5 BLANKING TIME SELECTION 1V UVLO COMPARATOR VDD 8.4/ 11.5V 0.5V STANDBY COMPARATOR 4V 150/400ns BLANKING PW M COMPARATOR 8V 0.5V HCOM P CURRENT AMPLIFIER 15V ERROR AMPLIFIER 125k 4.35V OVERLOAD COMPARATOR OVERVOLTAGE COMPARATOR 18V 4.5V T OVL COMP SOURCE November 2006 Rev 1 1/36 www.st.com 36 Contents VIPer53 - E Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Primary regulation configuration example . . . . . . . . . . . . . . . . . . . . . . 15 Secondary feedback configuration example . . . . . . . . . . . . . . . . . . . . 17 Current mode topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 High voltage Start-up current source . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Short-circuit and overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transconductance error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Special recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2/36 VIPer53 - E Electrical data 1 1.1 Electrical data Maximum rating Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 1. Symbol VDS ID VDD VOSC ICOMP ITOVL VESD TJ TC TSTG Absolute maximum rating Parameter Continuous drain source voltage (TJ= 25 ... 125°C) (1) Continuous drain current Supply voltage OSC input voltage range COMP and TOVL input current range (1) Electrostatic discharge: Machine model (R = 0Ω; C = 200pF) Charged device model Junction operating temperature Case operating temperature Storage temperature Value -0.3 ... 620 Internally limited 0 ... 19 0 ... VDD -2 ... 2 Unit V A V V mA 200 1.5 Internally limited -40 to 150 -55 to 150 V kV °C °C °C 1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1kΩ should be inserted in series with the TOVL pin.\ 1.2 Thermal data Table 2. Symbol RthJC RthJA Thermal data Parameter Thermal Resistance Junction-case Thermal Resistance Ambient-case Max Max PowerSO-10 (1) 2 60 DIP-8 (2) 20 80 Unit ° C/W ° C/W 1. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected to the DRAIN pin. 2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected to the device tab. 3/36 Electrical characteristics VIPer53 - E 2 Electrical characteristics TJ = 25°C, VDD = 13V, unless otherwise specified Table 3. Symbol BVDSS IDSS Power section Parameter Test conditions Min. 620 150 Typ. Max. Unit V µA Drain-source voltage ID = 1mA; VCOMP = 0V Off state drain current Static drain-source On state resistance Fall time Rise time Drain capacitance Effective output capacitance VDS = 500V; VCOMP = 0V; TJ = 125°C ID = 1A; VCOMP = 4.5V; VTOVL = 0V TJ = 25°C TJ = 100°C ID = 0.2A; VIN = 300V (1) ID = 1A; VIN = 300V (1) VDS = 25V 200V < VDSon < 400V (2) RDS(on) 0.9 1 1.7 Ω Ω ns ns pF pF tfv trv Coss CEon 100 50 170 60 1. On clamped inductive load 2. This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain to source voltage VDSon and the following formula: V DSon 1.5 1 2 E ton = -- ⋅ C Eon ⋅ 300 ⋅ ⎛ ----------------⎞ ⎝ 300 ⎠ 2 Table 4. Symbol FOSC1 Oscillator section Parameter Oscillator frequency initial accuracy Test conditions RT = 8kΩ; CT = 2.2nF Figure 12 on page 12 RT = 8kΩ; CT = 2.2nF Min. 95 Typ. 100 Max. 105 Unit kHz FOSC2 Oscillator frequency total variation Figure 16 on page 14 VDD = VDDon ... VDDovp; TJ = 0 ... 100°C 93 100 107 kHz VOSChi VOSClo Oscillator peak voltage Oscillator valley voltage 9 4 V V 4/36 VIPer53 - E Electrical characteristics Table 5. Symbol VDSstart IDDch1 IDDch2 IDDchoff IDD0 IDD1 VDDoff VDDon VDDhyst VDDovp Supply section Parameter Drain voltage starting threshold Startup charging current Startup charging current Startup charging current in thermal shutdown Operating supply current not switching Operating supply current switching VDD undervoltage shutdown threshold VDD startup threshold VDD threshold hysteresis VDD Overvoltage shutdown threshold Test conditions VDD = 5V; IDD = 0mA VDD = 0 ... 5V; VDS = 100V Figure 5 on page 10 VDD = 10V; VDS = 100VFigure 5. VDD = 5V; VDS = 100VFigure 7. TJ > TSD - THYST Fsw = 0kHz; VCOMP = 0V Fsw = 100kHz Figure 5 on page 10 Figure 5. Figure 5. Figure 5. 7.5 10.2 2.6 17 0 Min. Typ. 34 -12 -2 Max. Unit 50 V mA mA mA 8 9 8.4 11.5 3.1 18 11 mA mA 9.3 12.8 V V V 19 V Table 6. Symbol VDDreg ∆VDDreg Error amplifier section Parameter VDD regulation point VDD regulation point total variation Unity gain bandwidth Voltage gain DC transconductance Test conditions ICOMP = 0mA Figure 11. on page 11 ICOMP = 0mA; TJ = 0 ... 100°C From Input = VDD to Output = VCOMP ICOMP = 0mA Figure 14 and 15 ICOMP = 0mA Figure 14 and 15 VCOMP = 2.5V Figure 11. ICOMP = -0.4mA; VDD = 16V ICOMP = 0.4mA; VDD=14V(1) VCOMP = 2.5V; VDD = 16V Figure 11. on page 11 VCOMP = 2.5V; VDD= 14V Figure 11. 40 1 Min. 14.5 Typ. 15 2 Max. Unit 15.5 V % GBW AVOL Gm 700 45 1.4 0.2 4.5 -0.6 0.6 1.8 kHz dB mS V V mA mA VCOMPlo Output low level VCOMPhi Output high level ICOMPlo ICOMPhi Output sinking current Output sourcing current 1. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should always be present on the COMP pin. 5/36 Electrical characteristics VIPer53 - E Table 7. Symbol HCOMP PWM comparator section Parameter ∆VCOMP / ∆IDPEAK Test conditions VCOMP = 1 ... 4 V Figure 10. dID/dt = 0 dID/dt = 0 Figure 10. on page 11 ICOMP = 0mA; VTOVL = 0V Figure 10. dID/dt = 0 VCOMP = VCOMPovl; VTOVL = 0V dID/dt = 0 Min. Typ. Max. Unit 1.7 2 0.5 2.3 V/A V VCOMPos VCOMP Offset IDlim Peak drain current limitation Drain current capability 1.7 2 2.3 A IDmax td VCOMPbl tb1 tb2 tONmin1 tONmin2 VCOMPoff 1.6 1.9 250 1 2.3 A ns V Current sense delay to ID = 1A Turn-Off VCOMP blanking time change threshold Blanking time Blanking time Minimum On time Minimum On time VCOMP Shutdown Threshold Figure 6 on page 10 VCOMP < VCOMPBLFigure 6. VCOMP > VCOMPBLFigure 6. VCOMP < VCOMPBL VCOMP > VCOMPBL Figure 9 on page 11 300 100 450 250 400 150 600 350 0.5 500 200 750 450 ns ns ns ns V Table 8. Symbol VCOMPovl Overload protection section Parameter VCOMP overload threshold VCOMPhi to VCOMPovl voltage difference VTOVL overload threshold Overload delay Test conditions ITOVL = 0mA (1) Figure 4 on page 9 VDD = VDDoff ... VDDreg; ITOVL= 0mA Figure 4. (1) Min. Typ. 4.35 Max. Unit V VDIFFovl 50 150 250 mV VOVLth tOVL Figure 4. COVL = 100nF Figure 4. 4 8 V ms 1. VCOMPovl is always lower than VCOMPhi Table 9. Symbol TSD THYST Over temperature Protection Section Parameter Thermal shutdown temperature Thermal shutdown hysteresis Test Conditions Figure 7 on page 10 Figure 7 on page 10 Min. 140 Typ. 160 40 Max. Unit °C °C 6/36 VIPer53 - E Pin connections and function 3 Pin connections and function Figure 1. Pin connection (top view) COMP 1 8 TOVL OSC 2 7 VDD SOURCE 3 6 NC SOURCE 4 5 DRAIN DIP-8 PowerSO-10 Figure 2. Current and voltage conventions IDD ID VDD IOSC OSC 15V DRAIN VDD ITOVL VOSC TOVL COMP SOURCE V DS ICOMP VTOVL V COMP 7/36 Pin connections and function VIPer53 - E Table 10. Pin Name Pin function Pin function Power supply of the control circuits. Also provides the charging current of the external capacitor during start-up. The functions of this pin are managed by four threshold voltages: - VDDon: Voltage value at which the device starts switching (Typically 11.5 V). - VDDoff: Voltage value at which the device stops switching (Typically 8.4 V). - VDDreg: Regulation voltage point when working in primary feedback (Trimmed to 15 V). - VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V). Power MOSFET source and circuit ground reference. Power MOSFET drain. Also used by the internal high voltage current source during the start-up phase to charge the external VDD capacitor. Input of the current mode structure, and output of the internal error amplifier. Allows the setting of thedynamic characteristic of the converter through an external passive network. The useful voltage range extends from 0.5V to 4.5V. The Power MOSFET is always off below 0.5V, and the overload protection is triggered if the voltage exceeds 4.35V. This action is delayed by the timing capacitor connected tothe TOVL pin. Allows the connection of an external capacitor for delaying the overload protection, which is triggered by a voltage on the COMP pin higher than 4.35V. Allows the setting of the switching frequency through an external Rt-Ct network. VDD SOURCE DRAIN COMP TOVL OSC 8/36 VIPer53 - E Operation pictures 4 Operation pictures Figure 3. ID C -------------------------V DDhyst Figure 21 on page 23 shows a typical start-up event. VDD starts from 0V with a charging current IDDch1 at about 9 mA. When about VDDoff is reached, the charging current is reduced down to IDDch2 which is about 0.6mA. This lower current leads to a slope change on the VDD rise. Device starts switching for VDD equal to VDDon, and the auxiliary winding delivers some energy to VDD capacitor after the start-up time tss. The charging current change at VDDoff allows a fast complete start-up time tSDU, and maintains a low restart duty cycle. This is especially useful for short circuits and overloads conditions, as described in the following section. 22/36 VIPer53 - E Figure 21. Start-up waveforms High voltage Start-up current source IDD IDD1 t IDDch2 IDDch1 VDD VDDreg VDDst VDDsd tSU tSS t 23/36 Short-circuit and overload protection VIPer53 - E 10 Short-circuit and overload protection A VCOMPovl threshold of about 4.35V has been implemented on the COMP pin. When VCOMP goes above this level, the capacitor connected on the TOVL pin begins to charge. When reaching typically VOVLth (4V), the internal MOSFET driver is disabled and the device stops switching. This state is latched because of to the regulation loop which maintains the COMP pin voltage above the VCOMPovl threshold. Since the VDD pin does not receive any more energy from the auxiliary winding, its voltage drops down until it reaches VDDoff and the device is reset, recharging the VDD capacitor for a new restart cycle. Note: If VCOMP drops below the VCOMPovl threshold for any reason during the VDD drop, the device resumes switching immediately. The device enters an endless restart sequence if the overload or short circuit condition is maintained. The restart duty cycle DRST is defined as the time ratio for which the device tries to restart, thus delivering its full power capability to the output. In order to keep the whole converter in a safe state during this event, DRST must be kept as low as possible, without compromising the real start-up of the converter. A typical value of about 10% is generally sufficient. For this purpose, both VDD and TOVL capacitors can be used to satisfy the following conditions: Equation 6 C OVL > 12.5 ⋅ 10 –6 ⋅ tss Equation 7 C OVL ⋅ I DDch2 4 1C VDD > 8 ⋅ 10 ⋅ ⎛ ------------- – 1⎞ ⋅ -------------------------------------⎝D ⎠ V DDhyst RST Refer to the previous start-up section for the definition of tss, and CVDD must also be checked against the limit given in this section. The maximum value of the two calculus will be adopted. All this behavior can be observed on Figure 8 on page 10. In Figure 10 on page 11 the value of the drain current Id for VCOMP = VCOMPovl is shown. The corresponding parameter IDmax is the drain current to take into account for design purposes. Since IDmax represents the maximum value for which the overload protection is not triggered, it defines the power capability of the power supply. 24/36 VIPer53 - E Transconductance error amplifier 11 Transconductance error amplifier The VIPer53-E includes a transconductance error amplifier. Transconductance Gm is the change in output current ICOMP versus change in input voltage VDD. Thus: Equation 8 ∂I COMP G m = ------------------∂V DD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: Equation 9 ∂V COMP 1 - ∂V COMP Z COMP = --------------------- = --------- ⋅ --------------------∂I COMP Gm ∂V DD This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: Equation 10 A VOL = Gm ⋅ Z COMP where Gm value for VIPer53 is typically 1.4mA/V. Gm is well defined by specification, but ZCOMP, and therefore AVOL, are subject to large tolerances. An impedance Z must be connected between the COMP pin and ground in order to accurately define the transfer function F of the error amplifier, the following equation, very similar to the one above: Equation 11 F ( s ) = Gm ⋅ Z ( s ) The error amplifier frequency response is shown in .0 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 140KΩ More complex impedances can be connected on . the COMP pin to achieve different compensation methods. A capacitor provides an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, introducing a zero level and ensuring a correct phase margin. This configuration illustrated in Figure 22, for the schematic and Figure 23 on page 28 for the error amplifier transfer function for a typical set of values of CCOMP and RCOMP. Note that a 10nF capacitor (8nF, minimum value) should always be connected to the COMP pin to ensure a correct stability of the internal error amplifier. The complete converter open loop transfer function can be built from both power cell and error amplifier transfer functions. A theoretical example can be seen in Figure 24 for a discontinuous mode flyback loaded by a simple resistor, regulated from primary side (no 25/36 Transconductance error amplifier VIPer53 - E optocoupler, the internal error amplifier is fully used for regulation). A typical schematic corresponding to this situation can be seen on Figure 18. The transfer function of the power cell is represented as G(s) in Figure 24 Iexhibits a pole which depends on the output load and on the output capacitor value. As the load of a converter may change, two curves are shown for two different values of output resistance value, RL1 and RL2. A zero at higher frequency values then appears, due to the output capacitor ESR. Note: The overall transfer function does not depend on the input voltage because of the current mode control. The error amplifier has a fixed behavior, similar to the one shown in Figure 23. Its bandwidth is to avoid injection of high frequency noise in the current mode section. A zero due to the RCOMP-CCOMP network is set at the same value as the maximum load RL2 pole. The total transfer function is shown as F(s). G(s) at the bottom of Figure 24. For maximum load (plain line), the load pole is exactly compensated by the zero of the error amplifier, and the result is a perfect first order decreasing until it reaches the zero of the output capacitor ESR. The error amplifier cut-off then definitely any further spurious noise or resonance from disturbing the regulation loop. The point where the complete transfer function has a unity gain is known as the regulation bandwidth and has: – – The higher it is, the faster the reaction will be to an eventual load change, and the smaller the output voltage change will be. The phase shift in the complete system at this point has to be less than 135° to ensure good stability. Generally, a first-order slope gives 90° of phase shift, and a second-order gives 180°. In Figure 24, the unity gain is reached in a first order slope, so the stability is ensured. The dynamic load regulation is improved by increasing the regulation bandwidth, but some limitations have to be respected: As the transfer function above the zero due the capacitor ESR is not reliable (The ESR itself is not well specified, and other parasitic effects may take place), the bandwidth should always be lower than the minimum of FC and ESR zero. As the highest bandwidth is obtained with the highest output power (Plain line with RL2 load in Figure 24), the above criteria will be checked for this condition and allows to define the value of RCOMP, as the error amplifier gain depends only on this value for this frequency range. The following formula can be derived: Equation 12 R COMP = 2 P OUT2 F BW2 ⋅ R L2 ⋅ C OUT ---------------- ⋅ ----------------------------------------------------Gm P MAX 1 2 and: PMAX = -- ⋅ L P ⋅ I LIM ⋅ F SW 2 OUT With: POUT2 = -------------- V R L2 26/36 VIPer53 - E Transconductance error amplifier The lowest load gives another condition for stability: The frequency FBW1 must not encounter the second order slope generated by the load pole and the integrator part of the error amplifier. This condition can be met by adjusting the CCOMP value: Equation 13 R L1 ⋅ C OUT C COMP > ----------------------------------------------------- ⋅ 2 6.3 ⋅ Gm ⋅ R COMP P OUT1 -----------------P MAX With: 2 V OUT P OUT1 = --------------R L1 The above formula gives a minimum value for CCOMP. It can be then increased to provide a natural soft start function as this capacitor is charged by the error amplifier current capacity ICOMPhi at start-up. Figure 22. Typical compensation network VDD DRAIN OSC 15V TOVL COMP SOURCE Rcomp 10nF Ccomp 27/36 Transconductance error amplifier Figure 23. Typical transfer functions Gain (dB) 60 Rcomp=4.7k Ccomp=470nF VIPer53 - E 50 40 30 20 10 0 -10 1 10 100 1k 10k 100k 1M Phase (°) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 Frequency (Hz) Rcomp=4.7k Ccomp=470nF 100 1k 10k 100k 1M Frequency (Hz) 28/36 VIPer53 - E Figure 24. Complete converter transfer function Transconductance error amplifier G(S) 1 ---------------------------------------------π⋅ R ⋅C L1 OUT 1 ---------------------------------------------π⋅ R ⋅C L2 OUT F 1 1 ----------------------------------------------------------2 ⋅ π ⋅ ESR ⋅ C OUT F(S) 1 --------------------------------------------------------------------------2⋅ π⋅ R ⋅C COMP COMP FC F 1 F(S).G(S) 1 FBW1 FBW2 F 29/36 Special recommendations VIPer53 - E 12 Special recommendations As steted in the error amplifier section, a capacitor of 10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to ensure correct stability of the internal error amplifier Figure 18, 19 and 22. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1kΩ should be inserted in series with the TOVL pin, as shown on Figure 18, Figure 19 on page 17. Note that, this resistance does not impact the overload delay, as its value is negligible prior to the internal pull-up resistance (about 125kΩ). 13 Software implementation All the above considerations and some others are included included in ST design software which provides all of the needed components around the VIPer device for specified output configurations, and is available on www.st.com. 30/36 VIPer53 - E Package mechanical data 14 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 31/36 Package mechanical data VIPer53 - E Table 11. DIP8 mechanical data Dimensions Databook (mm) Ref. Nom. A A1 A2 b b2 c D E E1 e eA eB L 2.92 3.30 Gr. 470 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 10.92 3.81 4.95 0.56 1.78 0.36 10.16 8.26 7.11 Min Max 5.33 Package Weight Figure 25. Package dimensions 32/36 VIPer53 - E Table 12. PowerSO-10 mechanical data Dimensions Package mechanical data Databook (mm) Ref. Nom. A A1 B c D D1 E E1 E2 E3 E4 e F H h L q α 0° 1.20 1.70 8° 1.25 13.80 0.50 1.80 3.35 0.00 0.40 0.35 9.40 7.40 9.30 7.20 7.20 6.10 5.90 1.27 1.35 14.40 Min Max 3.65 0.10 0.60 0.55 9.60 7.60 9.50 7.40 7.60 6.35 6.10 Figure 26. Package dimensions 33/36 Order codes VIPer53 - E 15 Order codes Table 13. Order codes Package DIP-8 PowerSO-10 PowerSO-10 Shipment Tube Tube Tape and reel Part Number VIPer53DIP-E VIPer53SP-E VIPer53SPTR - E 34/36 VIPer53 - E Revision history 16 Revision history Table 14. Date 13-Nov-2006 Revision history Revision 1 Initial release. Changes 35/36 VIPer53 - E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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