VIPER53DIP

® VIPer53DIP VIPer53SP OFF LINE PRIMARY SWITCH TYPICAL OUTPUT POWER CAPABILITY TYPE DIP-8 PowerSO-10™ Note: European (195 - 265 Vac) 50W 65W US / Wide range (85 - 265 Vac) 30W 40W 10 1 Above power capabilities are given under adequate thermal conditions DIP-8 PowerSO-10™ FEATURES n SWITCHING FREQUENCY UP TO 300 kHz n CURRENT LIMITATION n CURRENT MODE CONTROL WITH ADJUSTABLE LIMITATION n SOFT START AND SHUT DOWN CONTROL n AUTOMATIC BURST MODE IN STAND-BY CONDITION (“BLUE ANGEL” COMPLIANT) n UNDERVOLTAGE LOCKOUT WITH HYSTERESIS n HIGH VOLTAGE STARTUP CURRENT SOURCE n OVERTEMPERATURE PROTECTION n OVERLOAD AND SHORT-CIRCUIT CONTROL BLOCK DIAGRAM OSC DESCRIPTION The VIPer53 combines in the same package an enhanced current mode PWM controller with a high voltage MDMesh Power Mosfet. Typical applications cover off line power supplies with a secondary power capability ranging up to 30W in wide range input voltage or 50W in single European voltage range and DIP-8 package, with the following benefits: – Overload and short circuit controlled by feedback monitoring and delayed device reset. – Efficient standby mode by enhanced pulse skipping. – Primary regulation or secondary loop failure protection through high gain error amplifier. DRAIN ON/OFF OSCILLATOR PWM LATCH OVERTEMP. DETECTOR R1 R2 R3 UVLO COMPARATOR VDD 8.4/ 11.5V 0.5V STANDBY COMPARATOR 4V 150/400ns BLANKING PWM COMPARATOR 8V S FF R4 Q R5 0.5V H COMP BLANKING TIME SELECTION 1V CURRENT AMPLIFIER 15V ERROR AMPLIFIER 125k 4.35V OVERLOAD COMPARATOR OVERVOLTAGE COMPARATOR 18V 4.5V TOVL COMP SOURCE June 2004 1/24 VIPer53DIP / VIPer53SP PIN FUNCTION Name Function Power supply of the control circuits. Also provides the charging current of the external capacitor during start-up. The functions of this pin are managed by four threshold voltages: - VDDon: Voltage value at which the device starts switching (Typically 11.5 V). - VDDoff: Voltage value at which the device stops switching (Typically 8.4 V). - VDDreg: Regulation voltage point when working in primary feedback (Trimmed to 15 V). - VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V). Power Mosfet source and circuit ground reference. Power Mosfet drain. Also used by the internal high voltage current source during the start-up phase, for charging the external VDD capacitor. Input of the current mode structure, and output of the internal error amplifier. Allows the setting of the dynamic characteristic of the converter through an external passive network. Useful voltage range extends from 0.5 V to 4.5 V. The Power Mosfet is always off below 0.5 V, and the overload protection is triggered if the voltage exceeds 4.35V. This action is delayed by the timing capacitor connected to the TOVL pin. Allows the connection of an external capacitor for delaying the overload protection, which is triggered by a voltage on the COMP pin higher than 4.35V. Allows the setting of the switching frequency through an external Rt-Ct network. VDD SOURCE DRAIN COMP TOVL OSC CURRENT AND VOLTAGE CONVENTIONS IDD ID VDD I OSC OSC 15V DRAIN VDD I TOVL VOSC TOVL COMP SOURCE VDS ICOMP VTOVL VCOMP CONNECTION DIAGRAM COMP 1 8 TOVL DRAIN NC 1 2 3 4 5 10 9 8 7 6 SOURCE NC NC OSC COMP OSC 2 7 VDD NC NC SOURCE 3 6 NC VDD TOVL SOURCE 4 5 DRAIN DIP-8 ORDER CODES PACKAGE PowerSO-10™ TUBE VIPer53DIP VIPer53SP TAPE and REEL VIPer53SP13TR D IP-8 PowerSO-10™ 2/24 VIPer53DIP / VIPer53SP ABSOLUTE MAXIMUM RATINGS Symbol VDS ID VDD VOSC ICOMP ITOVL VESD Tj Tc Tstg Parameter Continuous Drain Source Voltage (Tj=25 ... 125°C) Continuous Drain Current Supply Voltage OSC Input Voltage Range COMP and TOVL Input Current Range Electrostatic Discharge: Machine Model (R=0Ω; C=200pF) Charged Device Model Junction Operating Temperature Case Operating Temperature Storage Temperature (See note 1) (See note 1) Value -0.3 ... 620 Internally limited 0 ... 19 0 ... VDD -2 ... 2 Unit V A V V mA 200 1.5 Internally limited -40 to 150 -55 to 150 V kV °C °C °C Note: 1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1 kΩ should be inserted in series with the TOVL pin. THERMAL DATA Symbol Rthj-case Rthj-amb Rthj-case Rthj-amb DIP-8 DIP-8 (See note 2) Parameter Max Value 20 80 2 (See note 3) 60 Unit °C/W °C/W °C/W °C/W PowerSO-10™ PowerSO-10™ Note: 2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 µm thick) connected to the DRAIN pin. 3. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 µm thick) connected to the device tab. 3/24 VIPer53DIP / VIPer53SP ELECTRICAL CHARACTERISTICS (Tj=25°C, VDD=13V, unless otherwise specified) POWER SECTION Symbol BVDSS IDSS RDS(on) Parameter Drain-Source Voltage Off State Drain Current Static Drain-Source On State Resistance Fall Time Rise Time Drain Capacitance Effective Output Capacitance Test Conditions ID=1mA; VCOMP=0V VDS=500V; VCOMP=0V; Tj=125°C ID=1A; VCOMP=4.5V; VTOVL=0V Tj=25°C Tj=100°C ID=0.2A; VIN=300V (See figure 1 and note 4) ID=1A; VIN=300V (See figure 1 and note 4) VDS=25V 200V < VDSon < 400V (See note 5) 0.9 Min. 620 150 1 1.7 Typ. Max. Unit V µA Ω Ω ns ns pF pF tfv trv Coss CEon 100 50 170 60 Note 4. On clamped inductive load 5. This parameter can be used to compute the energy dissipated at turn on Eton according to the initial drain to source voltage VDSon 1.5 1 2 V DSon and the following formula: E ton = -- ⋅ C Eon ⋅ 300 ⋅  ---------------  300  2 OSCILLATOR SECTION Symbol FOSC1 FOSC2 VOSChi VOSClo Parameter Oscillator Frequency Initial Accuracy Oscillator Frequency Total Variation Oscillator Peak Voltage Oscillator Valley Voltage Test Conditions RT=8kΩ; CT=2.2nF (See figure 9) Min. 95 93 Typ. 100 100 9 4 Max. 105 107 Unit kHz kHz V V (See figure 12) RT=8kΩ; CT=2.2nF VDD=VDDon ... VDDovp; Tj=0 ... 100°C 4/24 VIPer53DIP / VIPer53SP ELECTRICAL CHARACTERISTICS (Tj=25°C, VDD=13V, unless otherwise specified) SUPPLY SECTION Symbol VDSstart IDDch1 IDDch2 IDDchoff IDD0 IDD1 VDDoff VDDon VDDhyst VDDovp Parameter Drain Voltage Starting Threshold Startup Charging Current Startup Charging Current Startup Charging Current in Thermal Shutdown Test Conditions VDD=5V; IDD=0mA VDD=0 ... 5V; VDS=100V (See figure 2) VDD=10V; VDS=100V VDD=5V; VDS=100V Tj > TSD - THYST (See figure 2) (See figure 5) 0 8 9 7.5 10.2 2.6 17 8.4 11.5 3.1 18 19 9.3 12.8 11 Min. Typ. 34 -12 -2 Max. 50 Unit V mA mA mA mA mA V V V V Operating Supply Current Fsw=0kHz; VCOMP=0V Not Switching Operating Supply Current F =100kHz sw Switching VDD Undervoltage Shutdown Threshold VDD Startup Threshold VDD Threshold Hysteresis VDD Overvoltage Shutdown Threshold (See figure 2) (See figure 2) (See figure 2) (See figure 7) ERROR AMPLIFIER SECTION Symbol VDDreg ∆VDDreg GBW AVOL Gm VCOMPlo VCOMPhi ICOMPlo ICOMPhi Parameter VDD Regulation Point VDD Regulation Point Total Variation Unity Gain Bandwidth Voltage Gain DC Transconductance Output Low Level Output High Level Output Sinking Current Output Sourcing Current Test Conditions ICOMP=0mA (See figure 3) Min. 14.5 Typ. 15 2 700 40 1 45 1.4 0.2 (See note 6) (See figure 3) (See figure 3) 4.5 -0.6 0.6 1.8 Max. 15.5 Unit V % kHz dB mS V V mA mA ICOMP=0mA; Tj=0 ... 100°C From Input =VDD to Output = VCOMP ICOMP=0mA (See figure 10) ICOMP=0mA VCOMP=2.5V ICOMP=-0.4mA; VDD=16V ICOMP=0.4mA; VDD=14V VCOMP=2.5V; VDD=16V VCOMP=2.5V; VDD=14V (See figure 10) (See figure 3) Note 6. In order to insure a correct stability of the error amplifier, a capacitor of 10nF (minimum value: 8nF) should always be present on the COMP pin. 5/24 VIPer53DIP / VIPer53SP ELECTRICAL CHARACTERISTICS (Tj = 25 °C, VDD = 13 V, unless otherwise specified) PWM COMPARATOR SECTION Symbol HCOMP VCOMPos IDlim IDmax td VCOMPbl tb1 tb2 tONmin1 tONmin2 VCOMPoff Parameter ∆VCOMP / ∆IDPEAK VCOMP Offset Peak Drain Current Limitation Drain Current Capability Current Sense Delay to Turn-Off VCOMP Blanking Time Change Threshold Blanking Time Blanking Time Minimum On Time Minimum On Time VCOMP Shutdown Threshold Test Conditions VCOMP=1 ... 4 V dID/dt=0 dID/dt=0 ICOMP=0mA; VTOVL=0V dID/dt=0 (See figure 8) 1.7 (See figure 8) (See figure 8) 1.7 1.6 2 1.9 250 1 (See figure 11) (See figure 11) 300 100 450 250 400 150 600 350 0.5 500 200 750 450 2.3 2.3 A A ns V ns ns ns ns V 2 0.5 2.3 V/A V Min. Typ. Max. Unit VCOMP=VCOMPovl; VTOVL=0V dID/dt=0 (See figure 8) ID=1A (See figure 11) VCOMP < VCOMPBL VCOMP > VCOMPBL VCOMP < VCOMPBL VCOMP > VCOMPBL (See figure 6) OVERLOAD PROTECTION SECTION Symbol VCOMPovl VDIFFovl VOVLth tOVL Parameter VCOMP Overload Threshold VCOMPhi to VCOMPovl Voltage Difference VTOVL Overload Threshold Overload Delay ITOVL=0mA Test Conditions (See figure 4 and note 7) 50 Min. Typ. 4.35 150 4 (See figure 4) 8 250 Max. Unit V mV V ms VDD=VDDoff ... VDDreg; ITOVL=0mA (See figure 4 and note 7) (See figure 4) COVL=100nF Note 7. VCOMPovl is always lower than VCOMPhi. OVERTEMPERATURE PROTECTION SECTION Symbol TSD THYST Parameter Thermal Shutdown Temperature Thermal Shutdown Hysteresis (See fig. 5) (See fig. 5) Test Conditions Min. 140 Typ. 160 40 Max. Unit °C °C 6/24 VIPer53DIP / VIPer53SP Figure 1: Rise and Fall Time ID C ---------------------V DDhyst Figure 17 shows a typical start-up event. VDD starts from 0 V with a charging current I DDch1 at about 9 mA. When about VDDoff is reached, the Figure 17: Startup Waveforms IDD IDD1 t IDDch2 IDDch1 VDD VDDreg VDDst VDDsd tsu tss t 15/24 VIPer53DIP / VIPer53SP charging current is reduced down to IDDch2 which is about 0.6 mA. This lower current leads to a slope change on the VDD rise. The device starts switching for a VDD equal to VDDon, and the auxiliary winding delivers some energy to the VDD capacitor after the start-up time tss. The charging current change at VDDoff allows a fast complete start-up time tsu, and maintains a low restart duty cycle. This is especially useful for short circuits and overloads conditions, as described in the following section. SHORT-CIRCUIT AND OVERLOAD PROTECTION A VCOMPovl threshold of about 4.35 V has been implemented on the COMP pin. When VCOMP goes above this level, the capacitor connected on the TOVL pin begins to charge. When reaching typically 4 V (VOVLth), the internal mosfet driver is disabled and the device stops switching. This state is latched thanks to the regulation loop which maintains the COMP pin voltage above the VCOMPovl threshold. Since the VDD pin doesn’t receive any more energy from the auxiliary winding, its voltage drops down until it reaches VDDoff and the device is reset, recharging the VDD capacitor for a new restart cycle. Note that if VCOMP drops down below the V COMPovl threshold for any reason during the VDD drop, the device resumes switching immediately. The device enters an endless restart sequence if the overload or short circuit condition is maintained. The restart duty cycle DRST is defined as the time ratio for which the device tries to restart, thus delivering its full power capability to the output. In order to keep the whole converter in a safe state during this event, D RST must be kept as low as possible, without compromising the real start up of the converter. A typical value of about 10 % is generally sufficient. For this purpose, both VDD and TOVL capacitors can be used to satisfy the following conditions: –6 C OVL > 12.5 ⋅ 10 ⋅ tss C OVL ⋅ I DDc h 2 1 4 C VDD > 8 ⋅ 10 ⋅  ----------- – 1 ⋅ -------------------------------- D RST  V DDhyst Refer to the previous start-up section for the definition of tss, and CVDD must also be checked against the limit given in this section. The maximum value of the two calculus will be adopted. All this behavior can be observed on figure 4. In Figure 8 the value of the drain current Id for VCOMP=VCOMPovl is shown. The corresponding parameter I Dmax is the drain current to take into account for design purpose. Since IDmax represents the maximum value for which the overload protection is not triggered, it defines the power capability of the power supply. TRANSCONDUCTANCE ERROR AMPLIFIER The VIPer53 includes a transconductance error amplifier. Transconductance Gm is the change in output current ICOMP versus change in input voltage VDD. Thus: Gm = ∂I COMP ∂ V DD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: Z C OMP = ∂V COMP 1 ∂VCOM P = -------- ⋅ Gm ∂ VDD ∂ I COMP This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: A VOL = Gm ⋅ Z COM P where Gm value for VIPer53 is typically 1.4 mA/V. Gm is well defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z must be connected between the COMP pin and ground in order to define accurately the transfer function F of the error amplifier, according to the following equation, very similar to the one above: F(s) = Gm ⋅ Z(s) The error amplifier frequency response is shown in figure 10 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 140 KΩ. More complex impedances can be connected on the COMP pin to achieve different compensation methods. A capacitor provides an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, Figure 18: Typical Compensation Network VDD DRAIN OSC 15V TOVL COMP SOURCE Rcomp 10nF Ccomp 16/24 VIPer53DIP / VIPer53SP introducing a zero and ensuring a correct phase margin. This configuration is illustrated in figure 18 Figure 19: Typical Transfer Functions Gain (dB) 60 Rcomp=4.7k Ccomp=470nF for the schematic and figure 19 for the error 50 40 30 20 10 0 -10 1 10 100 1k 10k 100k 1M Frequency (Hz) Phase (°) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 10 100 1k 10k 100k 1M Rcomp=4.7k Ccomp=470nF Frequency (Hz) amplifier transfer function for a typical set of values for CCOMP and RCOMP. Note that a capacitor of 10 nF (minimum value: 8 nF) should always be connected to the COMP pin to insure a correct stability of the internal error amplifier. The complete converter open loop transfer function can be built from both power cell and error amplifier transfer functions. A theoretical example can be seen in figure 20 for a discontinuous mode flyback loaded by a simple resistor, regulated from primary side (no optocoupler, the internal error amplifier is fully used for regulation). A typical schematic corresponding to this situation can be seen on figure 14. The transfer function of the power cell is represented as G(s) in figure 20. It exhibits a pole which depends on the output load and on the output capacitor value. As the load of a converter may change, two curves are shown for two different values of output resistance value, RL1 and RL2. A zero at higher frequency values then appears, due to the output capacitor ESR. Note that the overall transfer function doesn’t depend on the input voltage, thanks to the current mode control. The error amplifier has a fixed behavior, similar to the one shown in figure 19. Its bandwidth is limited, in order to avoid injection of high frequency noise 17/24 VIPer53DIP / VIPer53SP Figure 20: Complete Converter Transfer Function G(S) P M AX 3.2 ⋅ ------------------P O U T1 P MAX 3.2 ⋅ ------------------P OU T 2 1 --------------------------------------π⋅R ⋅C L1 O UT 1 --------------------------------------π⋅R ⋅C L2 O UT F 1 1 ----------------------------------------------2 ⋅ π ⋅ ES R ⋅ C O UT F(S) Gm ⋅ R 1 --------------------------------------------------------------2⋅π ⋅R C C O M P ⋅ CO M P COMP FC F 1 F(S).G(S) perfect first order decreasing slope until it reaches the zero of the output capacitor ESR. The error amplifier cut off then prevents definitely any further spurious noise or resonance from disturbing the regulation loop. The point where the complete transfer function has a unity gain is known as the regulation bandwidth and has a double interest: – The higher it is the faster will be the reaction to an eventual load change, and the smaller will be the output voltage change. – The phase shift in the complete system at this point has to be less than 135 ° to ensure a good stability. Generally, a first order gives 90 ° of phase shift, and 180 ° for a second order. In figure 20, the unity gain is reached in a first order slope, so the stability is ensured. The dynamic load regulation is improved by increasing the regulation bandwidth, but some limitations have to be respected: As the transfer function above the zero due the capacitor ESR is not reliable (The ESR itself is not well specified, and other parasitic effects may take place), the bandwidth should always be lower than the minimum of FC and ESR zero. As the highest bandwidth is obtained with the highest output power (Plain line with RL2 load in figure 20), the above criteria will be checked for this condition and allows to define the value of RCOMP, as the error amplifier gain depends only on this value for this frequency range. The following formula can be derived: R COMP = POUT 2 F BW 2 ⋅ RL 2 ⋅ C OUT ----------------- ⋅ -----------------------------------------------Gm PM AX With: 2 VOUT P OUT 2 = -------------RL 2 1 2 1 FBW 1 FBW 2 F And: P M AX = -- ⋅ LP ⋅ ILIM ⋅ F SW : 2 The lowest load gives another condition for stability: The frequency FBW1 must not encounter the second order slope generated by the load pole and the integrator part of the error amplifier. This condition can be met by adjusting the CCOMP value: R L 1 ⋅ COUT C COMP > -------------------------------------------- ⋅ 2 6.3 ⋅ Gm ⋅ R COMP POUT 1 ----------------PM AX in the current mode section. A zero due to the RCOMP-C COMP network is set at the same value as the maximum load RL2 pole. The total transfer function is shown as F(s).G(s) at the bottom of figure 20. For maximum load (plain line), the load pole is exactly compensated by the zero of the error amplifier, and the result is a 18/24 With: The above formula gives a minimum value for CCOMP. It can be then increased to provide a natural soft start function as this capacitor is charged by the error amplifier current capacity ICOMPhi at start-up. 2 V OUT POUT 1 = -------------RL 1 VIPer53DIP / VIPer53SP SPECIAL RECOMMENDATIONS As stated in the error amplifier section, a capacitor of 10 nF (minimum value: 8 nF) should always be connected to the COMP pin to insure a correct stability of the internal error amplifier. This is represented on figures 14, 15 and 18. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1 k Ω should be inserted in series with the TOVL pin, as shown on figures 14 and 15. Note that this resistance doesn’t impact the overload delay, as its value is negligible in front of the internal pull up resistance (about 125 kΩ). SOFTWARE IMPLEMENTATION All the above considerations and some others are included in a design software which provides all the needed components around the VIPer device for a specified output configuration. This software is available in download on the ST internet site. 19/24 VIPer53DIP / VIPer53SP Plastic DIP-8 MECHANICAL DATA DIM. A A1 A2 b b2 c D E E1 e eA eB L Package Weight 2.92 3.30 Gr. 470 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 10.92 3.81 4.95 0.56 1.78 0.36 10.16 8.26 7.11 mm. MIN. TYP MAX. 5.33 P001 20/24 VIPer53DIP / VIPer53SP PowerSO-10™ MECHANICAL DATA DIM. A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) α α (*) (*) Muar only POA P013P mm. MIN. 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 1.27 1.25 1.20 13.80 13.85 0.50 1.20 0.80 0º 2º 1.80 1.10 8º 8º 0.047 0.031 0º 2º 1.35 1.40 14.40 14.35 0.049 0.047 0.543 0.545 TYP MAX. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 MIN. 0.132 0.134 0.000 0.016 0.014 0.013 0.009 0.370 0.291 0.366 0.283 0.287 0.232 0.232 inch TYP. MAX. 0.144 0.142 0.004 0.024 0.021 0.022 0.0126 0.378 0.300 0.374 300 0.295 0.240 0.248 0.050 0.053 0.055 0.567 0.565 0.002 0.070 0.043 8º 8º B 0.10 A B 10 H E E2 E4 1 SEATING PLANE e 0.25 B DETAIL "A" A C D = D1 = = = SEATING PLANE h A F A1 A1 L DETAIL "A" α P095A 21/24 VIPer53DIP / VIPer53SP PowerSO-10™ SUGGESTED PAD LAYOUT 14.6 - 14.9 B TUBE SHIPMENT (no suffix) CASABLANCA MUAR C 10.8 - 11 6.30 A A C 0.67 - 0.73 1 2 3 4 5 10 9 8 7 6 0.54 - 0.6 B 9.5 All dimensions are in mm. 1.27 Base Q.ty Bulk Q.ty Tube length (± 0.5) Casablanca Muar 50 50 1000 1000 532 532 A B C (± 0.1) 0.8 0.8 10.4 16.4 4.9 17.2 TAPE AND REEL SHIPMENT (suffix “13TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 24 4 24 1.5 1.5 11.5 6.5 2 End All dimensions are in mm. Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components 22/24 1 VIPer53DIP / VIPer53SP DIP-8 TUBE SHIPMENT (no suffix) A C B Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) All dimensions are in mm. 20 1000 532 8.4 11.2 0.8 23/24 1 VIPer53DIP / VIPer53SP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http://www.st.com 24/24