VNL5050N3TR-E

VNL5050N3-E VNL5050S5-E OMNIFET III fully protected low-side driver Datasheet - production data Description 2 1 2 The VNL5050N3-E and VNL5050S5-E are monolithic devices made using STMicroelectronics VIPower® Technology, intended for driving resistive or inductive loads with one side connected to the battery. 3 SOT-223 SO-8 Built-in thermal shutdown protects the chip from overtemperature and short-circuit. Output current limitation protects the devices in an overload condition. In case of long duration overload, the devices limit the dissipated power to a safe level up to thermal shutdown intervention.Thermal shutdown, with automatic restart, allows the devices to recover normal operation as soon as a fault condition disappears. Fast demagnetization of inductive loads is achieved at turn-off. Features Type Vclamp RDS(on) ID 41 V 50 mΩ 19 A VNL5050N3-E VNL5050S5-E • Automotive qualified • Drain current: 19 A • ESD protection • Overvoltage clamp • Thermal shutdown • Current and power limitation • Very low standby current • Very low electromagnetic susceptibility • Compliant with European directive 2002/95/EC • Open drain status output (VNL5050S5-E only) Table 1. Devices summary Order codes Package Tube Tape and reel SOT-223 VNL5050N3-E VNL5050N3TR-E SO-8 VNL5050S5-E VNL5050S5TR-E December 2013 This is information on a product in full production. DocID15917 Rev 6 1/33 www.st.com Contents VNL5050N3-E, VNL5050S5-E Contents 1 Block diagrams and pins configurations . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 5 6 2/33 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID15917 Rev 6 VNL5050N3-E, VNL5050S5-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Devices summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Suggested connections for unused and n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power MOS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Source drain diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID15917 Rev 6 3/33 3 List of figures VNL5050N3-E, VNL5050S5-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. 4/33 VNL5050N3-E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VNL5050S5-E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VNL5050N3-E current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VNL5050S5-E current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration diagrams (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Source diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain source on-resistance vs. drain current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain source on-resistance vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Static drain source on-resistance vs. drain current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transfer characteristics (inside view for VIN = 2 V to 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Normalized on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Normalized input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VNL5050N3-E application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VNL5050S5-E application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SOT-223 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 19 SOT-223 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . 20 Thermal fitting model of a LSD in SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 22 SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal fitting model of a LSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SOT-223 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SOT-223 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DocID15917 Rev 6 VNL5050N3-E, VNL5050S5-E 1 Block diagrams and pins configurations Block diagrams and pins configurations Figure 1. VNL5050N3-E block diagram Drain LOGIC Control & Diagnostic Current Limitation IN Power Clamp DRIVER OVERTEMPERATURE PROTECTION OVERLOAD PROTECTION (ACTIVE POWER LIMITATION) GND Figure 2. VNL5050S5-E block diagram Drain SUPPLY SUPPLY LOGIC Control & Diagnostic OFF State Open load Current Limitation IN ST Power Clamp DRIVER OVERTEMPERATURE PROTECTION OVERLOAD PROTECTION (ACTIVE POWER LIMITATION) GND DocID15917 Rev 6 5/33 32 Block diagrams and pins configurations VNL5050N3-E, VNL5050S5-E Table 2. Pin function Name Function INPUT Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state(1) DRAIN Power MOS drain SOURCE Power MOS source and ground reference for the control section SUPPLY VOLTAGE Supply voltage connected to the signal part (5 V) Open drain digital diagnostic pin(2) STATUS 1. Internally connected to Vsupply in the VNL5050N3-E 2. Valid for VNL5050S5-E only. Figure 3. VNL5050N3-E current and voltage conventions *% 7%4 %3"*/ **/ */165 7*/ 4063$& ("1($'5 Figure 4. VNL5050S5-E current and voltage conventions *% %3"*/ 7%4 **/ */165 7*/ *45"5 45"564 745"5 *4 4611-: 70-5"(& 4063$& 7TVQQMZ ("1($'5 6/33 DocID15917 Rev 6 VNL5050N3-E, VNL5050S5-E Block diagrams and pins configurations Figure 5. Configuration diagrams (top view)  %3"*/    4063$& %3"*/ */165 %3"*/   /$ 4063$&   45"564 4063$&   */165 %3"*/   4611-:
70-5"(& 405 40 ("1($'5 Table 3. Suggested connections for unused and n.c. pins Connection / pin STATUS N.C. INPUT Floating X X X To ground Not allowed X Through 10 kΩ resistor DocID15917 Rev 6 7/33 32 Absolute maximum rating 2 VNL5050N3-E, VNL5050S5-E Absolute maximum rating Stressing the device above the rating listed in the Table 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.1 Absolute maximum ratings Table 4. Absolute maximum ratings Value Symbol Parameter Unit SOT-223 VDS ID DC drain current -ID Reverse DC drain current IS DC supply current IIN DC input current ISTAT DC status current VESD1 Electrostatic discharge (R = 1.5 kΩ; C = 100 pF) – DRAIN – SUPPLY, INPUT, STATUS VESD2 Electrostatic discharge on output pin only (R = 330 Ω, C = 150 pF) Internally clamped V Internally limited A 4 A - -1 to 10 -1 to 10 - mA mA -1 to 10 mA V 5000 4000 2000 V Junction operating temperature -40 to 150 °C Tstg Storage temperature -55 to 150 °C EAS Single pulse avalanche energy (L = 1.1 mH, TJ = 150 °C, RL = 0, IOUT = IlimL) 93 mJ Tj 2.2 Drain-source voltage (VIN = 0 V) SO-8 Thermal data Table 5. Thermal data Maximum value Symbol Parameter Rthj-amb Thermal resistance junction-ambient Unit SOT-223 SO-8 108.3(1) 87 1. When mounted on a standard single-sided FR4 board with 0.5 to all DRAIN pins 8/33 DocID15917 Rev 6 cm2 °C/W of Cu (at least 35 µm thick) connected VNL5050N3-E, VNL5050S5-E 3 Electrical characteristics Electrical characteristics Values specified in this section are for Vsupply = VIN = 4.5 V to 5.5 V, -40 °C < Tj < 150 °C, unless otherwise stated. Table 6. Power MOS section Symbol Vsupply RON Parameter Test conditions Min. Typ. Max. Unit - 3.5 5 5.5 V Operating supply voltage ON-state resistance ID = 2 A; Tj = 25 °C, Vsupply = VIN = 5 V 50 ID = 2 A; Tj = 150 °C, Vsupply = VIN = 5 V 100 mΩ VCLAMP Drain-source clamp voltage VIN = 0 V; ID = 2 A VCLTH IDSS Drain-source clamp threshold voltage OFF-state output current 41 46 52 VIN = 0 V; ID = 2 mA 36 VIN = 0 V; VDS = 13 V; Tj = 25 °C 0 3 VIN = 0 V; VDS = 13 V; Tj = 125 °C 0 5 V V µA Table 7. Source drain diode Symbol VSD Parameter Test conditions Forward on voltage ID = 2 A; VIN = 0 V Table 8. Input section(1) Typ. Max. Unit - 0.8 - V . Symbol Parameter Test conditions IISS Supply current from input pin ON-state: Vsupply = VIN = 5 V; VDS = 0 V VICL Input clamp voltage VINTH Min. Min. IS = 1 mA Max. Unit 30 65 µA 5.5 7 V IS = -1 mA Input threshold voltage Typ. -0.7 VDS = VIN; ID = 1 mA 1 3.5 V 1. Valid for VNL5050N3-E option (input and supply pins connected together) Table 9. Status pin(1) Symbol Parameter Test conditions Min. Typ. Max. Unit VSTAT Status low output voltage ISTAT = 1 mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 µA CSTAT Status pin input capacitance Normal operation; VSTAT = 5 V 100 pF DocID15917 Rev 6 9/33 32 Electrical characteristics VNL5050N3-E, VNL5050S5-E Table 9. Status pin(1) (continued) Symbol VSTCL Parameter Test conditions ISTAT = 1 mA Status clamp voltage Min. Typ. 5.5 Max. Unit 7 V ISTAT = -1 mA -0.7 1. Valid for VNL5050S5-E option Table 10. Logic input(1) Symbol Parameter Test conditions Min. Typ. Max. Unit 0.9 V VIL Low-level input voltage — IIL Low-level input current VIN = 0.9 V 1 µA VIH High-level input voltage — 2.1 V IIH High-level input current VIN = 2.1 V VI(hyst) Input hysteresis voltage — 0.13 IIN = 1 mA 5.5 VICL Input clamp voltage 10 µA V 7 V IIN = -1 mA -0.7 1. Valid for VNL5050S5-E option Table 11. Openload detection(1) Symbol VOl td(oloff) Parameter Test conditions Min. Typ. Max. Unit VIN = 0 V 0.6 1.2 1.7 V Delay between INPUT falling edge and STATUS falling edge IOUT = 0 A in openload condition 45 425 1100 µs Min. Typ. Max. Unit OFF-state: Tj = 25 °C; VIN = VDRAIN = 0 V; 10 25 ON-state: Tj = 25 °C; VIN = 5 V; VDS = 0 V 25 Openload OFF-state voltage detection threshold 1. Valid for VNL5050S5-E option Table 12. Supply section(1) Symbol IS VSCL Parameter Supply current Supply clamp voltage Test conditions ISCL = 1 mA ISCL = -1 mA 1. Valid for VNL5050S5-E option 10/33 DocID15917 Rev 6 µA 5.5 65 7 V -0.7 VNL5050N3-E, VNL5050S5-E Electrical characteristics Table 13. Switching characteristics(1) SOT-223(2) Symbol Parameter SO-8 Unit Test conditions Min. Typ. Max Min. Typ. Max. td(ON) Turn-on delay time RL = 6.5 Ω, VCC = 13 V(3) — 6 — — 6 — µs td(OFF) Turn-off delay time RL = 6.5 Ω, VCC = 13 V — 20 — — 20 — µs tr Rise time RL = 6.5 Ω, VCC = 13 V — 10 — — 10 — µs tf Fall time RL = 6.5 Ω, VCC = 13 V — 10 — — 10 — µs WON Switching energy losses at turn-on RL = 6.5 Ω, VCC = 13 V — 0.04 — — 0.04 — mJ WOFF Switching energy losses at turn-off RL = 6.5 Ω, VCC = 13 V — 0.06 — — 0.06 — mJ 1. see Figure 16: VNL5050N3-E application schematic and Figure 17: VNL5050S5-E application schematic 2. 3.5 V ≤ Vsupply = VIN ≤ 5.5 V 3. See Figure 15: Switching characteristics Table 14. Protection and diagnostics Test conditions(1) Symbol Parameter Min. Typ. Max. Unit IlimH DC short-circuit current VDS = 13 V; Vsupply = VIN = 5 V 19 27 38 A IlimL Short-circuit current during thermal cycling VDS = 13 V; TR < Tj < TTSD; Vsupply = VIN = 5 V 11 A tdlimL Step response current limit VDS = 13 V; Vinput = 5 V 44 µs TTSD Shutdown temperature — TR(2) Reset temperature — TRS (3) Thermal reset of STATUS — THYST Thermal hysteresis (TTSD - TR) — 150 175 TRS + 1 TRS + 5 135 200 °C °C °C 7 °C 1. Vsupply = Vinput in VNL5050N3-E version 2. Valid for VNL5050S5-E option DocID15917 Rev 6 11/33 32 Electrical characteristics 3.1 VNL5050N3-E, VNL5050S5-E Electrical characteristics curves Figure 6. Source diode forward characteristics Figure 7. Static drain source on-resistance vs. drain current 521PŸ  9IP9          & 9,1  9   %         $               ,G$     ,'$ $7M ƒ& %7M ƒ& &7M ƒ& 1RWH)NPUTANDSUPP LYPINSCONN ECTEDTO GETHE R ("1($'5 Figure 8. Static drain source on-resistance vs. input voltage ("1($'5 Figure 9. Static drain source on-resistance vs. drain current 5' 6RQ P Ÿ  521PŸ         $   &   ,'  $  %    %  &    $  ' (  )          $7M ƒ& %7M ƒ&   9,19      ,G$ &7M ƒ& 1RWH)NPUTANDSUPP LYPINSCONN ECTEDTO GETHE R $9,1 97 M ƒ& %9,1 97 M ƒ& &9,1 97 M ƒ& '9,1 97 M ƒ& (9,1 97 M ƒ& )9,1 97 M ƒ& 1RWH)NPUTANDSUPP LYPINSCONN ECTEDTO GETHE R ("1($'5 12/33  DocID15917 Rev 6 ("1($'5  VNL5050N3-E, VNL5050S5-E Electrical characteristics Figure 10. Transfer characteristics Figure 11. Transfer characteristics (inside view for VIN = 2 V to 3 V) ,'P$ ,'$      9 '6 9  &     $  %    %  &  9'6 9  & %   $  $              9,19 $7M ƒ&       9,19 %7M ƒ& &7M ƒ& $7M ƒ& 1RWH)NPUTANDSUPP LYPINSCONN ECTEDTO GETHE R %7M ƒ& &7M ƒ& 1RWH)NPUTANDSUPP LYPINSCONN ECTEDTO GETHE R ("1($'5 Figure 12. Output characteristics ("1($'5 Figure 13. Normalized on-resistance vs. temperature ,'$  5RQPŸ   $   %   &  ,RXW $                        9'69 $7M ƒ& %7M ƒ&   &7M ƒ&           7Mƒ& 1RWH)NPUTANDSUPP LYPINSCONN ECTEDTO GETHE R ("1($'5 DocID15917 Rev 6 ("1($'5 13/33 32 Electrical characteristics VNL5050N3-E, VNL5050S5-E Figure 14. Normalized input threshold vs. temperature 9LQWK9   ,G P$                     7Mƒ& 1RWH,QSXWDQGVXSSO\SLQVFRQQHFWHGWRJHWKHU ("1($'5 Table 15. Truth table(1) Conditions INPUT DRAIN STATUS Normal operation L H H L H H Current limitation L H H X H H Overtemperature L H H H H L Undervoltage L H H H X X Output voltage < VOL L H L L L H 1. 14/33 Valid for VNL5050S5-E option DocID15917 Rev 6 VNL5050N3-E, VNL5050S5-E Electrical characteristics Figure 15. Switching characteristics *%  US UG  U UE PGG UE PO 7HFO U ("1($'5 Figure 16. VNL5050N3-E application schematic 9FF 9 5/ 0LFUR&RQWUROOHU ,1387 '5$,1 5SURW 6285&( ("1($'5 DocID15917 Rev 6 15/33 32 Electrical characteristics VNL5050N3-E, VNL5050S5-E Figure 17. VNL5050S5-E application schematic 9FF 9 5/ 9 0LFUR&RQWUROOHU 5VXSSO\ 96833/< '5$,1 N ,1387 5SURW 67$786 5SURW 6285&( '!0'#&4 16/33 DocID15917 Rev 6 VNL5050N3-E, VNL5050S5-E 3.2 Electrical characteristics MCU I/O protection ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching up(a). The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the LSD I/Os (input levels compatibility) with the latch-up limit of microcontroller I/Os: Equation 1 0 .7 I latchup ≤ R prot ≤ (V OH μ C − V IH ) I IH max Let: • Ilatchup > 20 mA • VOHµC > 4.5 V • 35 Ω ≤ Rprot ≤ 100 KΩ Then, the recommended value is Rprot = 1 KΩ Figure 18 shows the turn-off current drawn during the demagnetization. a. In case of negative transient on the drain pin DocID15917 Rev 6 17/33 32 Electrical characteristics VNL5050N3-E, VNL5050S5-E Figure 18. Maximum demagnetization energy 91/[ 0D[LPXPWXUQRIIFXUUHQWYHUVXVLQGXFWDQFH  91/[6LQJOH3XOVH 5HSHWLWLYHSXOVH7MVWDUW ƒ& ,$ 5HSHWLWLYHSXOVH7MVWDUW ƒ&      /P+ 91/[ 0D[LPXPWXUQRII(QHUJ\YHUVXV7GHPDJ  91/[6LQJOH3XOVH 5HSHWLWLYHSXOVH7MVWDUW ƒ& 5HSHWLWLYHSXOVH7MVWDUW ƒ& (>P-@      7GHPDJ>PV@  ("1($'5 1. The voltage supply is VCC = 13.5 V 18/33 DocID15917 Rev 6 VNL5050N3-E, VNL5050S5-E Package and PC board thermal data 4 Package and PC board thermal data 4.1 SOT-223 thermal data Figure 19. SOT-223 PC board 1. Layout condition of Rth and Zth measurements (PCB FR4 area = 30 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 µm, copper areas: from minimum pad lay-out to 0.8 cm2). Figure 20. Rthj-amb vs. PCB copper area in open box free air condition RTHjamb (°C/W) 150 footprint 140 RTHj_amb(°C/W) 130 120 110 100 90 80 70 60 0 0.5 1 1.5 2 2.5 2 PCB Cu heatsink area (cm ) DocID15917 Rev 6 19/33 32 Package and PC board thermal data VNL5050N3-E, VNL5050S5-E Figure 21. SOT-223 thermal impedance junction ambient single pulse ZTH (°C/W) 1000 Cu footprint 100 Cu=2 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 Equation 2: pulse calculation formula Z THδ = R TH Þδ+Z THtp (1 – δ) where δ = tP/T Figure 22. Thermal fitting model of a LSD in SOT-223 1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 20/33 DocID15917 Rev 6 VNL5050N3-E, VNL5050S5-E Package and PC board thermal data Table 16. Thermal parameters Area/island (cm2) Footprint R1 (°C/W) 0.4 R2 (°C/W) 0.8 R3 (°C/W) 4.5 R4 (°C/W) 24 R5 (°C/W) 0.1 R6 (°C/W) 115 C1 (W.s/°C) 0.00006 C2 (W.s/°C) 0.0005 C3 (W.s/°C) 0.03 C4 (W.s/°C) 0.16 C5 (W.s/°C) 1000 C6 (W.s/°C) 0.4 DocID15917 Rev 6 2 45 2 21/33 32 Package and PC board thermal data 4.2 VNL5050N3-E, VNL5050S5-E SO-8 thermal data Figure 23. SO-8 PC board 1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 µm (front and back side), Copper areas: from minimum pad lay-out to 2 cm2). Figure 24. Rthj-amb vs. PCB copper area in open box free air condition RTHjamb (°C/W) 105 footprint RTHj_amb(°C/W) 95 85 75 65 0 0.5 1 1.5 PCB Cu heatsink area (cm2) 22/33 DocID15917 Rev 6 2 2.5 VNL5050N3-E, VNL5050S5-E Package and PC board thermal data Figure 25. SO-8 thermal impedance junction ambient single pulse ZTH (°C/W) 1000 Cu=footprint 100 Cu=2 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 Equation 3: pulse calculation formula Z THδ = R TH Þδ+Z THtp (1 – δ) where δ = tP/T Figure 26. Thermal fitting model of a LSD in SO-8 1. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. DocID15917 Rev 6 23/33 32 Package and PC board thermal data VNL5050N3-E, VNL5050S5-E Table 17. Thermal parameters 24/33 Area/island (cm2) Footprint R1 (°C/W) 0.4 R2 (°C/W) 2.4 R3 (°C/W) 3.5 R4 (°C/W) 21 R5 (°C/W) 16 R6 (°C/W) 58 C1 (W.s/°C) 0.00008 C2 (W.s/°C) 0.0016 C3 (W.s/°C) 0.0075 C4 (W.s/°C) 0.045 C5 (W.s/°C) 0.35 C6 (W.s/°C) 1.05 DocID15917 Rev 6 2 28 2 VNL5050N3-E, VNL5050S5-E Package and packing information 5 Package and packing information 5.1 ECOPACK® In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 SOT-223 mechanical data Figure 27. SOT-223 package dimensions 0046067 DocID15917 Rev 6 25/33 32 Package and packing information VNL5050N3-E, VNL5050S5-E Table 18. SOT-223 mechanical data mm. inch DIM. Min. Typ. A Max. Typ. 1.8 Max. 0.071 B 0.6 0.7 0.85 0.024 0.027 0.033 B1 2.9 3 3.15 0.114 0.118 0.124 c 0.24 0.26 0.35 0.009 0.01 0.014 D 6.3 6.5 6.7 0.248 0.256 0.264 e 2.3 0.09 e1 4.6 0.181 E 3.3 3.5 3.7 0.13 0.138 0.146 H 6.7 7 7.3 0.264 0.276 0.287 V A1 26/33 Min. 10 (max) 0.02 0.1 DocID15917 Rev 6 0.0008 0.004 VNL5050N3-E, VNL5050S5-E 5.3 Package and packing information SO-8 mechanical data Figure 28. SO-8 package dimensions DocID15917 Rev 6 27/33 32 Package and packing information VNL5050N3-E, VNL5050S5-E Table 19. SO-8 mechanical data Millimeters Symbol Min. Typ. A Max. 1.75 A1 0.10 A2 1.25 b 0.28 0.48 c 0.17 0.23 D(1) 4.80 4.90 5.00 E 5.80 6.00 6.20 E1(2) 3.80 3.90 4.00 e 0.25 1.27 h 0.25 0.50 L 0.40 1.27 L1 k 1.04 0° ccc 8° 0.10 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15 mm in total (both side). 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. 28/33 DocID15917 Rev 6 VNL5050N3-E, VNL5050S5-E 5.4 Package and packing information SOT-223 packing information The devices can be packed in tube or tape and reel shipments (see the Table 1: Devices summary on page 1 ). Figure 29. SOT-223 tape and reel shipment (suffix “TR”) Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 12.4 60 18.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (+ 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 All dimensions are in mm. End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed DocID15917 Rev 6 29/33 32 Package and packing information 5.5 VNL5050N3-E, VNL5050S5-E SO-8 packing information Figure 30. SO-8 tube shipment (no suffix) B Base q.ty Bulk q.ty Tube length (± 0.5) A B C (± 0.1) C A 100 2000 532 3.2 6 0.6 All dimensions are in mm. Figure 31. SO-8 tape and reel shipment (suffix “TR”) Reel dimensions Base q.ty Bulk q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm. Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing W P0 (± 0.1) P D (+ 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 All dimensions are in mm. End Start Top cover tape No components Components Empty components pockets saled with cover tape. User direction of feed 30/33 DocID15917 Rev 6 No components 500mm min 500mm min VNL5050N3-E, VNL5050S5-E 6 Revision history Revision history Table 20. Document revision history Date Revision 9-Jan-2008 1 Initial release. 2 Updated corporate template from V2 to V3 Table 3: Suggested connections for unused and n.c. pins – VESD1: updated parameter and value – VESD2: changed value Table 4: Absolute maximum ratings – Rthj-case: deleted max value for SO-8 – Rthj-amb: added max value for both SOT-223 and SO-8 Table 7: Source drain diode – VSD: added typ value Table 8: Input section. – VICL: added min/max value for IS = 1 mA – VINTH: added min/max value Table 9: Status pin – VSTCL: added max value for ISTAT = 1 mA Table 10: Logic input – VICL: added max value for IN = 1 mA Table 12: Supply section – IS: changed unit of measurement for ON-state. – VVSL: added max value for ISTAT = 1 mA Table 13: Switching characteristics – td(OFF): changed typ value both for SOT-223 and SO-8 – WON: added typ value for SO-8 – WOFF: added typ value for SO-8 – Added all typ column for SOT-223 Table 14: Protection and diagnostics – IlimL: changed typ value – tdlimL: changed typ value – Deleted row TR valid for VNL5050N3-E option Added Figure 6: Source diode forward characteristics Added Figure 7: Static drain source on-resistance vs. drain current Added Figure 8: Static drain source on-resistance vs. input voltage Added Figure 9: Static drain source on-resistance vs. drain current Added Figure 10: Transfer characteristics Added Figure 11: Transfer characteristics (inside view for VIN = 2 V to 3 V) Added Figure 12: Output characteristics Added Figure 13: Normalized on-resistance vs. temperature Added Chapter 4: Package and PC board thermal data 25-Jun-2009 Changes DocID15917 Rev 6 31/33 32 Revision history VNL5050N3-E, VNL5050S5-E Table 20. Document revision history (continued) Date 25-Jun-2009 Changes Deleted table 25: SOT-223 mechanical data & package outline Added Figure 27: SOT-223 package dimensions Added Table 18: SOT-223 mechanical data 2 (continued) Deleted table 26: SO-8 mechanical data & package outline Added Figure 28: SO-8 package dimensions Added Table 19: SO-8 mechanical data 3 Updated corporate template from V3 to V3-1 Deleted row for Rthj-case in Table 5: Thermal data 20-Nov-2009 4 Changed the document title Took the first line off the bullet list for Features on cover page Table 4: Absolute maximum ratings – EAS: added new row Table 6: Power MOS section – Vsupply: added new row – RON: updated test conditions Table 8: Input section. – ISS: updated test conditions – Updated the table footnote Table 13: Switching characteristics – Moved footnote 2 and changed its text – WON: changed typ value – WOFF: changed typ value Table 14: Protection and diagnostics – IlimH: updated test conditions – IlimL: updated test conditions – tdlimL: changed typ value Updated Figure 7: Static drain source on-resistance vs. drain current Updated Figure 8: Static drain source on-resistance vs. input voltage Updated Figure 9: Static drain source on-resistance vs. drain current Updated Figure 10: Transfer characteristics Added Figure 11: Transfer characteristics (inside view for VIN = 2 V to 3 V) Updated Figure 14: Normalized input threshold vs. temperature Added Section 3.2: MCU I/O protection 19-Sep-2013 5 Updated Disclaimer. 6 Table 4: Absolute maximum ratings: – -ID: updated value Table 8: Input section.: – IISS: updated value Table 12: Supply section: – IS: updated value Updated Figure 16: VNL5050N3-E application schematic and Figure 17: VNL5050S5-E application schematic Updated Section 3.2: MCU I/O protection 19-Aug-2009 17-Dec-2013 32/33 Revision DocID15917 Rev 6 VNL5050N3-E, VNL5050S5-E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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