TMF3201J

Preliminary Specification Dual N-Channel Dual-Gate MOSFET □ Description The TMF3201J is an N-channel enhancement type, dual-insulated gate, field-effect transistor that utilizes MOS construction. It is consists of two equal dual gate MOSFET amplifiers with shared source and gate2 leads. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT363 microminiature plastic package. TMF3201J SOT363 Unit in mm □ Features - Two AGC amplifiers in a single package - Integrated gate protection diodes - High AGC-range, high gain, low noise figure □ Applications 1. GATE 1(1) 4. DRAIN (2) 5. SOURCE 6. DRAIN (1) -Two gain controlled input stage for UHF and VHF tuners - Professional communications equipment 2. GATE 2 3. GATE 1(2) □ Absolute Maximum Ratings (Ta = 25 ℃) Parameter Per MOSFET ; unless otherwise specified Drain-Source Voltage Drain Current Gate 1 Current Total Power Dissipation Storage Temperature Operating Junction Temperature VDS ID IG1 P tot Ts tg Tj 10 30 ±10 200 -65 ~ 150 150 V mA mA mW ℃ ℃ Symbol Ratings Unit Caution : Electro Static Discharge sensitive device, observe handling precaution http://www.tachyonics.co.kr January 2005. Page 1 of 8 Rev. 1.0 Preliminary Specification □ DC Characteristics ( Tj = 25 ℃, per MOSFET, unless otherwise specified ) PARAMETER Drain-source breakdown voltage Gate1-source breakdown voltage Gate2-source breakdown voltage Forward source-gate1 voltage Forward source-gate2 voltage Gate1-source threshold voltage Gate2-source threshold voltage Drain-source current Gate1 cut-off current Gate2 cut-off current SYMBOL V(BR)DSS V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-S IG2-S CONDITION VG1-S=VG2-S=0; ID=10㎂ VG2-S=VDS=0; IG1-S=10㎃ VG1-S=VDS=0; IG2-S=10㎃ VG2-S=VDS=0; IS-G1=10㎃ VG1-S=VDS=0; IS-G2=10㎃ VDS=5V; VG2-S=4V; ID=100㎂ VDS=5V; VG1-S=4V; ID=100㎂ VG2-S=4V; VDS=5V; RG=62㏀ VG1-S=5V; VG2-S=VDS=0 VG2-S=5V; VG1-S=VDS=0 MIN. 10 6 6 0.5 0.5 0.3 0.3 8 - TMF3201J MAX. 10 10 1.5 1.5 1.0 1.2 16 50 20 UNIT V V V V V V V ㎃ ㎁ ㎁ □ AC Characteristics ( Common source; Ta = 25 ℃, VG2-S = 4V, VDS =5V, ID =12mA ; per MOSFET ;unless otherwise specified ) PARAMETER Forward transfer admittance Input capacitance at gate1 Input capacitance at gate2 Output capacitance Reverse transfer capacitance SYMBOL IyFSI Cig1-ss Cig2-ss Coss Crss CONDITIONS MIN. TYP. MAX. UNIT Tj=25℃ f=1MHz f=1MHz f=1MHz f=1MHz f=200MHz; Zi = S11 , Zo = S22 * * 25 30 26 21 90 30 1.9 3.3 1.4 20 31 28 25 1.5 1.7 - 40 2.5 2.5 - mS ㎊ ㎊ ㎊ fF ㏈ ㏈ ㏈ ㏈ ㏈ ㏈㎶ Power gain Gtr f=400MHz; Zi = S11*, Zo = S22* f=800MHz; Zi = S11*, Zo = S22* f=400MHz; Zi = S11 opt(NF) Noise figure NF f=800MHz; Zi = S11 opt(NF) k=1%, fw=50MHz; funw=60MHz AGC = 0dB Cross-modulation X mod k=1%, fw=50MHz; funw=60MHz AGC = 10dB k=1%, fw=50MHz; funw=60MHz AGC = 40dB - 92 - ㏈㎶ 100 105 - ㏈㎶ http://www.tachyonics.co.kr January. 2005. Page 2 of 8 Rev. 1.0 Preliminary Specification □ Equivalent circuit (Top view) □ Making 6: D(1) 6: D(1) 5: S 4: D(2) 5: S TMF3201J 4: D(2) DA1 1: G1(1) 2: G2 3: G1(2) □ Pin Configuration PIN NO SYMBOL G1(1) G2 G1(2) D(2) S D(1) DESCRIPTION Gate1_Amp1 Gate2 Gate1_Amp2 Drain_Amp2 Source Drain_Amp1 1: G1(1) 2: G2 3: G1(2) 1 2 3 4 5 6 □ Test circuit VAGC R1 10 K O hm C1 22 pF C3 4.7 nF RL C2 4.7 nF RG E N 50 O hm R2 50 O hm RG 1 L1 2.2 uH C4 4.7 nF 50 O hm VGG V DS Fig1. Test Cross-modulation test set-up (for one MOS-FET) http://www.tachyonics.co.kr January. 2005. Page 3 of 8 Rev. 1.0 Scattering parameters Preliminary Specification □ Graphs For One MOSFET TMF3201J ID [ m A ] 45 40 35 30 25 20 15 10 5 0 0.00 0.50 1.00 1.50 2.00 2V VG2=4V 3.5V 3V 2.5V ID [ m A ] 30 25 20 15 10 V G1-S : 1.5V 1.4V 1.3V 1.2V 1.1V 1V 0.9V 1.5V 5 1V 0 2.50 VG1-S [V] 0 1 2 3 4 5 6 V DS [V ] 7 VDS =5V, Tj = 25 ℃ Fig.2 Transfer characteristics 300 IG 1 [ u A ] VG2=4V 3.5V 3V VG2-S = 4V, Tj = 25 ℃ Fig3. Output characteristics | y fs| [m S ] 250 40 35 30 25 4V 3.5V 3V 200 2.5V 150 2V 20 15 2.5V 100 1.5V 10 5 0 50 1V VG2-S = 2 V 0 4 8 12 16 20 ID [mA] 0 0.00 0.50 1.00 1.50 2.00 VG1-S [V] 2.50 VDS =5V, Tj = 25 ℃ Fig.4 Gate1 Current as a function of gate1 Voltage VDS =5V, Tj = 25 ℃ Fig5. Forward transfer admittance as a function of drain current http://www.tachyonics.co.kr January. 2005. Page 4 of 8 Rev. 1.0 Preliminary Specification TMF3201J □ Graphs For One MOSFET ID [ m A ] ID [ m A ] 20 16 14 12 10 8 16 12 8 6 4 2 4 0 0 20 40 60 80 100 IG1 [uA] 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VGG [V] VDS= 5V, V G2-S = 4V, Tj = 25 ℃ Fig6. Drain current as a function of gate1 current VDS= 5V, V G2-S = 4V, RG1=62㏀, Tj = 25 ℃ Fig7. Drain current as a function of gate1 supply voltage 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 R G1 = 3 3KΩ 39KΩ 51KΩ ID [ m A ] ID [ m A ] 20 14 12 10 VGG = 5V 4.5V 4V 3.5V 3V 62KΩ 75KΩ 92KΩ 100KΩ 8 6 4 2 0 5 6 VGG=VDS [V] 0 1 2 3 4 5 6 VG2-S [V] V G2-S = 4V, Tj = 25 ℃, RG1= (Connected to VGG) Fig8. Drain current as a function of gate1 and drain supply voltage ; see Fig1 VDS= 5V, Tj = 25 ℃, RG1=62㏀ Fig9. Drain current as a function of gate2 voltage http://www.tachyonics.co.kr January. 2005. Page 5 of 8 Rev. 1.0 Preliminary Specification □ Graphs For One MOSFET TMF3201J IG 1 [ u A ] 70 60 50 40 30 20 10 0 0.00 3.5V 3V VGG : 5V 4.5V 4V 0 G a in r e d u c t io n [ d B ] -10 -20 -30 -40 -50 1.00 2.00 3.00 4.00 5.00 6.00 VG2-S [V] 0 1 2 3 4 VAGC [V] VDS= 5V, RG1= 62㏀, Tj = 25 ℃ ;Connected to VGG Fig10. Gate1 current as a function of gate2 voltage f=50MHz, Pin=-30dBm, VDS= 5V, VGG= 5V, RG1=62㏀ Tj = 25 ℃ Fig11. Typical Gain reduction as a function of AGC Voltage ; see Fig1 ID [ m A ] 14 12 10 8 6 4 2 0 0 10 20 30 40 50 gain reduction [dB] f=50MHz, Pin=-30dBm, VDS= 5V, VGG= 5V, RG1=62㏀ Fig12. Drain current as a function of gain reduction ; see Fig1 http://www.tachyonics.co.kr January. 2005. Page 6 of 8 Rev. 1.0 Preliminary Specification TMF3201J □ Graphs For One MOSFET Y iS [ m S] | yrs | [ u S ] 100 10 φrs 100 100 -100 bis 1 10 -10 10 |yrs| gis 0 10 100 1000 f [MHz] 1 10 100 -1 1 1000 f [MHz] VDS= 5V, V G2-S = 4V Fig13. Input admittance as a function of frequency VDS= 5V, V G2-S = 4V Fig14. Reverse transfer admittance and phase as a function of frequency | yfs | [ m S ] |yfs| φfs [ d eg ] 100 -100 100 10.00 bos 1.00 Y o S [ m S] 10 -10 10 φfs 0.10 gos 1 10 100 -1 1 1000 0.01 10 100 1000 f [MHz] f [MHz] VDS= 5V, V G2-S = 4V Fig15. Forward transfer admittance and phase as a function of frequency VDS= 5V, V G2-S = 4V Fig16. Output admittance as a function of frequency http://www.tachyonics.co.kr January. 2005. Page 7 of 8 Rev. 1.0 φ rs [ d e g ] 1000 -1000 1000 Preliminary Specification □ Scattering parameters (VG2-S = 4V, VDS =5V, ID =12mA, Τa = 25 ℃) Input Reflection Coefficient TMF3201J Reverse Transmission, dB 0 -20 dB(S(1,2)) freq (10.00MHz to 1.000GHz) S(1,1) -40 -60 -80 1E7 1E8 freq, Hz Output Reflection Coefficient 1E9 Forward Transmission, dB 12 10 8 dB(S(2,1)) 6 4 2 0 1E7 S(2,2) 1E8 freq, Hz 1E9 freq (10.00MHz to 1.000GHz) f (MHz) 50 100 200 300 400 500 600 700 800 S11 Magnitude (ratio) 0.972 0.969 0.963 0.943 0.914 0.889 0.850 0.828 0.791 Angle (deg) -1.335 -6.465 -16.725 -25.621 -33.060 -39.770 -46.540 -54.100 -61.560 Magnitude (ratio) 3.366 3.301 3.172 3.056 2.862 2.711 2.540 2.391 2.220 S21 Angle (deg) 172.420 166.020 153.210 139.903 128.420 117.280 105.930 95.160 84.550 Magnitude (ratio) 0.001 0.002 0.003 0.004 0.004 0.005 0.005 0.006 0.006 S12 Angle (deg) 88.960 86.210 80.730 77.220 76.136 76.090 76.970 77.860 77.315 Magnitude (ratio) 0.996 0.995 0.993 0.984 0.987 0.982 0.979 0.980 0.982 S22 Angle (deg) -2.468 -4.957 -9.935 -14.987 -19.550 -24.580 -28.830 -33.830 -38.460 http://www.tachyonics.co.kr January. 2005. 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