TSS463VAN

Qualpack TSS463 / TSS461C TSS463 VAN Van Controller Serial Interface TSS461C VAN Van Controller TSS463/TSS461C VAN Controllers 1999 January TEMIC SEMICONDUCTORS IS AN ATMEL COMPANY Rev. 2 – January 1999 1 Qualpack TS80C31X2/C32X2 1. Contents 1. Contents........................................................................................................................................................ 2 2. General Information ..................................................................................................................................... 3 3. Technology Information .............................................................................................................................. 4 3.1 W AFER PROCESS TECHNOLOGY ..................................................................................................................... 4 3.2 PRODUCT DESIGN .......................................................................................................................................... 5 3.3 PACKAGE TECHNOLOGY ................................................................................................................................. 6 3.3.1 SOIC.300 16 leads............................................................................................................................... 6 3.3.2 Other available packages .................................................................................................................... 7 3.4 TEST ............................................................................................................................................................. 7 3.5 DEVICE CROSS SECTION ................................................................................................................................ 8 3.6 W AFER PROCESS CONTROL ........................................................................................................................... 9 4. Qualification ............................................................................................................................................... 10 4.1 CHANGE PROCEDURE ................................................................................................................................... 11 4.2 QUALIFICATION FLOW ................................................................................................................................... 12 4.3 W AFER PROCESS QUALIFICATION ................................................................................................................. 13 4.4 PACKAGE QUALIFICATION ............................................................................................................................. 14 4.5 DEVICE QUALIFICATION ................................................................................................................................ 16 4.5.1 ESD and Latch-up results .................................................................................................................. 17 4.5.2 Failure Mechanisms and Corrective Actions ..................................................................................... 17 4.5.3 Qualification status............................................................................................................................. 17 4.6 OUTGOING QUALITY AND RELIABILITY ............................................................................................................ 18 4.6.1 AOQ (Average Outgoing Quality) ...................................................................................................... 18 4.6.2 EFR (Early Failure Rate).................................................................................................................... 19 4.6.3 LFR (Latent Failure Rate) .................................................................................................................. 19 5. User Information ........................................................................................................................................ 20 5.1 SOLDERING RECOMMENDATIONS .................................................................................................................. 20 5.2 DRY PACK ORDERING RULES ..................................................................................................................... 20 5.3 ESD CAUTION .............................................................................................................................................. 20 6. Environmental Information ....................................................................................................................... 21 7. Other Data ................................................................................................................................................... 22 7.1 ISO9001 APPROVAL CERTIFICATE................................................................................................................ 22 7.2 DATABOOK REFERENCE................................................................................................................................ 23 7.3 ADDRESS REFERENCE .................................................................................................................................. 23 8. Revision History......................................................................................................................................... 24 2 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 2. General Information Product Name: Function: Specific features: TSS463 / TSS461C Van Controllers Serial Interface (TSS463) Wafer process: Available plastic package types: Locations: Process, product development Wafer plant QC responsability Assembly Z86E SOIC16 (TSS463), SOIC24 (TSS461C) TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France ANAM, Korea, Philippines Probe test Final test TEMIC Semiconductors Nantes, France GATEWAY Philippines ANAM Korea Quality Assurance Reliability testing Failure analysis TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France TEMIC Semiconductors Nantes, France Quality Assurance Management Nantes Signed.......................................................... Rev. 2 – January 1999 3 Qualpack TS80C31X2/C32X2 3. Technology Information 3.1 Wafer Process Technology Process type (Name): Base material: Wafer Thickness (final) Wafer diameter Number of masks Gate oxide Material Thickness Polysilicon Number of layers Thickness Metal Number of layers Layer 1 material Layer 1 thickness Layer 2 material Layer 2 thickness Passivation Material Thickness CMOS (SCMOS1/2 - Z86E) Silicon Epi substrate type 475um 150mm 13 Silicon dioxide 195 A 1 3000 A 2 TiN/W 600 + 5000 A Ti/AlCu 7000 A Si3N4 on SiO2 10000 A 4 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 3.2 Product Design Die size (TSS463) Die size (TSS461C) Logic Effective channel length Gate poly width Gate poly spacing Metal 1 width Metal 1 spacing Metal 2 width Metal 2 spacing Contact size Via size 11.15mm2 (3610µm*3280µm) 8.46mm2 (3480µm*2610µm) 0.8µm 0.8µm 1.2µm 1.3um 1.5um 1.6um 1.6um 1.0µm 1.4µm Rev. 2 – January 1999 5 Qualpack TS80C31X2/C32X2 3.3 Package Technology 3.3.1 SOIC.300 16 leads Package weight Chip separation method Lead frame Material Thickness Size Lead plating Die attach Material Type Wire bonding Material Diameter Method Molding Material Flammability rating Marking Method Coding example 0,43 g Sawing Cu 10 mils 270*270 mils2 Electroplated Sn/Pb 85/15 Silver epoxy Ablestick 84-1 LMISR4 Gold 33um Thermosonic Nitto MP8000AN UL94V-0 Printed ink TEMIC optional special customer marking TSS463 YY MM No Tube Antistatic PVC 47 Box Cardboard 1692 Device type, Quantity, Date Code, Prod. code Code 39 to EIA-556-A Dry packing Tube packed Primary Material Number per unit Secondary Material Number per unit Labelling (minimum) Bar coding 6 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C Tape packed Primary Material Number per unit Secondary Material Number per unit Labelling (minimum) Bar coding Tape Antistatic PVC 31 Box Cardboard 1116 Device type, Quantity, Date Code, Prod. code Code 39 to EIA-556-A 3.3.2 Other available packages No other package available Dry packing SOIC 16 SOIC 24 No No 3.4 Test Probe equipement Probe temperature Test equipement Test temperature Sentry 15 125°C Sentry 15 25°C, 125°C(sampling) Rev. 2 – January 1999 7 Qualpack TS80C31X2/C32X2 3.5 Device Cross Section N N N N P P P P NMOS Epi Substrate PMOS N- Thin Oxide Polysilicon Planararization Transversal Isolation Oxide Metal 1 Passivation Metal 2 8 Rev. 2 – January 1999 Qualpack TSS463 / TSS461C 3.6 Wafer Process Control All the inspections and controls are defined as a process step in the production management software, and are led by using a centralized SPC software. PC system could be summarized as follows: Engineering Database - N ANTES : hermetic packages - S ubcontractors : plastic packages - N ANTES : hermetic packages - S ubcontractors : plastic packages Physical Critical process parameters are identified by using F.M.E.A. and other advanced tools. Those parameters are followed in real time with the SPC methodology and their capability is measured and monthly reported in the Operation Review. For end 1997, the Cpk target is the following : all parameters with Cpk above 1.67 % of all Parameters per Cpk categories 100% 80% 60% 40% 20% 0% 1995 1996 Q1Q2 97 Q3Q4 97 Obj. 98 >2