71M6403-IGTR

71M6403 Electronic Trip Unit SEPTEMBER 2006 GENERAL DESCRIPTION The Teridian 71M6403 is an electronic trip unit (ETU) system-on-chip device for air circuit breakers (ACB), molded case circuit breakers (MCCB) and other types of intelligent switchgear. Utilizing Teridian’s patented Single Converter Technology, the 71M6403 incorporates a 22-bit delta-sigma ADC, 7 current sensor inputs, digital temperature compensation, precision voltage reference, 32-bit programmable computation engine, timers, Real Time Clock (RTC), two UARTs and a single cycle execution 8-bit MCU. Armed with an internal digital di/dt integrator, this programmable device supports either current transformer (CT) or Rogowski-Coils for any or all input channels and provides instantaneous and delayed over current, earth-leakage, ground-fault and arc fault protection functions. Furthermore, the device may be configured to support any number of conventional or custom protection algorithms that fit specific load configurations in the field. The 71M6403 also includes a 5V LCD charge pump as well as 3V LCD support with up to 168 pixels display and up to 22 DIO pins. Easy conversion to ROM offers unprecedented cost structure for high volume MCCB applications. A complete suite of in-circuit emulator (ICE) and development tools, a powerful real-time signal monitoring tool, programming libraries and reference designs enable rapid development of advanced switchgear. CONVERTER I0 I1 V3.3A V3.3D GNDA GNDD LCD 5V BOOST FEATURES 22-bit Sigma-delta converter Six main sensor inputs One auxiliary input Supports CT or Rogowski Coils Internal di/dt integrators < 5 msec. startup time Better than 10ppm/°C accuracy Instantaneous and delay trip Peak & RMS current measurement Calculated or measured GND current Power measurement functions option Internal temperature sensor Digital temperature compensation Independent 32-bit compute engine Two UART ports Two timers Hardware watchdog Internal power fault detector Real Time Clock (RTC) Battery backup (RTC, RAM) 8-bit MPU (80515) - 1 clock cycle per instruction (5 Mhz max.) LCD driver ( ≤168 pixels) 3/5V LCD Current Sensors I2 I3 I4 I5 INEUTRAL VOLTAGE REF VREF VBIAS SERIAL PORTS TX RX OPTO RX SENSE DRIVE TX COMPARATOR Power Fault Detection V1 V2 INEUTRAL Teridian 71M6403 REGULATOR V2.5 TEMP SENSOR RAM COMPUTE ENGINE FLASH/ ROM LCD DRIVER DIO, PULSE COM0..3 SEG0..23 SEG 24..27 DIO 4..11 SEG 32..41 DIO 12..21 5V LCD charge pump Up to 22 general purpose I/O pins High speed serial interface (SSI) I2C EEPROM interface 64KB Flash, 7KB RAM Flash memory security 30mW @ 3.3V 100-lead LQFP package 88.88.8888 MPU TIMERS DIO 4,5 CLOCK CK38 Accumulator Indicator Trip Indicator External EEPROM 4040 Counter DC in ICE CK 19.6608MHz Page: 1 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Table of Contents GENERAL DESCRIPTION .........................................................................................................................1 FEATURES ..................................................................................................................................1 HARDWARE DESCRIPTION .....................................................................................................................8 Hardware Overview ......................................................................................................................8 External Components ...................................................................................................................8 Analog Front End (AFE) ...............................................................................................................8 Multiplexer......................................................................................................................8 ADC ...............................................................................................................................9 FIR Filter ........................................................................................................................9 Voltage Reference .........................................................................................................9 Temperature Sensor ......................................................................................................10 INEUTRAL .....................................................................................................................10 Functional Description....................................................................................................11 Computation Engine (CE).............................................................................................................11 CE Functional Overview.................................................................................................12 Real-Time Monitor..........................................................................................................13 Power Up Short Circuit Detection Time..........................................................................13 80515 MPU Core..........................................................................................................................14 80515 Overview .............................................................................................................14 Memory Organization .....................................................................................................14 Special Function Registers (SFRs) ................................................................................16 Special Function Registers (Generic 80515 SFRs) ........................................................17 Special Function Registers Specific to the 71M6403 .....................................................19 Instruction Set ................................................................................................................20 UART .............................................................................................................................21 Timers and Counters......................................................................................................24 WD Timer (Software Watchdog Timer) ..........................................................................27 Interrupts ........................................................................................................................29 External Interrupts..........................................................................................................32 Interrupt Priority Level Structure.....................................................................................33 Interrupt Sources and Vectors........................................................................................34 Page: 2 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 On-Chip Resources ......................................................................................................................35 DIO Ports .......................................................................................................................35 Physical Memory............................................................................................................36 Real-Time Clock (RTC)..................................................................................................37 Comparators (V2, INEUTRAL) .......................................................................................38 LCD Drivers....................................................................................................................38 LCD Voltage Boost Circuitry...........................................................................................38 UART (UART0) and Optical Port (UART1) ....................................................................39 Hardware Reset Mechanisms ........................................................................................39 Reset Pin (RESETZ) ......................................................................................................39 Hardware Watchdog Timer ............................................................................................39 Internal Voltages (VBIAS and V2P5)..............................................................................40 Internal Clocks and Clock Dividers.................................................................................41 I2C Interface (EEPROM) ................................................................................................41 Test Ports.......................................................................................................................42 FUNCTIONAL DESCRIPTION ...................................................................................................................44 System Timing Summary .............................................................................................................44 Data Flow .....................................................................................................................................46 CE/MPU Communication..............................................................................................................46 Fault, Reset, Power-Up ................................................................................................................48 Chopping Circuitry ........................................................................................................................48 Program Security..........................................................................................................................49 FIRMWARE INTERFACE...........................................................................................................................50 I/O RAM MAP – In Numerical Order.............................................................................................50 SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order .........................................51 I/O RAM (Configuration RAM) – Alphabetical Order.....................................................................52 CE Program and Environment......................................................................................................58 CE Program ...................................................................................................................58 Formats..........................................................................................................................58 Constants .......................................................................................................................58 Environment ...................................................................................................................58 CE Calculations..............................................................................................................59 CE RAM Locations .......................................................................................................................59 CE Front End Data (Raw Data)......................................................................................59 Input Configuration.........................................................................................................60 Accumulation Strobe Output ..........................................................................................60 Page: 3 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Processed Current Data.................................................................................................61 Overcurrent Detection ....................................................................................................61 MPU Firmware Library..................................................................................................................63 SPECIFICATIONS......................................................................................................................................64 Electrical Specifications................................................................................................................64 ABSOLUTE MAXIMUM RATINGS.................................................................................64 RECOMMENDED OPERATING CONDITIONS.............................................................65 LOGIC LEVELS .............................................................................................................65 SUPPLY CURRENT ......................................................................................................66 2.5V VOLTAGE REGULATOR ......................................................................................66 VREF, VBIAS .................................................................................................................67 ADC CONVERTER, VDD REFERENCED .....................................................................68 OPTICAL INTERFACE ..................................................................................................68 TEMPERATURE SENSOR............................................................................................68 LCD BOOST ..................................................................................................................69 LCD DRIVERS ...............................................................................................................69 RESETZ.........................................................................................................................69 COMPARATORS ...........................................................................................................69 RAM AND FLASH MEMORY .........................................................................................70 FLASH MEMORY TIMING.............................................................................................70 EEPROM INTERFACE ..................................................................................................70 Packaging Information..................................................................................................................71 Pinout (Top View)...........................................................................................................72 Pin Descriptions .............................................................................................................73 ORDERING INFORMATION ........................................................................................................75 Page: 4 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Figures Figure 1: IC Functional Block Diagram ................................................................................................................................ 7 Figure 2: General Topology of a Chopped Amplifier .......................................................................................................... 10 Figure 3: AFE Block Diagram ............................................................................................................................................ 11 Figure 4: Samples in Multiplexer Cycle ............................................................................................................................. 12 Figure 5: Memory Map ..................................................................................................................................................... 14 Figure 6: DIO Ports Block Diagram ................................................................................................................................... 35 Figure 7: LCD Voltage Boost Circuitry............................................................................................................................... 39 Figure 8: V1 Input Voltage Thresholds.............................................................................................................................. 40 Figure 9: Timing Relationship between ADC MUX, CE, and Serial Transfers ..................................................................... 44 Figure 10: RTM Output Format ......................................................................................................................................... 45 Figure 11: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) ................................................................................................... 45 Figure 12: SSI Timing, 16-bit Field Example (External Device Delays SRDY) .................................................................... 45 Figure 13: MPU/CE Data Flow........................................................................................................................................... 46 Figure 14: MPU/CE Communication (Functional).............................................................................................................. 47 Figure 15: MPU/CE Communication (Processing Sequence) ............................................................................................ 47 Figure 16: Chop Polarity w/ Automatic Chopping.............................................................................................................. 48 Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles (EQU = 5) ................................................................. 8 Table 2: CE DRAM Locations for ADC Results .................................................................................................................. 12 Table 3: Stretch Memory Cycle Width............................................................................................................................... 15 Table 4: Internal Data Memory Map.................................................................................................................................. 16 Table 5: Special Function Registers Locations.................................................................................................................. 16 Table 6: Special Function Registers Reset Values............................................................................................................. 17 Table 7: PSW Register Flags............................................................................................................................................. 18 Table 8: PSW bit functions ............................................................................................................................................... 18 Table 9: Port Registers ..................................................................................................................................................... 19 Table 10: Special Function Registers ................................................................................................................................ 20 Table 11: Baud Rate Generation ....................................................................................................................................... 21 Table 12: UART Modes..................................................................................................................................................... 21 Table 13: The S0CON Register ......................................................................................................................................... 22 Table 14: The S1CON register........................................................................................................................................... 22 Table 15: The S0CON Bit Functions .................................................................................................................................. 22 Table 16: The S1CON Bit Functions .................................................................................................................................. 23 Table 17: The TMOD Register........................................................................................................................................... 24 Table 18: TMOD Register Bit Description.......................................................................................................................... 24 Table 19: Timers/Counters Mode Description................................................................................................................... 25 Table 20: The TCON Register............................................................................................................................................ 25 Table 21: The TCON Register Bit Functions ...................................................................................................................... 25 Table 22: Timer Modes..................................................................................................................................................... 26 Page: 5 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Table 23: The PCON Register ........................................................................................................................................... 26 Table 24: PCON Register Bit Description .......................................................................................................................... 26 Table 25: The IEN0 Register ............................................................................................................................................. 27 Table 26: The IEN0 Bit Functions...................................................................................................................................... 27 Table 27: The IEN1 Register ............................................................................................................................................. 27 Table 28: The IEN1 Bit Functions...................................................................................................................................... 27 Table 29: The IP0 Register ............................................................................................................................................... 28 Table 30: The IP0 bit Functions ........................................................................................................................................ 28 Table 31: The WDTREL Register....................................................................................................................................... 28 Table 32: The WDTREL Bit Functions ............................................................................................................................... 28 Table 33: The IEN0 Register ............................................................................................................................................. 29 Table 34: The IEN0 Bit Functions...................................................................................................................................... 29 Table 35: The IEN1 Register ............................................................................................................................................. 30 Table 36: The IEN1 Bit Functions...................................................................................................................................... 30 Table 37: The IEN2 Register ............................................................................................................................................. 30 Table 38: The IEN2 Bit Functions...................................................................................................................................... 30 Table 39: The TCON Register............................................................................................................................................ 31 Table 40: The TCON Bit Functions .................................................................................................................................... 31 Table 41: The IRCON Register .......................................................................................................................................... 31 Table 42: The IRCON Bit Functions................................................................................................................................... 31 Table 43: External MPU Interrupts.................................................................................................................................... 32 Table 44: Control Bits for External Interrupts.................................................................................................................... 32 Table 45: Priority Level Groups ........................................................................................................................................ 33 Table 46: The IP0 Register: .............................................................................................................................................. 33 Table 47: The IP1 Register: .............................................................................................................................................. 33 Table 48: Priority Levels ................................................................................................................................................... 33 Table 49: Interrupt Polling Sequence................................................................................................................................ 34 Table 50: Interrupt Vectors............................................................................................................................................... 34 Table 51: Direction Registers and Internal Resources for DIO Pin Groups........................................................................ 35 Table 52: DIO_DIR Control Bit .......................................................................................................................................... 35 Table 53: Selectable Controls using the DIO_DIR Bits ...................................................................................................... 36 Table 54: MPU Data Memory Map.................................................................................................................................... 36 Table 55: Liquid Crystal Display Segment Table (Typical)................................................................................................. 38 Table 56: EECTRL Status Bits ........................................................................................................................................... 41 Table 57: TMUX[3:0] Selections ....................................................................................................................................... 42 Table 58: SSI Pin Assignment .......................................................................................................................................... 43 Table 59: CHOP_EN Bits................................................................................................................................................... 48 Page: 6 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 VREF I0 I1 I2 I3 I4 I5 INEUTRA L TEMP MUX CTRL MUX_ALT MUX_DIV VBIAS ∆Σ ADC CONVERTER V3P3A GNDA GNDA MUX VBIAS V3P3A + VREF CHOP_EN VREF_DIS VOLTAGE BOOST FIR FILTER FIR_LEN LCD_IBST LCD_BSTEN VDRV VREF GNDD GNDD CK32 VOLT REG V3P3D VBAT GNDD GNDD V2P5 CK38 CK CKTEST CKOUT_EN 38kHz 19.66MH z CLK divider PLLOUT CK_EN 4.9MHz CK_GEN ECK_DIS MPU_DIV MUX_SYNC CKCE 4.9MHz STRT CE 32-bit Compute Engine FAULT_PULSE STROBE RTM DATA 00-FF CKFIR 4.9MHz CE DATA RAM (1KB) 2.5V to logic V2P5 VLCD SSI MUX LCD DISPLAY DRIVER LCD_EN LCD_FS LCD_MODE LCD_NUM LCD_MODE LCD_CLK DIGITAL I/O DIO_EEX FAULT_PULSE STROBE DIO_IN DIO_OUT LCD_NUM DIO_GP I/O RAM COM0..3 SEG6/SRDY SEG0..2, SEG3/SCLK, SEG4/SSDATA, SEG5/SFR, SEG7..19 TEST3 MEMORY SHARE CE CONTROL PRE_SAMPS SUM_CYCLES RTM_EN CE_EN XFER BUSY CE_BUSY PROG 000-7FF 1000-13FF SEG20..23 SEG24/DIO4 .. SEG27/DIO7 SEG28/DIO8 .. SEG31/DIO11 SEG32/DIO12 .. SEG41/DIO21 CE_RUN CE PROG RAM (4KB) CE_LOAD FAULT_PULSE STROBE 3000-3FFF DIO_0..3 RTCLK CKMPU EEPROM INTERFACE 2000-20FF MPU (80515) DATA 0000-FFFF 0000-07FF RTC RTC_HOLD RTC_SET CONFIG RAM (I/O RAM) XFER_BUSY CE_BUSY TX UART SCL SDA CONFIGURATION PARAMETERS DMUX F E D C B A 9 8 7 6 5 4 3 2 1 0 ANALOG DIGITAL RX MPU XRAM (2KB) RTCLK reserved CK_MPU CK_10M MUX_SYNC OPTRX V3 OK V2 OK WDTR_EN RTM VBIAS PLL_2.5V IBIAS DGND OPT_TX OPT_RX OPTICAL I/F OPT_TXDIS VBIAS PROG 0000-FFFF FLASH (64KB) EERDSLOW EEWRSLOW V1 V2 WATCHDOG POWER FAULT GENERATOR AND COMPARATORS INEUTRAL COMP_STAT COMP_INT WAKE V3P3 FAULTZ EMULATOR PORT TMUXOUT TMUX RESETZ September 9, 2006 Figure 1: IC Functional Block Diagram Page: 7 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 HARDWARE DESCRIPTION Hardware Overview The TERIDIAN 71M6403 single chip Electronic Trip Unit integrates all primary functional blocks required to implement a solidstate circuit breaker. Included on chip are an analog front end (AFE), an 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515), an independent 32-bit digital computation engine (CE), a voltage reference, LCD drivers, RAM, FLASH memory, and a variety of I/O pins. Various current sensor technologies are supported including Current Transformers (CT), Resistive Shunts, and Rogowski (di/dt) Coils. Measurements can be displayed on either a 3V or a 5V LCD. Flexible mapping of LCD display segments will facilitate integration with any LCD format. The design trade-off between the number of LCD segments and DIO pins can be flexibly configured using memory-mapped I/O to accommodate various requirements. The 71M6403 includes several I/O peripheral functions that improve the functionality of the device and reduce the component count for most circuit breaker applications. The I/O peripherals include two UARTs, digital I/O, comparator inputs, LCD display drivers, I2C interface and an optical/IR interface. One of the two internal UARTs (UART1) is adapted to support an Infrared LED with higher internal drive output and sense input. It can also be configured to function as a standard UART with normal digital IOs. A block diagram of the chip is shown in Figure 1. A detailed description of various hardware blocks follows. External Components The 71M6403 is optimized for fast startup. To achieve this, an external 19.6608 MHz oscillator is required to drive CK, the primary clock input. The frequency for the CK38 input is generated from the 19.6608 MHz oscillator using an inexpensive ‘HC4040 counter chip. The divide-by-512 output of the ‘HC4040 generates a 38.4 kHz signal. Analog Front End (AFE) The AFE of the TERIDIAN 71M6403 Electronic Trip Unit IC is comprised of an input multiplexer, a delta-sigma A/D converter with internal voltage reference, followed by an FIR filter. A block diagram of the AFE is shown in Figure 3. Multiplexer The input multiplexer supports eight input signals that are applied to the pins I0 through I5, INEUTRAL plus the output of the internal temperature sensor. The multiplexer can be operated in two modes: • • During a normal multiplexer cycle, the signals from the six pins I0 through I5 are selected. During the alternate multiplexer cycle, the temperature signal (TEMP) , INEUTRAL, and I1, I3, I4, I5 (EQU = 101) signal sources are selected. Use of the alternate multiplexer cycle is not recommended for fast response circuit breaker applications. Upon enabling the alternate multiplexer cycle, the I0 and I2 current samples are interrupted delaying over current trip detection response time. Regular multiplexer sequence Mux State: 0 I0 1 I1 2 I2 3 I3 4 I4 5 I5 Alternate multiplexer sequence Mux State: 0 TEMP 1 I1 2 INEUTRAL 3 I3 4 I4 5 I5 Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles (EQU = 101) Note: Use of the alternate multiplexer cycle is not recommend. Page: 8 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 In a typical application, the I0 through I5 inputs are connected to current transformers or Rogowski coils that sense the current on each phase of the line voltage. The Multiplexer Control Circuit handles the setting of the multiplexer. The function of the Multiplexer Control Circuit is governed by the I/O RAM registers MUX_ALT (0x2005[2]) and MUX_DIV (0x2002[7:6]). MUX_DIV controls the number of samples per cycle. It can request 2, 3, 4, or 6 multiplexer states per cycle. Multiplexer Control Circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The Multiplexer Control Circuit is clocked by PLLOUT, the 32768Hz clock from the PLL block derived from CK, and launches each pass through the CE program. ADC A single 21/22-bit delta-sigma A/D converter digitizes the power inputs to the AFE. The ADC inputs I0 - I5 are referenced to V3P3A with an input voltage range of ± 250 mv. The resolution of the ADC is programmable using the I/O RAM register FIR_LEN register (0x2005[4]). ADC resolution may be selected to be 21 bits (FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversion time is two cycles of PLLOUT with FIR_LEN = 0 and three cycles with FIR_LEN = 1. Accuracy, timing and functional specifications in this data sheet are based on FIR_LEN = 0 (two PLLOUT cycles). Initiation of each ADC conversion is controlled by the Multiplexer Control Circuit as described previously. FIR Filter The finite impulse response (FIR) filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data of the FIR filter (raw data) is stored into the CE Data RAM (DRAM) location determined by the multiplexer selection. The location of the raw data in the CE DRAM is specified in the CE Program and Environment Section. Voltage Reference The 71M6403 includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference of the 71M6403 is trimmed in production to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient. The voltage reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register CHOP_ENA (0x2002[5:4]). The two bits in the CHOP_ENA register enable the MPU to operate the chopper circuit in regular or inverted operation, or in “toggling” mode. When the chopper circuit is toggled in between multiplexer cycles, DC offsets on the measured signals will automatically be averaged out. Page: 9 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 The general topology of a chopped amplifier is given in Figure 2. Vinp Vinn CROSS A B A B + G - A B A B Voutp Voutn Figure 2: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS in the “A” position, the output voltage is: Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff With all switches set to the “B” position by applying the inverted CROSS signal, the output voltage is: Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or Voutp – Voutn = G (Vinp – Vinn) - G Voff Thus, when CROSS is toggled, e.g. after each multiplexer cycle, the offset will alternately appear on the output as positive and negative, which results in the offset effectively being eliminated, regardless of its polarity or magnitude. The Functional Description Section contains a chapter with a detailed description on controlling the CHOP_ENA register. Temperature Sensor The 71M6403 includes an on-chip temperature sensor implemented as a bandgap reference. It is used to determine the die temperature. The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT. Reading the internal temperature sensor requires enabling the alternate multiplexer cycle. The alternate multiplexer cycle then displaces a normal I0-I5 current sensors acquisition cycle. Therefore, detection of an over current event may be delayed. INEUTRAL INEUTRAL is an analog monitor input that can be used for additional analog measurements, such as neutral current. It is sampled when the multiplexer performs an alternate multiplexer cycle. The zero reference for the INEUTRAL input is VBIAS. INEUTRAL is also routed into the comparator block where it is compared to VBIAS. External interrupt 2 should be disabled when the INEUTRAL input is used for analog measurements. Page: 10 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Functional Description The AFE functions as a data acquisition system, controlled by the MPU. The main signals (I0, I3, I1, I4, I2, I5) are sampled and the ADC counts obtained are stored in CE RAM where they can be accessed by the CE and, if necessary, by the MPU. VREF I0 I1 I2 I3 I4 I5 INEUTRAL TEMP MUX CTRL CK32 MUX_ALT MUX_DIV VBIAS ∆Σ ADC CONVERTER MUX VBIAS V3P3A + VREF CHOP_EN VREF_DIS FIR FILTER FIR_LEN VREF Figure 3: AFE Block Diagram Computation Engine (CE) The CE, a dedicated 32-bit RISC processor, performs the precision computations necessary to accurately measure currents. The CE calculations and processes include: • Scaling of the processed samples based on chip temperature (temperature compensation) and calibration coefficients. The CE program RAM (CE PRAM) is loaded at boot time by the MPU and then executed by the CE. Each CE instruction word is 2 bytes long. The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the multiplexer cycle ends (see System Timing Summary in the Functional Description Section). The CE data RAM (CE DRAM) is shared by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are reserved for FIR, RTM, and MPU, respectively, such that memory accesses to CE_RAM do not collide. Holding registers are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed, depending on the frequency of CKMPU. Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE. Page: 11 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Name I0 I1 I2 I3 I4 I5 TEMP INEUTRAL Zero Reference V3P3 V3P3 V3P3 V3P3 V3P3 V3P3 --VBIAS Description Current input 0 Current input 1 Current input 2 Current input 3 Current input 4 Current input 5 Temperature INEUTRAL monitor Table 2: CE DRAM Locations for ADC Results CE Functional Overview The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the six samples taken during one multiplexer cycle. The ADC sampling process and resultant accumulation interval calculations are described in the CE Program section. 1/2520.6Hz = 397µs I2 I3 I4 I0 I1 I1 I5 2/32768Hz = 61.04µs 13/32768Hz = 397µs per mux cycle Figure 4: Samples in Multiplexer Cycle Page: 12 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Real-Time Monitor The CE contains a Real Time Monitor (RTM), which can be programmed to monitor four selectable CE RAM locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass (see the Test Ports Section for details) Power Up Short Circuit Detection Time The 71M6403 detects a short circuit condition within less than 5 msec. (T2) after application of its power and a stable reference clock. This delay includes the firmware startup time for both the CE and the MPU, and for the CE to complete its initial measurements. The following diagram shows the timing delay of a CE trip indication relative to application of power and the reference clock. 71M6403 Power T1 Reference Clock T2 CE FAULT_PULSE CE STROBE T1: Delay to stable reference clock operation T2: Delay to CE FAULT_PULSE assertion and first CE STROBE pulse ( < 5 msec) Power Up Detection Time The T1 delay is a system parameter dependent on the system clock architecture. T1 could be the start up time for an external oscillator powered from the same power source as the 71M6403, or T1 could be the delay from a system wide reference clock. If the reference clock is already stable prior to application of power to the 71M6403 (using a system wide reference clock), the T1 delay is eliminated. The resultant start up delay reduces to T2 assuming a “clean” application of power to the 71M6403. Page: 13 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 80515 MPU Core 80515 Overview The 71M6403 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 5MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average) improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency. Actual processor clocking speed can be adjusted to the total processing demand of the application (current and trip calculations, memory management, LCD driver management and I/O management) using the I/O RAM register MPU_DIV[2:0]. Typical measurement and circuit breaker functions based on the internal 32-bit compute engine (CE) results are available for the MPU as part of TERIDIAN’s standard library. A standard ANSI “C” 80515-application programming interface library is available to help reduce design cycle time. Memory Organization The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program memory (Flash), external data memory (physically consisting of XRAM, CE Data RAM, CE Program RAM and I/O RAM), and internal data memory (Internal RAM). Figure 5 shows the memory map (see also Table 54). Internal and External Data Memory: Both internal and external data memory are physically located in the 71M6403 IC. External data memory is only meant to imply external to the 80515 MPU core. 0xFFFF Flash memory 0x0000 Program memory 0xFFFF 0x4000 0x3FFF 0x3000 0x2FFF 0x2100 0x20FF 0x2000 0x1FFF 0x1400 0x13FF 0x1000 0x0FFF 0x0800 0x07FF 0x0000 --CE PRAM --I/O RAM --CE DRAM --XRAM 0xFF 0x00 SFRs, RAM, reg. banks External data memory Figure 5: Memory Map Internal data memory Program Memory: The 80515 can address up to 64KB of program memory space from 0x0000 to 0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation. After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003. Page: 14 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 External Data Memory: While the 80515 can address up to 64KB of external data memory in the space from 0x0000 to 0xFFFF, only the memory ranges shown in Figure 5 contain physical memory. The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8 bytes for the MOVX A,@Ri instruction). Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low ordered bits of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very slow external RAM or external peripherals. Table 3 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state (001) of the CKCON register, which is in bold in the table, performs the MOVX instructions with a stretch value equal to 1. CKCON register CKCON.2 0 0 0 0 1 1 1 1 CKCON.1 0 0 1 1 0 0 1 1 CKCON.0 0 1 0 1 0 1 0 1 Stretch Value 0 1 2 3 4 5 6 7 Read signals width memaddr 1 2 3 4 5 6 7 8 memrd 1 2 3 4 5 6 7 8 Write signal width memaddr 2 3 4 5 6 7 8 9 memwr 1 1 2 3 4 5 6 7 Table 3: Stretch Memory Cycle Width Direct vs Paged Addressing: There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM. In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight lower-ordered bits of address. The eight high-ordered bits of address are specified with the USR2 SFR. This method allows the user paged access (256 pages of 256 bytes each) to the full 64KB of external data RAM. In the second type of MOVX instruction (MOVX A,@DPTR), the data pointer generates a sixteen-bit address. This form is faster and more efficient when accessing very large data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the eight high ordered bits of address. It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two with direct access and two with paged access to the entire 64KB of external memory range. Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called DPTR, the second data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located at the LSB of the DPS register (DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is selected when DPS.0 = 1. The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related instructions use the currently selected DPTR for any activity. The second data pointer may not be supported by certain compilers. Page: 15 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory address is always 1 byte wide and can be accessed by either direct or indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal RAM. The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addressees 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 4 shows the internal data memory map. Address 0xFF 0x80 0x7F 0x30 0x2F 0x20 0x1F 0x00 Direct addressing Special Function Registers (SFRs) Indirect addressing RAM Byte-addressable area Bit-addressable area Register banks R0…R7 Table 4: Internal Data Memory Map Special Function Registers (SFRs) A map of the Special Function Registers is shown in Table 5. Hex\Bin F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 X000 INTBITS B WDI A WDCON PSW IRCON IEN1 IEN0 P2 S0CON P1 TCON P0 X001 X010 X011 X100 X101 X110 X111 Bin/Hex FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 IP1 IP0 DIR2 S0BUF DIR1 TMOD SP S0RELH FLSHCTL S0RELL DIR0 IEN2 DPS TL0 DPL S1RELH USR2 PGADR S1CON TL1 DPH S1BUF ERASE TH0 DPL1 S1RELL TH1 DPH1 EEDATA CKCON WDTREL EECTRL PCON Table 5: Special Function Registers Locations Only a few addresses are occupied, the others are not implemented. SFRs specific to the 71M6403 are shown in bold print. Any read access to unimplemented addresses will return undefined data, while any write access will have no effect. Page: 16 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Special Function Registers (Generic 80515 SFRs) Table 6 shows the location of the SFRs and the value they assume at reset or power-up. Name P0 SP DPL DPH DPL1 DPH1 WDTREL PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 DPS S0CON S0BUF IEN2 S1CON S1BUF S1RELL P2 IEN0 IP0 S0RELL P3 IEN1 IP1 S0RELH S1RELH USR2 IRCON PSW WDCON A B Location 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x90 0x92 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0xA0 0xA8 0xA9 0xAA 0xB0 0xB8 0xB9 0xBA 0xBB 0xBF 0xC0 0xD0 0xD8 0xE0 0xF0 Reset value 0xFF 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xD9 0xFF 0x00 0x00 0x03 0x03 0x00 0x00 0x00 0x00 0x00 0x00 Description Port 0 Stack Pointer Data Pointer Low 0 Data Pointer High 0 Data Pointer Low 1 Data Pointer High 1 Watchdog Timer Reload register UART Speed Control Timer/Counter Control Timer Mode Control Timer 0, low byte Timer 1, high byte Timer 0, low byte Timer 1, high byte Clock Control (Stretch=1) Port 1 Data Pointer select Register Serial Port 0, Control Register Serial Port 0, Data Buffer Interrupt Enable Register 2 Serial Port 1, Control Register Serial Port 1, Data Buffer Serial Port 1, Reload Register, low byte Port 2 Interrupt Enable Register 0 Interrupt Priority Register 0 Serial Port 0, Reload Register, low byte Port 3 Interrupt Enable Register 1 Interrupt Priority Register 1 Serial Port 0, Reload Register, high byte Serial Port 1, Reload Register, high byte User 2 Port, high address byte for MOVX@Ri Interrupt Request Control Register Program Status Word Baud Rate Control Register (only WDCON.7 bit used) Accumulator B Register Table 6: Special Function Registers Reset Values Page: 17 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to the accumulator as “A”, not ACC. B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data. Program Status Word (PSW): MSB CV AC F0 RS1 RS OV P LSB Table 7: PSW Register Flags Bit PSW.7 PSW.6 PSW.5 PSW.4 Symbol CV AC F0 RS1 Function Carry flag Auxiliary Carry flag for BCD operations General purpose Flag 0 available for user. Not to be confused with the F0 flag in the CE STATUS register. Register bank select control bits. The contents of RS1 and RS0 select the working register bank: RS1/RS0 Bank selected Location 00 01 10 11 Bank 0 Bank 1 Bank 2 Bank 3 (0x00 – 0x07) (0x08 – 0x0F) (0x10 – 0x17) (0x18 – 0x1F) PSW.3 RS0 PSW.2 PSW.1 PSW.0 OV P Overflow flag User defined flag Parity flag, affected by hardware to indicate odd / even number of “one” bits in the Accumulator, i.e. even parity. Table 8: PSW bit functions Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08. Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2byte register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively). Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is incremented during the fetching operation code or when operating on data from program memory. Page: 18 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 9) causes the corresponding pin to be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level (GND). The data direction registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see the DIO section in On-Chip Resources for details. Register P0 DIR0 P1 DIR1 P2 DIR2 SFR Address 0x80 0xA2 0x90 0x91 0xA0 0xA1 R/W R/W R/W R/W R/W R/W R/W Description Register for port 0 read and write operations (pins DIO0…DIO7) Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is an output. Register for port 1 read and write operations (pins DIO8…DIO15) Data direction register for port 1. Register for port 2 read and write operations (pins DIO16…DIO21) Data direction register for port 2. Table 9: Port Registers All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P3’), an output driver, and an input buffer, therefore the MPU can output or read data through any of these ports if they are not used for alternate purposes. Special Function Registers Specific to the 71M6403 Table 10 shows the location and description of the 71M6403-specific SFRs. Register ERASE Alternative Name FLSH_ERASE SFR Address 0x94 R/W W Description This register is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle (default = 0x00). 0x55 – Initiate Flash Page Erase cycle. Must be preceded by a write to FLSH_PGADR @ SFR 0xB7. 0xAA – Initiate Flash Mass Erase cycle. Must be preceded by a write to FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled. Any other pattern written to FLSH_ERASE will have no effect. PGADDR FLSH_PGADR 0xB7 R/W Flash Page Erase Address register containing the flash memory page address (page 0 thru 127) that will be erased during the Page Erase cycle (default = 0x00). Must be re-written for each new Page Erase cycle. I2C EEPROM interface data register I2C EEPROM interface control register. If the MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates the transmit sequence. See the section I2C Interface (EEPROM) for a description of the command and status bits available for EECTRL. EEDATA EECTRL 0x9E 0x9F R/W R/W Page: 19 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 FLSHCRL 0xB2 R/W Bit 0 (FLSH_PWE): Program Write Enable: 0 – MOVX commands refer to XRAM Space, normal operation (default). 1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte is written to flash. Writes to this bit are inhibited when interrupts are enabled. Bit 1 (FLSH_MEEN): Mass Erase Enable: 0 – Mass Erase disabled (default). 1 – Mass Erase enabled. Must be re-written for each new Mass Erase cycle. Bit 6 (SECURE): Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored. Bit 7 (PREBOOT): Indicates that the preboot sequence is active. Only byte operations on the whole WDI register should be used when writing. The byte must have all bits set except the bits that are to be cleared. The multi-purpose register WDI contains the following bits: Bit 0 (IE_XFER): XFER Interrupt Flag: This flag monitors the XFER_BUSY interrupt. It is set by hardware and must be cleared by the interrupt handler Bit 1 (IE_ZP8): 0.8sec Interrupt Flag: This flag monitors the ZP8 0.8sec interrupt. It is set by hardware and must be cleared by the interrupt handler Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use. Refer to the External Interrupts description. W R/W R WDI 0xE8 R/W R/W INTBITS INT0…INT6 0xF8 R Table 10: Special Function Registers Instruction Set All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated opcodes is contained in the 64xx Software User’s Guide (SUG). Page: 20 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 UART The 71M6403 includes a UART (UART0) that can be programmed for general purpose communications. A second UART (UART1) is connected to the optical port, as described in the optical port description. The UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at up to 38,400 bits/s (with MPU clock = 1.2288MHz). The operation of each pin is as follows: RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. The voltage applied at RX must not exceed 3.6V. TX: This pin is used to output the serial data. The bytes are output LSB first. The 71M6403 has several UART-related registers, which can be read and written. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. Table 11 shows how the baud rates are calculated. Table 12 shows the selectable UART operation modes. Using Timer 1 Serial Interface 0 Serial Interface 1 2smod * fCKMPU/ (384 * (256-TH1)) N/A Using Internal Baud Rate Generator 2smod * fCKMPU/(64 * (210-S0REL)) fCKMPU/(32 * (210-S1REL)) Note: S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers. SMOD is the SMOD bit in the SFR PCON. TH1 is the high byte of timer 1. Table 11: Baud Rate Generation UART 0 Mode 0 Mode 1 Mode 2 Mode 3 N/A Start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1) Start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of fCKMPU Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator or timer 1) Table 12: UART Modes UART 1 Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator) Start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator) N/A N/A Note: Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits S0CON3 and S1CON3 in the S0COn and S1CON SFRs. Page: 21 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Serial Interface 0 Control Register (S0CON). The function of the UART0 depends on the setting of the Serial Port Control Register S0CON. MSB SM0 SM1 SM20 REN0 TB80 RB80 TI0 LSB RI0 Table 13: The S0CON Register Serial Interface 1 Control Register (S1CON). The function of the serial port depends on the setting of the Serial Port Control Register S1CON. MSB SM SM21 REN1 TB81 RB81 TI1 LSB RI1 Table 14: The S1CON register Bit S0CON.7 Symbol SM0 Function These two bits set the UART0 mode: Mode Description SM0 0 N/A 0 1 2 3 8-bit UART 9-bit UART 9-bit UART 0 1 1 SM1 0 1 0 1 S0CON.6 SM1 S0CON.5 S0CON.4 S0CON.3 SM20 REN0 TB80 Enables the inter-processor communication feature. If set, enables serial reception. Cleared by software to disable reception. The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.) In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0, RB80 is the stop bit. In Mode 0 this bit is not used. Must be cleared by software. Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. Table 15: The S0CON Bit Functions S0CON.2 RB80 S0CON.1 S0CON.0 TI0 RI0 Page: 22 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Bit S1CON.7 Symbol SM Function Sets the baud rate for UART1 SM 0 1 Mode A B Description 9-bit UART 8-bit UART Baud Rate variable variable S1CON.5 S1CON.4 S1CON.3 SM21 REN1 TB81 Enables the inter-processor communication feature. If set, enables serial reception. Cleared by software to disable reception. The 9th transmitted data bit in Mode A. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.) In Modes 2 and 3, it is the 9th data bit received. In Mode B, if sm21 is 0, rb81 is the stop bit. In Mode 0 this bit is not used. Must be cleared by software. Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. Table 16: The S1CON Bit Functions S1CON.2 RB81 S1CON.1 S1CON.0 TI1 RI1 Page: 23 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Timers and Counters The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the MPU clock signal. In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle. Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to select the appropriate mode. Timer/Counter Mode Control register (TMOD): MSB GATE C/T M1 Timer 1 M0 GATE C/T M1 Timer 0 LSB M0 Table 17: The TMOD Register Bits TR1 and TR0 start their associated timers when set. Bit TMOD.7 TMOD.3 TMOD.6 TMOD.2 TMOD.5 TMOD.1 TMOD.4 TMOD.0 Symbol Gate Function If set, enables external gate control (pin int0 or int1 for Counter 0 or 1, respectively). When int0 or int1 is high, and TRX bit is set (see TCON register), a counter is incremented every falling edge on t0 or t1 input pin Selects Timer or Counter operation. When set to 1, a Counter operation is performed. When cleared to 0, the corresponding register will function as a Timer. Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD description. Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD description. Table 18: TMOD Register Bit Description C/T M1 M0 Page: 24 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 M1 0 M0 0 Mode Mode 0 Function 13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1, respectively). The 3 high order bits of TL0 and TL1 are held at zero. 16-bit Counter/Timer. 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TL(x) overflows, a value from TH(x) is copied to TL(x). If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0 bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters. Table 19: Timers/Counters Mode Description 0 1 1 0 Mode 1 Mode2 1 1 Mode3 Note: TL0 is affected by TR0 and gate control bits, and sets TF0 flag on overflow. TH0 is affected by TR1 bit, and sets TF1 flag on overflow. Timer/Counter Control Register (TCON) MSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 LSB IT0 Table 20: The TCON Register Bit TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Function The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. Timer 1 Run control bit. If cleared, Timer 1 stops. Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. Timer 0 Run control bit. If cleared, Timer 0 stops. Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed. Cleared when an interrupt is processed. Interrupt 1 type control bit. Selects either the falling edge or low level on input pin to cause an interrupt. Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is observed. Cleared when an interrupt is processed. Interrupt 0 type control bit. Selects either the falling edge or low level on input pin to cause interrupt. Table 21: The TCON Register Bit Functions Page: 25 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Table 22 specifies the combinations of operation modes allowed for timer 0 and timer 1: Timer 1 Mode 0 Timer 0 - mode 0 Timer 0 - mode 1 Timer 0 - mode 2 YES YES Not allowed Mode 1 YES YES Not allowed Mode 2 YES YES YES Table 22: Timer Modes Timer/Counter Mode Control register (PCON): MSB SMOD -------LSB Table 23: The PCON Register The SMOD bit in the PCON register doubles the baud rate when set. Bit PCON.7 Symbol SMOD Function Table 24: PCON Register Bit Description Page: 26 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 WD Timer (Software Watchdog Timer) The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the internal reset signal becomes active. Note: It is recommended to use the hardware watchdog timer instead of the software watchdog timer. WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing the state of the WDT timer. Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of the WDTREL register and WDT is automatically reset. Special Function Registers for the WD Timer Interrupt Enable 0 Register (IEN0): MSB EAL WDT ET2 ES0 ET1 EX1 ET0 LSB EX0 Table 25: The IEN0 Register Bit IEN0.6 Symbol WDT Function Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT is reset by hardware 12 clock cycles after it has been set. Table 26: The IEN0 Bit Functions Note: The remaining bits in the IEN0 register are not used for watchdog control Interrupt Enable 1 Register (IEN1): MSB EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 LSB Table 27: The IEN1 Register Bit IEN1.6 Symbol SWDT Function Watchdog timer start/refresh flag. Set to activate/refresh the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock cycles after it has been set. Table 28: The IEN1 Bit Functions Note: The remaining bits in the IEN1 register are not used for watchdog control Page: 27 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Interrupt Priority 0 Register (IP0): MSB -WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 LSB IP0.0 Table 29: The IP0 Register Bit IP0.6 Symbol WDTS Function Watchdog timer status flag. Set when the watchdog timer was started. Can be read by software. Table 30: The IP0 bit Functions Note: The remaining bits in the IP0 register are not used for watchdog control Watchdog Timer Reload Register (WDTREL): MSB 7 6 5 4 3 2 1 0 LSB Table 31: The WDTREL Register Bit WDTREL.7 WDTREL.6 to WDTREL.0 Symbol 7 6-0 Function Prescaler select bit. When set, the watchdog is clocked through an additional divide-by-16 prescaler Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT. Table 32: The WDTREL Bit Functions The WDTREL register can be loaded and read at any time. Page: 28 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Interrupts The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and IEN2. External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6403, such as the CE, DIO, EEPROM interface, comparators. Interrupt Overview: When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 50. Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction, "RETI". When an RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address. Interrupt response will require a varying amount of time depending on the state of the MPU when the interrupt occurs. If the MPU is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. In other cases, the response time depends on the current instruction. The fastest possible response to an interrupt is 7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles to perform the LCALL. Special Function Registers for Interrupts: Interrupt Enable 0 register (IE0) MSB EAL WDT ES0 ET1 EX1 ET0 LSB EX0 Table 33: The IEN0 Register Bit IEN0.7 IEN0.6 IEN0.5 IEN0.4 IEN0.3 IEN0.2 IEN0.1 IEN0.0 Symbol EAL WDT ES0 ET1 EX1 ET0 EX0 Function EAL=0 – disable all interrupts Not used for interrupt control ES0=0 – disable serial channel 0 interrupt ET1=0 – disable timer 1 overflow interrupt EX1=0 – disable external interrupt 1 ET0=0 – disable timer 0 overflow interrupt EX0=0 – disable external interrupt 0 Table 34: The IEN0 Bit Functions Page: 29 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Interrupt Enable 1 Register (IEN1) MSB SWDT EX6 EX5 EX4 EX3 EX2 LSB Table 35: The IEN1 Register Bit IEN1.7 IEN1.6 IEN1.5 IEN1.4 IEN1.3 IEN1.2 IEN1.1 IEN1.0 Symbol SWDT EX6 EX5 EX4 EX3 EX2 - Function Not used for interrupt control EX6=0 – disable external interrupt 6 EX5=0 – disable external interrupt 5 EX4=0 – disable external interrupt 4 EX3=0 – disable external interrupt 3 EX2=0 – disable external interrupt 2 Table 36: The IEN1 Bit Functions Interrupt Enable 2 register (IE2) MSB LSB ES1 Table 37: The IEN2 Register Bit IEN2.0 Symbol ES1 Function ES1=0 – disable serial channel 1 interrupt Table 38: The IEN2 Bit Functions Page: 30 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Timer/Counter Control register (TCON) MSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 LSB IT0 Table 39: The TCON Register Bit TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Function Timer 1 overflow flag Not used for interrupt control Timer 0 overflow flag Not used for interrupt control External interrupt 1 flag External interrupt 1 type control bit External interrupt 0 flag External interrupt 0 type control bit Table 40: The TCON Bit Functions Interrupt Request register (IRCON) MSB EX6 IEX5 IEX4 IEX3 IEX2 LSB Table 41: The IRCON Register Bit IRCON.7 IRCON.6 IRCON.5 IRCON.4 IRCON.3 IRCON.2 IRCON.1 IRCON.0 Symbol IEX6 IEX5 IEX4 IEX3 IEX2 Table 42: The IRCON Bit Functions External interrupt 6 edge flag External interrupt 5 edge flag External interrupt 4 edge flag External interrupt 3 edge flag External interrupt 2 edge flag Function Note: Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware when the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is called). Page: 31 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 External Interrupts The external interrupts are connected as shown in Table 43. The polarity of interrupts 2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 43. SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). ZP8 has its own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 44). The ZP8 interrupt must be cleared by the MPU software. The ZP8 interrupt occurs every 853.4 msec. External Interrupt 0 1 2 3 4 5 6 Connection Digital I/O High Priority Digital I/O Low Priority Comparator 2 or 3 Reserved Comparator 2 or 3 EEPROM busy ZP8 Polarity see DIO_Rx see DIO_Rx falling rising falling falling Flag Reset automatic automatic automatic automatic automatic manual Table 43: External MPU Interrupts Interrupt 6 is edge-sensitive. The flag for the ZP8 interrupt is located in the WDI SFR (address 0xE8). Enable Bit EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX_ZP8 Description Enable external interrupt 0 Enable external interrupt 1 Enable external interrupt 2 Enable external interrupt 3 Enable external interrupt 4 Enable external interrupt 5 Enable external interrupt 6 Enable ZP8 interrupt Flag Bit IE0 IE1 IEX2 IEX3 IEX4 IEX5 IEX6 IE_ZP8 Description External interrupt 0 flag External interrupt 1 flag External interrupt 2 flag External interrupt 3 flag External interrupt 4 flag External interrupt 5 flag External interrupt 6 flag ZP8 interrupt flag Table 44: Control Bits for External Interrupts Page: 32 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 45: Group 0 1 2 3 4 5 External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Serial channel 1 interrupt Table 45: Priority Level Groups External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Each group of interrupt sources can be programmed individually to have one of four priority levels by setting or clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal polling sequence as per Table 49 determines which request is serviced first. IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). ZP8 has its own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 44). Note, the ZP8 interrupt must be cleared by the MPU software. Interrupt Priority 0 Register (IP0) MSB -WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 LSB IP0.0 Table 46: The IP0 Register: Note: WDTS is not used for interrupt control Interrupt Priority 1 Register (IP1) MSB IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 LSB IP1.0 Table 47: The IP1 Register: IP1.x 0 0 1 1 IP0.x 0 1 0 1 Priority Level Level0 (lowest) Level1 Level2 Level3 (highest) Table 48: Priority Levels Page: 33 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Table 49: Interrupt Polling Sequence Polling sequence Interrupt Vector Address 0x0003 0x000B 0x0013 0x001B 0x0023 0x0083 0x004B 0x0053 0x005B 0x0063 0x006B External interrupt 2 Interrupt Sources and Vectors Table 50 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 Description External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Serial channel 1 interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Table 50: Interrupt Vectors Page: 34 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 On-Chip Resources DIO Ports The 71M6402 includes up to 22 pins of general purpose digital I/O. 18 of these pins are dual function and can alternatively be used as LCD drivers. Figure 6 shows a block diagram of the DIO section. On reset or power-up, all DIO pins are inputs until they are configured for the desired direction. The pins are configured and controlled by the DIO and DIO_DIR registers (SFRs) and by the five bits of the I/O register LCD_NUM (0x2020[4:0]). See the description for LCD_NUM in the I/O RAM Section for a table listing the available segment pins versus DIO pins, depending on the selection for LCD_NUM. Generally, increasing the value for LCD_NUM will configure an increasing number of general purpose pins to be LCD segment pins, starting at the higher pin numbers. LCD DISPLAY DRIVER LCD_EN LCD_FS LCD_MODE LCD_NUM LCD_MODE LCD_CLK DIGITAL I/O DIO_EEX FAULT_PULSE STROBE DIO_IN DIO_OUT LCD_NUM DIO_GP COM0..3 SEG6/SRDY SEG0..2, SEG3/SCLK, SEG4/SSDATA, SEG5/SFR, SEG7..19 SEG20..23 SEG24/DIO4 .. SEG27/DIO7 SEG28/DIO8 .. SEG31/DIO11 SEG32/DIO12 .. SEG41/DIO21 DIO_0..3 Figure 6: DIO Ports Block Diagram Each pin declared as DIO can be configured independently as an input or output with the bits of the DIO_DIRn registers. Table 51 lists the direction registers and configurability associated with each group of DIO pins. Table 52 shows the configuration for a DIO pin through its associated bit in its DIO_DIR register. DIO Pin Group DIO_0…DIO_3 DIO 4…DIO7 DIO 8…DIO11 DIO 12…DIO15 DIO 16…DIO21 Type DIO only Multi-use Multi-use Multi-use Multi-use MPU Port P0 P0 P1 P1 P2 Direction Register Name DIR0 DIR1 DIR2 Direction Register (SFR) Location 0xA2 [3:0] 0xA2 [7:4] 0x91 [3:0] 0x91[7:4] 0xA1[5:0] Data Register Name P0 P1 P2 Data Register (SFR) Location 0x80 [3:0] 0x80 [7:4] 0x90 [3:0] 0x90[7:4] 0xA0[5:0] Internal resources selectable when configured as DIO Yes Yes Yes No No Table 51: Direction Registers and Internal Resources for DIO Pin Groups DIO_DIR bit 0 DIO Pin Function input 1 output Table 52: DIO_DIR Control Bit Page: 35 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Values read from and written into the DIO ports use the data registers P0, P1 and P2. A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 51 for DIO pins available for this option). This way, DIO pins can be tracked even if they are configured as outputs. This feature is useful for pulse counting. The control resources selectable for the DIO pins are listed in Table 53. If more than one input is connected to the same resource, the resources are combined using a logical OR. DIO_R Value 0 1 2 3 4 5 6 7 Resource Selected for DIO Pin NONE Reserved T0 (counter0 clock) T1 (counter1 clock) High priority I/O interrupt (INT0 rising) Low priority I/O interrupt (INT1 rising) High priority I/O interrupt (INT0 falling) Low priority I/O interrupt (INT1 falling) Table 53: Selectable Controls using the DIO_DIR Bits Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (STROBE = DIO6, FAULT_PULSE = DIO7) using the I/O RAM registers DIO_PW (0x2008[2]) and DIO_PV (0x2008[3]). In this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface by setting the I/O RAM register DIO_EEX (0x2008[4]). Physical Memory Data bus address space is allocated to on-chip memory as shown in Table 54. Address (hex) 0000-FFFF 0000-07FF 1000-13FF 2000-20FF 3000-3FFF Memory Technology Flash Memory Static RAM Static RAM Static RAM Static RAM Memory Type Non-volatile Battery-buffered Volatile Volatile Volatile Typical Usage Program and non-volatile data MPU data XRAM, CE data configuration RAM (I/O RAM) CE Program code Wait States (at 5MHz) 0 0 5 0 5 Memory Size (bytes) 64KB 2KB 1KB 256 4KB Table 54: MPU Data Memory Map Flash Memory: The 71M6403 includes 64KB of on-chip flash memory. The flash memory is intended to primarily contain MPU program code. In a typical application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O RAM. On power-up, before enabling the CE, the MPU must copy these images to their respective memory locations. The I/O RAM bit register FLASH66Z defines the pulse width for accessing flash memory. To minimize supply current draw, this bit should be set to 1. Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent inadvertent erasure of the flash memory. Page: 36 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 The mass erase sequence is: 1. 2. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1]. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94) Note: The mass erase cycle can only be initiated when the ICE port is enabled. The page erase sequence is: 1. 2. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1] Write pattern 0x55 to FLSH_ERASE (SFR address 0x94) The MPU may write to the flash memory. This is one of the non-volatile storage options available to the user. The I/O RAM register FLSH_PWE (flash program write enable, SFR B2[0]) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL =1. Note: Flash write operations in the range 0x2000 to 0x20FF will also affect the I/O RAM. Thus, flash writes to this range have to be either avoided (code must jump around the affected range), or they must contain the data that the I/O RAM expects. MPU RAM: The 71M6403 includes 2KB of static RAM memory on-chip (XRAM), which are backed-up by the battery plus 256bytes of internal RAM in the MPU core. The 2KB of static RAM are used for data storage during normal MPU operations. CE Data RAM: The CE DRAM is the data memory of the CE. The MPU can read and write the CE DRAM as the primary means of data communication between the two processors. CE Program RAM: The CE PRAM is the program memory of the CE. The CE PRAM has to be loaded with CE code before the CE starts operating. CE PRAM cannot be accessed by the MPU when the CE is running. Real-Time Clock (RTC) The RTC is driven directly by an external clock signal provided at the CK38 pin. In the absence of the 3.3V supply, the RTC is powered by the external battery (VBAT pin). The RTC consists of a counter chain and output registers. The counter chain consists of seconds, minutes, hours, day of week, day of month, month, and year. The RTC is capable of processing leap years. Each counter has its own output register. Whenever the MPU reads the seconds register, all other output registers are automatically updated. Since the RTC clock is not coherent to the MPU clock, the MPU must read the seconds register multiple times until two consecutive reads are the same (requires either 2 or 3 reads). At this point, all RTC output registers will have the correct time. Regardless of the MPU clock speed, RTC reads require one wait state. The RTC interrupt must be enabled using the I/O RAM register EX_RTC (address 0x2002[1]). RTC time is set by writing to the I/O RAM registers RTC_SEC, RTC_MIN, through RTC_YR. Each byte written to RTC must be delayed at least 3 CK38 cycles from any previous byte written to the RTC. The RTC counter chain is designed for use with a 32.768 kHz clock source. The 71M6403 requires a 19.6608 MHz master clock for proper CE filter operation. The external (low cost) ‘HC4040 counter generates an approximate clock frequency for the RTC. The ‘HC4040’s divide-by-512 output provides a 38.4 kHz clock signal. Therefore, the RTC runs about 17% faster using the ‘HC4040. A divide-by-600 would generate the ideal 32.768 kHz clock from the 19.6608 MHz oscillator. Alternatively, a 32.768 kHz clock can be sourced independently from the system. Two time-correction bits, the I/O RAM registers RTC_DEC_SEC (0x201C[1]) and RTC_INC_SEC (0x201C[0]) are provided to adjust the RTC time. A pulse on one of these bits causes the time to be decremented or incremented by an additional second at the next update of the RTC_SEC register. Thus, if the temperature coefficient of the clock source at the CK38 pin is known, the MPU firmware can integrate temperature and correct the RTC time as necessary as discussed in temperature compensation. Page: 37 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Comparators (V2, INEUTRAL) The 71M6403 includes two programmable comparators that are connected to the V2 (comparator 2) and INEUTRAL (comparator 3) pins. The I/O RAM register COMP_INT (0x2003[4:3]) allows the user to determine if comparators 2 and 3 will trigger an interrupt to the MPU. The output of each comparator is available in the COMPSTAT register. VBIAS is used as the threshold, and built-in hysteresis prevents each comparator from repeatedly responding to low-amplitude noise. Comparators 2 and 3 can be used for early warning of power faults, or for monitoring of battery or other DC voltages. If they are both selected to interrupt the MPU, their outputs will be XORed together. The voltage at INEUTRAL is also available to the ADC in the AFE, but the comparator should not be used when INEUTRAL is used for analog measurements. LCD Drivers The 71M6403 contains 24 dedicated LCD segment drivers and an additional 18 multi-purpose pins which may be configured as additional LCD segment drivers (see I/O RAM register LCD_NUM). The 71M6403 is capable of driving between 96 to 168 pixels of LCD display with 25% duty cycle. At seven segments per digit, the LCD can be designed for 13 to 24 digits for display. Since each pixel is addressed individually, the LCD display can be a combination of alphanumeric digits and enunciator symbols. The information to be displayed is written into the lower four bits of I/O RAM registers LCD_SEG0 through LCD_SEG41. Bit 0 corresponds to the segment selected when COM0 pin is active while bit 1 is allocated to COM1. The LCD driver circuitry is grouped into 4 common outputs (COM0 to COM3) and up to 42 segment outputs (see Table 55). The typical LCD map is shown below. SEG0 COM0 COM1 COM2 COM3 P0 P1 P2 P3 SEG1 P4 P5 P6 P7 SEG2 P8 P9 P10 P11 SEG3 P12 P13 P14 P15 … ... … ... ... SEG30 P108 P109 P110 P111 … ... ... ... ... SEG41 P164 P165 P166 P167 Table 55: Liquid Crystal Display Segment Table (Typical) Note: P0, P1, … Represent the pixel/segment numbers on the LCD. A charge pump suitable for driving VLCD is included on-chip. This circuit creates 5V from the 3.3V supply. A contrast DAC is provided that permits the LCD full-scale voltage to be adjusted between VLCD and 70% of VLCD. The LCD_NUM register defines the number of dual purpose pins used for LCD segment interface. LCD Voltage Boost Circuitry A voltage boost circuit may be used to generate 5V from the 3.3V supply to support low-power 5V devices, such as LCDs. Figure 7 shows a block diagram of the voltage boost circuitry including the voltage regulators for V2P5 and V2P5NV. When activated using the I/O RAM register LCD_BSTEN (0x2020[7]), the boost circuitry provides an AC voltage at the VDRV output pin (see the Applications section for details). Page: 38 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 VOLTAGE BOOST LCD_IBST LCD_BSTEN VDRV GNDD V2P5NV V3P3D GNDD VOLT REG V3P3D VBAT GNDD GNDD V2P5 0.1V V2P5 VLCD Figure 7: LCD Voltage Boost Circuitry UART (UART0) and Optical Port (UART1) The 71M6403 includes an interface to implement an IR or optical port. The pin OPT_TX is designed to directly drive an external LED for transmitting data on an optical link (low-active). The pin OPT_RX, also low-active, is designed to sense the input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated UART port. OPT_TX can be tristated if it is desired to multiplex another I/O pin to the OPT_TX output. The control bit for the OPT_TX output is the I/O RAM register OPT_TXDIS (0x2008[5]). Hardware Reset Mechanisms Several conditions will cause a hardware reset of the 71M6403: • • Voltage at the RESETZ pin low Voltage at the E_RST pin low Reset Pin (RESETZ) When the RESETZ pin is pulled low, all digital activity in the chip stops while analog circuits are still active. Additionally, all I/O RAM bits are cleared. Hardware Watchdog Timer In addition to the basic software watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, hardware watchdog timer (WDT) is included in the 71M6403. This timer will reset the MPU if it is not refreshed periodically, and can be used to recover the MPU in situations where program control is lost. The watchdog timer uses the RTC clock source as its time base and requires a reset under MPU program control at least every 1.3 (for CK38 = 38.4 kHz) seconds. When the WDT overflow occurs, the MPU is momentarily reset as if RESETZ were pulled low for half of a clock cycle. Thus, after 4100 cycles of CK38, the MPU program will be launched from address 00. An I/O RAM register status bit, WD_OVF (0x2002[2]), is set when WDT overflow occurs. This bit is powered by the VBAT pin and can be read by the MPU to determine if the part is initializing after a WDT overflow event or after a power up. After reading this bit, MPU firmware must clear WD_OVF. The WD_OVF bit is also cleared by the RESETZ pin. Page: 39 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Because the watchdog timer uses CK38 as its clock reference, if the CK clock signal stops or slows down, WD_OVF is set and a system reset will be performed when the CK clock resumes. In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when WAKE=0 and, during development, when a 0x14 command is received from the ICE port. There is no internal digital state that deactivates the WDT. For debug purposes, the WDT can be disabled by tying the V1 pin to V3P3. This also deactivates the power fault detection implemented with V1. Since there is no way in firmware to disable the WDT, it is guaranteed that whatever state the MPU might find itself in, it will be reset to a known state upon watchdog timer overflow. V1 V3P3 V3P3-10mV V3P3 400mV Normal operation, WDT enabled when (V1 < VBIAS) the battery is enabled Battery or reset mode WDT disabled VBIAS = 1.6V 0V Figure 8: V1 Input Voltage Thresholds Internal Voltages (VBIAS and V2P5) The 71M6403 requires two supply voltages, V3P3A, for the analog section, and V3P3D, for the digital section. Both voltages can be tied together outside the chip. The internal supply voltage V2P5 is generated by an internal regulator from the 3.3V supplies. VBIAS (1.6V) is generated internally and is used by the comparators V2 and INEUTRAL. Page: 40 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Internal Clocks and Clock Dividers All internal clocks are based on CK. This frequency is divided by 4 to generate 4.9152MHz, the frequency supplied to the ADC, the FIR filter (CKFIR), the CE DRAM and the clock generator. The clock generator provides two clocks, one for the MPU (CKMPU) and one for the CE (CKCE). The MPU clock frequency is determined by the I/O RAM register MPU_DIV (0x2004[2:0]) and can be CE*2-MPU_DIV Hz where MPU_DIV varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz down to 38.4kHz. The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when the I/O RAM register ECK_DIS (0x2005[5]) is asserted by the MPU. I2C Interface (EEPROM) A dedicated 2-pin serial interface implements an I2C driver that can be used to communicate with external EEPROM devices (type 24C1024). The I2C interface can be enabled onto the DIO pins DIO4 (SCK) and DIO5 (SDA) by setting the I/O RAM register DIO_EEX (0x2008[4]). The MPU communicates with the interface through two SFR registers: EEDATA (0x9E) and EECTRL (0x9F). If the MPU wishes to write a byte of data to the EEPROM, it places the data in EEDATA and then writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates the transmit sequence. By observing the BUSY bit in EECTRL the MPU can determine when the transmit operation is finished (i.e. when the BUSY bit transitions from 1 to 0). INT5 is also asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission. A byte is read by writing the ‘Receive’ command to EECTRL and waiting for BUSY to fall. Upon completion, the received data will appear in EEDATA. The serial transmit and receive clock is 78kHz during each transmission, and SCL is held in a high state until the next transmission. The bits in EECTRL are shown in Table 56. The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. Note: Clock stretching and multi-master operation is not supported for the I2C interface. Status Bit 7 6 5 4 Name ERROR BUSY RX_ACK TX_ACK Read/ Write R R R R Polarity High High High High Description Asserted when an illegal command is received. Asserted when serial data bus is busy. Indicates that the EEPROM sent an ACK bit. Indicates when an ACK bit has been sent to the EEPROM CMD 0 Operation No-op. Applying the no-op command will stop the I2C clock (SCK, DIO4). Failure to issue the no-op command will keep the SCK signal toggling. Receive a byte from EEPROM and send ACK. Transmit a byte to EEPROM Issue a ‘STOP’ sequence Receive the last byte from EEPROM and don’t send ACK. Issue a ‘START’ sequence No Operation, assert ERROR bit 2 3-0 CMD[3:0] W See CMD Table 3 5 6 9 Others Table 56: EECTRL Status Bits Page: 41 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Test Ports TMUXOUT Pin: One out of 16 digital or 4 analog signals can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX (0x2000[3:0]), as shown in Table 57. TMUX[3:0] 0 1 2 3 4 5 6 7 8 9 A B C D E F Mode analog analog analog analog digital digital digital digital digital digital digital digital -digital digital digital Function DGND IBIAS Reserved for production test VBIAS RTM (Real time output from CE) Reserved for production test V2_OK (Comparator 2 Output) INEUTRAL_OK (Comparator 3 Output) RXD (from Optical interface) MUX_SYNC CK_10M CK_MPU reserved for production test CK38 Reserved Reserved Table 57: TMUX[3:0] Selections Emulator Port: The emulator port, consisting of the pins E_RST, E_TCLK and E_RXTX provides control of the MPU through an external in-circuit emulator. The E_TBUS[3:0] pins, together with the E_ISYNC/BRKRQ add trace capability to the emulator. The emulator port is compatible with the ADM51 emulators manufactured by Signum Systems. The signals of the emulator port have weak pull-ups. Adding 3kΩ pull-up resistors on the PCB is recommended. Real-Time Monitor: The RTM output of the CE is available as one of the digital multiplexer options. RTM data is read from the CE DRAM locations specified by I/O RAM registers RTM0, RTM1, RTM2, and RTM3 after the rise of MUX_SYNC. The RTM can be enabled and disabled with I/O RAM register RTM_EN. The RTM output is clocked by CK/4. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. Figure 9 in the System Timing Section illustrates the RTM output format. RTM is low when not in use. Page: 42 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Synchronous Serial Interface (SSI): A high-speed serial interface with handshake capability is available to send a contiguous block of CE data to an external data logger or DSP. The block of data, configurable as to location and size, is sent starting 1 cycle of 32kHz before each CE code pass begins. If the block of data is big enough such that transmission has not completed when the code pass begins, it will complete during the CE code pass with no timing impact to the CE or the serial data. In this case, care must be taken that the transmitted data is not modified unexpectedly by the CE. The SSI interface is enabled by the SSI_EN bit and consists of SCLK, SSDATA, and SFR as outputs and, optionally, SRDY as input. The interface is compatible with 16bit and 32bit processors. The operation of each pin is as follows: SCLK is the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The SSI_CKGATE bit controls whether SCLK runs continuously or is gated off when no SSI activity is occurring. If SCLK is gated, it will begin 3 cycles before SFR rises and will persist 3 cycles after the last data bit is output. The pins used for the SSI are multiplexed with the LCD segment outputs, as shown in Table 58. Thus, the LCD should be disabled when the SSI is in use. SSI Signal SCLK SSDATA SFR SRDY LCD Segment Output Pin SEG3 SEG4 SEG5 SEG6 Table 58: SSI Pin Assignment SRDY is an optional handshake input that indicates that the DSP or data-logging device is ready to receive data. SRDY must be high to enable SFR to rise and initiate the transfer of the next field. It is expected that SRDY changes state on the rising edges of SCLK. If SRDY is not high when the SSI port is ready to transmit the next field, transmission will be delayed until it is. SRDY is ignored except at the beginning of a field transmission. If SRDY is not enabled (by SSI_RDYEN), the SSI port will behave as if SRDY is always one. SSDATA is the serial output data. SSDATA changes on the rising edge of SCLK and outputs the contents of a block of CE RAM words starting with address SSI_STRT and ending with SSI_END. The words are output MSB first. The field size is set with the SSI_FSIZE register: 0 entire data block, 1-8 bit fields, 2-16 bit fields, 3-32 bit fields. The polarity of the SFR pulse can be inverted with SSI_FPOL. If SRDY does not delay it, the first SFR pulse in a frame will rise on the third SCLK after MUX_SYNC (fourth SCLK if 10MHz). MUX_SYNC can be used to synchronize the fields arriving at the data logger or DSP. Page: 43 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 FUNCTIONAL DESCRIPTION System Timing Summary Figure 9 summarizes the timing relationships between the input MUX states. In this example, MUX_DIV=0 (six mux states) and FIR_LEN = 0 (2 PLLOUT cycles). Since FIR filter conversions require two or three PLLOUT cycles, the duration of each MUX cycle is 1 + 2 * states defined by MUX_DIV if FIR_LEN = 0, and 1 + 3 * states defined by MUX_DIV if FIR_LEN = 1. Followed by the conversions is a single PLLOUT cycle. Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue running until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete. The CE code is designed to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into DRAM is shown in Figure 9. Figure 9 also shows that the two serial data streams, RTM and SSI, begin transmitting at the beginning of MUX_SYNC. RTM, consisting of 140 CK cycles, will always finish before the next code pass starts. The SSI port begins transmitting at the same time as RTM, but may significantly overrun the next code pass if a large block of data is required. Neither the CE nor the SSI port will be affected by this overlap. ADC, CE and SERIAL TIMING ADC MUX Frame ADC TIMING PLLOUT MUX_SYNC MUX STATE ADC EXECUTION ADC0 S 150 0 MUX_DIV Conversions (MUX_DIV=4 is shown) Settle 1 2 3 S ADC1 900 ADC2 1350 ADC3 1800 MAX CK COUNT CE TIMING CE_EXECUTION 0 450 CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5) NOTES: 1. ALL DIMENSIONS ARE 5MHZ CK COUNTS. 2. THE PRECISE FREQUENCY OF CK COUNTS IS 150*CRYSTAL FREQUENCY = 4.9152MHz. . Figure 9: Timing Relationship between ADC MUX, CE, and Serial Transfers Page: 44 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Figure 10, Figure 11, and Figure 12 show the RTM and SSI timing, respectively. PLLOUT CK32 MUX_SYNC CK/4 TMUXOUT/RTM LSB 0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31 SIG N SIG N SIG N LSB LSB LSB RTM DATA0 (32 bits) RTM DATA1 (32 bits) RTM DATA2 (32 bits) RTM DATA3 (32 bits) Figure 10: RTM Output Format If SSI_CKGATE =1 If 16bit fields If 32bit fields If SSI_CKGATE =1 SFR (Output) SRDY (Input) SCLK (Output) SSDATA (Output) MUX_SYNC 31 30 16 15 1 0 31 30 16 15 1 0 31 1 SSI_END 0 SSI_BEG SSI_BEG+1 Figure 11: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) Next field is delayed while SRDY is low SFR (Output) SRDY (Input) SCLK (Output) SSDATA (Output) 31 30 29 18 17 16 16 16 16 15 14 13 12 Figure 12: SSI Timing, 16-bit Field Example (External Device Delays SRDY) SFR is the framing pulse. Although CE words are always 32 bits, the SSI interface will frame the entire data block as a single field, as multiple 16-bit fields, or as multiple 32-bit fields. The SFR pulse is one SCLK clock cycle wide, changes state on the rising edge of SCLK and precedes the first bit of each field. Page: 45 of 75 SIG N FLAG FLAG FLAG FLAG © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Data Flow The data flow between CE and MPU is shown in Figure 13. In a typical application, the 32-bit compute engine (CE) sequentially processes the samples from the inputs on pins I0 through I5, performing calculations to measure the currents for circuit breaker operation. These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. IRQ CE CE PreProcessor Data MPU PostProcessor Processed Data I/O RAM (Configuration RAM) Figure 13: MPU/CE Data Flow CE/MPU Communication Figure 14 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and by registers in the CE DRAM. Figure 15 shows the sequence of events between CE and MPU upon reset or power-up. In a typical application, the sequence of events is as follows: 1) 2) 3) 4) 5) Upon power-up, the MPU initializes the hardware, including disabling the CE The MPU loads the code for the CE into the CE PRAM The MPU loads CE data into the CE DRAM. The MPU starts the CE by setting the CE_EN bit in the I/O RAM. The CE then repetitively executes its code, generating results and storing them in the CE DRAM Page: 46 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 FAULT_PULSE DIO7 LCD Comparator STROBE DIO6 FAULT_THRESH SERIAL (UART0/1) MPU DATA ADC SAMPLES EEPROM (I2C) DIO CE Mux Ctrl. I/O RAM (CONFIGURATION RAM) Figure 14: MPU/CE Communication (Functional) The MPU will wait for the CE to signal that fresh data is ready (the XFER interrupt). It will read the data and perform additional processing. CE PRAM FLASH ACCUMULATE INTERRUPT COMPUTATION ENGINE CE DRAM MPU Figure 15: MPU/CE Communication (Processing Sequence) Page: 47 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Fault, Reset, Power-Up Reset Mode: When the RESETZ pin is pulled low, all digital activity in the chip stops while analog circuits are still active. Additionally, all I/O RAM bits are cleared.. When RESETZ goes high the MPU will begin executing its preboot and boot sequences from address 00. See the security section for more description of preboot and boot. Chopping Circuitry As explained in the hardware section, the bits of the I/O RAM register CHOP_ENA[1:0] have to be toggled in between multiplexer cycles to achieve the desired elimination of DC offset. The amplifier within the reference is auto-zeroed by means of an internal signal that is controlled by the CHOP_EN bits. When this signal is HIGH, the connection of the amplifier inputs is reversed. This preserves the overall polarity of the amplifier gain but inverts the input offset. By alternately reversing the connection, the offset of the amplifier is averaged to zero. The function of the two bits of the CHOP_EN register are described in Table 59. CHOP_EN[1] 0 0 1 1 CHOP_EN[0] 0 1 0 1 Function Toggle chop signal Reference connection positive Reference connection reversed Toggle chop signal Table 59: CHOP_EN Bits For automatic chopping, the CHOP_EN bits are set to either 00 or 11. In this mode, the polarity of the signals feeding the reference amplifier will be automatically toggled for each multiplexer cycle as shown in Figure 16. With an even number of multiplexer cycles in each accumulation interval, the number of cycles with positive reference connection will equal the number of cycles with reversed connection, and the offset for each sampled signal will be averaged to zero. This sequence is acceptable when only the primary signals (circuit breaker voltage, circuit breaker current) are of interest. Accumulation Interval m MUX cycle 1 MUX cycle 2 MUX cycle 3 MUX cycle n MUX cycle 1 Accumulation Interval m+1 MUX cycle n Accumulation Interval m+2 MUX cycle 1 Chop Polarity Positive Reversed Positive Reversed Positive Reversed Positive Reversed Positive Reversed Positive CE_BUSY interrupt (falling edge) XFER_BUSY interrupt (falling edge) Figure 16: Chop Polarity w/ Automatic Chopping Page: 48 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Program Security When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked. This guarantees the security of the user’s MPU and CE program code. Security is enabled by MPU code that is executed in a 32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the flash memory, followed by a chip reset. Global flash erase also clears the CE PRAM. The first 32 cycles of the MPU boot code are called the preboot phase because during this phase the ICE is inhibited. A readonly status bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU. Upon completion of the preboot sequence, the ICE can be enabled and is permitted to take control of the MPU. SECURE (SFR 0xB2[6]), the security enable bit, is reset whenever the MPU is reset. Hardware associated with the bit permits only ones to be written to it. Thus, preboot code may set SECURE to enable the security feature but may not reset it. Once SECURE is set, the preboot code is protected and no external read of program code is possible. Specifically, when SECURE is set: • • • The ICE is limited to bulk flash erase only. Page zero of flash memory, the preferred location for the user’s preboot code, may not be page-erased by either MPU or ICE. Page zero may only be erased with global flash erase. Note that global flash erase erases CE program RAM whether SECURE is set or not. Writes to page zero, whether by MPU or ICE, are inhibited. Additionally, by setting the I/O RAM register ECK_DIS to 1, the emulator clock is disabled, inhibiting access to the program with the emulator. Page: 49 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 FIRMWARE INTERFACE I/O RAM MAP – In Numerical Order ‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and should not be changed. Name CE0 CE1 CE2 COMP0 CONFIG0 CONFIG1 VERSION DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 LCDX LCDY LCDZ LCD0 LCD1 LCD2 LCD3 … LCD39 LCD40 LCD41 Note 1: Note 2: Addr Bit 7 Bit 6 Bit 5 Bit 4 CE_EN Bit 3 Bit 2 Bit 1 Bit 0 2000 EQU 1 PRE_SAMPS[1:0] 2001 MUX_DIV[1:0] 2002 2003 2004 VREF_CAL 2005 RESERVED 2006 2008 2009 200A 200B 200C 200D 200E 2020 LCD_BSTEN 2021 2022 2030 2031 2032 2033 … 2057 2058 2059 Configuration: TMUX[3:0] SUM_CYCLES[5:0] CHOP_EN[1:0] RTM_EN WD_OVF EX_ZP8 EX_XFR COMP_INT[1:0] COMP_STAT[2:0] 2 RESERVED Reserved VREF_DIS MPU_DIV ECK_DIS FIR_LEN ADC_DIS MUX_ALT FLASH66Z MUX_E VERSION[7:0] Digital I/O: OPT_TXDIS DIO_R1[2:0] DIO_R3[2:0] DIO_R5[2:0] DIO_R7[2:0] DIO_R9[2:0] DIO_R11[2:0] DIO_EEX DIO_STR DIO_FLT DIO_R0[2:0] DIO_R2[2:0] DIO_R4[2:0] DIO_R6[2:0] DIO_R8[2:0] DIO_R10[2:0] LCD_NUM[4:0] LCD_MODE[2:0] LCD_CLK[1:0] LCD_FS[4:0] LCD_SEG0[3:0] LCD_SEG1[3:0] LCD_SEG2[3:0] LCD_SEG3[3:0] … LCD_SEG39[3:0] LCD_SEG40[3:0] LCD_SEG41[3:0] LCD Display Interface: LCD_EN … Set EQU = 101. Set bit 2004:4 to 0. Page: 50 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 RTM Probes: RTM0 RTM1 RTM2 RTM3 2060 2061 2062 2063 SSI_EN SSI_10M SSI_CKGATE RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] Synchronous Serial Interface: SSI 2070 S S I _ B E G 2071 SSI_END 2072 TRIMSEL 20FD TRIM 20FF SSI_FSIZE[1:0] SSI_BEG[7:0] SSI_END[7:0] TRIMSEL[7:0] TRIM[7:0] SSI_FPOL SSI_RDYEN SSI_RDYPOL Fuse Selection Registers: SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order ‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers. Name P0 DIR0 P1 DIR1 P2 DIR2 INTBITS WDI ERASE FLSHCTL PGADR EEDATA EECTRL SFR Addr 80 A2 90 91 A0 A1 Bit 7 Bit 6 Bit 5 Bit 4 Digital I/O: Bit 3 Bit 2 DIO_0[7:0] DIO_DIR0[7:0] DIO_1[7:0] DIO_DIR1[7:0] DIO_2[5:0] DIO_DIR2[5:0] Bit 1 (Port 0) (Port 1) (Port 2) Bit 0 Interrupts and WD Timer: F8 E8 94 B2 B7 9E 9F INT6 WD_RST INT5 INT4 INT3 INT2 INT1 IE_ZP8 INT0 IE_XFER Flash: FLSH_ERASE[7:0] PREBOOT SECURE FLSH_PGADR[6:0] FLSH_MEEN FLSH_PWE Serial EEPROM: EEDATA[7:0] EECTRL[7:0] Page: 51 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 I/O RAM (Configuration RAM) – Alphabetical Order Many functions of the chip can be controlled via the I/O RAM (Configuration RAM). The CE will also take some of its parameters from the I/O RAM. Bits with a W (write) direction are written by the MPU into I/O RAM. Typically, they are initially stored in flash memory and copied to the I/O RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to 2xxx. Bits with R (read) direction can only be read by the MPU. On power up, all bits are cleared to zero unless otherwise stated. Generic SFR registers are not listed. Name ADC_DIS CE_EN CHOP_EN[1:0] RESERVED COMP_INT[1:0] Location [Bit(s)] 2005[3] 2000[4] 2002[5:4] 2004[5] 2003[4:3] Dir R/W R/W R/W R/W R/W Description Disables ADC and removes bias current CE enable. Chop enable for the reference band gap circuit. 00: enabled 01: disabled 10: disabled 11: enabled Must be 0. Two bits establishing whether a comparator state change should create MPU interrupts. 1: interrupt, 0: no interrupt. If 11, the comparator outputs are XOR’ed. Bit0 = comp2, Bit1 = comp3 Three bits containing comparator output status. Bit0 = comp1, Bit1 = comp2, Bit2 = comp3 Connects dedicated I/O pins 0 to 11 to selectable internal resources. If more than one input is connected to the same resource, the ‘Multiple’ column below specifies how they are combined. See Software User’s Guide for details). DIO_GP 0 1 2 3 4 5 6 7 Resource NONE Reserved T0 (counter0 clock) T1 (counter1 clock) High priority I/O interrupt (int0 rising) Low priority I/O interrupt (int1 rising) High priority I/O interrupt (int0 falling) Low priority I/O interrupt (int1 falling) Multiple -OR OR OR OR OR OR OR COMP_STAT[2:0] DIO_R0[2:0] DIO_R1[2:0] DIO_R2[2:0] DIO_R3[2:0] DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0] 2003[2:0] 2009[2:0] 2009[6:4] 200A[2:0] 200A[6:4] 200B[2:0] 200B[6:4] 200C[2:0] 200C[6:4] 200D[2:0] 200D[6:4] 200E[2:0] 200E[6:4] R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DIO_DIR0[7:0] SFR A2 R/W Programs the direction of DIO pins 7 through 0. 1 indicates output. Ignored if the pin is not configured as I/O. See DIO_EEX for special option for DIO4 and DIO5. Programs the direction of DIO pins 15 through 8. 1 indicates output. Ignored if the pin is not configured as I/O. Programs the direction of DIO pins 21 through 16. 1 indicates output. Ignored if the pin is not configured as I/O. DIO_DIR1[7:0] DIO_DIR2[5:0] SFR 91 SFR A1[5:0] R/W R/W Page: 52 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 DIO_0[7:0] DIO_1[7:0] DIO_2[5:0] DIO_FLT DIO_STR DIO_EEX SFR 80 SFR 90 SFR A0[5:0] 2008[2] 2008[3] 2008[4] R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 The value on the DIO pins. Pins configured as LCD will read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input will ignore writes. Causes FAULT_PULSE to be output on DIO7, if DIO7 is configured as output. LCD_NUM must be less than 15. Initialize DIO_FLT to 1. Causes STROBE to be output on DIO6, if DIO6 is configured as output. LCD_NUM must be less than 16. Initialize DIO_STR to 1. When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 becomes SCK and DIO5 becomes bi-directional SDA. LCD_NUM must be less than 18. Serial EEPROM interface data Serial EEPROM interface control Emulator clock disable. When one, the emulator clock is disabled. Interrupt enable bits. These bits enable the XFER_BUSY and the ZP8 interrupts to the MPU. Note that if either interrupt is to be enabled, EX6 in the 80515 must also be set. The length of the ADC decimation FIR filter. 1: 22 ADC bits/3 PLLOUT cycles (384 CKFIR cycles), 0: 21 ADC bits/2 PLLOUT cycles (288 CKFIR cycles) EEDATA[7:0] EECTRL[7:0] ECK_DIS EX_XFR EX_ZP8 FIR_LEN SFR 9E SFR 9F 2005[5] 2002[0] 2002[1] 2005[4] R/W R/W R/W R/W R/W FLASH66Z FLSH_ERASE 2005[1] SFR 94 R/W W Should be set to 1 to minimize supply current. Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle. (default = 0x00). 0x55 – Initiate Flash Page Erase cycle. Must be preceded by a write to FLSH_PGADR @ SFR 0xB7. 0xAA – Initiate Flash Mass Erase cycle. Must be preceded by a write to FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled. Any other pattern written to FLSH_ERASE will have no effect. FLSH_MEEN SFR B2[1] W Mass Erase Enable 0 – Mass Erase disabled (default). 1 – Mass Erase enabled. Must be re-written for each new Mass Erase cycle. FLSH_PGADR SFR B7[7:1] W Flash Page Erase Address FLSH_PGADR[6:0] – Flash Page Address (page 0 thru 127) that will be erased during the Page Erase cycle. (default = 0x00). Must be re-written for each new Page Erase cycle. Page: 53 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 FLSH_PWE SFR B2[0] R/W Program Write Enable 0 – MOVX commands refer to XRAM Space, normal operation (default). 1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled. Reserved IE_ZP8 INTBITS SFR E8[0] SFR E8[1] SFR F8[6:0] R/W Interrupt flags. These flags are part of the WDI SFR register and monitor the ZP8 interrupt. The flags are set by hardware and must be cleared by the interrupt handler. Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use. Enables the LCD voltage boost circuit. Sets the LCD clock frequency for COM/SEG pins (not the frame rate). Note: fw = CKFIR/128 R LCD_BSTEN LCD_CLK[1:0] 2020[7] 2021[1:0] R/W R/W 00: fw/29, 01: fw/28, 10: fw/27, 11: fw/26 LCD_EN LCD_FS[4:0] 2021[5] 2022[4:0] R/W R/W Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are the COM and SEG outputs. Controls the LCD full scale voltage, VLC2: VLC 2 = VLCD ⋅ (0.7 + 0.3 LCD_MODE[2:0] 2021[4:2] R/W The LCD bias mode. 000: 4 states, 1/3 bias 001: 3 states, 1/3 bias 010: 2 states, ½ bias 011: 3 states, ½ bias 100: static display LCD _ FS ) 31 Page: 54 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 LCD_NUM[4:0] 2020[4:0] R/W Number of dual-purpose LCD/DIO pins to be configured as LCD. This number can be between 0 and 18. The first dual-purpose pin to be used as LCD is SEG41/DIO21. If LCD_NUM = 2, SEG41 and SEG 40 will be configured as LCD. The remaining SEG39 to SEG24 will be configured as DIO19 to DIO4. LCD_NUM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SEG None SEG41 SEG40-41 SEG39-41 SEG38-41 SEG37-41 SEG36-41 SEG35-41 SEG34-41 SEG33-41 SEG32-41 SEG31-41 SEG30-41 SEG29-41 SEG28-41 SEG27-41 SEG26-41 SEG25-41 SEG24-41 DIO4-21 DIO4-20 DIO4-19 DIO4-18 DIO4-17 DIO4-16 DIO4-15 DIO4-14 DIO4-13 DIO4-12 DIO4-11 DIO4-10 DIO4-9 DIO4-8 DIO4-7 DIO4-6 DIO4-5 DIO4 None DIO LCD_SEG0[3:0] … LCD_SEG41[3:0] MPU_DIV[2:0] 2030[3:0] … 2059[3:0] 2004[2:0] R/W LCD Segment Data. Each word contains information for from 1 to 4 time divisions of each segment. In each word, bit 0 corresponds to COM0, on up to bit 3 for COM3. The MPU clock divider (from CKCE). These bits may be programmed by the MPU without risk of losing control. 000 - CKCE, 001 - CKCE/2, …, 111 - CKCE/27 MPU_DIV is 000 on power-up. R/W MUX_ALT MUX_DIV[1:0] 2005[2] 2002[7:6] R/W R/W The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an alternate set of inputs. The number of states in the input multiplexer. 00 - 6 states (I0-I5) 01 - 4 states (I0-I3) 10 - 3 states (I0-I2) 11 - 2 states (I0-I1) MUX_SYNC enable. When high, converts SEG7 into a MUX_SYNC output. MUX_E 2005[0] R/W Page: 55 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 OPT_TXDIS PREBOOT Reserved[1:0] RTM_EN RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] SECURE 2008[5] SFR B2[7] 2001[7:6] 2002[3] 2060 2061 2062 2063 SFR B2[6] R/W R R/W R/W R/W Tristates the OPT_TX output. Indicates that the preboot sequence is active. Reserved Real Time Monitor enable. When ‘0’, the RTM output is low. This bit enables the two wire version of RTM Four RTM probes. Before each CE code pass, the values of these registers are serially output on the RTM pin. The RTM registers are ignored when RTM_EN=0. Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored. Enables the Synchronous Serial Interface (SSI) on SEG3, SEG4, and SEG5 pins. If SSI_RDYEN is set, SEG6 is enabled also. The pins take on the new functions SCLK, SSDATA, SFR, and SRDY, respectively. When SSI_EN is high and LCD_EN is low, these pins are converted to the SSI function, regardless of LCDEN and LCD_NUM. For proper LCD operation, SSI_EN must not be high when LCD_EN is high. SSI clock speed: 0: 5MHz, 1: 10MHz SSI gated clock enable. When low, the SCLK is continuous. When high, the clock is held low when data is not being transferred. SSI frame pulse format: 0: once at beginning of SSI sequence (whole block of data), 1: every 8 bits, 2: every 16 bits, 3: every 32 bits. SFR pulse polarity: 0: positive, 1: negative SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is configured as SRDY. Otherwise, it is an LCD driver. SRDY polarity: 0: positive, 1: negative The beginning and ending address of the transfer region of the CE data memory. If the SSI is enabled, a block of words starting with SSI_BEG and ending with SSI_END will be sent. SSI_END must be larger than SSI_BEG. The maximum number of output words is limited by the number of SSI clocks in a CE code pass—see FIR_LEN, MUX_DIV, and SSI_10M. Reserved R/W SSI_EN 2070[7] R/W SSI_10M SSI_CKGATE SSI_FSIZE[1:0] 2070[6] 2070[5] 2070[4:3] R/W R/W R/W SSI_FPOL SSI_RDYEN SSI_RDYPOL SSI_BEG[7:0] SSI_END[7:0] 2070[2] 2070[1] 2070[0] 2071[7:0] 2072[7:0] R/W R/W R/W R/W Reserved 2001[5:0] R/W Page: 56 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 TMUX[3:0] 2000[3:0] R/W Selects one of 16 inputs for TMUXOUT. 0 – DGND (analog) 1 – IBIAS (analog) 2 – Reserved for production test 3 – VBIAS (analog) 4 – RTM (Real time output from CE) 5 – Reserved for production test 6 – V2_OK (Comparator 2 Output) 7 – INEUTRAL_OK (Comparator 3 Output) 8 – RXD (from Optical interface) 9 – MUX_SYNC (from MUX_CTRL) A – CK_10M B – CK_MPU C – reserved for production test D – CK38 E – Reserved F – Reserved Must be zero. Selects the temperature trim fuse to be read with the TRIM register (TRIMM[2:0]: 4, TRIMBGA: 5, TRIMBGB: 6) Contains TRIMBGA, TRIMBGB, or TRIMM[2:0] depending on the value written to TRIMSEL. The silicon revision number. This data sheet does not apply to revisions preceding revision 000 0100. Enables VREF out to the VREF pin. This feature is disabled when VREF_DIS=1. Disables the internal voltage reference. RESERVED TRIMSEL TRIM VERSION[7:0] VREF_CAL VREF_DIS 2005[7] 20FD 20FF 2006 2004[7] 2004[3] R/W W R R R/W R/W Page: 57 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 CE Program and Environment CE Program The CE program is supplied by TERIDIAN as a data image that can be merged with the MPU operational code for circuit breaker applications. Typically, the CE program covers most applications and does not need to be modified. Proper operation of the CE requires the following environment variables to be set as follows: FIR_LEN = 0, MUX_DIV = 0 and EQU = 101. Formats All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement (-1 = 0xFFFFFFFF). ‘Calibration’ parameters are defined in flash memory (or external EEPROM) and must be copied to CE memory by the MPU before enabling the CE. ‘Internal’ variables are used in internal CE calculations. ‘Input’ variables allow the MPU to control the behavior of the CE code. ‘Output’ variables are outputs of the CE calculations. The corresponding MPU address for the most significant byte is given by 0x1000 + 4 x CE_address and 0x1003 + 4 x CE_address for the least significant byte. Constants Constants used in the CE Data Memory tables are: Sampling frequency: FS = 32768Hz/13 = 2520.62Hz. IMAX is the external rms current corresponding to 250mV pk at the inputs I0 through I5. The system constant IMAX is used by the MPU to convert internal digital quantities (as used by the CE) to external, i.e. current quantities. Their values are determined by the scaling of the current sensors used in an actual circuit breaker. The LSB values used in this document relate digital quantities at the CE or MPU interface to external circuit breaker input quantities. Environment Before starting the CE using the CE_EN bit, the MPU has to establish the proper environment for the CE by implementing the following steps: • • • • • Loading the image for the CE code into CE PRAM. Loading the CE data into CE DRAM. FIR_LEN = 0 (two cycles per conversion) MUX_DIV = 0 (6 conversions per mux cycle) EQU = 101 During operation, the MPU is in charge of controlling the multiplexer cycles. For example, by inserting an alternate multiplexer sequence at regular intervals using MUX_ALT to enable temperature measurement. The polarity of CHOP must be altered for each sample. It must also alternate for each alternate multiplexer reading. Page: 58 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 CE Calculations The CE performs the precision computations necessary to accurately measure and detect current. firmware implements the following: 1. 2. 3. 4. 5. 6. 7. 8. Supports 6 current sensing channels Each channel individually configurable for Current Transformer or Rogowski coil Each channel individually configurable for x8 gain for low signal sensors (MAX out < 20 mV) Channel I4 configurable for Ground Fault current with fundamental frequency band pass filter or the vectorial sum of first current input channel data (Insqsum) Channel I5 includes a band pass filter to process the components of fundamental frequency of operation only Programmable accumulation interval generates interrupt on DIO6 for data collection Programmable FAULT_THRESH register sets over current detection to generate FAULT_PULSE on DIO7 Individual channel calibration coefficients to adjust the gain for desired accuracy The compute engine CE RAM Locations CE Front End Data (Raw Data) Access to the raw data provided by the AFE is possible by reading addresses 0 through 7, as listed below. The table also shows the Configuration Register location for each input channel. Address (HEX) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Input Channel I0 I1 I2 I3 I4 I5 TEMP INEUTRAL Configuration Register 0x28 0x29 0x2A 0x2B 0x2C 0x2D --- Description Current input 0 Current input 1 Current input 2 Current input 3 Current input 4 Current input 5 Temperature INEUTRAL monitor/comparator input to power fault block Page: 59 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Input Configuration The input sensor type and its gain can be set for each current input using the configuration registers 0x28 thru 0x2D, as listed in the table below (bits labeled “X” are “don’t care”): Bit Address 0x28 0x29 0x2A 0x2B 0x2C 0x2D Channel I0 I1 I2 I3 I4 I5 7 X X X X X X 6 X X X X X X 5 X X X X X X 4 X X X X X X 3 X X X X X X 2 X X X X I4SUM X 1 CT/ROG CT/ROG CT/ROG CT/ROG CT/ROG CT/ROG 0 GAIN GAIN GAIN GAIN GAIN GAIN By setting bit 0 = 1, a gain of 8 is applied to the input raw signal associated with the configuration register. When bit 1 is set to 1, the compute engine will process the input signal as a signal from a Rogowski coil sensor. Example: When 0x03 is written to the configuration register at address 0x29, the I1_RAW input signal is processed with a gain of 8 and is also integrated, assuming that it is generated by a Rogowski coil current sensor. The processing for I4 can be selected to implement either a regular current input (I4SUM = 0) or to calculate a vectorial sum of inputs I0, I1, I2, and I3 (I4SUM = 1). When I4SUM is set to 1, all other configuration bits for I4 are ignored. Likewise, the CE ignores the I4SUM bit for all channels other than I4. The NB (narrow-band) register (0x2E) allows control of the band-pass filtering for fundamental components in the channels I4 and I5. When NB is set to 1, the narrow-band filter is activated: Bit Function 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 NB Accumulation Strobe Output Since circuit breaker applications tend to have very short accumulation intervals, the CE supports signaling the end of the accumulation interval by a strobe on the DIO6 pin. This can be used for generating a hardware interrupt. If a hardware interrupt is desired, DIO6 should be configured as an output, and the associated DIO_Rx register in I/O RAM should be used to associate an interrupt source with the pin. The CE generates a low-going strobe of 397µs at the end of each accumulation interval. The control register for the accumulation interval is STR_CNT (address 0x31). This register has a resolution of 397 microseconds. The accumulation interval is controlled by STR_CNT as follows: Accumulation interval = (STR_CNT + 1) * 397µs Example: When STR_CNT is set to (decimal) 12, the accumulation interval will be 5.1 ms. The processed data is available in the following registers. Page: 60 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Processed Current Data Processed current data is available in CE addresses 0x4A through 0x4F, as listed below: Output Register I0SQSUM_X I1SQSUM_X I2SQSUM_X I3SQSUM_X I4SQSUM_X I5SQSUM_X CE Address 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F Description LSB = (IMAX/ln8)2 * 3.3335*10-8 A2 peak LSB = (IMAX/ln8)2 * 3.3335*10-8 A2 Peak LSB = (IMAX/ln8)2 * 3.3335*10-8 A2 Peak LSB = (IMAX/ln8)2 * 3.3335*10-8 A2 Peak LSB = (IMAX/ln8)2 * 3.3335*10-8 A2 Peak LSB = (IMAX/ln8)2 * 3.3335*10-8 A2 Peak The CE writes the output data into the I0SQSUM_X, I1SQSUM_X etc. registers at the end of each accumulation interval. The values for IXSQSUM_X are based on the formula: IXSQSUM _ X = STR _ CNT +1 0 ∑ IXSQ Overcurrent Detection The main task in circuit breaker applications is to detect an over-current situation as quickly as possible and to apply the tripping procedures. The CE firmware has an integrated comparator function that helps to verify each measured sample with reference to the value stored in the FAULT_THRESH register at address 0x2F. If a sample above the programmed FAULT_TRHESH is encountered in one of the input signals I0, I1, I2 or I3, the FAULT_PULSE is generated on the DIO7 pin. This pin should be configured by the MPU to be an output pin and should be internally set to generate an interrupt in order to initiate the necessary routines of the circuit breaker application firmware. The process for generating the FAULT_PULSE from encountering a sample above the programmed threshold can be less than 400µs. CE Register FAULT_THRESH STR_CNT CE Address 0x2F 0x31 Description LSB = (IMAX/ln8) * 5.5719*10-9 A peak STROBE_PULSE = (STR_CNT + 1) * 3.9673*10-4 s Page: 61 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 CE Calibration Parameters The table below lists the parameters that are typically entered to effect calibration of circuit breaker accuracy. CE Address 0x08 0x09 0x0A 0x0B 0x0C 0x0D Name CAL_I0 CAL_I1 CAL_I2 CAL_I3 CAL_I4 CAL_I5 Default 16384 16384 16384 16384 16384 16384 Description These six constants control the gain of their respective channels. The nominal value for each parameter is 214 = 16384. The gain of each channel is directly proportional to its calibration parameter. Thus, if the gain of a channel is 1% slow, CAL should be increased by 1%. Page: 62 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Flash Programming Operational or test code can be programmed into the flash memory using either an in-circuit emulator or the Flash Download Board Module (FDBM) available from TERIDIAN. The flash programming procedure uses the E_RTS, E_RXTX, and E_TCLK pins. MPU Firmware Library All application-specific MPU functions mentioned above under “Application Information” are available from TERIDIAN as a standard ANSI C library and as ANSI “C” source code. The code is available as part of the Demonstration Kit for the 71M6403. The Demonstration Kits come with the 71M6403 IC preprogrammed with demo firmware mounted on a functional example of a circuit breaker PCB (Demo Board). The Demo Boards allow for quick and efficient evaluation of the IC without having to write firmware or having to supply an in-circuit emulator (ICE). A reference guide for firmware development on the 71M6403 is available as a separate document (Software User’s Guide, “SUG”). The User’s Manual supplied with the Demo Kit contains MPU address maps for the demo code as well as other useful information, such as sample calibration procedures. Page: 63 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 SPECIFICATIONS Electrical Specifications ABSOLUTE MAXIMUM RATINGS Supplies and Ground Pins: V3P3D, V3P3A | V3P3D - V3P3A | VLCD GNDD Analog Output Pins: VREF, VBIAS V2P5 Analog Input Pins: I0, I1, I2, I3, I4, I5, V2, INEUTRAL CK38 RX OPT_RX Digital Input Pins: DIO0-21, E_RXTX, E_RST, E_ISYNC/BRKRQ RESETZ All Other Pins: Input pins Output pins Temperature: Operating junction temperature (peak, 100ms) Operating junction temperature (continuous) Storage temperature Solder temperature – 10 second duration ESD Stress: Pins I0, I1, I2, I3, I4, I5, RX, TX, E_RST, E_TCLK, E_RXTX, E_TBUS[n] All other pins 4kV 2kV 140 °C 125 °C −45 °C to 165 °C 250 °C -5mA to 5mA -0.5V to V3P3D+0.5V -30mA to 30mA -0.5 to V3P3D+0.5V -0.5 to 6V -0.5 to V3P3D+0.5V -0.5V to V3P3A+0.5V -0.5V to 3.0V -0.5V to 3.6V -1mA to 1mA -0.5 to V3P3A+0.5V -1mA to 1mA, -0.5 to V3P3A+0.5V -1mA to 1mA, -0.5V to 3.0V −0.5V to 4.6V 0V to 0.5V -0.5V to 7V -0.5V to +0.5V Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. Page: 64 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 RECOMMENDED OPERATING CONDITIONS PARAMETER 3.3V Supply Voltage (V3P3A, V3P3D) † VLCD Operating Temperature † CONDITION Normal Operation Battery Backup MIN 3.0 0 2.9 -40 TYP 3.3 MAX 3.6 3.45 5.5 85 UNIT V V V ºC V3P3A and V3P3D should be shorted together on the circuit board. GNDA and GNDD should also be shorted on the circuit board. LOGIC LEVELS PARAMETER Digital high-level input voltage, VIH Digital low-level input voltage, VIL ILOAD = 1mA Digital high-level output voltage VOH ILOAD = 15mA Digital low-level output voltage VOL Input pull-up current, IIL RESETZ E_RXTX, E_ISYNC/BRKRQ E_RST Input pull down current, IIH CK Input current Other digital inputs -1 1 µA VIN=V3P3D 10 100 µA ILOAD = 1mA ILOAD = 15mA VIN=0V 10 100 µA CONDITION MIN 2 −0.3 V3P3D –0.4 V3P3D0.6 0 0.4 0.8 TYP MAX V3P3D 0.8 V3P3D UNIT V V V V V V Page: 65 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 SUPPLY CURRENT PARAMETER V3P3A + V3P3D + VLCD current V3P3A current V3P3D current VLCD current CONDITION Normal Operation, V3P3A=V3P3D=VLCD=3.3V No Flash memory write VBAT = 3.3V RTM_EN = 0 ECK_DIS = 1 MPU_DIV = 3 Power save/sleep mode V3P3A + V3P3D current V3P3A=V3P3D=VLCD=3.3V ADC_DIS = 1 CE_EN = 0 MPU_DIV = 3 Normal Operation as above, except write Flash at maximum rate. 6 7 mA MIN TYP 8.4 4.4 3.7 0.2 MAX 9.6 4.9 4.2 0.4 UNIT mA mA mA mA V3P3D current, Write Flash 7 mA 2.5V VOLTAGE REGULATOR Unless otherwise specified, load = 5mA PARAMETER Voltage overhead V3P3-V2P5 PSSR ∆V2P5/∆V3P3 CONDITION Reduce V3P3 until V2P5 drops 200mV RESETZ=1, iload=0 -3 MIN TYP MAX 440 +3 UNIT mV mV/V Page: 66 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 VREF, VBIAS Unless otherwise specified, VREF_DIS=0 PARAMETER VREF output voltage, VNOM(25) VREF chop step VREF output impedance VNOM definition 1 VREF temperature coefficients TC1 (linear) TC2 (quadratic) VREF(T) deviation from VNOM(T) CAL =1, ILOAD = 10µA, -10µA 2 VNOM(T) = VREF(22) + (T–22)TC1 + (T–22) TC2 CONDITION Ta = 22ºC MIN 1.193 TYP 1.195 MAX 1.197 40 2.5 UNIT V mV kΩ V µV/ºC µV/°C2 -6.68 -0.341 VREF(T ) − VNOM (T ) 106 VNOM max(| T − 22 |,40) VBIAS output voltage VBIAS output impedance FOOTNOTE 1 Ta = -40ºC to +85ºC -40 +40 ppm/ºC Ta = 25ºC Ta = -40ºC to 85ºC ILOAD = 1mA, -1mA (-1%) (-2%) 1.6 1.6 240 (+1%) (+2%) 500 V V Ω This relationship describes the nominal behavior of VREF at different temperatures. Page: 67 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 ADC CONVERTER, VDD REFERENCED FIR_LEN=0, VREF_DIS=0, VDDREFZ=0 PARAMETER Recommended Input Range (Vin-V3P3A) THD (First 10 harmonics) 250mV-pk 20mV-pk Input Impedance Temperature coefficient of Input Impedance LSB size Digital Full Scale ADC Gain Error vs %Power Supply Variation Vin=65Hz, 64kpts FFT, BlackmanHarris window Vin=65Hz Vin=65Hz 40 1.7 355 +884736 CONDITION MIN -250 TYP MAX 250 -75 -90 90 UNIT mV peak dB dB kΩ Ω/°C nV/LSB LSB 10 6 ∆Nout PK 357 nV / VIN 100 ∆V 3P3 A / 3.3 Input Offset (Vin-V3P3A) Vin=200mV pk, 65Hz V3P3A=3.0v, 3.6V 50 ppm/% -10 10 mV OPTICAL INTERFACE PARAMETER OPT_TX VOH (V3P3D-OPT_TX) OPT_TX VOL OPT_RX Vin Threshold (VinRISING+VinFALLING)/2 OPT_RX Vin Hysteresis (VinRISING-VinFALLING) OPT_RX input impedance |Vin|≤300mV CONDITION ISOURCE=1mA ISINK=20mA 200 5 1 250 MIN TYP MAX 0.4 0.7 300 30 UNIT V V mV mV MΩ TEMPERATURE SENSOR PARAMETER Nominal Sensitivity (Sn) 2 Nominal Offset (Nn) 2 Temperature Error 3 CONDITION TA=25ºC, TA=75ºC Nominal relationship: N(T)= Sn*T+Nn TA = -40ºC to +85ºC MIN TYP -900 400000 -3 3 MAX UNIT LSB/ºC LSB ºC ERR = (T − 25) − FOOTNOTES ( N (T ) − N (25)) Sn This parameter defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with other specs that use this nominal relationship as a reference. 31 This parameter is has been verified in production samples, but is not measured in production. 2 Page: 68 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 LCD BOOST PARAMETER VDRV Frequency VDRV Sink Current VDRV Source Current VLCD Target Voltage VLCD Input Current VLCD=5.0V, LCD_FS=1F, LCD_MODE=0,1,2,3 LCD_BSTEN=1 CONDITION Vol=1.5V Voh=1.5V MIN 1.6 1.2 4.5 TYP CK / 1200 MAX 3.0 2.6 5.7 450 UNIT Hz mA mA V µA LCD DRIVERS Applies to all COM and SEG pins. Unless otherwise stated, VLCD=5.0V, LCD_FS=1F CONDITION PARAMETER MIN VLC0 Max Voltage (LCD_FS =1F) VLC0 Min Voltage (LCD_FS =00) VLC1 Voltage, 1/3 bias ½ bias VLC0 Voltage, 1/3 bias ½ bias Output Impedance With respect to VLCD With respect to VLCD*0.7 With respect to 2*VLCD/3 With respect to VLCD/2 With respect to VLCD/3 With respect to VLCD/2 ∆ILOAD=10µA -0.2 -0.2 -10 -10 -15 -10 TYP MAX 0 0.2 +10 +10 +15 +10 30 UNIT V V % % % % kΩ RESETZ PARAMETER Reset pulse width Reset pulse fall time CONDITION MIN 5 1 TYP MAX UNIT µs µs COMPARATORS PARAMETER Offset Voltage V2-VBIAS INEUTRAL-VBIAS Hysteresis Current V2 INEUTRAL Response Time V2 INEUTRAL CONDITION MIN -20 -20 Vin = VBIAS - 100mV +100mV overdrive 0.5 0.5 50 50 µs µs 0.8 0.8 TYP MAX 15 15 1.2 1.2 UNIT mV mV µA µA Page: 69 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 RAM AND FLASH MEMORY PARAMETER CE RAM wait states Flash write cycles Flash data retention 25°C CONDITION CKMPU = 4.9MHz MIN 5 20,000 100 TYP MAX UNIT Cycles Cycles Years FLASH MEMORY TIMING PARAMETER Write Time per Byte Read Time: No wait states Page Erase (512 bytes) Mass Erase 20 200 ms ms CONDITION MIN TYP 42 MAX UNIT µs EEPROM INTERFACE PARAMETER Write Clock frequency CONDITION CKMPU=4.9MHz, Using interrupts CKMPU=4.9MHz, “bit-banging” DIO4/5 MIN TYP 78 150 MAX UNIT kHz kHz Page: 70 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Packaging Information 100-Pin LQFP PACKAGE OUTLINE (Bottom View) 16.000 +/- 0.300 100 1 14.000 +/- 0.200 MAX. 1.600 1.50 +/- 0.10 0.225 +/- 0.045 0.50 TYP. 0.10 +/- 0.10 0.60 TYP> Side View Page: 71 of 75 16.000 +/- 0.300 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Pinout (Top View) E_TCLK SEG33/DIO13 SEG32/DIO12 E_RST VLCD NC CK38 TEST3Z GNDD GNDA NC OPT_RX V1 V2 INEUTRAL VREF I0 I2 I4 VBIAS I1 I3 I5 V3P3A GNDA 100 99 98 97 96 95 94 90 89 88 87 86 85 84 83 82 81 80 79 78 77 93 92 91 76 GNDD E_RXTX OPT_TX TMUXOUT T X SEG3/SCLK VDRV CK V3P3D SEG4/SSDATA SEG5/SFR E_TBUS[3] E_TBUS[2] E_TBUS[1] E_TBUS[0] SEG37/DIO17 SEG38/DIO18 DIO_0 DIO_1 DIO_2 DIO_3 COM0 COM1 COM2 COM3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TERIDIAN 71M6403 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GNDD RESETZ V2P5 VBAT RX SEG31/DIO11 SEG30/DIO10 SEG29/DIO9 SEG28/DIO8 SEG41/DIO21 SEG40/DIO20 SEG39/DIO19 SEG27/DIO7 SEG26/DIO6 SEG25/DIO5 SEG24/DIO4 SEG23 SEG22 SEG21 SEG20 NC SEG19 SEG18 SEG17 SEG16 Page: 72 of 75 SEG0 SEG1 SEG2 E_ISYNC/BRKRQ SEG34/DIO14 SEG35/DIO15 NC NC SEG36/DIO16 SEG6/SRDY NC SEG7/MUX_SYNC SEG8 SEG9 GNDD SEG10 NC NC NC SEG11 SEG12 NC SEG13 SEG14 SEG15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Pin Descriptions Power/Ground Pins NAME GNDA GNDD V3P3A V3P3D V2P5 VBAT VLCD NC PIN # 76,91 1, 40, 75, 92 77 9 73 72 96 32,33,36, 42,43,44, 47,55,90,95 TYPE P P P P O O P -DESCRIPTION Analog ground: This pin should be connected directly to the analog ground plane. Recommend a common ground plane consisting of both GNDA and GNDD. Digital ground: This pin should be connected directly to the digital ground plane. Recommend a common ground plane consisting of both GNDA and GNDD. Analog power supply: A 3.3V analog power supply should be connected to this pin. Recommend a common power plane consisting of both V3P3A and V3P3D. Digital power supply: A 3.3V digital power supply should be connected to this pin. Recommend a common power plane consisting of both V3P3A and V3P3D. Output of the 2.5V regulator. A 0.1µF capacitor to GNDA should be connected to this pin. Battery backup power supply pin. A battery or super-capacitor may be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3D. LCD power supply. The DC source for the LCD driver circuitry is connected here. No Connect Analog Pins NAME I0 I1 I2 I3 I4 I5 PIN # 84 80 83 79 82 78 TYPE DESCRIPTION I Line Current Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the output of a current transformer. V1 V2 INEUTRAL VBIAS VREF CK38 VDRV 88 87 86 81 85 94 7 I O I/O I O Comparator Inputs - voltage inputs to the internal comparator: The voltages applied to these pins are compared to an internal BIAS voltage of 1.6V. If the input voltage is above VBIAS, the corresponding comparator output will be high (1). V1 is a status signal to the reset circuitry. It may also be used to disable the watchdog timer. Place a 0.1µF capacitor between pin V1 and GNDA. The V2 and INEUTRAL comparator outputs are maintained in COMP_STAT as follows: bit 1 = V2, bit 3 = INEUTRAL. A typical application is to sense the voltage on the DC supply. Reference voltage used by the power fault detection circuit. Voltage Reference for the ADC. A 0.1µF capacitor to GNDA should be connected to this pin. Low-frequency clock input. Provides time base for RTC, watchdog timer and ZP8. Voltage boost output. Page: 73 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 Digital Pins: NAME DIO_3, DIO_2, DIO_1, DIO_0 COM3, COM2, COM1, COM0 SEG0…SEG2, SEG8…SEG23 SEG24/DIO4… ……. SEG41/DIO21 SEG7/MUX_SYNC SEG6/SRDY SEG5/SFR SEG4/SDATA SEG3/SCLK RESETZ RX TX OPT_RX OPT_TX CK TMUXOUT E_RXTX E_TBUS[3] E_TBUS[2] E_TBUS[1] E_TBUS[0] E_ISYNC/BRKRQ E_TCLK E_RST TEST3 PIN # 21 20 19 18 25 24 23 22 See pinout See pinout 37 35 11 10 6 74 71 5 89 3 8 4 2 12 13 14 15 29 100 97 93 TYPE I/O DESCRIPTION Digital input/output pins 0 through 3 O O I/O O I/O O O O I I O I O O O I/O O I/O O I I LCD Common Outputs: These 4 pins provide the select signals for the LCD display. Dedicated LCD segment outputs Multi-use pins, configurable as either LCD SEG driver or DIO. (DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface, STROBE = DIO6, FAULT_PULSE = DIO7 when configured as pulse outputs) Multi-use-pin LCD Segment Output/ MUX_SYNC is output for Synchronous serial interface Multi-use-pin, LCD Segment Outputs/ SRDY input for Synchronous serial interface. Multi-use-pin, LCD Segment Output/ SFR output for SSI. Multi-use-pin, LCD Segment Output/ SDATA output for SSI. Multi-use-pin, LCD Segment Output/ SCLK output for SSI. Chip reset: This pin is used to reset the chip into a known state. For normal operation, this pin is set to 1. To reset the chip, this pin is driven to 0. This pin has an internal 30µA (nominal) current source pull-up but no Schmitt-trigger input circuitry. The minimum width of the pulse is 5µs. A 0.1µF capacitor to GNDA should be connected to this pin. UART input. The voltage applied at this input must be below 3.6V. UART output. Optical Receive Input: This pin receives a signal from an external photo-detector used in an IR serial interface. Optical LED Transmit Output: This pin is designed to directly drive an LED for transmitting data in an IR serial interface. Can be tristated with OPT_TXDIS to be multiplexed with other DIO pins. Clock input (19.6608 MHz) Digital output test multiplexer. Controlled by DMUX[3:0]. Emulator serial data. Emulator trace bus. These pins have internal pull-up resistors. Emulator handshake. This pin has an internal pull-up resistor. Emulator clock. This pin has an internal pull-up resistor. Emulator reset. This pin has an internal pull-up resistor. For TERIDIAN internal use. This pin must be connected to GNDD via a 1kΩ resistor. Page: 74 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0 71M6403 Electronic Trip Unit SEPTEMBER 2006 ORDERING INFORMATION PART DESCRIPTION 71M6403 Electronic Trip Unit, 100-pin LQFP 71M6403 Electronic Trip Unit, 100-pin Lead-Free LQFP 71M6403 Electronic Trip Unit, 100-pin LQFP, T&R 71M6403 Electronic Trip Unit, 100-pin Lead-Free LQFP, T&R ORDERING NUMBER 71M6403-IGT PACKAGE MARKING 71M6403-IGT xxxxxxxxxxxx 71M6403-IGT xxxxxxxxxxxxF 71M6403-IGT xxxxxxxxxxxx 71M6403-IGT xxxxxxxxxxxxF 71M6403-IGT/F 71M6403-IGTR 71M6403-IGTR/F Data Sheet: This Data Sheet is proprietary to TERIDIAN Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corp., 6440 Oak Canyon, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com © 2004-2006 TERIDIAN Semiconductor Corporation 9/21/2006 Page: 75 of 75 © 2006 TERIDIAN Semiconductor Corporation REV 1.0