SiE854DF
Vishay Siliconix
N-Channel 100-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• Ultra Low Thermal Resistance Using TopExposed PolarPAK® Package for DoubleSided Cooling
• Leadframe-Based New Encapsulated Package
- Die Not Exposed
- Same Layout Regardless of Die Size
• Low Qgd/Qgs Ratio Helps Prevent Shoot-Through
• 100 % Rg and UIS Tested
• Compliant to RoHS directive 2002/95/EC
ID (A)
VDS (V)
RDS(on) (Ω)
Silicon
Limit
100
0.0142 at VGS = 10 V
64
Package
Qg (Typ.)
Limit
60a
50 nC
Package Drawing
www.vishay.com/doc?72945
PolarPAK
10
D
9
G
8
S
7
S
6
D
6
7
8
9
10
APPLICATIONS
D
D
S
G
D
• Primary Side Switch
• Half-Bridge
D
G
D
1
G
2
S
S
3
4
Top View
D
5
5
4
3
2
1
Bottom View
S
Top surface is connected to pins 1, 5, 6, and 10
Ordering Information: SiE854DF-T1-E3 (Lead (Pb)-free)
SiE854DF-T1-GE3 (Lead (Pb)-free and Halogen-free)
N-Channel MOSFET
For Related Documents
www.vishay.com/ppg?69824
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage
Gate-Source Voltage
Symbol
VDS
VGS
TC = 25 °C
Continuous Drain Current (TJ = 150 °C)
TC = 70 °C
TA = 25 °C
TA = 70 °C
Pulsed Drain Current
Continuous Source-Drain Diode Current
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
ID
IDM
TC = 25 °C
TA = 25 °C
IS
L = 0.1 mH
IAS
EAS
TC = 25 °C
TC = 70 °C
Maximum Power Dissipation
TA = 25 °C
TA = 70 °C
Operating Junction and Storage Temperature Range
PD
Limit
100
± 20
64 (Silicon Limit)
60a (Package Limit)
52
13.2b, c
10.5b, c
60
60a
4.3b, c
40
80
125
80
5.2b, c
3.3b, c
- 55 to 150
260
Unit
V
A
mJ
W
TJ, Tstg
°C
Soldering Recommendations (Peak Temperature)d, e
Notes:
a. Package limited.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See Solder Profile (www.vishay.com/doc?73257). The PolarPAK is a leadless package. The end of the lead terminal is exposed copper (not
plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
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1
SiE854DF
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Symbol
RthJA
t ≤ 10 s
Maximum Junction-to-Ambienta, b
Maximum Junction-to-Case (Drain Top)
Steady State
Maximum Junction-to-Case (Source)a, c
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. Maximum under Steady State conditions is 68 °C/W.
c. Measured at source pin (on the side of the package).
Typical
Maximum
20
24
RthJC (Drain)
0.8
1
RthJC (Source)
2.2
2.7
Unit
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
VGS = 0 V, ID = 250 µA
100
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS
ΔVDS/TJ
ΔVGS(th)/TJ
VGS(th)
IGSS
Zero Gate Voltage Drain Current
IDSS
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
ID(on)
On-State Drain Currenta
a
R
Drain-Source On-State Resistance
DS(on)
gfs
Forward Transconductancea
Dynamicb
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Total Gate Charge
Qg
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
Rg
Gate Resistance
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Drain-Source Body Diode Characteristics
IS
Continuous Source-Drain Diode Current
ISM
Pulse Diode Forward Currenta
VSD
Body Diode Voltage
trr
Body Diode Reverse Recovery Time
Qrr
Body Diode Reverse Recovery Charge
ta
Reverse Recovery Fall Time
tb
Reverse Recovery Rise Time
ID = 250 µA
VDS = VGS , ID = 250 µA
VDS = 0 V, VGS = ± 20 V
VDS = 100 V, VGS = 0 V
VDS = 100 V, VGS = 0 V, TJ = 55 °C
VDS ≥ 5 V, VGS = 10 V
VGS = 10 V, ID = 13.2 A
VDS = 15 V, ID = 13.2 A
VDS = 50 V, VGS = 0 V, f = 1 MHz
VDS = 50 V, VGS = 10 V, ID = 13.2 A
f = 1 MHz
VDD = 50 V, RL = 5 Ω
ID ≅ 10 A, VGEN = 10 V, Rg = 1 Ω
V
120
- 10
2.5
4.4
± 100
1
10
25
0.0117
30
3100
250
95
50
16
13
1
15
10
30
10
TC = 25 °C
IS = 10 A
IF = 10 A, dI/dt = 100 A/µs, TJ = 25 °C
mV/°C
0.8
70
195
56
14
0.0142
V
nA
µA
A
Ω
S
pF
75
nC
1.5
25
15
45
15
60
60
1.2
110
300
Ω
ns
A
V
ns
nC
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
SiE854DF
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
60
20
TC = - 55 °C
VGS = 10 V thru 7 V
16
I D - Drain Current (A)
I D - Drain Current (A)
50
40
VGS = 6 V
30
20
8
TC = 25 °C
4
10
VGS = 4 V
0
0.0
TC = 125 °C
VGS = 5 V
0
0.4
0.8
1.2
1.6
2.0
0
2
3
4
5
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.0120
4000
0.0118
3200
0.0116
VGS = 10 V
0.0114
1
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
12
0.0112
6
Ciss
2400
1600
800
Coss
0.0110
0
0
10
20
30
40
50
60
Crss
0
20
ID - Drain Current (A)
40
80
100
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
10
2.2
ID = 13.2 A
2.0
VDS = 50 V
8
ID = 13.2 A
1.8
RDS(on) - On-Resistance
(Normalized)
VGS - Gate-to-Source Voltage (V)
60
VDS = 80 V
6
4
2
VGS = 10 V
1.6
1.4
1.2
1.0
0.8
0.6
0
0
10
20
30
40
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
50
60
0.4
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
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SiE854DF
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
0.030
ID = 13.2 A
RDS(on) - On-Resistance (Ω)
I S - Source Current (A)
0.025
TJ = 25 °C
TJ = 150 °C
10
TA = 125 °C
0.020
0.015
TA = 25 °C
0.010
0.005
0
0.2
0.4
0.6
0.8
1.0
4
1.2
6
7
8
9
10
VSD - Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
4.0
50
3.5
40
3.0
ID = 250 µA
2.5
2.0
1.5
- 50
5
Source-Drain Diode Forward Voltage
Power (W)
V GS(th) (V)
1
0.0
30
20
10
- 25
0
25
50
75
100
125
150
0
0.01
0.1
1
TJ - Temperature (°C)
10
100
1000
Time (s)
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
100
Limited by R DS(on)*
100 us
I D - Drain Current (A)
10
1 ms
10 ms
1
100 ms
1s
0.1
10 s
TA = 25 °C
Single Pulse
BVDSS
DC
0.01
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which R DS(on) is specified
Safe Operating Area, Junction-to-Ambient
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Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
SiE854DF
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
80
140
70
120
Power Dissipation (W)
I D - Drain Current (A)
60
Package Limited
50
40
30
20
100
80
60
40
20
10
0
0
0
25
50
75
100
TC - Case Temperature (°C)
Current Derating*
125
150
25
50
75
100
125
150
TC - Case Temperature (°C)
Power Derating, Junction-to-Case
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
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5
SiE854DF
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 55 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.1
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case (Drain Top)
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Source
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?69824.
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Document Number: 69824
S09-1338-Rev. B, 13-Jul-09
Legal Disclaimer Notice
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Disclaimer
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Revision: 01-Jan-2022
1
Document Number: 91000