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TPS54318 - 2.95V To 6V Input, 3A Output, 2MHz, Synchronous Step Down Switcher With Integrated FETs ( SWIFT™) - Texas Instruments

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TPS54318
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TPS54318 - 2.95V To 6V Input, 3A Output, 2MHz, Synchronous Step Down Switcher With Integrated FETs (...
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TPS54318 www.ti.com ......................................................................................................................................................................................... SLVS975 – SEPTEMBER 2009 2.95V To 6V Input, 3A Output, 2MHz, Synchronous Step Down Switcher With Integrated FETs ( SWIFT™) Check for Samples :TPS54318 1 FEATURES • Two 30 mΩ (typical) MOSFETs for High Efficiency at 3 A loads 200kHz to 2MHz Switching Frequency 0.8 V ± 1% Voltage Reference Over temperature Synchronizes to External Clock Adjustable Slow Start/Sequencing UV and OV Power Good Output Low Operating and Shutdown Quiescent Current Safe Start-up into Pre-Biased Output Cycle by Cycle Current Limit, Thermal and Frequency Fold Back Protection –40°C to 150°C Operating Junction Temperature Range Thermally Enhanced 3mm × 3mm 16-pin QFN DESCRIPTION The TPS54318 device is a full featured 6 V, 3 A, synchronous step down current mode converter with two integrated MOSFETs. The TPS54318 enables small designs by integrating the MOSFETs, implementing current mode control to reduce external component count, reducing inductor size by enabling up to 2 MHz switching frequency, and minimizing the IC footprint with a small 3mm x 3mm thermally enhanced QFN package. The TPS54318 provides accurate regulation for a variety of loads with an accurate ±1% Voltage Reference (Vref) over temperature. Efficiency is maximized through the integrated 30mΩ MOSFETs and 350μA typical supply current. Using the enable pin, shutdown supply current is reduced to 2 μA by entering a shutdown mode. Undervoltage lockout is internally set at 2.6 V, but can be increased by programming the threshold with a resistor network on the enable pin. The output voltage startup ramp is controlled by the slow start pin. An open drain power good signal indicates the output is within 93% to 107% of its nominal voltage. Frequency fold back and thermal shutdown protects the device during an overcurrent condition. The TPS54318 is supported in the SwitcherProTM Software Tool at www.ti.com/switcherpro. CBOOT BOOT 2 • • • • • • • • • • APPLICATIONS • • • Low-Voltage, High-Density Power Systems Point of Load Regulation for High Performance DSPs, FPGAs, ASICs and Microprocessors Broadband, Networking and Optical Communications Infrastructure SIMPLIFIED SCHEMATIC VIN VIN CI R4 TPS54318 EN R5 PWRGD VSENSE SS RT /CLK COMP C ss RT R3 C1 PH CO R1 LO VOUT For more SWIFTTM documentation, see the TI website at www.ti.com/swift. 100 95 90 85 Efficiency - % 80 75 70 65 60 55 50 0 0.5 1 1.5 2 GND AGND POWERPAD R2 VI = 5 V, VO = 1.8 V, FS = 1000 kHz 2.5 3 IO - Output Current - A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SWIFT is a trademark of Texas Instruments. Copyright © 2009, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TPS54318 SLVS975 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TJ –40°C to 150°C (1) PACKAGE 3 × 3 mm QFN PART NUMBER (1) TPS54318RTET TPS54318RTER The RTE package is only available taped and reeled. To order, add the suffix “R” to the end of the part number for a reel of 3000, or add the suffix “T” to the end of the part number for a reel of 250 (e.g., TPS54318RTER). ABSOLUTE MAXIMUM RATINGS VALUE VIN EN BOOT Input voltage VSENSE COMP PWRGD SS RT/CLK BOOT-PH Output voltage PH PH 10 ns Transient Source current EN RT/CLK COMP Sink current PWRGD SS Electrostatic discharge (HBM) Electrostatic discharge (CDM) Operating Junction temperature, TJ Storage temperature, Tstg –0.3 to 7 –0.3 to 7 PH + 8 –0.3 to 3 –0.3 to 3 –0.3 to 7 –0.3 to 3 –0.3 to 6 8 –0.6 to 7 –2 to 7 100 100 100 10 100 2 500 –40 to 150 –65 to 150 (2) (3) UNIT V V μA μA μA mA μA kV V °C °C PACKAGE DISSIPATION RATINGS (1) PACKAGE RTE (1) (2) over operating free-air temperature range (unless otherwise noted) THERMAL IMPEDANCE JUNCTION TO AMBIENT 37°C/W θJT THERMAL CHARACTERISTIC JUNCTION TO TOP 1°C/W (3) Maximum power dissipation may be limited by overcurrent protection Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information. Test boards conditions: (a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch (b) 2 oz. copper traces located on the top of the PCB (c) 2 oz. copper ground planes on the 2 internal layers and bottom layer (d) 4 thermal vias (10mil) located under the device package 2 Submit Documentation Feedback Product Folder Link(s) :TPS54318 Copyright © 2009, Texas Instruments Incorporated TPS54318 www.ti.com ......................................................................................................................................................................................... SLVS975 – SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION SUPPLY VOLTAGE (VIN PIN) Operating input voltage Internal under voltage lockout threshold Shutdown supply current Quiescent Current - Iq ENABLE AND UVLO (EN PIN) Enable threshold Input current VOLTAGE REFERENCE (VSENSE PIN) Voltage Reference MOSFET High side switch resistance Low side switch resistance ERROR AMPLIFIER Input current Error amplifier transconductance (gm) Error amplifier transconductance (gm) during slow start Error amplifier source/sink COMP to Iswitch gm CURRENT LIMIT Current limit threshold THERMAL SHUTDOWN Thermal Shutdown Hysteresis TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching frequency range using RT mode Switching frequency Switching frequency range using CLK mode Minimum CLK pulse width RT/CLK voltage RT/CLK high threshold RT/CLK low threshold RT/CLK falling edge to PH rising edge delay PLL lock in time PH (PH PIN) Minimum On time Measured at 50% points on PH, IOUT = 3 A Measured at 50% points on PH, VIN = 5 V, IOUT = 0 A Minimum Off time Rise/Fall Time Prior to skipping off pulses, BOOT-PH = 2.95 V, IOUT = 3 A VIN = 5 V 60 110 60 1.5 ns V/ns ns Measure at 500 kHz with RT resistor in series Measure at 500 kHz 0.4 R(RT/CLK) = 400kΩ RT = 400 kΩ 200 400 300 75 0.5 1.6 0.6 90 14 2.2 500 2000 600 2000 kHz kHz kHz ns V V V ns μs 175 15 °C °C 3.7 5.5 A –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V, VSENSE = 0.4 V V(COMP) = 1 V, 100 mV overdrive 7 225 70 ±20 13 nA μmhos μmhos μA A/V BOOT-PH = 5 V BOOT-PH = 2.95 V VIN = 5 V VIN = 2.95 V 30 44 30 44 60 70 60 70 mΩ mΩ 2.95 V ≤ VIN ≤ 6 V, –40°C COUT 2 ´ DIOUT ¦ sw ´ DVOUT (22) 1 1 ´ > VOripple 8 ´ ¦ sw Iripple Where ΔIOUT is the change in output current, Fsw is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. (23) Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 24 indicates the ESR should be less than 39 mΩ. In this case, the ESR of the ceramic capacitor is much less than 39 mΩ. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, three 22 μF 10 V X5R ceramic capacitors with 3 mΩ of ESR are used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 25 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields 222 mA. VOripple RESR < Iripple Icorms = VOUT ´ (VINmax - VOUT ) 12 ´ VINmax ´ L1 ´ ¦ sw (25) (24) INPUT CAPACITOR The TPS54318 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54318. The input ripple current can be calculated using Equation 26. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 27. Using the design example values, IOUTmax = 3 A, CIN = 10 μF, Fsw = 1 MHz, yields an input voltage ripple of 51 mV and a rms input ripple current of 1.47 A. Icirms = IOUT ´ VOUT ´ VINmin (VINmin - VOUT ) (26) VINmin DVIN I max ´ 0.25 = OUT CIN ´ ¦ sw (27) Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS54318 21 TPS54318 SLVS975 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com SLOW START CAPACITOR The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54318 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The slow start capacitor value can be calculated using Equation 28. For the example circuit, the slow start time is not too critical since the output capacitor value is 44 μF which does not require much current to charge to 1.8 V. The example circuit has the slow start time set to an arbitrary value of 4 ms which requires a 10 nF capacitor. In TPS54318, Iss is 2 μA and Vref is 0.8 V. T (mS) ´ ISS (mA) CSS (nF) = SS Vref (V) (28) BOOTSTRAP CAPACITOR SELECTION A 0.1 μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating. UNDERVOLTAGE LOCK OUT SET POINT The Undervoltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54318. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 3.1 V (VSTART). After the regulator starts switching, it should continue to do so until the input voltage falls below 2.8 V (VSTOP). The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN pin. Equation 29 and Equation 30 can be used to calculate the resistance values necessary. From Equation 29 and Equation 30, a 48.7 kΩ between Vin and EN and a 32.4 kΩ between EN and ground are required to produce the 3.1 and 2.8 volt start and stop voltages. 0.944 × VSTART - VSTOP R1 = 2.59 ´ 10-6 (29) R2 = 1.18 × R1 VSTOP - 1.18 + R1 × 3.2 ´ 10 - 6 (30) OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION For the example design, 100 kΩ was selected for R6. Using Equation 31, R7 is calculated as 80 kΩ. The nearest standard 1% resistor is 80.5 kΩ. Vref R7 = R6 VOUT - Vref (31) Due to the internal design of the TPS54318, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by Equation 32 VOUT min = Ontimemin ´ FSmax ´ VINmax - IOUT min ´ (2 ´ RDS ) Where: VOUTmin = minimum achievable output voltage Ontimemin = minimum controllable on-time (60 ns typical. 110 nsec no load) Fsmax = maximum switching frequency including tolerance VINmax = maximum input voltage 22 Submit Documentation Feedback Product Folder Link(s) :TPS54318 Copyright © 2009, Texas Instruments Incorporated ( ( ( )))- (IOUTmin ´ (RL + RDS )) (32) TPS54318 www.ti.com ......................................................................................................................................................................................... SLVS975 – SEPTEMBER 2009 IOUTmin = minimum load current RDS = minimum high side MOSFET on resistance (30 - 44 mΩ) RL = series resistance of output inductor There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum output voltage is given by Equation 33 VOUT max = 1 - (Offtimemax ´ FSmax ) ´ VINmin - IOUT max ´ (2 ´ RDS ) - IOUT max ´ (RL + RDS ) Where: VOUTmax = maximum achievable output voltage Offtimeman = maximum off time (60 nsec typical) Fsmax = maximum switching frequency including tolerance VINmin = minimum input voltage IOUTmax = maximum load current RDS = maximum high side MOSFET on resistance (60 - 70 mΩ) RL = series resistance of output inductor ( )( ( )) (33) COMPENSATION There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54318. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design. To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 34 and Equation 12. For COUT, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer information to derate the capacitor value. Use Equation 36 and Equation 37 to estimate a starting point for the crossover frequency, fc. For the example design, fpmod is 4.02 kHz and fzmod is 804 kHz. Equation 36 is the geometric mean of the modulator pole and the esr zero and Equation 37 is the mean of modulator pole and the switching frequency. Equation 36 yields 5.6 kHz and Equation 37 gives 44.8 kHz. Use the lower value of Equation 36 or Equation 37 as the maximum crossover frequency. For this example, fc is 45 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if needed). IOUT max ¦p mod = 2p ´ VOUT ´ COUT (34) ¦ z mod = 1 2p ´ RESR ´ COUT (35) (36) ¦C = ¦C = ¦p mod ´ ¦ z mod ¦p mod ´ ¦ sw 2 (37) The compensation design takes the following steps: 1. Set up the anticipated cross-over frequency. Use Equation 38 to calculate the compensation network’s resistor value. In this example, the anticipated cross-over frequency (fc) is 45 kHz. The power stage gain (gmps) is 13 A/V and the error amplifier gain (gmea) is 225 μA/V. 2p × ¦ c ´ VOUT ´ COUT R3 = gm ´ Vref ´ VIgm (38) 2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation network’s capacitor can be calculated from Equation 39. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS54318 23 TPS54318 SLVS975 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com ROUT ´ COUT R3 (39) 3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to add it. C3 = From the procedures above, the compensation network includes a 9.53 kΩ resistor and a 3900 pF capacitor. APPLICATION CURVES EFFICIENCY vs LOAD CURRENT 100 VI = 3.3 V 95 90 85 VI = 5 V 95 90 85 VI = 3.3 V 100 EFFICIENCY vs LOAD CURRENT Efficiency - % 80 75 70 65 60 55 50 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 IO - Output Current - A 2.25 2.5 2.75 3 Efficiency - % 80 75 70 65 60 55 50 0.001 0.01 0.1 IO - Output Current - A 1 10 VI = 5 V Figure 34. TRANSIENT RESPONSE, 1.5 A STEP Figure 35. TRANSIENT RESPONSE, 3 A STEP VOUT = 50 mV/div (ac coupled) VOUT = 50 mV/div (ac coupled) IOUT = 1 A/div 0.75 to 2.25 A step IOUT = 1 A/div 0 to 3 A step Time = 2 ms/div Time = 2 ms/div Figure 36. Figure 37. 24 Submit Documentation Feedback Product Folder Link(s) :TPS54318 Copyright © 2009, Texas Instruments Incorporated TPS54318 www.ti.com ......................................................................................................................................................................................... SLVS975 – SEPTEMBER 2009 POWER UP VOUT, VIN VIN = 2 V/div POWER DOWN VOUT, VIN VIN = 2 V/div EN = 1 V/div EN = 1 V/div SS = 1 V/div SS = 1 V/div VOUT = 1 A/div VOUT = 1 A/div Time = 5 ms/div Time = 500 ms/div Figure 38. POWER UP VOUT, EN VIN = 2 V/div Figure 39. POWER DOWN VOUT, EN VIN = 2 V/div EN = 1 V/div EN = 1 V/div SS = 1 V/div SS = 1 V/div VOUT = 1 A/div VOUT = 1 A/div Time = 5 ms/div Time = 500 ms/div Figure 40. OUTPUT RIPPLE, 0 A Figure 41. OUTPUT RIPPLE, 3 A VIN = 50 mV/div (ac coupled) VOUT = 10 mV/div (ac coupled) PH = 2 V/div PH = 2 V/div Time = 500 ns/div Time = 500 ns/div Figure 42. Figure 43. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS54318 25 TPS54318 SLVS975 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com INPUT RIPPLE, 0 A VIN = 50 mV/div INPUT RIPPLE, 3 A VOUT = 10 mV/div (ac coupled) PH = 2 V/div PH = 2 V/div Time = 500 ns/div Time = 500 ns/div Figure 44. Figure 45. LOAD REGULATION vs LOAD CURRENT 180 150 0.25 0.2 0.15 CLOSED LOOP RESPONSE, VIN (3.3 V), 3 A 60 50 40 30 20 Gain Phase 120 Output Voltage Change - % 90 60 30 Gain Phase - Deg 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 0.5 1 1.5 2 IO - Output Current - A 2.5 3 VI = 3.3 V 10 0 -10 -20 -30 -40 -50 -60 10000 100000 1000 100 0.25 0.2 0.15 0 -30 -60 -90 -120 -150 -180 1000000 Frequency - Hz Figure 46. LOAD REGULATION vs LOAD CURRENT 1.8 Figure 47. REGULATION vs INPUT VOLTAGE 1.798 IO = 1.5 A VI = 5 V Output Voltage Change - % VO - Output Voltage - V 2.5 3 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 0 0.5 1 1.5 2 IO - Output Current - A 1.796 1.794 1.792 1.79 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 Figure 48. Figure 49. 26 Submit Documentation Feedback Product Folder Link(s) :TPS54318 Copyright © 2009, Texas Instruments Incorporated TPS54318 www.ti.com ......................................................................................................................................................................................... SLVS975 – SEPTEMBER 2009 POWER DISSIPATION ESTIMATE The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching loss (Psw), gate drive loss (Pgd) and supply current loss (Pq). Pcon = IO 2 × RDS(on) Pd = ƒsw × IOUT × 0.7 × 60 × 10-9 Psw = 2 × VIN 2 × ƒsw × Io × 0.25 × 10-9 Pgd = 2 × VIN × 3 × 10-9 × ƒsw Pq = 350 × 10-6 × VIN Where: IOUT is the output current (A). RDS(on) is the on-resistance of the high-side MOSFET (Ω). VOUT is the output voltage (V). VIN is the input voltage (V). ƒsw is the switching frequency (Hz). So Ptot = Pcon + Pd + Psw + Pgd + Pq For given TA, TJ = TA + Rth × Ptot For given TJmax = 150°C TAmax = TJ max – Rth × Ptot Where: Ptot is the total device power dissipation (W). TA is the ambient temperature (°C). TJ is the junction temperature (°C). Rth is the thermal resistance of the package (°C/W). TJmax is maximum junction temperature (°C). TAmax is maximum ambient temperature (°C). There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace resistance that impact the overall efficiency of the regulator. As an example, the maximum ambient temperature versus power dissipation for the EVM is shown in Figure 51. 150 140 130 TA = room temperature, no air flow TJ - Junction Temperature - °C 120 110 100 90 80 70 60 50 40 30 20 0 0.5 1 1.5 2 2.5 PD - Power Dissipated - W 3 3.5 Figure 50. Junction Temperature vs IC Power Dissipation Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS54318 27 TPS54318 SLVS975 – SEPTEMBER 2009 ......................................................................................................................................................................................... www.ti.com 150 TAmax - Maximum Ambient Temperature - °C 140 130 120 110 100 90 80 70 60 50 40 30 20 0 0.5 1 1.5 2 2.5 PD - Power Dissipated - W 3 3.5 TJmax = 150°C, no air flow Figure 51. Maximum Ambient Temperature vs IC power Dissipation LAYOUT Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 52 for a PCB layout example. The GND pins and AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the top side ground area to the internal planes near the input and output capacitors. For operation at full rated load, the top side ground area along with any additional internal ground planes must provide adequate heat dissipating area. Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output inductor. Since the PH connection is the switching node, the output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot capacitor must also be located close to the device. The sensitive analog ground connections for the feedback voltage divider, compensation components, slow start capacitor and frequency set resistor should be connected to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It is possible to obtain acceptable performance with alternate PCB layouts; however, this layout has been shown to produce good results and is meant as a guideline. 28 Submit Documentation Feedback Product Folder Link(s) :TPS54318 Copyright © 2009, Texas Instruments Incorporated TPS54318 www.ti.com ......................................................................................................................................................................................... SLVS975 – SEPTEMBER 2009 UVLO SET RESISTRORS VIA to Ground Plane VIN PWRGD BOOT VIN EN VIN INPUT BYPASS CAPACITOR BOOT CAPACITOR PH VIN OUTPUT INDUCTOR VOUT OUTPUT FILTER CAPACITOR VIN GND EXPOSED POWERPAD AREA PH PH PH SLOW START CAPACITOR GND SS VSENSE FEEDBACK RESISTORS RT/CLK COMP AGND ANALOG GROUND TRACE FREQUENCY SET RESISTOR TOPSIDE GROUND AREA COMPENSATION NETWORK VIA to Ground Plane Figure 52. PCB Layout Example Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TPS54318 29 PACKAGE OPTION ADDENDUM www.ti.com 8-Dec-2009 PACKAGING INFORMATION Orderable Device TPS54318RTER TPS54318RTET (1) Status (1) ACTIVE ACTIVE Package Type WQFN WQFN Package Drawing RTE RTE Pins Package Eco Plan (2) Qty 16 16 3000 Green (RoHS & no Sb/Br) 250 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing WQFN WQFN RTE RTE 16 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 180.0 12.4 12.4 3.3 3.3 B0 (mm) 3.3 3.3 K0 (mm) 1.1 1.1 P1 (mm) 8.0 8.0 W Pin1 (mm) Quadrant 12.0 12.0 Q2 Q2 TPS54318RTER TPS54318RTET 3000 250 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2009 *All dimensions are nominal Device TPS54318RTER TPS54318RTET Package Type WQFN WQFN Package Drawing RTE RTE Pins 16 16 SPQ 3000 250 Length (mm) 346.0 190.5 Width (mm) 346.0 212.7 Height (mm) 29.0 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DLP® Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com Applications Audio Automotive Communications and Telecom Computers and Peripherals Consumer Electronics Energy Industrial Medical Security Space, Avionics & Defense Video and Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/communications www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video www.ti.com/wireless-apps RF/IF and ZigBee® Solutions www.ti.com/lprf Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2010, Texas Instruments Incorporated

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