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TPS54318
SLVS975C – SEPTEMBER 2009 – REVISED APRIL 2018
TPS54318 2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down
SWIFT™ Converter
1 Features
3 Description
•
TheTPS54318 device is a full-featured, 6-V, 3-A,
synchronous, step-down current-mode converter with
two integrated MOSFETs.
1
•
•
•
•
•
•
•
•
•
•
•
Two, 30-mΩ (typical) MOSFETs for HighEfficiency at 3-A loads
Switching Frequency: 200 kHz to 2 MHz
Voltage Reference Over Temperature: 0.8 V ± 1%
Synchronizes to External Clock
Adjustable Soft Start/Sequencing
UV and OV Power-Good Output
Low Operating and Shutdown Quiescent Current
Safe Start-Up into Prebiased Output
Cycle-by-Cycle Current Limit, Thermal and
Frequency Foldback Protection
Operating Junction Temperature Range: –40°C to
150°C
Thermally Enhanced 3 mm × 3 mm 16-pin WQFN
Package
Create a Custom Design Using the TPS54318
With the WEBENCH® Power Designer
2 Applications
•
•
•
Low-Voltage, High-Density Power Systems
Point-of-Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
The TPS54318 device enables small designs by
integrating the MOSFETs, implementing current
mode control to reduce external component count,
reducing inductor size by enabling up to 2-MHz
switching frequency, and minimizing the device
footprint with a small, 3 mm x 3 mm, thermally
enhanced, QFN package.
The TPS54318 device provides accurate regulation
for a variety of loads with an accurate ±1% voltage
reference (VREF) over temperature.
Efficiency is maximized through the integrated 30-mΩ
MOSFETs and a 350-μA typical supply current. Using
the EN pin, shutdown supply current is reduced to 2
μA by entering a shutdown mode.
Undervoltage lockout is internally set at 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The output
voltage startup ramp is controlled by the soft-start pin.
An open-drain power-good signal indicates the output
is within 93% to 107% of its nominal voltage.
Frequency foldback and thermal shutdown protects
the device during an overcurrent condition.
For more SWIFT™ documentation, see the TI
website at www.ti.com/swift.
Device Information(1)
PART NUMBER
PACKAGE
TPS54318
WQFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VIN
Efficiency vs Output Current
TPS54318
100
BOOT
EN
PH
PWRGD
SS
RT/CLK
COMP
VSENSE
PowerPad
95
90
VOUT
85
Efficiency (%)
VIN
80
75
70
65
GND
AGND
60
VIN = 5 V
55
VOUT = 1.8 V
fSW = 1 MHz
50
0
0.5
1
1.5
2
Output Current (A)
2.5
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54318
SLVS975C – SEPTEMBER 2009 – REVISED APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 17
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 30
10 Layout................................................................... 30
10.1 Layout Guidelines ................................................. 30
10.2 Layout Example .................................................... 31
11 Device and Documentation Support ................. 32
11.1
11.2
11.3
11.4
Device Support ....................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2014) to Revision C
•
update title ............................................................................................................................................................................. 1
Changes from Revision A (September 2013) to Revision B
•
Page
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
Changes from Original (September 2009) to Revision A
Page
•
Added "Instantaneous peak current" specification to the Current Limit section in the Electrical Characteristics table ........ 5
•
Added Figure 22 to Typical Characteristics section ............................................................................................................... 9
2
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SLVS975C – SEPTEMBER 2009 – REVISED APRIL 2018
5 Pin Configuration and Functions
VIN
EN
PWRGD
BOOT
RTE Package
16 Pin WQFN
(TOP VIEW)
16
15
14
13
VIN 1
12 PH
VIN 2
11 PH
Thermal
Pad
GND 3
10 PH
GND 4
5
6
7
8
AGND
VSENSE
COMP
RT/CLK
9
SS
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
AGND
5
G
Analog ground should be electrically connected to GND close to the device.
BOOT
13
I
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
COMP
7
O
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
EN
15
I
Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to
set the on/off threshold (adjust UVLO) with two additional resistors.
G
Power ground. This pin should be electrically connected directly to the power pad under the device.
O
The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
rectifier MOSFET.
GND
3
4
10
PH
11
12
PWRGD
14
O
An open drain output, asserts low if output voltage is low due to thermal shutdown, overcurrent,
over/under-voltage or EN shut down.
RT/CLK
8
I/O
Resistor Timing or External Clock input pin.
SS
9
I/O
Slow-start. An external capacitor connected to this pin sets the output voltage rise time. Soft
1
VIN
2
I
Input supply voltage, 2.95 V to 6 V.
I
Inverting node of the transconductance (gm) error amplifier.
G
GND pin should be connected to the exposed power pad for proper operation. This power pad should
be connected to any internal PCB ground plane using multiple vias for good thermal performance.
16
VSENSE
Thermal Pad
(1)
6
I = Input, O = Output, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
(1)
MIN
MAX
EN, PWRGD, VIN
–0.3
7
RT/CLK
–0.3
6
COMP, SS, VSENSE
–0.3
3
BOOT
8
PH
PH (10 ns transient)
Source current
Sink current
V
VPH+ 8 V
BOOT-PH
Output voltage
UNIT
–0.6
7
–2
7
V
EN, RT/CLK
100
COMP, SS
100
µA
µA
PWRGD
10
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
VALUE
UNIT
±2000
V
±500
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VVIN
Input voltage
TJ
Operating junction temperature
MAX
UNIT
3
6
V
–40
150
°C
6.4 Thermal Information (1)
TPS54318
THERMAL METRIC (2)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
59.1
RθJB
Junction-to-board thermal resistance
23.1
ψJT
Junction-to-top characterization parameter
1.4
ψJB
Junction-to-board characterization parameter
23.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.9
(1)
(2)
(3)
4
50
(3)
37
°C/W
Unless otherwise specified, metrics listed in this table refer to JEDEC high-K board measurements
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Test Board Conditions:
(a) 2 inches × 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes located on the two internal layers and bottom layer
(d) 4 thermal vias (10 mil) located under the device package
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6.5 Electrical Characteristics
–40°C ≤ TJ ≤ 150°C, 2.95 ≤ VVIN ≤ 6 V (unless otherwise noted) over operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN)
VVIN
Operating input voltage
VUVLO
Internal under voltage lockout
threshold
No voltage hysteresis, rising and falling
IQ(vin)
Shutdown supply current
VEN = 0 V, TA = 25°C, 2.95 V ≤ VVIN ≤ 6 V
Quiescent current
VVSENSE = 0.9 V, VVIN = 5 V, 25°C,
RT = 400 kΩ
Iq
2.95
6
V
2.6
2.8
V
2
5
μA
350
500
μA
1.25
1.37
ENABLE AND UVLO (EN)
VTH(en)
Enable threshold
IEN
Input current
Rising
1.16
Falling
1.18
Enable rising threshold + 50 mV
–3.2
Enable falling threshold – 50 mV
–0.65
V
μA
VOLTAGE REFERENCE (VSENSE)
VREF
Voltage reference
2.95 V ≤ VVIN ≤ 6 V, –40°C
8 × fSW × VOUT (ripple )
COUT (transient ) >
(25)
(26)
where
•
•
•
•
•
ΔIOUT is the load step size
ΔVOUT is the acceptable output deviation
fSW is the switching frequency
IRipple is the inductor ripple current
VOUT(Ripple) is the acceptable DC output voltage ripple
Equation 27 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 27 indicates the ESR should be less than 39 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 39 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, three 22-μF, 10-V, X5R ceramic capacitors with 3 mΩ of ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (root mean square) value of the maximum ripple current. Equation 28 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 28 yields
222 mA.
R ESR <
VOUT (ripple )
IRipple
ICO(rms ) =
22
(
VOUT ´ VIN(max ) - VOUT
(27)
)
12 ´ VIN(max ) ´ L1´ fSW
(28)
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8.2.2.4 Step Four: Select the Input Capacitor
The TPS54318 device requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least
4.7 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes
any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.
The capacitor must also have a ripple current rating greater than the maximum input current ripple of the device.
The input ripple current can be calculated using Equation 29.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10 V voltage rating is required to support the
maximum input voltage. For this example, one 10 μF and one 0.1 μF 10 V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 30.
ICIN(rms ) = IOUT ´
DVIN =
(
VIN(min ) - VOUT
VOUT
´
VIN(min )
VIN(min )
)
(29)
IOUT(max ) ´ 0.25
CIN ´ fSW
(30)
Using the design example values, IOUT(max) = 3 A, CIN = 10 μF, fSW = 1 MHz, yields an input voltage ripple of 51
mV and a rms input ripple current of 1.47 A.
8.2.2.5 Step Five: Minimum Load DC COMP Voltage
The TPS54318 implements a minimum COMP voltage clamp for improved load-transient response. The COMP
voltage tracks the peak inductor current, increasing as the peak inductor current increases, and decreases as the
peak inductor current decreases. During a severe load-dump event, for instance, the COMP voltage decreases
suddenly, falls below the minimum clamp value, then settles to a lower DC value as the control loop
compensates for the transient event. During the time when COMP reaches the minimum clamp voltage, turnon of
the high-side power switch is inhibited, keeping the low-side power switch on to discharge the output voltage
overshoot more quickly.
Proper application circuit design must ensure that the minimum load steady-state COMP voltage is above the +3
sigma minimum clamp to avoid unwanted inhibition of the high side power switch. For a given design, the steadystate DC level of COMP must be measured at the minimum designed load and at the maximum designed input
voltage, then compared to the minimum COMP clamp voltage shown in Figure 22. These conditions give the
minimum COMP voltage for a given design. Generally, the COMP voltage and minimum clamp voltage move by
about the same amount with temperature. Increasing the minimum load COMP voltage is accomplished by
decreasing the output inductor value or the switching frequency used in a given design.
8.2.2.6 Step Six: Choose the Soft-Start Capacitor
The soft-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
device reach the current limit or excessive current draw from the input power supply may cause the input voltage
rail to sag. Limiting the output voltage slew rate solves both of these problems.
The soft-start capacitor value can be calculated using Equation 31. For the example circuit, the soft-start time is
not too critical since the output capacitor value is 66 µF which does not require much current to charge to 1.8 V.
The example circuit has the soft-start time set to an arbitrary value of 4 ms which requires a 10 nF capacitor. In
the device, ISS is 2 μA and VREF is 0.8 V. For this application, maintain the soft-start time in the range between
1 ms and 10 ms.
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I ´t
CSS = SS SS
VREF
where
•
•
•
•
CSS is in nF
ISS is in µA
tSS is in ms
VREF is in V
(31)
8.2.2.7 Step Seven: Select the Bootstrap Capacitor
A 0.1-μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
8.2.2.8 Step Eight: Undervoltage Lockout Threshold
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54318. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 3.1 V (VSTART). Switching continues until the input voltage falls
below 2.8 V (VSTOP).
The programmable UVLO and enable voltages are set using a resistor divider between the VIN pin and GND to
the EN pin. Equation 32 and Equation 33 can be used to calculate the resistance values necessary. From
Equation 32 and Equation 33, a 48.7 kΩ between the VIN pin and the EN pin and a 32.4-kΩ resistor between the
EN pin and GND are required to produce the 3.1-V start voltage and the 2.8-V stop voltage.
0.944 × VSTART - VSTOP
R1 =
2.59 ´ 10-6
(32)
R2 =
1.18 × R1
VSTOP - 1.18 + R1 × 3.2 ´ 10 - 6
(33)
8.2.2.9 Step Nine: Select Output Voltage and Feedback Resistors
For the example design, 100 kΩ was selected for R6. Using Equation 34, R7 is calculated as 80 kΩ. The nearest
standard 1% resistor is 80.6 kΩ.
Vref
R7 =
R6
VOUT - Vref
(34)
8.2.2.9.1 Output Voltage Limitations
Due to the internal design of the TPS54318, there are limitations to the minimum and maximum achievable
output voltages. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V,
the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case
is given by Equation 35. There is also a maximum achievable output voltage which is limited by the minimum off
time. The maximum output voltage is given by Equation 36. These equations represent the results when the
power MOSFETs are matched. Refer to SLYT293 for more information.
VOUT :min ; = t ON (min ) × fSW (max ) × VIN:max ; F IOUT (min )kRLS (min ) + RDCR o
where
•
•
•
•
•
•
•
24
VOUT(min) is the minimum achievable output voltage
tON(min) is the minimum controllable on-time (110 nsec typical)
fSW(max) is the maximum switching frequency including tolerance
VIN(max) is the maximum input voltage
IOUT(min) is the minimum load current
RLS(min) is the minimum low-side MOSFET on-resistance. (30 mΩ typical)
RDCR is the series resistance of output inductor
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VOUT :max ; = k1 F tOFF :max ;fSW (max )oVIN:min ; F IOUT :max ;kRLS(max ) + RDCR o
where
•
•
•
•
•
•
•
VOUT(max) is the maximum achievable output voltage
tOFF(max) is the maximum, minimum controllable off time (60 ns typical)
fSW(max) is the maximum switching frequency including tolerance
VIN(min) is the minimum input voltage
IOUT(max) is the maximum load current
RHS(max) is the maximum high-side MOSFET on-resistance. (70 mΩ max)
RDCR is the series resistance of output inductor
(36)
8.2.2.10 Step 10: Select Loop Compensation Components
There are several industry techniques used to compensate DC/DC regulators. The method presented here is
easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between
60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to
the TPS54318. Because the slope compensation is ignored, the actual crossover frequency is usually lower than
the crossover frequency used in the calculations. Use SwitcherPro software for a more accurate design.
To get started, the modulator pole, fP(mod), and the esr zero, fZ1 must be calculated using Equation 37 and
Equation 38. For COUT, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V
capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer
information to derate the capacitor value. Use Equation 39 and Equation 40 to estimate a starting point for the
crossover frequency, fC. For the example design, fP(mod) is 4.02 kHz and fZ1 is 804 kHz. Equation 39 is the
geometric mean of the modulator pole and the esr zero and Equation 40 is the mean of modulator pole and the
switching frequency. Equation 39 yields 56 kHz and Equation 40 gives 44.8 kHz. Use the lower value of
Equation 39 or Equation 40 as the maximum crossover frequency. For this example, fc is 45 kHz. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole (if needed).
IOUT(max )
fP(mod) =
2p ´ VOUT ´ COUT
(37)
fZ1 =
COUT
1
× RESR × tN
(38)
fC = §fP:mod ; + fZ1
(39)
f
fC = fP(mod) ´ SW
2
(40)
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. Use Equation 41 to calculate the compensation network’s
resistor value. In this example, the anticipated cross-over frequency fC is 45 kHz. The power stage gain
(gM(ps)) is 13 A/V and the error amplifier gain (gM(ea)) is 225uA/V.
2p ´ fC ´ VOUT ´ COUT
R3 =
gM(ea ) ´ VREF ´ gM(ps )
(41)
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation
network’s capacitor can be calculated from Equation 42.
´ COUT
R
C3 = OUT
R3
(42)
3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to
add it.
From the procedures above, start with a 14.3 kΩ resistor and a 2760 pF capacitor. After prototyping and bode
plot measurement, the optimized compensation network selected for this design includes a 14.3 kΩ resistor and
a 2700 pF capacitor.
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8.2.2.11 Power Dissipation Estimate
Use Equation 43 through Equation 52 to help estimate the device power dissipation under continuous conduction
mode (CCM) operation. The power dissipation of the device (PTOT) includes conduction loss (PCOND), dead time
loss (PD), switching loss (PSW), gate drive loss (PGD) and supply current loss (PQ).
PCOND= (IOUT)2 × RDS(on)
PD = ƒSW × IOUT × 0.7 × 60 × (10)–9
PD = ƒSW × IOUT × 0.7 × 60 × (10)–9
PSW = 2 × (VIN)2 × ƒSW × IOUT × 0.25 × (10)–9
PSW = 2 × (VIN)2 × ƒSW × IOUT × 0.25 × (10)–9
PGD = 2 × VIN × 3 × (10)–9 × ƒSW
PQ = 350 × (10)–6 × VIN
(43)
(44)
(45)
(46)
(47)
(48)
where
• IOUT is the output current (A)
• RDS(on) is the on-resistance of the high-side MOSFET (Ω)
• VOUT is the output voltage (V)
• VIN is the input voltage (V)
• ƒSW is the switching frequency (Hz)
PTOT = PCOND + PD + PSW + PGD + PQ
(49)
(50)
For a given ambient temperature,
TJ = TA + RTH × PTOT
(51)
For maximum junction temperature (TJ(max) = 150°C)
TA(max) = TJ(max) – RTH × PTOT
where
•
•
•
•
•
•
PTOT is the total device power dissipation (W)
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RTH is the thermal resistance of the package (°C/W)
TJ(max) is maximum junction temperature (°C)
TA(max) is maximum ambient temperature (°C)
(52)
3.5
3.5
3
3
Power Dissipation (W)
Power Dissipation (W)
Additional power can be lost in the regulator circuit due to the inductor ac and dc losses and trace resistance that
impact the overall regulator efficiency. Figure 36 and Figure 37 show power dissipation for the EVM.
2.5
2
1.5
1
0.5
2.5
2
1.5
1
0.5
0
0
20 30 40 50 60 70 80 90 100 110 120 130 140 150
20 30 40 50 60 70 80 90 100 110 120 130 140 150
Junction Temperature (°C)
TA = 25°C
Maximum Ambient Temperature (°C)
No air flow
Figure 36. Power Dissipation vs Junction Temperature
26
TJ(max) = 150°C
No air flow
Figure 37. Power Dissipation vs Ambient Temperature
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8.2.3 Application Curves
100
100
VI = 3.3 V
95
95
90
85
Efficiency - %
85
Efficiency - %
VI = 3.3 V
90
VI = 5 V
80
75
70
80
70
65
65
60
60
55
55
50
0
0.25 0.5
0.75
1
1.25 1.5 1.75 2
IO - Output Current - A
2.25 2.5
2.75
3
VI = 5 V
75
50
0.001
0.01
1
10
Figure 39. Efficiency vs Load Current
Figure 38. Efficiency vs Load Current
VOUT = 50 mV/div (ac coupled)
0.1
IO - Output Current - A
VOUT = 50 mV/div (ac coupled)
IOUT = 1 A/div
0.75 to 2.25 A step
IOUT = 1 A/div
0 to 3 A step
Time = 2 ms/div
Time = 2 ms/div
1.5-A Load Step
3-A Load Step
Figure 40. Transient Response
Figure 41. Transient Response
VIN = 2 V/div
VIN = 2 V/div
EN = 1 V/div
EN = 1 V/div
SS = 1 V/div
SS = 1 V/div
VOUT = 1 V/div
VOUT = 1 V/div
Time = 500 ms/div
Time = 5 ms/div
Figure 42. Power-Up, VOUT, VIN
Figure 43. Power-Down, VOUT, VIN
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VIN = 2 V/div
VIN = 2 V/div
EN = 1 V/div
EN = 1 V/div
SS = 1 V/div
SS = 1 V/div
VOUT = 1 A/div
VOUT = 1 A/div
Time = 500 ms/div
Time = 5 ms/div
Figure 44. Power-Up, VOUT, EN
VIN = 50 mV/div (ac coupled)
Figure 45. Power-Down, VOUT, EN
VOUT = 10 mV/div (ac coupled)
PH = 2 V/div
PH = 2 V/div
Time = 500 ns/div
Time = 500 ns/div
IOUT = 0 A
IOUT = 3 A
Figure 46. Output Ripple
Figure 47. Output Ripple
VIN = 50 mV/div
VOUT = 10 mV/div (ac coupled)
PH = 2 V/div
PH = 2 V/div
Time = 500 ns/div
Time = 500 ns/div
IOUT = 3 A
IOUT = 0A
Figure 49. Input Ripple
Figure 48. Input Ripple
28
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60
180
50
150
0.2
40
120
Phase
90
20
60
10
30
0
Gain
0
-10
-30
-20
-60
-30
-90
-40
-120
-50
-150
-60
-180
Output Voltage Change - %
0.15
30
Phase - Deg
Gain
0.25
0.1
VI = 3.3 V
0.05
0
-0.05
-0.1
-0.15
-0.2
1000000
VIN = 3.3. V
100000
10000
1000
100
Frequency - Hz
-0.25
0
0.5
1
1.5
2
IO - Output Current - A
2.5
3
IOUT = 3 A
Figure 51. Load Regulation vs Load Current
Figure 50. Closed-Loop Response
1.8
0.25
0.2
1.798
IO = 1.5 A
0.1
VO - Output Voltage - V
Output Voltage Change - %
0.15
VI = 5 V
0.05
0
-0.05
-0.1
-0.15
1.796
1.794
1.792
-0.2
1.79
-0.25
0
0.5
1
1.5
2
IO - Output Current - A
2.5
3
3
Figure 52. Load Regulation vs Load Current
3.5
4
4.5
5
VI - Input Voltage - V
5.5
Figure 53. Regulation vs Input Voltage
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9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply between 2.95 V and 6 V. This supply must
be well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise
performance, as is PCB layout and grounding scheme. See the recommendations in the Layout Guidelines
section.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance.
• Minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 54 for a
PCB layout example.
• The GND pins and AGND pin should be tied directly to the power pad under the TPS54318 device. The
power pad should be connected to any internal PCB ground planes using multiple vias directly under the
device. Additional vias can be used to connect the top-side ground area to the internal planes near the input
and output capacitors. For operation at full rated load, the top-side ground area along with any additional
internal ground planes must provide adequate heat dissipating area.
• Place the input bypass capacitor as close to the device as possible.
• Route the PH pin to the output inductor. Because the PH connection is the switching node, place the output
inductor close to the PH pins. Minimize the area of the PCB conductor to prevent excessive capacitive
coupling.
• The boot capacitor must also be located close to the device.
• The sensitive analog ground connections for the feedback voltage divider, compensation components, softstart capacitor and frequency set resistor should be connected to a separate analog ground trace as shown in
Figure 54.
• The RT/CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to
the device and routed with minimal trace lengths.
• The additional external components can be placed approximately as shown. It is possible to obtain
acceptable performance with alternate PCB layouts, however, this layout has been shown to produce good
results and can be used as a guide.
30
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10.2 Layout Example
VIA to
Ground
Plane
UVLO SET
RESISTRORS
VIN
INPUT
BYPASS
CAPACITOR
BOOT
PWRGD
EN
VIN
VIN
BOOT
CAPACITOR
VIN
OUTPUT
INDUCTOR
PH
VIN
PH
EXPOSED
POWERPAD
AREA
GND
PH
GND
VOUT
OUTPUT
FILTER
CAPACITOR
PH
SLOW START
CAPACITOR
RT/CLK
COMP
VSENSE
AGND
SS
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
COMPENSATION
NETWORK
TOPSIDE
GROUND
AREA
VIA to Ground Plane
Figure 54. PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS54318 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.1.2 Development Support
For more SWIFTTM documentation, see the TI website at www.ti.com/swift.
11.2 Trademarks
SWIFT is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54318RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
54318
TPS54318RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
54318
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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