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TPS43060, TPS43061
SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
TPS4306x Low Quiescent Current Synchronous Boost
DC-DC Controller With Wide VIN Range
1 Features
2 Applications
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58-V Maximum Output Voltage
4.5 to 38 V (40 V Absolute Max) VIN Range
TPS43060: 7.5-V Gate Drive Optimized for
Standard Threshold MOSFETs
TPS43061: 5.5-V Gate Drive Optimized for Low
Qg NexFET™ Power MOSFETs
Current-Mode Control With Internal Slope
Compensation
Adjustable Frequency from 50 kHz to 1 MHz
Synchronization Capability to External Clock
Adjustable Soft-Start Time
Inductor DCR or Resistor Current Sensing
Output Voltage Power-Good Indicator
±0.8% Feedback Reference Voltage
5-µA Shutdown Supply Current
600-µA Operating Quiescent Current
Integrated Bootstrap Diode (TPS43061)
Cycle-by-Cycle Current Limit and Thermal
Shutdown
Adjustable Undervoltage Lockout (UVLO) and
Output Overvoltage Protection
Small 16-Pin WQFN (3 mm × 3 mm) Package
With PowerPAD™
–40°C to 150°C Operating TJ Range
Thunderbolt Port for PCs
Automotive Power Systems
Synchronous Flyback
GaN RF Power Amplifiers
Tablet Computer Accessories
Battery-Powered Systems
5-V, 12-V, and 24-V DC Bus Power Systems
3 Description
The TPS43060 and TPS43061 are low IQ currentmode synchronous boost controllers with wide-input
voltage range from 4.5 to 38 V (40 V absolute max)
and boosted output range up to 58 V. Synchronous
rectification enables high-efficiency for high-current
applications, and lossless inductor DCR sensing
further improves efficiency. The resulting low-power
losses combined with a 3-mm × 3-mm WQFN-16
package with PowerPAD™ supports high powerdensity and high-reliability boost converter solutions
over extended (–40°C to 150°C) temperature range.
The TPS43060 includes a 7.5-V gate drive supply,
which is suitable to drive a broad range of MOSFETs.
The TPS43061 has a 5.5-V gate drive supply and
driver strength optimized for low Qg NexFET power
MOSFETs. Also, TPS43061 provides an integrated
bootstrap diode for the high-side gate driver to reduce
the external parts count.
Device Information(1)
PART NUMBER
TPS43060
TPS43061
PACKAGE
RTE (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
VIN
L
RSENSE
QH
TPS43060/61
CI
ISNS-
CBOOT
VOUT
CO
BOOT
ISNS+
VCC
DBOOT
(Note1)
QL
VIN
CVCC
EN
PGND
PGOOD
COMP
RC
RT/CLK
RT
CSS
CC
RSL
LDRV
SW
SS
HDRV
FB
AGND
RSH
Note 1: DBOOT is required for TPS43060, but optional for TPS43061.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS43060, TPS43061
SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
8
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Characteristics ............................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 18
9
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Applications ................................................ 21
10 Power Supply Recommendations ..................... 33
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 34
11.3 Thermal Considerations ........................................ 34
12 Device and Documentation Support ................. 35
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
13 Mechanical, Packaging, and Orderable
Information ........................................................... 35
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2013) to Revision D
•
Page
Added Handling Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
Changes from Revision B (August 2013) to Revision C
Page
•
Changed Equation 3............................................................................................................................................................. 14
•
Deleted sections Layout Considerations and Thermal Considerations................................................................................ 18
•
Changed Equation 13 from Dmin to (1-Dmax), 60% to (1-60%) and 2.4 MHz to 1.6 MHz ................................................. 22
•
Changed 2 MHz to 1.6 MHz in para below Equation 13 ...................................................................................................... 22
•
Changed in Equation 28 – DS(on)LS to DS(on)HS ............................................................................................................. 25
•
Changed in Equation 29 – from (60 ns + 65 ns) to (65 ns _65 ns)...................................................................................... 25
•
Changed in paragraph above Equation 37 - 1.93 kHz to 0.97 kHz...................................................................................... 27
•
Changed in Equation 38 – from 1.93 kHz to 0.97 kHz......................................................................................................... 27
•
Changed in paragraph above Equation 43 – 7.44 kΩ to 7.45 kΩ ........................................................................................ 27
•
Changed in Equation 43 – 21 µF to 22 µF, 20 mΩ to 10 mΩ, 19.3 kHz to 14.5 kHz, = 7.44 to = 7.45, and deleted
3/40 factor from denominator ............................................................................................................................................... 27
Changes from Revision A (December 2012) to Revision B
Page
•
Aligned package description throughout datasheet................................................................................................................ 1
•
Removed ordering information table. ..................................................................................................................................... 3
Changes from Original (December 2012) to Revision A
•
2
Page
Changed the devices From: Preview To: Production ............................................................................................................. 1
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Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS43060 TPS43061
TPS43060, TPS43061
www.ti.com
SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
6 Pin Configuration and Functions
COMP
3
FB
4
EN
PGOOD
HDRV
13
PowerPAD
(17)
12
SW
11
BOOT
10
VCC
9
5
6
7
8
LDRV
2
14
VIN
SS
15
ISNS+
1
16
ISNS-
RT/CLK
AGND
WQFN-16 PACKAGE
(TOP VIEW)
PGND
Pin Functions
PIN
NAME
DESCRIPTION
NO.
RT/CLK
1
Resistor timing and external clock. An external resistor from this pin to the AGND pin programs the switching
frequency between 50 kHz and 1 MHz. Driving the pin with an external clock between 300 kHz to 1 MHz
synchronizes the switching frequency to the external clock.
SS
2
Soft-start programming pin. A capacitor between the SS pin and AGND pin sets soft-start time.
COMP
3
Output of the internal transconductance error amplifier. The feedback loop compensation network is connected from
this pin to AGND.
FB
4
Error amplifier input and feedback pin for voltage regulation. Connect this pin to the center tap of a resistor divider to
set the output voltage.
ISNS–
5
Inductor current sense comparator inverting input pin. This pin is normally connected to the inductor side of the
current sense resistor.
ISNS+
6
Inductor current sense comparator non-inverting input pin. This pin is normally connected to the VIN side of the
current sense resistor.
VIN
7
The input supply pin to the IC. Connect VIN to a supply voltage between 4.5 and 38 V. It is acceptable for the
voltage on the VIN pin to be different from the boost power stage input, ISNS+, and ISNS– pins.
LDRV
8
Low-side gate driver output. Connect this pin to the gate of the low-side N-channel MOSFET. When VIN bias is
removed, an internal 200-kΩ resistor pulls LDRV to PGND.
PGND
9
Power ground of the IC. Connect this pin to the source of the low-side MOSFET. PGND should be connected to
AGND via a single point on the PCB.
VCC
10
Output of an internal LDO and power supply for internal control circuits and gate drivers. VCC is typically 7.5 V for
the TPS43060 and 5.5 V for the TPS43061. Connect a low-ESR ceramic capacitor from this pin to PGND. TI
recommends a capacitance range from 0.47 to 10 µF.
BOOT
11
Bootstrap capacitor node for high-side MOSFET gate driver. Connect the bootstrap capacitor from this pin to the SW
pin. For the TPS43060, also connect a bootstrap diode from VCC to BOOT.
SW
12
Switching node of the boost converter. Connect this pin to the junction of the drain of the low-side MOSFET, the
source of high-side synchronous MOSFET, and the inductor.
HDRV
13
High-side gate driver output. Connect this pin to the gate of the high-side synchronous rectifier MOSFET. When VIN
bias is removed, this pin is connected to SW through an internal 200-kΩ resistor.
PGOOD
14
Power good indicator. This pin is an open-drain output. TI recommends a 10-kΩ pullup resistor between PGOOD and
VCC or an external logic supply pin.
EN
15
Enable pin with internal pullup current source. Floating this pin will enable the IC. Pull below 1.2 V to enter low
current standby mode. Pull below 0.4 V to enter shutdown mode. The EN pin can be used to implement adjustable
UVLO using two resistors.
AGND
16
Analog signal ground of the IC. AGND should be connected to PGND at a single point on the PCB.
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS43060 TPS43061
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TPS43060, TPS43061
SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
www.ti.com
Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
PowerPAD
17
The PowerPAD should be connected to AGND. If possible, use thermal vias to connect to an internal ground plane
for improved power dissipation.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
MIN
MAX
Input: VIN, EN, ISNS+, ISNS–
–0.3
40
V
DC voltage: SW
–0.6
60
V
–2
60
V
–0.3
Transient voltage (10 ns max): SW
Voltage
FB, RT/CLK, COMP, SS
UNIT
3.6
V
BOOT, HDRV voltage with respect to ground
65
V
BOOT, HDRV voltage with respect to SW pin
8
V
VCC, PGOOD, LDRV
Operating junction temperature
–0.3
8
V
–40
150
°C
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
discharge
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
(1)
(2)
MIN
MAX
UNIT
–65
150
°C
–2000
2000
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage range
4.5
38
V
VOUT
Output voltage range
VIN
58
V
VEN
EN voltage range
0
38
V
VCLK
External switching frequency logic input range
0
3.6
V
TJ
Operating junction temperature
–40
150
°C
7.4 Thermal Characteristics
over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC
WQFN
(16-PINS)
(1)
RθJA
Junction-to-ambient thermal resistance
65.7
RθJC(top)
Junction-to-case (top) thermal resistance
42.3
RθJB
Junction-to-board thermal resistance
18
ψJT
Junction-to-top characterization parameter
0.9
ψJB
Junction-to-board characterization parameter
17.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
22.7
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS43060 TPS43061
TPS43060, TPS43061
www.ti.com
SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
7.5 Electrical Characteristics
VIN = 4.5 to 38 V, TJ = –40ºC to 150ºC, unless otherwise noted. Typical values are at TA = 25ºC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY AND ENABLE
VIN
VUV
Vhys
Input voltage range
4.5
Input undervoltage threshold
38
V
VIN falling
3.7
3.9
4
V
VIN rising
3.9
4.1
4.3
V
Undervoltage lockout hysteresis
200
mV
IQ
Operating quiescent current into VIN
Device non-switching,
RT = 115 kΩ, VFB = 2 V
ISD
Shutdown current
VEN = 0.4 V
EN pin voltage threshold to standby
VEN ramping down
EN pin voltage threshold to enable the device
VEN ramping up
EN pin voltage threshold to disable the device
VEN ramping down
EN pin pullup current
VEN = 1 V
1.8
EN pin hysteresis current
VEN = 1.3 V
3.2
EN to start switching time
CVCC = 0.47 µF
125
µs
VIN = 12 to 38 V,
IVCC = 0 µA
7.5
V
VIN = 4.5 V,
IVCC = 0 µA
4.5
V
VIN = 12 to 38 V,
IVCC = 0 µA
5.5
V
VIN = 4.5 V,
IVCC = 0 µA
4.5
V
VEN
IEN
tEN
TPS43060
VCC
VCC voltage
TPS43061
IVCC
600
VCC pin maximum output current
800
µA
1.5
5
µA
0.4
0.7
0.9
V
1.12
1.21
1.29
V
1
1.14
1.28
V
µA
4.6
50
µA
mA
VOLTAGE REFERENCE AND ERROR AMPLIFIER
VREF
Feedback voltage reference
IFB
Error amplifier input bias current
ICOMP
VCLAMP
TJ = 25°C
TJ = –40°C to 150°C
1.21
1.22
1.23
1.195
1.22
1.244
V
20
nA
COMP pin sink current
VFB = VREF + 250 mV, VCOMP = 1.5 V
160
µA
COMP pin source current
VFB = VREF – 250 mV, VCOMP = 1.5 V
160
µA
High clamp, VFB = 1 V
2.1
V
Low clamp, VFB = 1.5 V
0.7
COMP pin clamp voltage
COMP pin threshold
Duty cycle = 0%
1
V
Gea
Error amplifier transconductance
1.1
mS
Rea
Error amplifier output resistance
10
MΩ
Fea
Error amplifier crossover frequency
2
MHz
CURRENT SENSE
VCSmax
Maximum current sense threshold
At 0% duty cycle
64
73
82
mV
Maximum current sense threshold
At max duty cycle
50
61
72
mV
VRCsns
Reverse current sense threshold
3.8
mV
ISNS+
Sense+ pin current
70
µA
ISNS–
Sense– pin current
70
µA
RT/CLK
Operating frequency range using
resistor timing mode
ƒSW
Switching frequency
VRT/CLK
RT/CLK pin voltage
tCLK-min
Minimum input clock pulse duration
50
1000
kHz
RT = 115 kΩ
450
500
550
kHz
RT = 75 kΩ
675
750
825
kHz
60
ns
0.5
PLL = 500 kHz
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS43060 TPS43061
14
V
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TPS43060, TPS43061
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Electrical Characteristics (continued)
VIN = 4.5 to 38 V, TJ = –40ºC to 150ºC, unless otherwise noted. Typical values are at TA = 25ºC
PARAMETER
vCLK-H
ƒCLK
TEST CONDITIONS
MIN
RT/CLK high threshold
RT/CLK low threshold
0.4
PLL frequency sync range
300
TYP
MAX
1.78
2
1.35
UNIT
V
V
1000
kHz
tPLLIN
PLL lock in time
100
250
µs
tPLLEXIT
Last RT/CLK falling edge to return to resistor timing mode if CLK is not present
140
250
µs
POWER SWITCH DRIVERS
TPS43060
LDRV pullup resistance
TPS43061
RLDRV
TPS43060
LDRV pulldown resistance
TPS43061
TPS43060
HDRV pullup resistance
TPS43061
RHDRV
TPS43060
HDRV pulldown resistance
TPS43061
VIN = 12 to 40 V
2
VIN = 4.5 V
3
VIN = 12 to 40 V
1.6
VIN = 4.5 V
2
VIN = 12 to 40 V
2
VIN = 4.5 V
2.8
VIN = 12 to 40 V
5
VIN = 4.5 V
5.5
VIN = 12 to 40 V
1.2
VIN = 4.5 V
1.9
VIN = 12 to 40 V
3
VIN = 4.5 V
3.7
CLOAD = 2.2 nF,
VIN = 12 to 40 V
15
CLOAD = 2.2 nF,
VIN = 12 to 40 V
10
15
10
tHF
High-side gate fall time, 90%
to 10%
TPS43060
tLR
Low-side gate rise time, 10%
to 90%
TPS43060
TPS43061
CLOAD = 2.2 nF,
VIN = 12 to 40 V
tLF
Low-side gate fall time, 90% to TPS43060
10%
TPS43061
CLOAD = 2.2 nF,
VIN = 12 to 40 V
VF
BOOT diode forward voltage
drop
TPS43061
IF = 10 mA, TA = 25ºC
IBOOT
BOOT pin leakage current
TPS43061
tON
LDRV minimum on pulse duration
tOFF
LDRV minimum off pulse duration
20
15
20
15
Ω
Ω
Ω
Ω
Ω
Ω
Ω
ns
ns
ns
ns
0.75
V
Vr = 60 V
0.1
µA
ƒSW = 500 kHz
100
ns
ƒSW = 500 kHz
250
ns
TPS43060,
CLOAD = open,
ƒSW = 500 kHz
VIN = 12 V
65
ns
VIN = 4.5 V
75
ns
TPS43061,
CLOAD = open,
ƒSW = 500 kHz
VIN = 12 V
65
ns
VIN = 4.5 V
75
ns
TPS43060,
CLOAD = open,
Time delay between HDRV fall ƒSW = 500 kHz
(50%) to LDRV rise (50%),
TPS43061,
tnon-overlap2
CLOAD = open,
ƒSW = 500 kHz
VIN = 12 V
65
ns
VIN = 4.5 V
75
ns
VIN = 12 V
65
ns
VIN = 4.5 V
75
ns
Time delay between LDRV
fall(50%) to HDRV rise (50%),
tnon-overlap1
6
2
VIN = 12 to 40 V
TPS43060
tdelay
1.2
VIN = 4.5 V
High-side gate rise time, 10%
to 90%
TPS43061
3
VIN = 12 to 40 V
tHR
TPS43061
2.5
VIN = 4.5 V
Ω
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Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS43060 TPS43061
TPS43060, TPS43061
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SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
Electrical Characteristics (continued)
VIN = 4.5 to 38 V, TJ = –40ºC to 150ºC, unless otherwise noted. Typical values are at TA = 25ºC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
86%
90%
93%
UNIT
POWER GOOD, SS AND OVP
PGOOD low threshold
VFB with respect to feedback voltage
reference, VFB falling
PGOOD low hysteresis
VFB with respect to feedback voltage
reference
PGOOD high threshold
VFB with respect to feedback voltage
reference, VFB rising
PGOOD high hysteresis
VFB with respect to feedback voltage
reference
PGDSC
PGOOD sink current
VPGOOD = 0.4 V
PGDLK
PGOOD pin leakage current
VPGOOD = 7 V
PGDL
PGDH
2%
107%
Soft-start bias current
RSS
Soft-start discharge resistance
1.8
4
mA
100
nA
2.5
VSS = 0 V
OVP threshold
VFB with respect to feedback voltage
reference, VFB rising
OVP hysteresis
VFB with respect to feedback voltage
reference
VOVP
114%
2%
VIN_PGD Minimum VIN for valid PGOOD
ISS
110%
104%
4.3
V
5
µA
250
Ω
107%
110%
2%
THERMAL SHUTDOWN
TSD
Thermal shutdown set threshold
Thyst
Thermal shutdown hysteresis
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS43060 TPS43061
165
°C
15
°C
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7.6 Typical Characteristics
VIN = 12 V, ƒSW = 500 kHz, TA = 25ºC (unless otherwise noted)
4.5
6
VIN Rising
4.4
VIN Falling
5
Shutdown Current (µA)
4.3
Input Voltage ( V)
VSeries4
IN = 4.5 V
VSeries5
IN = 12 V
4.2
4.1
4.0
3.9
3.8
3.7
VSeries6
IN = 24 V
VSeries7
IN = 40 V
4
3
2
1
3.6
3.5
0
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
±50
150
0
640
620
600
580
50
75
100
125
150
C003
Figure 2. Shutdown Supply Current vs Temperature
600
RT = 115 k
580
560
Frequency (kHz)
VIN
= 4.5 V
Series1
VIN
= 12 V
Series2
VINSeries4
= 24 V
VIN
= 40 V
Series5
660
25
Temperature (ƒC)
Figure 1. Input Start and Stop Voltage vs Temperature
680
Non-Switching Supply Current (uA)
±25
C002
560
540
520
500
480
460
440
540
420
520
400
±50
±25
0
25
50
75
100
125
Temperature ( C)
±50
150
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C004
Figure 3. Non-Switching Supply Current vs Temperature
C005
Figure 4. Frequency vs Temperature
3.0
1.240
COMP Pin Clamp High
1.230
1.225
1.220
1.215
2.0
1.5
1.0
1.210
0.5
1.205
1.200
0.0
±50
±25
0
25
50
75
Temperature ( ƒC)
100
125
150
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±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C006
Figure 5. Feedback Voltage Reference vs Temperature
8
COMP Pin Clamp Low
2.5
COMP Voltage (V)
Voltage Reference (V)
1.235
150
C007
Figure 6. COMP Clamp Voltage vs Temperature
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS43060 TPS43061
TPS43060, TPS43061
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SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
Typical Characteristics (continued)
3.0
7
2.5
6
EN Hysteresis Current (µA)
EN Pull-up Current (µA)
VIN = 12 V, ƒSW = 500 kHz, TA = 25ºC (unless otherwise noted)
2.0
1.5
1.0
0.5
5
4
3
2
1
0.0
0
±50
±25
0
25
50
75
100
125
±50
150
Temperature (ƒC)
EN Voltage Falling
75
100
125
150
C009
1200
Transconductance (µA/V)
Enable Voltage (V)
50
Figure 8. EN Hysteresis Current vs Temperature
1.22
1.20
1.18
1.16
1100
1000
900
800
1.14
700
1.12
600
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
±50
150
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C010
Figure 9. Enable Threshold vs Temperature
C011
Figure 10. Error Amplifier Transconductance vs
Temperature
7
2.0
1.8
Normalized Driver Resistance
6
SS Charge Current (µA)
25
1300
EN Voltage Rising
1.24
0
Temperature (ƒC)
Figure 7. EN Pullup Current vs Temperature
1.26
±25
C008
5
4
3
2
1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.0
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±50
±25
Figure 11. SS Charge Current vs Temperature
0
25
50
75
100
125
Temperature (ƒC)
C012
150
C013
Figure 12. Gate Driver Output Resistance vs Temperature
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Typical Characteristics (continued)
VIN = 12 V, ƒSW = 500 kHz, TA = 25ºC (unless otherwise noted)
110
100
0% Duty Cycle
Max Duty Cycle
Max Current Threshold (mV)
FB Rising
OVP Threshold (%)
108
106
104
102
80
60
40
20
VIN = 12 V
fsw = 500 kHz
100
0
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
±50
150
25
50
75
100
125
150
C015
Figure 14. Maximum Current Sense Threshold vs
Temperature
5
10
TPS43060
9
4
TPS43061
8
VCC Voltage (V)
Reverse Current Sense Threshold (mV)
0
Temperature (ƒC)
Figure 13. OVP Threshold vs Temperature
3
2
1
7
6
5
4
3
2
VIN = 12 V
IVCC = 0 µA
1
0
0
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
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±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C016
Figure 15. Reverse Current Sense Threshold vs
Temperature
10
±25
C014
150
C017
Figure 16. VCC Voltage vs Temperature
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8 Detailed Description
8.1 Overview
The TPS4306x is a high-performance, wide-input range synchronous boost controller that accepts a 4.5 to 38 V
(40-V absolute max) input and support output voltages up to 58 V. The devices have gate drivers for both the
low-side N-channel MOSFET and the high-side synchronous rectifier N-channel MOSFET. Voltage regulation is
achieved employing constant frequency current mode pulse-duration modulation (PWM) control. The switching
frequency is set either by an external timing resistor or by synchronizing to an external clock signal. The
switching frequency is programmable from 50 kHz to 1 MHz in the resistor programmed mode or can be
synchronized to an external clock between 300 kHz to 1 MHz.
The PWM control circuitry turns on the low-side MOSFET at the beginning of each oscillator clock cycle, as the
error amplifier compares the output voltage feedback signal at the FB pin to the internal 1.22-V reference
voltage. The low-side MOSFET is turned-off when the inductor current reaches a threshold level set by the error
amplifier output. After the low-side MOSFET is turned off, the high-side synchronous MOSFET is turned on until
the beginning of the next oscillator clock cycle or until the inductor current reaches the reverse current sense
threshold. The input voltage is applied across the inductor and stores the energy as inductor current ramps up
during the portion of the switching cycle when the low-side MOSFET is on. Meanwhile, the output capacitor
supplies load current. When the low-side MOSFET is turned off by the PWM controller, the inductor transfers
stored energy with the synchronous MOSFET to replenish the output capacitor and supply the load current. This
operation repeats every switching cycle.
The devices feature internal slope compensation to avoid subharmonic oscillation that is intrinsic to peak current
mode control at duty cycles higher than 50%. They also feature adjustable soft-start time, optional lossless
inductor DCR current sensing, an output power good indicator, cycle-by-cycle current limit, and overtemperature
protection.
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8.2 Functional Block Diagram
VIN
ISNS- ISNS+
5.5V or 7.5V
LDO
ILIM
TPS43061
only
BOOT
5µA
Slope
Compensation
1.22V
SS
Reverse
Current
Detect
HDRV
SW
R
LOGIC
and
CONTROL
FB
S
VCC
COMP
LDRV
OVP
OSC/PLL
RT/CLK
PGND
3.2µA
1.342V
1.8µA
PGOOD
O
FB
EN
1.21V
1.098V
AGND
8.3 Feature Description
8.3.1 Switching Frequency
The switch frequency is set by a resistor (RT) connected to the RT/CLK pin of the TPS4306x. Figure 17 shows
the relationship between the timing resistance (RT) and frequency. The resistor value required for a desired
frequency can be calculated using Equation 1.
RT (k W) =
12
57500
f sw (kHz )
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Feature Description (continued)
1200
VCC Voltage (V)
1000
800
600
400
200
0
30
100
Resistance (kΩ)
900
G001
Figure 17. Frequency vs RT Resistance
The device switching frequency can be synchronized to an external clock that is applied to the RT/CLK pin. The
external clock should be in the range of 300 kHz to 1 MHz. The required logic levels of the external clock are
shown in the specification table. The pulse duration of the external clock should be greater than 20 ns to ensure
proper synchronization. A resistor between 57.5 and 1150 kΩ must always be connected from the RT/CLK pin to
ground when the converter is synchronized to an external clock. Do not leave this pin open.
8.3.2 Low-Dropout Regulator
The TPS4306x contains a low-dropout regulator that provides bias supply for the controller and the gate driver.
The output of the LDO of TPS4306x is regulated to 7.5 and 5.5 V, respectively. When the input voltage is below
the VCC regulation level, the VCC output tracks VIN with a small dropout voltage. The output current of the VCC
regulator should not exceed 50 mA. The value of the VCC capacitance depends on the total system design and
its startup characteristics. The recommended range of values for the VCC capacitor is from 0.47 to 10 µF.
8.3.3 Input Undervoltage (UV)
A UV detection circuit prevents misoperation of the device at input voltages below 3.9 V (typical). When the input
voltage is below the VIN UV threshold, the internal PWM control circuitry and gate drivers are turned off. The
threshold is set below the minimum operating voltage of 4.5 V to ensure that a transient VIN dip does not cause
the device to reset. For input voltages between the UV threshold and 4.5 V, the device attempts to operate, but
the electrical specifications are not ensured. The EN pin can be used to achieve adjustable UVLO if the desired
start-up threshold is higher than 3.9 V. Details are provided in the following section.
8.3.4 Enable and Adjustable UVLO
The EN pin voltage must be greater than 1.21 V (typical) to enable TPS4306x. The device enters a shutdown
mode when the EN voltage is less than 0.4 V. In shutdown mode, the input supply current for the device is less
than 5 µA. The EN pin has an internal 1.8-μA pullup current source that provides the default enabled condition
when the EN pin floats. When the EN pin voltage is higher than the shutdown threshold but less than 1.21 V, the
devices are in standby mode.
Adjustable input UVLO can be accomplished using the EN pin. As shown in Figure 18, a resistor divider from the
VIN pin to AGND sets the UVLO level. When EN pin voltage crosses the 1.21 V (typical) threshold voltage, an
additional 3.2-μA hysteresis current is sourced out of the EN pin. When the EN pin voltage falls below 1.14 V
(typical), the hysteresis current is removed. The addition of hysteresis current at the EN threshold facilitates
adjustable input voltage hysteresis. RUVLO_H and RUVLO_L are calculated using Equation 2 and Equation 3,
respectively.
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Feature Description (continued)
VIN
RUVLO_H
3.2 µA
1.8 µA
EN
1.21 V
RUVLO_L
AGND
Figure 18. Adjustable UVLO Using EN Pin
æV
ö
VSTART ´ ç EN _ DIS ÷ - VSTOP
çV
÷
è EN _ ON ø
RUVLO _ H =
æ V
ö
I EN _ pup ´ ç1 - EN _ DIS ÷ + I EN _ hys
ç V
÷
EN _ ON ø
è
RUVLO _ H ´ VEN _ DIS
RUVLO _ L =
VSTOP - VEN _ DIS + RUVLO _ H ´ (I EN _ pup + I EN _ hys )
(2)
where
•
•
•
•
•
•
VSTART is the desired turn-on voltage at the VIN pin.
VSTOP is the desired turn-off voltage at the VIN pin.
VEN_ON is the EN pin voltage threshold to enable the device, 1.21 V (typical).
VEN_DIS is the EN pin voltage threshold to disable the device, 1.14 V (typical).
IEN_hys is the hysteresis current inside the device, 3.2 μA (typical).
IEN_pup is the internal pullup current at EN pin, 1.8 μA (typical).
(3)
8.3.5 Voltage Reference and Setting Output Voltage
An internal voltage reference provides a precise 1.22-V voltage reference at the error amplifier non-inverting
input. To set the output voltage, select the FB pin resistor RSH and RSL according to Equation 4.
æR
ö
VOUT = 1.22V ´ ç SH + 1÷
è RSL
ø
(4)
8.3.6 Minimum On-Time and Pulse Skipping
The TPS4306x also features a minimum on-time of 100 ns for the low-side gate driver. This minimum on-time
determines the minimum duty cycle of the PWM for any set switching frequency. When the voltage regulation
loop requires a minimum on-time pulse duration less than 100 ns, the controller enters pulse-skipping mode. In
this mode, the devices hold the power switch off for multiple switching cycles to prevent the output voltage from
rising above the desired regulated voltage. This operation typically occurs in light load conditions when the DCDC converter operates in discontinuous conduction mode (DCM). Pulse skipping increases the output ripple as
shown in Figure 27.
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Feature Description (continued)
8.3.7 Zero-Cross Detection and Duty Cycle
The TPS4306x features zero-cross detection, which turns off the high-side driver when the sensed current falls
below the reverse current sense threshold (3.8 mV typical), then the converter runs in DCM. The duty cycle is
dependent on the mode in which the converter is operating. The duty cycle in DCM varies widely with changes of
the load. In continuous conduction mode (CCM), where the inductor maintains a minimum dc current, the duty
cycle is related primarily to the input and output voltages as computed in Equation 5.
D=
VOUT - VIN
VOUT
(5)
When the converter operates in DCM, the duty cycle is a function of the load, input and output voltages,
inductance, and switching frequency in Equation 6.
D=
2´ VOUT ´ I OUT ´ L ´ f SW
VIN 2
(6)
Equation 5 and Equation 6 provide an estimation of the duty cycle. A more accurate duty cycle can be calculated
by including the voltage drops of the external MOSFETs, sense resistor, and DCR of the inductor.
8.3.8 Minimum Off-Time and Maximum Duty Cycle
The low-side driver LDRV of TPS4306x has a minimum off-time of 250 ns or 5% of the switching cycle period,
whichever is longer. Figure 19 shows maximum duty cycle versus switching frequency. The maximum duty cycle
limits the maximum achievable step-up ratio in a boost converter. When the converter operates in CCM, the stepup ratio of the boost converter can be calculated using Equation 7.
VOUT
1
=
VIN
1- D
(7)
For instance, if the maximum duty cycle is 90%, the achievable maximum output voltage to input voltage ratio is
limited to:
VOUT
1
=
= 10
VIN
1 - 90%
(8)
100
Max Duty Cycle (%)
95
90
85
80
75
70
50
150
250
350
450
550
650
750
850
Frequency (kHz)
950 1050
C019
Figure 19. Maximum Duty Cycle vs Frequency
8.3.9 Soft-Start
The TPS4306x has a built-in soft-start circuit, which significantly reduces the start-up current spike and output
voltage overshoot. When the IC is enabled, an internal bias current source (5 µA typical) charges the capacitor
(CSS) on the SS pin. When the SS pin voltage is less than the internal 1.22-V reference, the device regulates the
FB pin voltage to the SS pin voltage rather than the internal 1.22-V reference voltage. When the SS pin voltage
exceeds the reference voltage, the device regulates the FB pin voltage to 1.22 V. The soft-start time of the output
voltage can be calculated using Equation 9.
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Feature Description (continued)
tss = Css
1.22V
5mA
(9)
8.3.10 Power Good
The TPS4306x PGOOD pin indicates when the output voltage is within predetermined limits of the desired
regulated output voltage by monitoring the FB pin voltage. The PGOOD pin is driven by the open-drain signal of
an internal MOSFET. When the output voltage of the power converter is not within ±10% of the output voltage
set point, the PGOOD MOSFET turns on and pulls the PGOOD pin low. Otherwise, the PGOOD MOSFET stays
off and the PGOOD pin can be pulled up by an external resistor to a voltage supply up to 8 V.
The PGOOD signal is also pulled low if the EN voltage or VIN voltage is below their respective voltage
thresholds.
8.3.11 Overvoltage Protection (OVP)
The TPS4306x integrates an OVP circuit that turns off the low-side MOSFET when the output voltage reaches
the OVP threshold, which is internally fixed to 107% of the output voltage set point. The low-side MOSFET
resumes normal PWM control when the output voltage drops below 105% of the output voltage set point. The
OVP circuit protects the power MOSFETs and minimizes the output voltage overshoot during transients or fault
conditions.
8.3.12 OVP and Current Sense Resistor Selection
The TPS4306x provides cycle-by-cycle current limit protection that turns off the low-side MOSFET when the
inductor current reaches the current limit threshold. The cycle-by-cycle current limit circuitry is reset at the
beginning of the next switching cycle. During an overcurrent event, the output voltage begins to droop as a
function of the load on the output.
A slope compensation ramp is added to the current sense ramp to prevent subharmonic oscillations at high duty
cycle. The slope compensation reduces the overcurrent limit threshold (maximum current sense threshold) with
increasing duty cycle as detailed in Figure 20.
Max Current Sense Threshold (mV)
78
74
70
66
62
58
54
50
0
10
20
30
40
50
60
70
80
Duty Cycle (%)
90
100
C020
Figure 20. Overcurrent Limit Threshold With Respect to Duty Cycle
The maximum current sense threshold VCSmax sets the maximum peak inductor current, which is the sum of
maximum average inductor (input) current, Iave_max, and half the peak-to-peak inductor ripple, ΔIL. Choose the
sense resistor value based on the desired maximum input current and the ripple current, which can be calculated
using Equation 10.
RSENSE =
VCS max
I ave _ max +
16
DI L
2
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Feature Description (continued)
8.3.13 Gate Drivers
The TPS4306x contains powerful high-side and low-side gate drivers supplied by the VCC bias regulator. The
nominal VCC voltage of the TPS43060 and TPS43061 is 7.5 V and 5.5 V, respectively. The TPS43061 gate
drivers operate from a 5.5-V VCC supply, with drive strength optimized for low Qg NexFETs. It also features an
integrated bootstrap diode for the high-side gate driver to reduce the external part count. The TPS43060 gate
drivers operate from a 7.5-V VCC supply, which is suitable to drive a wide range of standard MOSFETs. The
TPS43060 requires an external bootstrap diode from VCC to BOOT to charge the bootstrap capacitor. It also
requires a 2-Ω resistor connected in series with the VCC pin to limit the peak current drawn through the internal
circuitry when the external bootstrap diode is conducting. See the Electrical Characteristics for typical rise and
fall times and the output resistance of the gate drivers.
The LDRV and HDRV outputs are controlled with an adaptive dead-time control that ensures both the outputs
are never high at the same time. This minimizes any cross conduction and protects the power converter. The
typical dead-time from LDRV fall to HDRV rise is 65 ns.
The Qg versus VGS and the VGS versus RDS(on) curves for a given MOSFET should be used to determine which
gate drive voltage is appropriate. For example, the CSD86330Q3D synchronous power block has sufficient gate
drive voltage for low RDS(on) with the 5.5-V gate drive of the TPS43061. However, the CSD18537NQ5A MOSFET
has better RDS(on) performance with the 7.5-V gate drive of the TPS43060.
The designer needs to make important considerations if the stronger gate drivers of the TPS43060 are used with
low Qg and low-voltage threshold MOSFETs. The stronger gate driver causes the low-side MOSFET to turn on
very quickly resulting in large voltage undershoot below PGND at the SW node. The BOOT capacitor then
temporarily has a voltage across it exceeding the 8-V absolute maximum ratings. The external BOOT Schottky
diode with fast-switching speeds allows the BOOT capacitor to receive some charge during this short time
period. At light loads when the high-side MOSFET is not switching, there is no load on the BOOT capacitor. The
BOOT capacitor can then charge to a voltage exceeding the absolute maximum ratings. To limit the voltage
across the BOOT-SW pins, the RC time constant for charging the BOOT capacitor should be increased to avoid
charging while the SW node is below ground and/or the SW voltage undershoot should be reduced. Do this by
following these recommendations:
• Resistor in series with the external Schottky diode to increase RC time constant for charging the BOOT
capacitor
• Resistor in series with the LDRV signal to slow down the low-side MOSFET switching speed and reduce SW
ringing
• RC snubber across the high-side MOSFET to reduce SW ringing
• Proper layout techniques as recommended in Layout to reduce SW ringing
Figure 21 shows these components. A typical value for either series resistor is 4.7 Ω.
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Feature Description (continued)
RSNUB
CSNUB
VIN
VOUT
TPS43060
ISNS±
RCHARGE
BOOT
ISNS+
VCC
VIN
LDRV
RLDRV
PGND
SW
HDRV
Figure 21. External Components for Limiting the BOOT-SW Voltage
8.3.14 Thermal Shutdown
An internal thermal shutdown turns off the TPS4306x when the junction temperature exceeds the thermal
shutdown threshold (165°C typical). The device restarts when the junction temperature drops by 15°C.
8.4 Device Functional Modes
8.4.1 Typical Operation (VIN < VOUT)
The TPS4306x is designed to operate with a minimum input voltage of 4.5 V. It will turn on when the VIN voltage
exceeds the typical 4.1-V UVLO threshold and the EN voltage exceeds the typical 1.21-V enable voltage
threshold. If EN is left floating, an internal current source pulls the voltage above the EN threshold. In a boost
topology, the input is passed to the output through the inductor and high-side FET body diode. As a result, while
the TPS4306x is disabled, the output voltage will track the input voltage. When both thresholds are exceeded,
the VCC LDO output comes into regulation. Switching is enabled and the SS current source begins charging the
external soft-start capacitor for a controlled soft-start of the output voltage with a time period determined by the
value of the external SS capacitor. If either pin's voltage drops below its respective threshold, the TPS4306x is
shutdown.
8.4.2 Pass Through (VIN > VOUT)
If there is an operation condition where the input voltage exceeds the output voltage set by the external FB
resistor divider, the TPS4306x stops switching. The input voltage is directly connected to the output voltage
through the inductor and body diode of the external high-side MOSFET. The output voltage then follows the input
voltage with a voltage drop determined mainly by the forward voltage of the high-side MOSFET body diode. If
there is an output load while in this mode, pay attention to power dissipation in the high-side MOSFET body
diode. The TPS4306x begins switching again after the input voltage drops below the output voltage set by the
external FB resistor divider.
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Device Functional Modes (continued)
8.4.3 Split-Rail Operation
The TPS4306x can also operate in a split-rail topology where a separate voltage is provided to bias the VIN pin
of the IC to 4.5 V or greater. The power for the boost power stage can then be powered from a separate input
lower than the 4.5-V minimum VIN voltage. When operating in this mode, the boost power stage voltage must be
greater than 2.5 V to bias the ISNS pins or the current limit accuracy may degrade. If used in split rail, the
TPS4306x is enabled and disabled in the same VIN and EN conditions as described in Typical Operation (VIN <
VOUT).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS4306x device is a 4.5- to 38-V input, 58-V maximum output, step-up controller with integrated MOSFET
drivers to create a synchronous boost power supply. This device is typically used to convert a lower DC voltage
to a higher DC voltage. The maximum current is limited using an external resistor between the ISNS+ and ISNS–
pins or the thermal performance of the external MOSFETs. Example applications are: 5, 12, and 24 V industrial,
automotive and communications power systems, or battery-powered systems. Use the following design
procedure to select component values for the TPS4306x device. This procedure illustrates the design of a high
frequency switching regulator using ceramic output capacitors. Calculations can be done with the excel
spreadsheet (SLVC471) located on the product page for TPS43060 and TPS43061. Alternately, use the
WEBENCH® software to generate a complete design. The WEBENCH software uses an iterative design
procedure and accesses a comprehensive database of components when generating a design. This section
presents a simplified discussion of the design process.
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9.2 Typical Applications
9.2.1 Synchronous Boost Converter Typical Application Using TPS43061
NOTES
For DCR sensing, open R14 and short R15, R16, and R17. For resistor sensing, open R15.
For Split Rail application, open R11.
J5
1
VIN
VIN
2
R16
20m
TP8
J6
VIN
1
GND
2
L1
R17
VIN: 6V-12.6V
3.3uH
20m
+
C13
C14
10uF
1
TP9
C15
10uF
J1
R14
10
R13
10
R15
2
1
VOUT
1
J7
2
GND
ISNS+
ISNS-
1
TP3
J2
15V @ 2A
R1
VIN
JP1
3
C2
C3
C4
C5
VSW 6
10uF
10uF
10uF
10uF
17 16
R5
76.8k
15
2
1
9
U1
TPS43061RTE
3 COMP
ISNS+
VIN
LDRV
C8
0.1uF
7.50k
BOOT 11
5
6
7
8
150pF
C9
C10
VCC 10
PGND 9
4 FB
ISNS-
C7
49.9
0.1uF
SW 12
2 SS
FB
TP6
C1
1 RT/CLK
R7
GND
R6
13
14
J3
1
BG
R4
59.0k
GND
C16
5
TGR PGND
TP5
+
VSW 7
VIN
TG
HDRV
3
VOUT
1
VSW 8
VIN
2
4
EN
OFF
0
221k
PGOOD
EN
2
R2
AGND
1
TP2
TP1
PWPD
ON
1
100k
R3
TP4
Q1
CSD86330Q3D
VCC
2
VCC
R8
TP7
1
C6
124k
FB
4.7uF
R9
11.0k
0.015uF
C12 100pF
VIN
R12
1
R10
C11
0
0.1uF
R11
J4
ISNS-
ISNS+
0
1
2
VBIAS (OPTIONAL)
1
Not Populated
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9.2.1.1 Design Requirements
The following section provides a step-by-step design guide of a high-frequency, high-power-density synchronous
boost converter with the TPS43061 controller combined with a NexFET power block. This design procedure is
also applicable to the TPS43060. The designer must know a few parameters to start the design process. These
requirements are typically determined at the system level. For this example, start with the following known
parameters.
Table 1. Key Parameters of the Boost Converter Example
Parameter
Value
Input voltage (VIN)
6 to 12.6 V, 9 V nominal
Output voltage (VOUT)
15 V
Maximum output current (IOUT)
2A
Transient response to 0.5 A to 1.5 A load step (ΔVOUT)
4% of VOUT = 0.6 V
Output voltage ripple (VRIPPLE)
0.5% of VOUT = 0.075 V
Start input voltage (VSTART)
5.34 V
Start input voltage (VSTOP)
4.3 V
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Selecting the Switching Frequency
The first step is to determine the switching frequency of the power converter. Be sure to consider the tradeoffs
when selecting a higher or lower switching frequency. Typically, the designer uses the highest switching
frequency possible because this results in the smallest solution size. A higher switching frequency allows for
lower-value inductors and smaller-output capacitors compared to a power converter that switches at a lower
frequency. A lower switching frequency produces a larger solution size, but typically has better efficiency. Setting
the frequency for the minimum tolerable efficiency produces the optimum solution size for the application.
The switching frequency can also be limited by the minimum on-time and off-time of the controller based on the
input voltage and the output voltage of the application. To determine the maximum allowable switching
frequency, first estimate the CCM duty cycle using Equation 11 with the minimum and maximum input voltages.
Equation 12 and Equation 13 should then be used to calculate the upper limit of switching frequency for the
regulator. Choose the lower value result from these two equations. Switching frequencies higher than the
calculated values result in either pulse skipping if the minimum on-time restricts the duty cycle or insufficient
boost output voltage if the PWM duty cycle is limited by the minimum off-time.
V
- VIN
D = OUT
VOUT
(11)
f SW ontime =
D min
20%
=
= 2MHz
ton min 100ns
(12)
f SW offtime =
(1 - D max) (1 - 60%)
=
= 1.6 MHz
toffmin
250ns
(13)
The typical minimum on-time and off-time of the device are 100 ns and 250 ns, respectively. For this design, the
duty cycle is estimated at 20% and 60% with the maximum input voltage and minimum input voltage,
respectively. When operating at switching frequencies less than 200 kHz, the minimum off-time starts to increase
and is equal to 5% of the switching period. 1.6 MHz is the estimated allowed maximum switching frequency
based on Equation 12 and Equation 13 . When operating near the estimated maximum duty cycle, more accurate
estimations of the duty cycle should be made by including the voltage drops of the external MOSFETs, sense
resistor, and DCR of the inductor.
A switching frequency of 750 kHz was chosen as a compromise between efficiency and small solution size. To
determine the timing resistance for a given switching frequency, use either Equation 14 or the curve in Figure 17.
The switching frequency is set by resistor R5, shown in the schematic in Synchronous Boost Converter Typical
Application Using TPS43061. For 750-kHz operation, the closest standard value resistor is 76.8 kΩ.
57500
57500
=
= 76.7k W
RT ( k W) =
f SW ( kHz ) 750( kHz )
(14)
22
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9.2.1.2.2 Inductor Selection
The selection of the inductor affects the steady-state operation as well as transient behavior and loop stability.
These factors make it an important component in a switching power-supply design. The three most important
inductor specifications to consider are inductor value, DC resistance (DCR), and saturation current rating. Let the
parameter KIND represent the ratio of inductor peak-to-peak ripple current to the average inductor current. In a
boost topology, the average inductor current is equal to the input current. The current delivered to the output is
the input current modulated at the duty cycle of the PWM. The inductor ripple current contributes to the output
current ripple that must be filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor. The value of KIND in the design using low-ESR output capacitors,
such as ceramics, can be relatively higher than that in the design using higher-ESR output capacitors. Higher
values of KIND lead to DCM operation at moderate to light loads.
To calculate the minimum value of the output inductor, use Equation 16 or Equation 17. In a boost topology,
maximum current ripple occurs at 50% duty cycle. Use Equation 16 if the design will operate with 50% duty
cycle. If not, use Equation 17. In Equation 17, use the input voltage value that is nearest to 50% duty-cycle
operation.
For this design example, Equation 15 produces the estimated maximum input current (IIN) of 5 A. In reality, IIN will
be higher because the simplified equations do not include the efficiency losses of the power supply. Using KIND =
0.3 with Equation 16, the minimum inductor value is calculated to be 3.33 µH. The nearest standard value of 3.3
µH is chosen. It is important that the RMS current and saturation current ratings of the inductor are not
exceeded. The RMS and peak inductor current can be found from Equation 18 and Equation 19, respectively.
The calculated RMS inductor current is 5 A, and the peak inductor current is 5.73 A. The chosen inductor is a
Vishay IHLP2525CZER3R3M1, which has an RMS current rating of 6 A, a saturation current rating of 10 A, and
30-mΩ DCR.
I OUT
2A
I IN =
=
= 5A
1
D
max
1
(
) ( 60%)
(15)
L³
L³
VOUT
1
15V
1
´
=
´
= 3.33mH
I IN ´ K IND 4 ´ f SW 5 A ´ 0.3 4 ´ 750kHz
(16)
VIN
D
´
I IN ´ K IND f SW
(17)
2
2
2
2
ö
6V ´ 60%
æ I OUT ö æ VIN min´ D max ö
æ 2A ö æ
I L rms = ç
+
=
+ çç
ç
÷
÷ = 5A
÷ ç
ç
÷
÷
÷
è 1 - 60% ø è 12 ´ 3.3mH ´ 750kHz ø
è 1 - D max ø è 12 ´ L ´ f SW ø
I L peak =
I OUT
V min´ D max
2A
6V ´ 60%
+ IN
=
+
= 5.73 A
1 - D max
2 ´ L ´ f SW
1 - 60% 2 ´ 3.3mH ´ 750kHz
(18)
(19)
Selecting higher ripple currents increases the output voltage ripple of the regulator, but allows for a lower
inductance value.
The current flowing through the inductor is the inductor ripple current plus the average input current. During
power-up, load faults, or transient load conditions, the inductor current can increase above the peak inductor
current calculated previously. The prior equations also do not include the efficiency of the regulator. For this
reason, a more conservative design approach is to choose an inductor with a saturation current rating greater
than the typical switch current limit set by the current sense resistor or the inductor DC resistance if lossless
DCR sensing is used.
9.2.1.2.3 Selecting the Current Sense Resistor
The external current sense resistor sets the cycle-by-cycle peak current limit. The peak current limit should be
set to assure the maximum load current can be supported at the minimum input voltage. The typical overcurrent
threshold voltage (VCS) with respect to duty cycle is shown in Figure 20. In this design example, the typical
current limit threshold voltage at the 60% maximum duty cycle is 68 mV.
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When selecting the current limit for the design, TI recommends a 20% margin from the calculated peak current
limit in Equation 19 to allow for load and line transients and the efficiency loss of the design. Calculate the
recommended current sense resistance with Figure 20. In this example, the minimum resistance is calculated at
9.89 mΩ and two 20-mΩ resistors in parallel are used. The sense resistors must be rated for the power
dissipation calculated in Equation 22. Using the maximum current limit threshold of 82 mV according to the
electrical specification table, the maximum power loss in the current sense resistor is 0.672 W. Two 0.5-W rated
sense resistors are used in parallel in this design.
VCS max typ = 68mV
(20)
RCS =
VCS max typ
68mV
=
= 9.89mW
1.2 ´ I L peak 1.2 ´ 5.73 A
2
PRCS =
(21)
2
(VCS max max)
(82mV )
=
= 0.672W
10mW
RCS
(22)
The 10-Ω series resistors, R13 and R15, with the 100-pF capacitor C12 filter high-frequency switching noise from
the ISNS pins.
9.2.1.2.4 Output Capacitor Selection
In a boost topology, the current supplied to the output capacitor is discontinuous and proper selection of the
output capacitor is important for filtering the high di/dt path of the supply. The designer must account for two
primary considerations for selecting the value of the output capacitor. The output capacitor determines the output
voltage ripple and how the supply responds to a large change in load current. The output capacitance must be
selected based on the more stringent of these two criteria.
The first criterion is the desired response to a large change in load current. A PWM controller cannot immediately
respond to a fast increase or decrease in the load current. The response time is determined by the loop
bandwidth. The output capacitor must supply the increased load current or absorb the excess inductor current
until the controller responds. Equation 23 estimates the minimum output capacitance needed for the desired
ΔVOUT for a given ΔIOUT. The loop bandwidth (ƒBW) is typically limited by the right-half-plane zero (RHPZ) of the
boost topology. The maximum recommended bandwidth can be calculated from Equation 41 and Equation 42.
See the compensation section for more information. In this example, to limit the voltage deviation to 600 mV from
a 1-A load step with a 14.5-kHz maximum bandwidth, a minimum of 18.3-µF output capacitance is needed. This
value does not take into account the ESR of the output capacitor, which can typically be ignored when using
ceramic capacitors.
The output capacitor absorbs the ripple current through the synchronous switch to limit the output voltage ripple.
Equation 24 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
In this example, a minimum of 21.3 µF is needed. Again, this value does not take into account the ESR of the
output capacitor.
DITRAN
1A
COUT >
=
= 18.3mF
2p ´ f BW ´ DVTRAN 2p ´ 14.5kHz ´ 0.6V
(23)
COUT >
D max´ I OUT
60% ´ 5 A
=
= 21.3mF
f SW ´ VRIPPLE 750kHz ´ 0.075V
(24)
The most stringent criterion for the output capacitor is 21.3 µF required to limit the output voltage ripple. When
using ceramic capacitors for switching power supplies, TI recommends high-quality type X5R or X7R. They have
a high capacitance-to-volume ratio and are fairly stable over temperature. Capacitance deratings for aging,
temperature, and dc bias increase the minimum value required. The voltage rating must be greater than the
output voltage with some tolerance for output voltage ripple and overshoot in transient conditions. For this
example, 4 × 10-µF, 25-V ceramic capacitors with 5 mΩ of ESR are used. The estimated derated capacitance is
22 µF, approximately equal to the calculated minimum.
9.2.1.2.5 MOSFET Selection – NexFET Power Block
The TPS43061 5.5-V gate drive is optimized for low Qg NexFET power devices. NexFET power blocks with both
the high-side and low-side MOSFETs integrated are ideal for high-power-density designs. This design example
uses the CSD86330Q3D. Two primary considerations when selecting the power MOSFETs are the average gate
drive current required and the estimated MOSFET power losses.
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The average gate drive current must be less than the 50-mA (minimum) VCC supply current limit. This current is
calculated using Equation 25. With the selected power block and 5.5-V VCC, the low-side FET has a total gate
charge of 11 nC and the high-side FET has a total gate charge of 5 nC. The required gate drive current is 12
mA.
I GD = (Qg HS + Qg LS ) ´ f SW = (5nC + 11nC ) ´ 750kHz = 12mA
(25)
The target efficiency of the design dictates the acceptable power loss in the MOSFETs. The two largest
components of power loss in the low-side FET are switching and conduction losses. Both losses are highest at
the minimum input voltage when low-side FET current is maximum. The conduction power loss in the low-side
FET can be calculated with Equation 26. Switching losses occur during the turn-off and turn-on time of the
MOSFET. During these transitions, the low-side FET experiences both the input current and output voltage. The
switching loss can be estimated with Equation 27. The low-side FET of the CSD86330Q3D has RDS(on)LS = 4.2
mΩ, gate-to-drain charge Qgd = 1.6 nC, output capacitance COSS = 680 pF, series gate resistance RG = 1.2 Ω,
and gate-to-source voltage threshold VGS(th) = 1.1 V. The conduction power losses are estimated at 0.042 W and
the switching losses are estimated at 0.070 W.
PCONDLS = D max´ I L rms 2 ´ RdsonLS = 60% ´ 5.0 A2 ´ 4.2mW = 0.042W
(26)
Qgd ´ RG ö
f SW æ
I OUT
÷
´ ç COSS ´ VOUT 2 + VOUT ´
´
ç
2
1 - D max VCC - VGS (th ) ÷
è
ø
750kHz æ
2A
1.6nC ´ 1.2W ö
=
´ ç 680 pF ´ 15V 2 + 15V ´
´
= 0.070W
2
1
60%
5.5V - 1.1V ø÷
è
(27)
PSW =
Two power losses in the high-side FET to consider are the dead time body diode loss and the FET conduction
loss. The conduction loss is highest at the minimum PWM duty cycle. The conduction power loss in the high-side
FET can be calculated with Equation 28. Dead time losses are caused by conduction in the body diode of the
high-side FET during the delay time between the LDRV and HDRV signals. The dead time loss varies mainly
with switching frequency. The dead time losses are estimated with Equation 29. The high-side FET of the
CSD86330Q3D has RDS(ON)HS = 8 mΩ and body diode forward voltage drop VSD = 0.75 V. The conduction power
losses are estimated at 0.080 W and the dead time losses are estimated at 0.366 W. For designs targeting
highest efficiency, dead time losses can be reduced by adding a Schottky diode in parallel with the high-side FET
to reduce the diode forward voltage drop during the dead time.
PCONDHS = (1 - D max )´ I L rms 2 ´ RDS ( on ) HS = (1 - 60% )´ 5.0 A2 ´ 8mW = 0.080W
(
(28)
)
PDT = VSD ´ I L rms ´ tnon -overlap1 + tnon -overlap 2 ´ f SW
= 0.75V ´ 5 A ´ (65ns + 65ns )´ 750kHz = 0.366W
(29)
9.2.1.2.6 Bootstrap Capacitor Selection
A capacitor must be connected between the BOOT and SW pins for proper operation. This capacitor provides
the instantaneous charge and gate drive voltage needed to turn on the high-side FET. TI recommends a ceramic
with X5R or better grade dielectric. Use Equation 30 to calculate the minimum bootstrap capacitance to limit the
BOOT capacitor ripple voltage to 250 mV. In this example with the selected high-side FET, the minimum
calculated capacitance is 0.042 µF and a 0.1-µF capacitor is used. The capacitor should have a 10-V or higher
voltage rating.
Qg HS
5nC
CBOOT =
=
= 0.042mF
DVBOOT 250mV
(30)
9.2.1.2.7 VCC Capacitor
An X5R or better grade ceramic bypass capacitor is required for the internal VCC regulator at the VCC pin with a
recommended range of 0.47 to 10 µF. This example uses a capacitance of 4.7 µF. The capacitor should have a
10-V or higher voltage rating.
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9.2.1.2.8 Input Capacitor
The TPS4306x requires a high-quality 0.1 µF or higher ceramic-type X5R or X7R bypass capacitor at the VIN pin
for proper decoupling. Based on the application requirements, additional bulk capacitance may be needed to
meet input voltage ripple and/or transient requirements. The minimum capacitance for a specified input voltage
ripple is calculated using Equation 31. The voltage rating of the input capacitor must be greater than the
maximum input voltage. The capacitor must also have a ripple current rating greater than the RMS current
calculated with Equation 32. If ceramic input capacitors are used, they should be a high-quality ceramic, type
X5R or X7R.
For this example design, the capacitors must be rated for at least 12 V to support the maximum input voltage.
Designing for a 45-mV input voltage ripple (0.5% the nominal input voltage), the minimum input capacitance is
10.8 µF. The input capacitor must also be rated for 0.42 A RMS current. The capacitors selected are 2 × 10-µF,
25-V ceramic capacitors with 5 mΩ of ESR. The estimated voltage derated total capacitance is 15 µF.
I RIPPLE
1.46 A
CIN >
=
= 10.8mF
4 ´ f SW ´ VINRIPPLE 4 ´ 750kHz ´ 0.045V
(31)
I CIN rms =
1.46 A
I RIPPLE
12
=
12
= 0.42 A
(32)
9.2.1.2.9 Output Voltage and Feedback Resistors Selection
The voltage divider of R8 and R9 sets the output voltage. To balance power dissipation and noise sensitivity, R9
should be selected between 10 and 100 kΩ. For the example design, 11 kΩ was selected for R9. Using
Equation 33, R8 is calculated as 124.2 kΩ. The nearest standard 1% resistor 124 kΩ is used.
V
- VFB
15V - 1.22V
RHS = RLS ´ OUT
= 11.0k W ´
= 124.2k W
1.22V
VFB
where
•
•
RLS = R9
RHS = R8
(33)
9.2.1.2.10 Setting the Soft-Start Time
The soft-start capacitor determines the amount of time allowed for the output voltage to reach its nominal
programmed value during power-up. This is especially useful if a load requires a controlled voltage slew rate. A
controlled start-up time is necessary with large output capacitance to limit the current into the capacitor during
start-up. Large input currents charging the output capacitors during start-up could trigger the current limit.
Excessive current draw from the input power supply may also cause the input voltage rail to sag. The soft-start
capacitor can be sized to limit in-rush current or output voltage overshoot during startup. Use Equation 34 to
calculate the required capacitor for a desired soft-start time. In this example application for a desired soft-start
time of 20 ms, a 0.082-µF capacitance is calculated, and the nearest standard value of 0.1-µF capacitor is
chosen.
t ´I
20ms ´ 5mA
CSS = SS SS =
= 0.082mF
1.22V
VREF
(34)
9.2.1.2.11 UVLO Set Point
The UVLO can be adjusted using an external voltage divider connected to the EN pin of the TPS4306x. The
UVLO has two thresholds, one for power-up when the input voltage is rising and one for power-down or brown
outs when the input voltage is falling. The necessary voltage divider resistors are calculated with Equation 35
and Equation 36. If the application does not require an adjustable UVLO, the EN pin can be left floating or tied to
the VIN pin.
For the example design, the supply should start switching when the input voltage increases to 5.34 V (VSTART).
After start-up, it should continue to operate until the input voltage falls to 4.3 V (VSTOP). To produce the desired
start and stop voltages, this example uses resistor divider values R3 = 221 kΩ between VIN and EN and a R4 =
59 kΩ between EN and GND.
26
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æ VEN _ DIS ö
æ 1.14V ö
VSTART ´ ç
÷ -V
5.34V ´ ç
- 4.3V
ç VEN _ ON ÷ STOP
1.21V ÷ø
è
ø
è
RUVLO _ H =
=
= 221.26k W
æ VEN _ DIS ö
æ 1.14V ö
1.8
1
3.2
A
A
m
´
+
m
ç 1.21V ÷
I EN _ pus ´ ç 1 ÷+I
ç VEN _ ON ÷ EN _ hys
è
ø
è
ø
RUVLO _ H ´ VEN _ DIS
221k W ´ 1.14V
=
RUVLO _ L =
4.3V - 1.14V + 221k W ´ (1.8mA + 3.2mA )
-V
+R
´ I
+I
V
STOP
EN _ DIS
UVLO _ H
(
EN _ pup
EN _ hys
(35)
)
= 59k W
(36)
9.2.1.2.12 Power Good Resistor Selection
The PGOOD pin is an open-drain output requiring a pullup resistor connected to a voltage supply of no more
than 8 V. TI recommends a value between 10 and 100 kΩ. If the Power Good indicator feature is not needed,
this pin can be grounded or left floating.
9.2.1.2.13 Control Loop Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation internal to the device. Because the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and ESR zero of the
output capacitor. In this simplified model, the DC gain (Adc), modulator pole (ƒPmod), and the ESR zero (ƒZmod)
are calculated with Equation 37 to Equation 39. Use the derated value of COUT, which is 22 µF in this example. In
a boost topology, the maximum crossover frequency is typically limited by the RHPZ. The RHPZ can be
estimated with Equation 40. The compensation design should be done at the minimum input voltage when the
RHPZ is at the lowest frequency. The crossover frequency should also be limited to less than 1/5 of the switching
frequency. Equation 41 and Equation 42 are used to calculate the maximum recommended crossover frequency.
For this example design, Adc = 11.3 V/V, ƒPmod = 0.97 kHz, ƒZmod = 1.45 MHz, ƒRHPZ = 57.9 kHz, ƒco1 = 14.5
kHz, and ƒco2 = 150 kHz. The target ƒco is 14.5 kHz.
VIN min
3
3
6V
V
Adc =
´
=
´
= 11.3
40 2 ´ RSENSE ´ I OUT 40 2 ´ 10mW ´ 2 A
V
(37)
f P mod =
1
1
=
= 0.97kHz
VOUT
15V
´ 22mF
2p ´
´ COUT 2p ´
2A
I OUT
(38)
1
1
=
= 1.45 MHz
2p ´ ESR ´ COUT 2p ´ 5mW ´ 22mF
VOUT
15V
2
2
I OUT æ VIN ö
æ 6V ö
2A
f RHPZ =
´ç
=
´
= 57.9kHz
÷
2p ´ L è VOUT ø
2p ´ 3.3mH çè 15V ÷ø
f
57.9kHz
fco1 < RHPZ =
= 14.5kHz
4
4
f
750kHz
fco2 < SW =
= 150kHz
5
5
f Z mod =
(39)
(40)
(41)
(42)
The compensation components can now be calculated. A resistor in series with a capacitor creates a
compensating zero. A capacitor in parallel to these two components can be added to form a compensating pole.
Use Equation 43 to determine the compensation resistor (R7). R7 is calculated to be 7.45 kΩ and a standard 1%
value of 7.5 kΩ is selected. Use Equation 44 to set the compensation zero to 1/10 the target crossover
frequency. C9 is calculated at 0.0147 µF and a standard value of 0.015 µF is used.
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R 7 = R COMP =
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40 2p ´ COUT ´ R SENSE ´ VOUT ´ fco ´ ( R SH + R SL )
´
3
R SL ´ VIN min´ Gea
40 2p ´ 22mF ´ 10mW ´ 15V ´ 14.5kHz ´ (124kW + 11kW)
´
= 7.45kW
mA
3
11kW ´ 6V ´ 1100
V
1
1
C 9 = CCOMP =
=
= 0.0147mF
fco
14.5kHz
2p ´
´ RCOMP 2p ´
´ 7.50k W
10
10
=
(43)
(44)
A compensation pole can be implemented, if desired, with capacitor C8 in parallel with the series combination of
R7 and C9. Use the larger value calculated from Equation 45 and Equation 46. The selected value of C8 is 150
pF for this example.
C
´ ESR 22mF ´ 5mW
CHF = OUT
=
= 14.7 pF
7.50k W
RCOMP
(45)
CHF =
1
1
=
= 150 pF
20p ´ fco ´ RCOMP 20p ´ 14.5kHz ´ 7.50k W
(46)
9.2.1.2.14 DCM, Pulse-Skip Mode, and No-Load Input Current
The reverse current sensing of the TPS4306x allows the power supply to operate in DCM at light loads for higher
efficiency. The supply enters DCM when the inductor current ramps to 0 at the end of a PWM cycle and the
reverse current sense turns off the high-side FET for the remainder of the cycle. In DCM, the duty cycle is a
function of the load, input and output voltages, inductance, and switching frequency as computed in Equation 47.
The load current at which the inductor current falls to 0 and the converter enters DCM can be calculated using
Equation 48. Additionally, after the converter enters DCM, decreasing the load further reduces the duty cycle. If
the DCM on-time reaches the minimum on-time of the TPS4306x, the converter begins pulse skipping to
maintain output voltage regulation. Pulse skipping can increase the output voltage ripple.
In this example with the 9-V nominal input voltage, the estimated load current where the converter enters DCM
operation is 0.44 A. The measured boundary is 0.36 A. In most designs, the converter enters DCM at lower load
currents because Equation 48 does not account for the efficiency losses. The design example power supply
enters pulse-skip mode when the output current is lower than 12 mA and the input current draw is 1.3 mA with
no load.
D=
2 ´ (VOUT - VIN )´ L ´ I OUT ´ f SW
I OUT crit =
28
VIN
(VOUT
- VIN )´ VIN
(47)
2
2
2 ´ VOUT ´ f SW ´ L
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=
(15V - 9V )´ 9V
2
2 ´ 15V 2 ´ 750kHz ´ 3.3mH
= 0.44 A
(48)
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SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
9.2.1.3 Application Curves
Vout (ac coupled)
200mV/div
VIN
5V/div
VCC
5V/div
VCC
5V/div
VOUT
5V/div
Iout
1A/div
PGOOD
5V/div
Time - 200 ms/div
Time – 5ms/div
Figure 22. Load Transient
Figure 23. Start-Up With VIN
VOUT(ac coupled )
100mV/div
EN
5V/div
IL
1A/div
VCC
5V/div
Vout
5V/div
SW
10V/div
PGood
5V/div
Time – 1µs/div
Time - 5 ms/div
Figure 24. Start-Up With EN
VOUT(ac coupled )
100mV/div
Figure 25. Output Ripple in CCM
VOUT(ac coupled )
100mV/div
IL
1A/div
IL
1A/div
SW
10V/div
SW
10V/div
Time – 1µs/div
Time – 500µs/div
Figure 26. Output Ripple in DCM
Figure 27. Output Ripple in Pulse-Skipping Mode
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VIN(ac coupled)
50mV/div
VOUT(ac coupled )
100mV/div
IL
1A/div
IL
1A/div
SW
10V/div
SW
10V/div
Time – 1µs/div
Time – 1µs/div
Figure 28. Input Ripple in CCM
Figure 29. Input Ripple in DCM
95
90
Gain (dB)
Efficiency (%)
85
80
75
70
65
VIN = 6 V
Series1
VIN = 9 V
Series2
VIN = 12 V
Series4
60
55
50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Output Current (A)
180
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
100
Gain
Phase
60
0
−60
−120
1k
100k
−180
1M
G030
C030
Figure 31. Loop Gain and Phase
0.05
0.1
0.04
0.08
Output Voltage Normalized (%)
Output Voltage Normalized (%)
10k
Frequency (Hz)
4.5
Figure 30. Efficiency vs Output Current
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Output Current (A)
1.6
1.8
2
6
6.5
7
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7.5
8
8.5
9
9.5 10 10.5 11 11.5 12
Input Voltage (V)
C031
Figure 32. Load Regulation
30
120
Phase (°)
100
C033
Figure 33. Line Regulation
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS43060 TPS43061
TPS43060, TPS43061
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9.2.2
SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
High-Efficiency 40-V Synchronous Boost Converter Typical Application Using TPS43060
R16
10m
J5
VIN
R17
VIN: 10V-38V
VIN
10m
TP8
2
L1
R18
15uH
J6
VIN
1
GND
2
+
C13
TP9
1
C14
C15
10uF
10uF
1
C16
R14
10
R13
10uF 10
R15
1
ISNS+
ISNS-
J7
J1
GND
TP2
R2
VCC
R4
FB
R7
C7
1
RT/CLK
2
SS
3
COMP
4
FB
SW
12
BOOT
11
VCC
10
PGND
C8
0.1uF 1500pF
5
6
7
8
C9
C2
C3
C4
10uF
10uF
10uF
C5
+
68uF
1
GND
J3
TP7
D1
Q2
BSC123N08NS3G
G
TP6
R6
GND
49.9
S
R19 2.0
9
VCC
C10
C6
R8
4.7uF
1
348k
FB
R9
R10
R12
VOUT
1
1
C12 100pF
VIN
2
C17 +
D
0.1uF
U1
TPS43060RTE
12.1k
0.033uF
HDRV
191k
C1
13
14
EN
R5
47.5k
15
PGOOD
17 16
LDRV
3
AGND
OFF
VIN
2
TP4
TP5
PWPD
EN
357k
ISNS+
1
ISNS-
ON
TP3
J2
S
JP1
Q1
BSC123N08NS3G
100k
D
TP1
R3
G
R1
VIN
VOUT
40V @ 3A
0
0
11.0k
C11
0.1uF
R11
J4
ISNS-
ISNS+
0
1
Not Populated
2
For DCR sensing, open R14 and short R15, R16, R17 and R18. For resistor sensing, open R15.
For Split Rail application, open R11.
VBIAS (OPTIONAL)
Figure 34. High Voltage Synchronous Boost Converter Using TPS43060
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9.2.2.1 Design Requirements
The design requirements and procedure of TPS43061 is also applicable to the TPS43060; however, several
differences should be noted. Unlike the TPS43061, which has a 5.5-V gate drive supply and is optimized for low
Qg NexFETs, the TPS43060 has a 7.5-V gate drive supply and is suitable to drive standard threshold MOSFETs.
The TPS43060 requires an external bootstrap diode (D1 as shown in Figure 34) from VCC to BOOT to charge
the bootstrap capacitor, and the external diode should have a breakdown voltage rating greater than the output
voltage. In addition, the TPS43060 also requires a 2-Ω resistor (R19 shown in Figure 34) connected in series
with the VCC pin to limit the peak current drawn through the internal circuitry when the external bootstrap diode
is conducting.
See Synchronous Boost Converter Typical Application Using TPS43061 for more application details.
9.2.2.2 Detailed Design Procedure
See Synchronous Boost Converter Typical Application Using TPS43061 for more application details.
9.2.2.3 Application Curve
100
Efficiency (%)
95
90
VOUT = 40 V
fsw = 300 kHz
85
80
10 VIN
24 VIN
38 VIN
75
70
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Output Current (A)
5
C001
Figure 35. Efficiency of High Voltage Boost Converter Using TPS43060
32
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SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4.5 and 38 V. This input supply
should be well regulated. It is important to remember a boost topology requires an input current greater than the
output current. The power supply must then be capable of supporting a current approximately equal to IOUT ×
VOUT / (VIN). If the input supply is located more than a few inches from the TPS4306x converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 100 μF is a typical choice.
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of a good power converter design. Several signal paths that conduct fast changing
currents or voltages can interact with stray inductance or parasitic capacitance to generate noise or degrade
performance. Guidelines are as follows, and the EVM layouts can be used as a reference.
• The high-speed switching current path includes the high-side FET, low-side FET, and output capacitors. This
is a critical loop to minimize in order to reduce noise and achieve best performance.
• Components connected to noise-sensitive circuitry should be located as close to the TPS4306x as possible,
and be connected the AGND pin. This includes components connected to FB, COMP, SS, and RT/CLK pins.
• The PowerPAD should be connected to the quiet analog ground for the AGND pin to limit internal noise. For
thermal performance, multiple vias directly under the device should be used to connect to any internal ground
planes.
• Components in the power conversion path should be connected to the PGND. This includes the bulk input
capacitors, output capacitors, low-side FET, and EN UVLO resistors.
• A single connection must connect the quiet AGND to the noisy PGND near the PGND pin.
• The low-ESR ceramic bypass capacitor for the VIN pin should be connected to the quiet AGND as close as
possible to the TPS4306x.
• The distance between the inductor, low-side FET, and high-side FET should be minimized to reduce noise.
This connection is the high-speed switching voltage node.
• The high-side and low-side FETs should be placed close to the device to limit the trace length required for the
HDRV and LDRV gate drive signals.
• The bypass capacitor between the ISNS+ and ISNS– pins should be placed next to the TPS4306x. Minimize
the distance between the device and the sense resistors.
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11.2 Layout Example
PGOOD signal output
To pull up supply voltage
RUVLO_L
RUVLO_H
EN
PGOOD
HDRV
16
15
14
13
PAD (17)
RT/CLK 1
10 VCC
FB 4
RVCC
8
QLS
LDRV
7
VIN
ISNS±
6
ISNS+
5
RSH
9 PGND
TPS43060/1
CSNS
PGND
CVIN
RISNS±
RISNS+
VIN
CVCC
11 BOOT
COMP 3
RSL
DBOOT
12 SW
SS 2
RCOMP
VOUT
COUT
QHS
CBOOT
AGND
CSS
RRT
CHF
CCOMP
AGND
RPGOOD
CIN
RSENSE
L
PGND
NOTE
DBOOT and RVCC are only required if using the TPS43060.
11.3 Thermal Considerations
The TPS4306x junction temperature should not exceed 150°C under normal operating conditions. This restriction
limits the power dissipation of the device. Power dissipation of the controller includes gate drive power loss and
bias power loss of the internal VCC regulator. The TPS4306x is packaged in a thermally-enhanced WQFN
package, which includes a PowerPAD that improves the thermal capabilities. The thermal resistance of the
WQFN package depends on the PCB layout and the PowerPAD connection. As mentioned in the layout
considerations, the PowerPAD must be soldered to the analog ground on the PCB with thermal vias underneath
the PowerPAD to achieve good thermal performance.
For best thermal performance, PCB copper area should be sized to improve thermal capabilities of the
components in the power path dissipating the most power. This includes the sense resistors, inductor, low-side
FET, and high-side FET. Follow the manufacturer guidelines for the selected external FETs.
34
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TPS43060, TPS43061
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SLVSBP4D – DECEMBER 2012 – REVISED SEPTEMBER 2014
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS43060
Click here
Click here
Click here
Click here
Click here
TPS43061
Click here
Click here
Click here
Click here
Click here
12.3 Trademarks
NexFET, PowerPAD are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS43060 TPS43061
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS43060RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
43060
TPS43060RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
43060
TPS43061RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
43061
TPS43061RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
43061
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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