TPS2544RTET

TPS2544 www.ti.com SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 USB Charging Port Controller and Power Switch Check for Samples: TPS2544 FEATURES APPLICATIONS • • • • 1 • • • • • • • • • • • • • D+/D– CDP/DCP Modes per USB Battery Charging Specification 1.2 D+/D– Shorted Mode per Chinese Telecommunication Industry Standard YD/T 1591-2009 Support non-BC1.2 charging modes by automatic selection – D+/D– Divider Modes 2.0V/2.7V and 2.7/2.0V – D+/D- 1.2V Mode Supports Sleep-Mode Charging and Mouse/Keyboard Wake Up Automatic SDP/CDP Switching for devices that do not connect to CDP ports Compatible with USB 2.0 and 3.0 Power Switch requirements Integrated 73-mΩ (typ) High-Side MOSFET Adjustable Current-Limit up to 3.0 A (typ) Operating Range: 4.5V to 5.5V Max device current – 2µA when device disabled – 270µA when device enabled Drop-In and BOM Compatible with TPS2543 and TPS2546 Available in 16-Pin QFN (3x3) Package 8KV ESD rating on DM/DP pins UL Listed and CB File No. E169910 USB Ports (Host and Hubs) Notebook and Desktop PCs Universal Wall Charging Adapters DESCRIPTION The TPS2544 is a USB charging port controller and power switch with an integrated USB 2.0 high-speed data line (D+/D–) switch. TPS2544 provides the electrical signatures on D+/D– to support charging schemes listed under device feature section. TI tests charging of popular mobile phones, tablets and media devices with the TPS2544 to ensure compatibility with both BC1.2 compliant and non-compliant devices. In addition to charging popular devices, TPS2544 also supports system wake up (from S3) with a mouse/keyboard; both low speed and full speed are supported. The TPS2544 73-mΩ power-distribution switch is intended for applications where heavy capacitive loads and short-circuits are likely to be encountered. Two programmable current thresholds provide flexibility for setting current limits. IN ILIM_LO FAULT 16 GND ILIM_HI TPS2544 RTE PACKAGE AND TYPICAL APPLICATION DIAGRAM 15 14 13 1 To Portable Device à Power Bus DM_OUT 2 11 DM_IN DP_OUT 3 10 DP_IN Power Switch EN ILIM_SEL 4 9 NC Mode Select I/O 8 EN CLT1 CLT2 CLT3 Thermal Pad 7 IN OUT CUSB ILIM_LO ILIM_HI TPS2544 OUT Fault Signal 6 0.1 uF RFAULT (10 kW) 12 5 4.5V – 5.5V ILIM Select FAULT ILIM_SEL EN CTL1 CTL2 CTL3 RILIM_HI VBUS DD+ GND RILIM_LO GND DM_IN DP_IN DM_OUT DP_OUT USB Connector To Host Controller à 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS2544 SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) TA PACKAGE DEVICE TOP-SIDE MARKING –40°C to 85°C QFN16 TPS2544 2544 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range, voltages are referenced to GND (unless otherwise noted) LIMIT IN, EN, ILIM_LO, ILIM_HI, FAULT, ILIM_SEL, CTL1, CTL2, CTL3, OUT Voltage range IN to OUT UNIT –0.3 to 7 V –7 to 7 DP_IN, DM_IN, DP_OUT, DM_OUT –0.3 to (IN + 0.3) or 5.7 Input clamp current DP_IN, DM_IN, DP_OUT, DM_OUT ±20 mA Continuous current in SDP or CDP mode DP_IN to DP_OUT or DM_IN to DM_OUT ±100 mA Continuous current in BC1.2 DCP mode DP_IN to DM_IN ±50 mA Continuous output current OUT Continuous output sink current FAULT Continuous output source current ILIM_LO, ILIM_HI ESD rating Internally limited mA Internally limited mA HBM 2 HBM wrt GND and each other, DP_IN, DM_IN, OUT 8 CDM Operating junction temperature, TJ (1) 25 kV 500 V –40 to Internally limited °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION THERMAL METRIC (1) TPS2546 RTE (16 PIN) θJA Junction-to-ambient thermal resistance 53.4 θJCtop Junction-to-case (top) thermal resistance 51.4 θJB Junction-to-board thermal resistance 17.2 ψJT Junction-to-top characterization parameter 3.7 ψJB Junction-to-board characterization parameter 20.7 θJCbot Junction-to-case (bottom) thermal resistance 3.9 (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 TPS2544 www.ti.com SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 RECOMMENDED OPERATING CONDITIONS voltages are referenced to GND (unless otherwise noted) MIN VIN Input voltage, IN NOM MAX UNIT 4.5 5.5 V Input voltage, logic-level inputs, EN, CTL1, CTL2, CTL3, ILIM_SEL 0 5.5 V Input voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT 0 VIN V VIH High-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL 1.8 V VIL Low-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL 0.8 V Continuous current, data line inputs, SDP or CDP mode, DP_IN to DP_OUT, DM_IN to DM_OUT ±30 mA ±15 mA Continuous current, data line inputs, BC1.2 DCP mode, DP_IN to DM_IN IOUT Continuous output current, OUT 0 2.5 A Continuous output sink current, FAULT 0 10 mA RILIM_XX Current-limit set resistors 16.9 750 kΩ TJ Operating virtual junction temperature –40 125 °C ELECTRICAL CHARACTERISTICS Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. R FAULT = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SWITCH RDS(on) On resistance (1) tr OUT voltage rise time tf OUT voltage fall time ton OUT voltage turn-on time toff OUT voltage turn-off time IREV Reverse leakage current TJ = 25°C, IOUT = 2 A 73 84 –40°C ≤ TJ ≤ 85°C, IOUT = 2 A 73 105 –40°C ≤ TJ ≤ 125°C, IOUT = 2 A 73 120 0.7 1.0 1.60 0.2 0.35 0.5 2.7 4 1.7 3 VIN = 5 V, CL = 1 µF, RL = 100 Ω (see Figure 20 and Figure 21) VIN = 5V, CL = 1 µF, RL = 100 Ω (see Figure 20 and Figure 22) VOUT = 5.5 V, VIN = VEN = 0 V, –40 ≤ TJ ≤ 85°C, Measure IOUT mΩ ms ms 2 µA DISCHARGE RDCHG OUT discharge resistance VOUT = 4 V, VEN = 0 V 400 500 630 Ω tDCHG OUT discharge hold time Time VOUT < 0.7 V (see Figure 23) 1.30 2.0 2.9 s (1) Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account separately. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 3 TPS2544 SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. R FAULT = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN, ILIMSEL, CTL1, CTL2, CTL3 INPUTS Input pin rising logic threshold voltage 1 1.35 1.70 Input pin falling logic threshold voltage 0.85 1.15 1.45 Hysteresis (2) Input current 200 Pin voltage = 0 V or 5.5 V –0.5 VILIM_SEL = 0 V, RILIM_LO = 210 kΩ 205 V mV 0.5 µA ILIMSEL CURRENT LIMIT OUT short circuit current limit (3) IOS Response time to OUT shortcircuit (2) tIOS 240 275 625 680 VILIM_SEL = 0 V, RILIM_LO = 80.6 kΩ 575 VILIM_SEL = 0 V, RILIM_LO = 22.1 kΩ 2120 2275 2430 VILIM_SEL = VIN, RILIM_HI= 20 kΩ 2340 2510 2685 VILIM_SEL = VIN, RILIM_HI = 16.9 kΩ 2770 2970 3170 VIN = 5.0 V, R = 0.1Ω, lead length = 2 inches (see Figure 24) 1.5 mA µs SUPPLY CURRENT IIN_OFF IIN_ON Disabled IN supply current Enabled IN supply current VEN = 0 V, VOUT = 0 V, –40 ≤ TJ ≤ 85°C 0.1 2 VCTL1 = VCTL2 = VIN, VCTL3 = 0 V, VILIM_SEL = 0 V 165 220 VCTL1 = VCTL2 = VCTL3 = VIN, VILIM_SEL = 0 V 175 230 VCTL1 = VCTL2 = VIN, VCTL3 = 0V, VILIM_SEL = VIN 185 240 VCTL1 = VCTL2 = VIN, VCTL3 = VIN, VILIM_SEL = VIN 195 250 VCTL1 = 0V, VCTL2 = VCTL3 = VIN 215 270 4.1 4.3 µA µA UNDERVOLTAGE LOCKOUT VUVLO IN rising UVLO threshold voltage 3.9 Hysteresis (2) 100 V mV FAULT Output low voltage I FAULT = 1 mA Off-state leakage V FAULT = 5.5 V Over current FAULT rising and falling deglitch 5 8.2 100 mV 1 µA 12 ms THERMAL SHUTDOWN Thermal shutdown threshold 155 Thermal shutdown threshold in current-limit 135 Hysteresis (2) (3) 4 (2) °C 20 These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty. Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account separately. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 TPS2544 www.ti.com SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 ELECTRICAL CHARACTERISTICS, HIGH-BANDWIDTH SWITCH Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. R FAULT = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HIGH-BANDWIDTH ANALOG SWITCH DP/DM switch on resistance VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA 2 4 VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA 3 6 Switch resistance mismatch between DP / DM channels VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA 0.05 0.15 VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA 0.05 0.15 DP/DM switch off-state capacitance (1) VEN = 0 V, VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk, f = 1 MHz 3 3.6 6.2 DP/DM switch on-state capacitance (2) Ω Ω pF VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk, f = 1 MHz 5.4 OIRR Off-state isolation (3) VEN = 0 V, f = 250 MHz 33 dB XTALK On-state cross channel isolation (3) f = 250 MHz 52 dB Off state leakage current VEN = 0 V, VDP/DM_IN = 3.6 V, VDP/DM_OUT = 0 V, measure IDP/DM_OUT 0.1 BW Bandwidth (–3dB) (3) RL = 50 Ω tpd Propagation delay (3) tSK Skew between opposite transitions of the same port (tPHL – tPLH) (1) (2) (3) 1.5 pF µA 2.6 GHz 0.25 ns 0.1 0.2 ns The resistance in series with the parasitic capacitance to GND is typically 250 Ω. The resistance in series with the parasitic capacitance to GND is typically 150 Ω These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 5 TPS2544 SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS, CHARGING CONTROLLER Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = 0 V, VCTL2 = VCTL3 = VIN. R FAULT = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND. PARAMETER TEST CONDITIONS TYP MAX UNIT 125 200 Ω 1.19 1.25 1.31 V 60 75 94 kΩ DP_IN Divider1 output voltage 1.9 2.0 2.1 V DM_IN Divider1 output voltage 2.57 2.7 2.84 V 8 10.5 12.5 kΩ 8 10.5 12.5 kΩ DP_IN Divider2 output voltage 2.57 2.7 2.84 V DM_IN Divider2 output voltage SHORTED MODE (BC1.2 DCP) MIN VCTL1 = VIN, VCTL2 = VCTL3 = 0V DP_IN / DM_IN shorting resistance 1.2V Mode DP_IN /DM_IN output voltage DP_IN /DM_IN output impedance DIVIDER1 MODE DP_IN output impedance DM_IN output impedance DIVIDER2 MODE IOUT = 1A 1.9 2.0 2.1 V DP_IN output impedance 8 10.5 12.5 kΩ DM_IN output impedance 8 10.5 12.5 kΩ 0.5 0.6 0.7 V 0.4 V CHARGING DOWNSTREAM PORT VCTL1 = VCTL2 = VCTL3 = VIN VDP_IN = 0.6 V, –250 µA < IDM_IN < 0 µA VDM_SRC DM_IN CDP output voltage VDAT_REF DP_IN rising lower window threshold for VDM_SRC activation 0.25 Hysteresis (1) VLGC_SRC 50 DP_IN rising upper window threshold for VDM_SRC de-activation 0.8 hysteresis (1) IDP_SINK (1) 6 DP_IN sink current mV 1 100 VDP_IN = 0.6 V 40 70 V mV 100 µA These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 TPS2544 www.ti.com SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 TYPICAL CHARACTERISTICS POWER SWITCH ON RESISTANCE vs TEMPERATURE REVERSE LEAKAGE CURRENT vs TEMPERATURE 0.3 100 0.25 Reverse Leakage Current (µA) On Resistance (mΩ) 90 80 70 60 0.2 0.15 0.1 0.05 50 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 0 −40 −25 −10 110 125 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 G001 G002 Figure 1. Figure 2. OUT DISCHARGE RESISTANCE vs TEMPERATURE OUT SHORT CIRCUIT CURRENT LIMIT vs TEMPERATURE 580 3000 OUT Short Circuit Current Limit (mA) OUT Discharge Resistance (Ω) 560 3500 VIN = 4.5 V VIN = 5 V VIN = 5.5 V 540 520 500 480 460 −40 −25 −10 2500 2000 1500 RILIM_LO = 210 kΩ RILIM_LO = 80.6 kΩ RILIM_HI = 20 kΩ RILIM_HI = 16.9 kΩ 1000 500 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 0 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 G003 Figure 3. G004 Figure 4. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 7 TPS2544 SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) DISABLED IN SUPPLY CURRENT vs TEMPERATURE ENABLED IN SUPPLY CURRENT - SDP vs TEMPERATURE 1.2 190 VIN = 5.5 V 180 Enabled IN Supply Current (µA) Disabled IN Supply Current (µA) 1 0.8 0.6 0.4 0.2 0 −40 VIN = 4.5 V VIN = 5 V VIN = 5.5 V 170 160 150 Device configured for SDP VILIMSEL = 0 V 140 −20 0 20 40 60 Junction Temperature (°C) 80 130 −40 −25 −10 100 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 G005 G006 Figure 5. Figure 6. ENABLED IN SUPPLY CURRENT - CDP vs TEMPERATURE ENABLED IN SUPPLY CURRENT - DCP AUTO vs TEMPERATURE 220 230 Enabled IN Supply Current (µA) Enabled IN Supply Current (µA) 210 240 VIN = 4.5 V VIN = 5 V VIN = 5.5 V 200 190 180 170 VIN = 4.5 V VIN = 5 V VIN = 5.5 V 220 210 200 190 Device configured for CDP 160 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 Device configured for DCP AUTO 110 125 180 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) G007 Figure 7. 8 95 110 125 G008 Figure 8. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 TPS2544 www.ti.com SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 TYPICAL CHARACTERISTICS (continued) FAULT OUTPUT LOW VOLTAGE vs SINKING CURRENT DATA TRANSMISSION CHARACTERISTICS vs FREQUENCY 0 700 TJ = −40°C TJ = 25°C TJ = 125°C 600 500 Transmission Gain - dB Output Low Voltage (mV) -5 400 300 200 -10 -15 -20 100 VIN = 4.5 V 0 0 1 2 3 4 5 6 7 Sinking Current (mA) 8 9 10 -20 0.01 G009 1 10 Frequency - GHz Figure 10. Figure 9. OFF STATE DATA SWITCH ISOLATION vs FREQUENCY ON STATE CROSS-CHANNEL ISOLATION vs FREQUENCY 60 XTALK - ON State Cross-Channel Isolation - dB 80 50 OIRR - Off State Isolation - dB 0.1 40 30 20 10 70 60 50 40 30 20 10 0 0 0.01 0.1 1 10 0.01 0.1 1 10 Frequency - GHz Figure 12. Frequency - GHz Figure 11. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 9 TPS2544 SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) EYE DIAGRAM USING USB COMPLIANCE TEST PATTERN (with data switch) 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 Differential Signal (V) Differential Signal (V) EYE DIAGRAM USING USB COMPLIANCE TEST PATTERN (with no switch) 0.1 0 –0.1 –0.2 0.1 0 –0.1 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 0.2 0.4 0.6 0.8 1 1.2 Time (ns) 1.4 1.6 1.8 0 2 G013 0.4 0.6 0.8 1 1.2 Time (ns) 1.4 1.6 1.8 2 G014 Figure 13. Figure 14. TURN-ON RESPONSE TURN-OFF RESPONSE VOUT 2 V/div VOUT 2 V/div VEN 5 V/div VEN 5 V/div RLOAD = 5 Ω CLOAD = 150 µF RLOAD = 5 Ω CLOAD = 150 µF IIN 500 mA/div t - Time - 1 ms/div Figure 15. 10 0.2 IIN 500 mA/div G021 Submit Documentation Feedback t - Time - 1 ms/div Figure 16. G022 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 TPS2544 www.ti.com SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 TYPICAL CHARACTERISTICS (continued) DEVICE ENABLED INTO SHORT CIRCUIT - THERMAL CYCLING DEVICE ENABLED INTO SHORT CIRCUIT V/FAULT 5 V/div V/FAULT 5 V/div VEN 5 V/div VEN 5 V/div RILM_LO = 80.6 kΩ IIN 500 mA/div t - Time - 2 ms/div Figure 17. RILM_HI = 20 kΩ IIN 1 A/div t - Time - 5 ms/div Figure 18. G023 G024 SHORT CIRCUIT to FULL LOAD RECOVERY V/FAULT 5 V/div VOUT 2 V/div RILIM_HI = 20 kΩ RLOAD = 5 Ω CLOAD = 150 µF IIN 2 A/div t - Time - 2 ms/div Figure 19. G025 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 11 TPS2544 SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com PARAMETER MEASUREMENT DESCRIPTION OUT RL VOUT CL tr tf 90% 10% Figure 20. OUT Rise/Fall Test Load Figure 21. Power-On and Off Timing 5V VEN 50 % 50 % tDCHG VOUT ton toff 0V 90 % VOUT 10 % Figure 22. Enable Timing, Active High Enable Figure 23. OUT Discharge During Mode Change IOS IOUT tIOS Figure 24. Output Short Circuit Parameters 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 TPS2544 www.ti.com SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 DEVICE INFORMATION IN 1 DM_OUT 2 ILIM_HI ILIM_LO GND FAULT TPS2544 RTE PACKAGE (Top View) 16 15 14 13 12 OUT 11 DM_IN DP_IN Thermal Pad ILIM_SEL 4 9 6 7 NC 8 CLT3 5 CLT2 10 CLT1 3 EN DP_OUT PIN FUNCTIONS NO. (1) NAME TYPE (1) P DESCRIPTION Input voltage and supply voltage; connect 0.1 μF or greater ceramic capacitor from IN to GND as close to the device as possible 1 IN 2 DM_OUT I/O D– data line to USB host controller 3 DP_OUT I/O D+ data line to USB host controller 4 ILIM_SEL I Logic-level input signal used to control the charging mode current limit threshold; see the control truth table. Can be tied directly to IN or GND without pull-up or pull-down resistor. 5 EN I Logic-level input for turning the power switch and the signal switches on/off; logic low turns off the signal and power switches and holds OUT in discharge. Can be tied directly to IN or GND without pull-up or pull-down resistor. 6 CTL1 I 7 CTL2 I 8 CTL3 9 - N/C Connect to GND or leave open 10 DP_IN I/O D+ data line to downstream connector 11 DM_IN I/O D– data line to downstream connector 12 OUT P Power-switch output 13 FAULT O Active-low open-drain output, asserted during over-temperature or current limit conditions 14 GND P Ground connection 15 ILIM_LO I External resistor connection used to set the low current-limit threshold. A resistor to ILIM_LO is optional; see Current-Limit Settings in DETAILED DESCRIPTION. 16 ILIM_HI I External resistor connection used to set the high current-limit threshold NA PowerPAD Logic-level inputs used to control the charging mode and the signal switches; see the control truth table. Can be tied directly to IN or GND without pull-up or pull-down resistor. I Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect to GND plane. G = Ground, I = Input, O = Output, P = Power, N/C = No Connect Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 13 TPS2544 SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com TPS2544 FUNCTIONAL BLOCK DIAGRAM Current Sense CS IN OUT Disable + UVLO+Discharge ILIM_HI Current Limit Current Limit select Charge Pump ILIM_LO GND OC 8-ms Deglitch OTSD Thermal Sense UVLO ILIM_SEL Driver EN discharge FAULT 8-ms Deglitch (falling edge) DM_OUT DM_IN DP_OUT DP_IN ILIM_SEL OC CTL1 CTL2 Logic control CDP Detection DCP Detection Divider Mode Auto-Detection Discharge CTL3 Discharge 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 TPS2544 www.ti.com SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 DETAILED DESCRIPTION Overview The following overview references various industry standards. It is always recommended to consult the most upto-date standard to ensure the most recent and accurate information. Rechargeable portable equipment requires an external power source to charge its batteries. USB ports are a convenient location for charging because of an available 5V power source. Universally accepted standards are required to make sure host and client-side devices operate together in a system to ensure power management requirements are met. Traditionally, host ports following the USB 2.0 specification must provide at least 500mA to downstream client-side devices. Because multiple USB devices can be attached to a single USB port through a bus-powered hub, it is the responsibility of the client-side device to negotiate its power allotment from the host to ensure the total current draw does not exceed 500mA. In general, each USB device is granted 100mA and may request more current in 100mA unit steps up to 500mA. The host may grant or deny based on the available current. A USB 3.0 host port not only provides higher data rate than USB 2.0 port but also raises the unit load from 100mA to 150mA. It is also required to provide a minimum current of 900mA to downstream client-side devices. Additionally, the success of USB has made the mini-USB connector a popular choice for wall adapter cables. This allows a portable device to charge from both a wall adapter and USB port with only one connector. As USB charging has gained popularity, the 500mA minimum defined by USB 2.0 or 900mA for USB 3.0 has become insufficient for many handset and personal media players which need a higher charging rate. Wall adapters can provide much more current than 500mA/900mA. Several new standards have been introduced defining protocol handshaking methods that allow host and client devices to acknowledge and draw additional current beyond the 500mA/900mA minimum defined by USB 2.0/3.0 while still using a single micro-USB input connector. The TPS2544 supports four of the most common USB charging schemes found in popular hand-held media and cellular devices: • USB Battery Charging Specification BC1.2 • Chinese Telecommunications Industry Standard YD/T 1591-2009 • Divider Mode • 1.2V Mode YD/T 1591-2009 is a subset of BC1.2 spec. supported by vast majority of devices that implement USB changing. Divider and 1.2V charging schemes are supported in devices from specific yet popular device makers. BC1.2 lists three different port types as listed below. • Standard Downstream Port (SDP) • Charging Downstream Port (CDP) • Dedicated Charging Port (DCP) BC1.2 defines a charging port as a downstream facing USB port that provides power for charging portable equipment, under this definition CDP and DCP are defined as charging ports Table 1 shows the differences between these ports. Table 1. Operating Modes PORT TYPE SUPPORT USB 2.0 COMMUNICATION MAX. ALLOWABLE CURRENT DRAW BY PORTABLE DEVICE (A) SDP (USB 2.0) Yes 0.5 SDP (USB 3.0) Yes 0.9 CDP Yes 1.5 DCP No 1.5 Standard Downstream Port (SDP) USB 2.0/USB 3.0 An SDP is a traditional USB port that follows USB 2.0/3.0 protocol and supplies a minimum of 500mA/900mA per port. USB 2.0/3.0 communications is supported, and the host controller must be active to allow charging. TPS2544 supports SDP mode in system power state S0 when system is completely powered ON and fully operational. For more details on control pin (CTL1-CTL3) settings to program this state please refer to device truth table. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2544 15 TPS2544 SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013 www.ti.com Charging Downstream Port (CDP) A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5A per port. It provides power and meets USB 2.0 requirements for device enumeration. USB 2.0 communications is supported, and the host controller must be active to allow charging. What separates a CDP from an SDP is the host-charge handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and allows for additional current draw by the client device. The CDP hand-shaking process is done in two steps. During step one the portable equipment outputs a nominal 0.6V output on its D+ line and reads the voltage input on its D- line. The portable device concludes it is connected to an SDP if the voltage is less than the nominal data detect voltage of 0.3V. The portable device concludes that it is connected to a Charging Port if the D- voltage is greater than the nominal data detect voltage of 0.3V and optionally less than 0.8V. The second step is necessary for portable equipment to determine if it is connected to CDP or DCP. The portable device outputs a nominal 0.6V output on its D- line and reads the voltage input on its D+ line. The portable device concludes it is connected to a CDP if the data line being read remains less than the nominal data detect voltage of 0.3V. The portable device concludes it is connected to a DCP if the data line being read is greater than the nominal data detect voltage of 0.3V. TPS2544 supports CDP mode in system power state S0 when system is completely powered ON and fully operational. For more details on control pin (CTL1-CTL3) settings to program this state please refer to device truth table. Dedicated Charging Port (DCP) A DCP only provides power but does not support data connection to an upstream port. As shown in following sections, a DCP is identified by the electrical characteristics of its data lines. The TPS2544 emulates DCP in two charging states, namely DCP Forced and DCP Auto as shown in Figure 32. In DCP Forced state the device will support one of the two DCP charging schemes, namely Divider1 or Shorted. In the DCP Auto state, the device charge detection state machine is activated to selectively implement charging schemes involved with the Shorted, Divider1, Divider2, and 1.2V modes. Shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009, while the Divider and 1.2V modes are employed to charge devices that do not comply with BC1.2 DCP standard. DCP BC1.2 and YD/T 1591-2009 Both standards define that the D+ and D- data lines should be shorted together with a maximum series impedance of 200 Ω. This is shown in Figure 25. TPS2546 D- Out D1.2V 2.7V CDP Detect Auto Detect D+ USB Connector 2.0V