TC78B009FTG,EL

TC78B009FTG CDMOS Linear Integrated Circuit Silicon Monolithic TC78B009FTG Sensorless PWM predriver for 3-phase brushless motor 1. Outline The TC78B009FTG is a 3-phase PWM chopper predriver for sensorless brushless motor. Motor speed can be controlled by selecting among the PWM duty cycle, analog voltage, and I2C. Non-volatile memory (NVM) is implemented and it can set according to the motors and directions for use. It also realizes closed loop speed control function without an external microcomputer. TC78B009FTG is used with six external MOSFETs inverter to drive sensorless brushless motors of which output range is wide. P-WQFN36-0505-0.50-001 Weight: 0.06 g (typ.) 2. Applications Fan, Pump, Portable Vacuum motors 3. Features ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Sensorless PWM drive Capable to drive Delta or Wye configured motors Operating voltage: 5.5 to 27V (absolute maximum rating: 30V) Predriver for high side and low side N-ch MOSFETs drive 8 selectable levels of gate drive current Built-in closed loop speed control with adjustable speed curve Motor speed control by analog voltage, PWM duty cycle, or I2C Serial interface (I2C) for various settings Standby mode (by STBY pin) Current monitor output (PHBF pin) CW/CCW control (CWCCW pin) Brake input pin (BRAKE pin) Rotation speed output (FG pin) Abnormality detection output (ALERT pin) Thermal shutdown (TSD) Under voltage lockout (UVLO) Charge pump low voltage detection (CPVSD) Output current limit (OCP) Over current detection (ISD) Lock protection Small QFN36 package © 2019-2021 Toshiba Electronic Devices & Storage Corporation 1 2021-09-17 TC78B009FTG 4. Block Diagram I2C Note: Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. Figure 4.1 Block Diagram 2 2021-09-17 TC78B009FTG 5. Pin assignment CWCCW SEL VREG NC VM VCP CPP CPM NC 27 26 25 24 23 22 21 20 19 BRAKE 28 18 GHW STBY 29 17 OUTW SPD 30 16 GLW SCL 31 15 GHV (Top View) SDA 32 14 OUTV ID1 33 13 GLV ID2 34 12 GHU 11 FG 35 ALERT OUTU 10 GLU 36 6 7 8 9 RSB RSA NC 5 RSG PH 4 GND PHBF 3 TESTI 2 TESTO 1 Figure 5.1 Pin assignment 3 2021-09-17 TC78B009FTG 6. Pin Description Table 6.1 Pin description Pin No. Pin name 1 PHBF 2 Input / output Pin description OUT Output pin for output current monitor PH — Peak hold setting pin 3 TESTO — TEST output pin 4 TESTI — TEST pin 5 GND — GND pin 6 RSG — Connection pin for shunt resistor at GND side 7 RSB IN Input pin for output current monitor 8 RSA IN Input pin for output current control — Non connection pin OUT Output pin for U-phase low side FET gate drive IN Input pin for U-phase motor connection 9 NC 10 GLU 11 OUTU 12 GHU OUT Output pin for U-phase high side FET gate drive 13 GLV OUT Output pin for V-phase low side FET gate drive 14 OUTV IN Input pin for V-phase motor connection 15 GHV OUT Output pin for V-phase high side FET gate drive 16 GLW OUT Output pin for W-phase low side FET gate drive 17 OUTW IN Input pin for W-phase motor connection 18 GHW OUT Output pin for W-phase high side FET gate drive 19 NC — Non connection pin 20 CPM — Connection pin for a capacitor to pump up at negative side of charge pump 21 CPP — Connection pin for a capacitor to pump up at positive side of charge pump 22 VCP — Connection pin for a capacitor of charge pump accumulation 23 VM — Power supply pin 24 NC — Non connection pin 25 VREG — Output pin for 5V reference voltage 26 SEL IN Input pin for selecting speed control command 27 CWCCW IN Input pin for selecting rotation direction 28 BRAKE IN Brake input pin 29 STBY IN Standby input pin 30 SPD IN Input pin for speed control command 31 SCL IO Clock line pin for I2C communication 32 SDA IO Data line pin for I2C communication 33 ID1 IN Input pin for slave address setting 1 34 ID2 IN Input pin for slave address setting 2 35 FG OUT Output pin for rotation speed 36 ALERT OUT Output pin for abnormality detection 4 2021-09-17 TC78B009FTG 7. I/O Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. Remarks I/O internal circuit CWCCW BRAKE Connect to GND when unused. SEL ID1 ID2 STBY Connect to High voltage when unused. 200 kΩ STBY CWCCW BRAKE SEL ID1 ID2 50 kΩ Pin symbol SPD SPD Connect to GND when unused. SCL . When I2C communication is unused, the voltage of SCL pin should be stable voltage, high or low (GND). SDA ALERT FG SCL SDA When I2C communication is unused, the voltage of SDA pin should be stable voltage, high or low (GND). ALERT FG Connect a pull-up resistor. It should be open when unused. 5 2021-09-17 TC78B009FTG Pin symbol Remarks I/O internal circuit VREG VREG VREG PH RSB RSG Connecting a 100 kΩ resistor and 0.1μF capacitor between GND and PH is recommended. Connect RSG and RSB to GND when unused. The PH should be open when unused. RSB PH RSG VREG PHBF VREG Connect a resistor and a capacitor of low pass filter to PHBF, in consideration with ripple voltage. PHBF should be open when unused. PHBF VREG VREG RSA RSG RSA Connect RSA and RSG to GND when unused. VREG RSG 8V — 200 kΩ GLU GLV GLW VM 6 GLU GLV GLW 2021-09-17 TC78B009FTG Remarks I/O internal circuit VCP VCP VCP GHU GHV GHW VCP VCP VCP — OUTU OUTV OUTW 16kΩ VCP VCP GHV OUTW 200 kΩ 200 kΩ GHW VCP GHU 200 kΩ Pin symbol OUTV 16kΩ OUTU 16kΩ VM VREG Connecting 0.1μF capacitor between GNDs is recommended. VREG VCP TESTI VM CPM TESTI should be used connecting to GND. TESTI 50 kΩ VCP CPP CPM CPP Connecting 0.1μF capacitor between VCP and VM is recommended. Connecting 0.01μF capacitor between CPP and CPM is recommended. VREG TESTO TESTO should be used connecting to GND. TESTO 7 2021-09-17 TC78B009FTG 8. Functional Description 8.1. Basic Operation This IC can drive a 3-phase brushless motor without hall sensors. Non-volatile memory (NVM) is implemented and it can set according to the motors and directions for use. It also realizes closed loop speed control function without an external microcomputer. Standby mode is available to reduce the power consumption during idling. After power-on, if STBY pin is disabled, IC reads parameters from NVM and stores them to the registers. After that, IC goes to brake sequence and moves to idle mode. When speed control command is set, IC starts the motor by startup sequence. When speed control command is stopped, IC stops the motor. When abnormal condition is detected, IC moves to error mode, and restart after restart time automatically. In error mode, if speed control command is stop, IC will move to idle mode. Power ON Yes 3.5ms(typ.) STBY=ON Standby mode No Read NVM STBY=OFF STBY=ON Brake sequence BRAKE=OFF & Speed control=OFF BRAKE=ON Restart time Idle mode Speed control=ON Speed control=OFF ISD/TSD/CPVSD Startup sequence Error mode No Brake mode (BRAKE pin) BRAKE=OFF& Speed control=ON BRAKE=ON Free run? Yes Reversed? No Yes DC excitation Speed control=OFF BRAKE=ON STARTUP FAIL Force commutation Speed control=OFF FMIN/FMAX BRAKE=ON FMIN/FMAX BRAKE=ON Sensorless Soft start current limit Speed control=OFF Sensorless Normal current limit Speed control=OFF Figure 8.1 Flowchart of basic operation 8 2021-09-17 TC78B009FTG Standby Mode The standby mode can be enabled by STBY pin. In the standby mode, each output pin turns OFF (Hi-Z state), and each error state is cleared. To move to the standby mode, the conditions are changed by the register settings, STBY_MODE, in case of STBY pin is "Low" only, or in case of both STBY pin =Low and speed control command =0. Also, when the normal operation state is moved to the standby mode, the standby mode condition is required 100 ms or more. Table 8.1 Conditions to move to standby mode STBY pin Register setting 14[7] STBY_MODE Standby mode condition State 0 Moves to standby mode only if STBY pin is set to Low. Standby mode 1 Moves to standby mode under the conditions: STBY pin is set to Low and the speed control command is input to 0. (When MAXOFF=1, NOSTOP=1, or SPDINV=1 in the register settings, the mode cannot move to the standby mode.) Standby mode ― ― Low High Normal operation Brake sequence The period and function of brake sequence are set by register. The external FET states can be set by register. Table 8.2 Period setting of Brake sequence Register setting 19[7:5] WAIT_TIME Period of brake sequence (s) 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Table 8.3 External FET state setting of Brake sequence Register setting 19[4] WAIT_MODE Status of external FET 0 OFF(Hi-Z) 1 Short brake 9 2021-09-17 TC78B009FTG Table 8.4 State after Brake sequence Register setting 19[3] WAIT_CON State 0 After period of brake sequence, the external FET state of WAIT_MODE is released, and is moved to idle mode. 1 After period of brake sequence, the brake sequence of the external FET state of WAIT_MODE is held. After the speed control command, the sequence moves to startup sequence without moving via idle mode. (Disable at period of brake sequence = 0s) Idle mode When the speed control command stops during normal rotation or error stop mode, IC moves to idle mode. In idle mode, all external FETs are turned off. When the speed control command is detected, IC moves to the startup sequence. Startup sequence After speed control command is set, if motor is stopped or rotating in reverse direction, IC moves to sensorless step to drive motor through 1st DC excitation, 2nd DC excitation and forced commutation steps. The periods of 1st and 2nd DC excitations, and the forced commutation frequency can be set individually. After setting the speed control command, if the motor is idling in the forward direction, the IC moves to sensorless step directly. The minimum frequency at which the idling of the motor can be detected depends on the forced commutation frequency. Table 8.5 Period of 1st DC excitation Register setting 20[4:3] PreTIP Period of 1st DC excitation (s) 00 0 01 0.2 10 0.5 11 1.0 Table 8.6 Period of 2nd DC excitation Register setting 20[2:0] TIP Period of 2nd DC excitation (s) 000 0.1 001 0.2 010 0.4 011 0.6 100 0.8 101 1 110 1.5 111 2 10 2021-09-17 TC78B009FTG Table 8.7 Forced commutation frequency Register setting 21[1:0] FST Electrical angle frequency Idling detection time 00 1.6Hz 200ms (5Hz) 01 3.2Hz 100ms (10Hz) 10 6.4Hz 50ms (20Hz) 11 12.8Hz 25ms (40Hz) (electrical angle frequency) Table 8.8 Hysteresis voltage of position detection comparator in case of idling detection Register setting 24[7:6] COMP_HYS Hysteresis voltage 00 None 01 ±100mV 10 ±200mV 11 ±300mV Output current limit (OCP) The IC has an output current limit function to restrain the current flowing to the motor. Motor current is detected by external shunt resistor and the detected voltage is inputted to RSA pin. When the voltage of RSA pin reaches or exceeds the output current limit circuit threshold voltage VOC, IC turns off the high side of external FETs to limit the motor current. The limitation is released in every PWM cycle. Output current limit [A] = VOC/ resistance of shunt resistor Output current limit moves from a startup current limit to a normal current limit after moving to sensorless step. Additionally, the output current limit function has digital noise filter and analog noise filter to avoid malfunction by noises. Table 8.9 Normal current limit (VOC) setting Register setting 23[6] OCP_LVL Threshold of current limitation (VOC) Gain of internal amplifier 0 0.25V 10x 1 0.125V 20x ･ VOC value changes with an amplifier gain of output current monitor function. Table 8.10 Startup current limit setting Register setting 16[3:1] STARTCURRENT Startup current VOC Voltage (V) 000 VOC 001 VOC×87.5% 010 VOC×75.0% 011 VOC×62.5% 100 VOC×50.0% 101 VOC×37.5% 110 VOC×25.0% 111 VOC×12.5% 11 2021-09-17 TC78B009FTG Table 8.11 Digital filter (OCP, ISD) period setting Register setting 15[1:0] OCPMASK Number of OCP CLK 00 OCP Filter time Number of ISD CLK ISD filter time 0 None 1 83 ns 01 4 500 ns 5 583 ns 10 6 666 ns 7 750 ns 11 7 750 ns 8 833 ns ･ OCP filter time changes with ISD fiter time. Table 8.12 Analog filter setting of RSA pin Register setting 18[2:1] RS_SEL Cutoff frequency 00 None 01 200kHz 10 100kHz 11 50kHz Table 8.13 Enable/Disable setting of OCP function Register setting 16[0] OCPDIS OCP function 0 Enable 1 Disable 12 2021-09-17 TC78B009FTG Soft Start The startup sequence operates with a soft start to prevent rush current. Soft start increases the output duty gradually from 0 % until the output current reaches the startup current. If the speed control limitation is enabled, increasing speed of Duty is according to the register setting of the soft start duty change limitation. If the speed control limitation is disabled, increasing speed of Duty at soft start is limited to 8counts/2.7ms. After moving to sensorless step, startup current limit moves to normal current limit. The moving acceleration rises by the current value determined by SS_UP_SEL every 350 ms to the current value set by a SS_ADD_SEL register after the Wait time progresses for 0 to 699 ms. However, when SS_ADD_SEL current value exceeds an output current limit, it does not exceed the output current limit value, and the output current limit value is the setting value. If the motor is idling, the motor starts to rotate with sensorless (Normal current limit) step, without moving to startup sequence. The initial output Duty in this rotation depends on the max speed setting. Figure 8.2 Output current limit setting at startup 13 2021-09-17 TC78B009FTG Table 8.14 Soft start duty change limit setting Soft start duty change limit Register setting 17[3:1] SS_DUTYCHGLIMIT Duty change for every 2.7ms (Δ/512) Speed control time (s) 0% to 100% 000 64/8 0.17 001 2/8 5.53 010 3/8 3.69 011 4/8 2.76 100 6/8 1.84 101 10/8 1.11 110 20/8 0.55 111 56/8 0.20 Table 8.15 SS_ADD_SEL register setting Register setting 17[7:6] SS_ADD_SEL SS_ADD_SEL current (A) Startup current limit setting value + {(Reference voltage Voc of output current limit circuit / shunt resistor)×0%} (=Startup current limit setting value) Startup current limit setting value + {(Reference voltage Voc of output current limit circuit / shunt resistor)×30%} Startup current limit setting value + {(Reference voltage Voc of output current limit circuit / shunt resistor)×40%} Startup current limit setting value + {(Reference voltage Voc of output current limit circuit / shunt resistor)×50%} 00 01 10 11 Table 8.16 SS_UP_SEL register setting Register setting 17[5:4] SS_UP_SEL SS_UP_SEL current (A) 00 01 10 11 (Reference voltage Voc of output current limit circuit / shunt resistor)×1% (Reference voltage Voc of output current limit circuit / shunt resistor)×2% (Reference voltage Voc of output current limit circuit / shunt resistor)×5% (Reference voltage Voc of output current limit circuit / shunt resistor)×10% Table 8.17 When the motor rotates from idling state, initial output Duty is settled by max speed setting Register setting 14[2:1] MAXSPEED • Max speed setting(rpm) 0 0 4096 0 1 8192 1 0 16384 1 1 32768 When the motor rotates from idling state, initial output Duty is settled by max speed setting (MAXSPEED). Initial output Duty = Detected rotation count / max speed / 2 Example: In case of setting to MAXSPEED= 1,0, the max speed is 16384 rpm. When 3000-rpm rotation is detected at startup, the initial output Duty is 3000 / 16384/ 2 =9.2%. 14 2021-09-17 TC78B009FTG Speed control In sensorless step, motor speed is controlled by limiting the output Duty change. The speed control is set with Duty change limit and Duty up time. Table 8.18 Register setting of Duty up time Register setting 17[0] DUTY_UP_TIME Duty up time 2.7ms 0 1 10.8ms Table 8.19 Register setting of Duty change limit Register setting 16[6:4] DUTYCHGLIMIT Duty change (Δ/512) Speed control time (s) at 2.7-ms Duty up time 0% to 100% 000 Disable: Open loop 64/8: Closed loop 0.17 2/8 5.53 3/8 3.69 4/8 2.76 6/8 1.84 10/8 1.11 20/8 0.55 56/8 0.20 001 010 011 100 101 110 111 Table 8.20 Setting description of speed control During Closed loop Item DC excitation to Forced commutation Acceleration Up timing 2.7ms 10.8ms/2.7ms Increasing and decreasing of Duty Soft start duty change limit Duty change limit Stability Slow 2.7ms PI control (Duty change limit is enabled.) During Open loop 10.8ms/2.7ms Duty change limit 102/512 Target output duty 100/512 Internal triangle wave Output duty: 100/512 (Internal duty: 100/512) 100/512 (100.375/512) 100/512 (100.75/512) 101/512 (101.125/512) 101/512 (101.5/512) 101/512 (101.875)/512 102/512 (102/512) Output duty 2.7ms 2.7ms 2.7ms 2.7ms 2.7ms Figure 8.3 Example of output Duty change timing at Duty change amount (3/8): Duty change limit = 010 15 2021-09-17 TC78B009FTG Current monitor output (PHBF) The motor’s output current can be monitored from the PHBF pin by amplifying the RSB pin voltage detected by the external shunt resistor and converting it to a DC level with peak hold circuit. The constant C1 for peak hold of the PH pin is 0.1 µF, and R2 is 100kΩ. In consideration with ripple voltage of PHBF pin, low pass filter C2 and R3 should be connected. Table 8.21 Output current monitor function Register setting 23[6] OCP_LVL Threshold of current limitation (VOC) Gain of internal amplifier 0 0.25V 10x 1 0.125V 20x ∙The gain of the internal amplifier is corresponding to VOC. (Table 8.21 is same as Table 8.9.) R3 C2 Amplifier:10x 20x R1 R2 C1 Low pass filter output PH pin Amplifier output RSB pin Figure 8.4 Output current monitor function 16 2021-09-17 TC78B009FTG Commutation Method and Lead Angle Control The commutation angle and lead angle are controlled by register setting. The commutation angle can be selected among 120°, 135°, 142.5°, and 150°. Also, when a soft switching is selected, Duty changes gradually at switching commutation. According to the motor characteristics, the efficiency and noise are changed by adjustment of each commutation method and lead angle setting. Additionally, the lead angle setting has a limitation. In case of 120° commutation, the lead angle can be set from 0° to 30°. But in case of 135° commutation, the lead angle setting is from 0° to 22.5°, so that the setting more than 22.5° is also 22.5°. In case of 142.5° and 150° commutations, the lead angle setting is from 0° to 15°, so that the setting more than 15° is also 15°. Table 8.22 Commutation method setting Register setting 22 [7] SLOP Register setting 22[6:5] LAP 0 Soft switching Commutation angle 00 No 120° 01 Yes 135° 10 Yes 150° 11 Yes 142.5° 00 120° 01 1 135° No 10 150° 11 150° Table 8.23 Lead angle setting Register setting 21[1:0] FST Register setting 21[7:4] LA Rotation speed (electrical angle) Speed up 00 Speed down Speed up 01 10 11 Speed down 0Hz < f ≤ 100Hz 0Hz < f ≤50Hz 100Hz < f ≤ 200Hz 50Hz < f ≤ 150Hz 200Hz < f ≤ 300Hz 150 Hz < f ≤ 250Hz 300Hz < f ≤ 400Hz 250 Hz < f ≤ 350Hz 400Hz < f ≤ 500Hz 350 Hz < f ≤ 450Hz 0Hz < f ≤200Hz 0Hz < f ≤100Hz 200Hz < f ≤ 400Hz 100Hz < f ≤ 300Hz 400 Hz < f ≤ 600Hz 300 Hz < f ≤ 500Hz 600 Hz < f ≤ 800Hz 500 Hz < f ≤ 700Hz 800 Hz < f ≤ 1kHz 700 Hz < f ≤ 900Hz 500Hz < f 450Hz < f 1kHz < f 900Hz < f 0000 0 0° 0001 0010 1 2 3.75° 7.5° 0011 0100 3 4 11.25° 15° 0101 0110 5 6 18.75° 22.5° 0111 1000 7 8 26.25° 30° 1001 1010 9 10 7.5° 7.5° 15° 7.5° 15° 15° 15° 15° 18.75° 18.75° 22.5° 22.5° 1011 1100 11 12 0° 3.75° 3.75° 7.5° 7.5° 11.25° 11.25° 15° 15° 18.75° 18.75° 22.5° 1101 1110 13 14 7.5° 11.25° 11.25° 15° 15° 18.75° 18.75° 22.5° 22.5° 26.25° 26.25° 30° 1111 15 3.75° 11.25° 18.75° 26.25° 30° 30° 17 2021-09-17 TC78B009FTG 120°commutation U V W U V W Induced voltage 1. (0°lead angle) 30° U V W 2. (15°lead angle) 15° U V W 3. (30°lead angle) 0° U V W 135°commutation Induced voltage 4. (0°lead angle) 22.5° U V W 5. (15°lead angle) 7.5° U V W 6. (22.5°lead angle) 0° U V W OFF (Hi-Z) term 18 2021-09-17 TC78B009FTG 150°commutation U Induced voltage 7. (0°Lead angle) V W 15° U V W 8. (7.5°Lead angle) 7.5° U V W 9. (15°Lead angle) 0° U V W OFF (Hi-Z) term 135°commutation, soft switching,0°Lead angle U Induced voltage V 7.5° W 7.5° U V W OFF (Hi-Z) term Soft switching term 150°commutation, soft switching,0°Lead angle U Induced voltage 15° V W 15° U V W OFF (Hi-Z) term Soft switching term Figure 8.5 Timing chart of commutation waveform 19 2021-09-17 TC78B009FTG Rotation Direction The rotation direction is determined by CWCCW pin and register setting. Table 8.24 Rotation direction setting Register setting 14[6] DIR Register setting state 0 Polarity reversal disable 1 Polarity reversal enable CWCCW pin Direction Low CW High CCW Low CCW High CW Brake Function The short brake mode can be set by BRAKE pin and register setting. Table 8.25 Brake function BRAKE pin Register setting 18[4] BRK_INV Register setting description State 1 Polarity reversal enable (Low Active) Short brake mode 0 Polarity reversal disable (High Active) ― 1 Polarity reversal enable (Low Active) ― 0 Polarity reversal disable (High Active) Short brake mode Low High 20 2021-09-17 TC78B009FTG PWM Frequency The output PWM frequency of output is generated by dividing the IC internal clock. Table 8.26 Output PWM frequency corresponding to dividing Dividing Output PWM frequency 512 256 128 64 23.4 kHz 46.9 kHz 93.7 kHz 187.5 kHz Table 8.27 Output PWM frequency setting Rotation speed (electrical angle) Register setting 22[4:2] FPWM Speed up 0Hz < f ≤ 200Hz 200Hz < f ≤ 400Hz 400Hz < f ≤ 600Hz 600Hz < f ≤ 800Hz 800Hz < f ≤ 1000Hz 1000Hz < f Speed down 0Hz < f ≤ 100Hz 100Hz < f ≤ 300Hz 300Hz < f ≤ 500Hz 500Hz < f ≤ 700Hz 700Hz < f ≤ 900Hz 900Hz < f 000 0 23.4kHz 001 1 46.9kHz 010 2 93.7kHz 011 3 187.5kHz 100 4 46.9kHz 46.9kHz 93.7kHz 93.7kHz 93.7kHz 187.5kHz 101 5 23.4kHz 46.9kHz 93.7kHz 93.7kHz 93.7kHz 93.7kHz 110 6 23.4kHz 23.4kHz 46.9kHz 46.9kHz 93.7kHz 93.7kHz 111 7 23.4kHz 46.9kHz 93.7kHz 93.7kHz 187.5kHz 187.5kHz 21 2021-09-17 TC78B009FTG External FET Gate Drive Output The external FET gate drive signal is output by a drive signal generated in the IC. This product incorporates 3 half bridge predrivers, and can drive high side and low side N-ch MOSFETs. The high side of external FET gate drive voltage is VM + 8V (typ.), low side of that is 8V (typ.). Slew rate adjustment is possible with the register settings of SOURCE, and SINK. Table 8.28 Source current setting for high side and low side FET Register setting 23[5:3] SOURCE Source current setting for high side and low side FET (mA) 000 10.0 001 13.9 010 19.3 011 26.8 100 37.3 101 51.8 110 72.0 111 100.0 Table 8.29 Sink current setting for high side and low side FET Register setting 23[2:0] SINK Sink current setting for high side and low side FET (mA) 000 20.0 001 27.8 010 38.6 011 53.7 100 74.6 101 103.6 110 143.9 111 200.0 Dead Time Setting When the normal operation mode moves to the short brake mode with BRAKE pin and moves reverse rotation with CWCCW pin , the dead time can be set not to flow rush current to external FETs. Table 8.30 Auto dead time control enable / disable setting Register setting 18[0] ANTITHROUGH Auto Dead time control 0 Enable 1 Disable Table 8.31 Dead time setting Register setting 22[1:0] DEADTIME Dead time 00 250ns (3clk) 01 500ns (6clk) 10 1000ns (12clk) 11 1500ns (18clk) 22 2021-09-17 TC78B009FTG Speed Control Command The speed control command is a signal which can control start, stop, and rotation count of the motor. The type of signal is determined by SEL pin and register setting, and it can be selected among I2C, PWM duty signal, and analog voltage signal. In case of PWM Duty signal and analog voltage signal, it is controlled by SPD pin. The polarity of the signal can be set by the register setting. Table 8.32 Positive / negative logic process SEL pin Register setting 15[4] TSPSEL Register setting 15[3] SPDINV Speed control command High ― ― I2C Signal polarity ― 1 Register setting: 27[7:0], 28[7:6] SPD [9:0] 512 to 1023 = 100% 1 Analog voltage Negative logic VVSP(L) -> SPD command = 512 (100%) VVSP(H) -> SPD command =0 (0%) 0 Analog voltage Positive logic VVSP(L) -> SPD command =0 (0%) VVSP(H) -> SPD command = 512 (100%) 0 Low State 1 PWM Duty Negative logic Low active 0 PWM Duty Positive logic High active When the SPD signal is an analog voltage signal, the resolution is 9 bit to the voltage between VVSP(L) and VVSP(H). When the SPD signal is PWM Duty signal, the frequency range of input signal is 1 kHz to 100kHz. The Duty signal frequency is in the range of 1 kHz to 20 kHz. The resolution is 9 bit. When the frequency is 20 kHz or more, the resolution is lowered. For example, in case of 40 kHz, the resolution is 8 bit, and in case of 100 kHz, that is 7 bit. 23 2021-09-17 TC78B009FTG 8.1.15.1. Speed Control Command PWM Duty In case of positive logic, Duty is updated at a rising edge of SPD. In case of negative logic, the polarity of the input signal is reversed in the IC. After that, the reversed signal is used as the positive logic. SPD Internal duty 40% 60% Figure 8.6 Duty update at rising edge ･When ”H” is held for 1.5ms or more from the last rising edge, the Duty is judged as 100%. Figure 8.7 When “H” is held for 1.5ms or more from the last rising edge ･When next rising edge does not come for 100ms or more from the last rising edge, the Duty is judged as 0%. Figure 8.8 When next rising edge does not come for 100ms or more from the last rising edge ･In case of Duty=100%, a pseudo edge is generated for every 1.5ms in the IC. 1.5ms Figure 8.9 In case of Duty=100% 24 2021-09-17 TC78B009FTG ･ Since the maximum resolution is 9 bit to the PWM Duty input, the narrow pulses are rounded up. Figure 8.10 In case of rounding up the narrow pulse 25 2021-09-17 TC78B009FTG Rotation Count Signal The rotation count is determined by the signal which detects the motor position. It is also measured by pulse count of FG pin, or reading a value of I2C register. FG pin is an open drain output. Register can set the pulse count outputted per rotation of the motor. Additionally, the settings are possible that the FG signal stops according to the stop of the speed control command, and outputs during idling of the motor. Table 8.33 Relational equation between register setting value and rotation frequency Register setting 29[7:0] 30[7:0] Relational equation of rotation frequency per 1 electrical angle hz_cnt[15:0] Rotation frequency[Hz]=250000/hz_cnt[15:0] Table 8.34 FG setting and output pulse per rotation of motor Number of poles of motor Register setting 15[7:5] FGSEL FG signal setting 000 2 poles 4 poles 6 poles 8 poles 10 poles 1 ppr 1 2 3 4 5 001 2/3 ppr 2/3 4/3 2 8/3 10/3 010 1/2 ppr 0.5 1 1.5 2 2.5 011 2 ppr 2 4 6 8 10 100 3 ppr 3 6 9 12 15 101 2.4 ppr 2.4 4.8 7.2 9.6 12 110 1/3 ppr 1/3 2/3 1 4/3 5/3 111 The signal is same as ALERT pin ― Table 8.35 FG signal control setting Register setting 14[0] FG_ON FG signal setting 0 FG stops without speed control command 1 FG outputs without speed control command 26 2021-09-17 TC78B009FTG Number of Poles and Rotation count of Motor The part which is controlled by the rotation count [rpm] such as a speed control, is controlled by the number of poles (POLEPAIR) setting. It converts 1 electric angle frequency to the rotation count [rpm], and is controlled. Rotation count [rpm] = 1 electric angle frequency × (60s/ (Number of poles/2)) Table 8.36 Number of pole pairs of motor Register setting 14[5:3] POLEPAIR Number of poles of motor 000 2 001 4 010 6 011 8 100 10 101 12 110 14 111 16 27 2021-09-17 TC78B009FTG 8.2. Speed control The speed control of motors can be selected from Closed loop control and Open loop control. Table 8.37 Speed control setting Register setting 11[0] OPENLOOP Speed control 0 Closed loop 1 Open loop Closed loop Control The basic speed curve (relation between SPD signal value and rotation speed) of Closed loop speed control is as follows; Speed (rpm) Speed (RPM) (5) ⑤ (6) ⑥ (4) ④ 0% (2) ② (1) ① SPD input duty (%) (3) ③ 100% Figure 8.11 Speed curve example in Closed loop speed control Table 8.38 List of Closed loop setting Description Setting range Setting method Resolution (1) Start Duty 0 to 49.8% STARTDUTY / 512 0.2% (2) Stop Duty 0 to 49.6% STOPDUTY × 2 / 512 0.4% (3) Max Duty 50.2 to 100% (MAXDUTY + 257) / 512 0.2% (4) Start rotation count (Start RPM) 0 to 4095 STARTRPM 1rpm (5) Max rotation count (Max RPM) Depending on (1), (3), and (6) N/A (6) Speed Slope 0 to 1280 rpm/% SPEEDSLOP × 0.08 N/A 0.08rpm/% The maximum resolution is 9 bit for the SPD signal. When the SPD signal is an analog voltage signal, the resolution is 9 bit to the voltage between VVSP(L) and VVSP(H). • In the PWM Duty input, when the frequency of Duty signal is in the range of 1 kHz to 20 kHz, the resolution is 9 bit. When the frequency is 20 kHz or more, the resolution is lowered. For example, in case of 40 kHz, the resolution is 8 bit, and in case of 100 kHz, that is 7 bit. • 28 2021-09-17 TC78B009FTG Example of parameter setting: Setting target: Start Duty=20%, Stop Duty=18%, Max Duty=90% Start RPM=1500rpm, Max RPM=15000rpm Table 8.39 Example of parameter setting Register address 3[7:0] 2[6:0] Register name Setting range STARTDUTY [7:0] STOPDUTY [6:0] 0 to 255 (0% to 49.8%) 0 to 127 (0% to 49.6%) 0 to 255 (50.2% to 100%) 0 to 4095 (0rpm to 4095rpm) 5[7:0] MAXDUTY[7:0] 6[7:0] 7[7:4] STARTRPM[11:0] 8[7:0] 9[7:2] SPEEDSLOP [13:0] 0 to 16383 (0rpm/% to 1280rpm/%) 29 Equation Calculation example Start Duty × 512 0.20 × 512 =102 Stop Duty × 256 0.18 × 256 = 46 Max Duty × 512 – 257 0.90 × 512 – 257 = 204 Start rotation count 1500 64×(Max RPM – Start RPM) / (MAXDUTY –STARTDUTY + 257) (15000 – 1500) / (204 – 102 + 257) × 64=2407 2021-09-17 TC78B009FTG Option (1): Max Duty or more Closed loop-> Open loop (Output Duty= Input Duty) If it is enabled, MAXOPEN should be set to 1. The hysteresis to the change Duty can be set in MAXDUTYHYS. (5) ⑤ e rv e pe o Speed Speed (rpm) (RPM) nl al Ide e op s op u dc (6) ⑥ (4) ④ 0% (1) ① (2) ② SPD input duty (%) (7) (3) ⑦ ③ 100% Figure 8.12 Example of Closed loop speed curve (option (1)) Table 8.40 Closed loop setting of option (1) Description Setting range Setting method Resolution (1) Start Duty 0 to 49.8% STARTDUTY / 512 0.2% (2) Stop Duty 0 to 49.6% STOPDUTY × 2 / 512 0.4% (3) Max Duty 50.2 to 100% (MAXDUTY + 257) / 512 0.2% (4) Start rotation count (Start RPM) 0 to 4095 STARTRPM 1rpm (5) Max rotation count (Max RPM) Depending on (1), (3), and (6) N/A (6) Speed Slope 0 to 1280 rpm/% SPEEDSLOP × 0.08 (7) Open loop to Closed loop (Max Duty – 6.4%) to (Max Duty – 0.4%) (MAXDUTY + 257 - (MAXDUTYHYS + 1) × 2) / 512 30 N/A 0.08rpm/% 0.4% 2021-09-17 TC78B009FTG Example of parameter setting: Setting target: Start duty=20%, Stop duty=18%, Max duty=90%, Max duty hysteresis=4%(86%) Start RPM=1500 rpm, Max RPM=15000 rpm Table 8.41 Example of Closed loop parameter setting for option (1) Register address 3[7:0] 2[6:0] 5[7:0] Register name Setting range STARTDUTY [7:0] STOPDUTY [6:0] MAXDUTY [7:0] 0 to 255 (0% to 49.8%) 0 to 127 (0% to 49.6%) 0 to 255 (50.2% to 100%) 0 to 4095 (0rpm to 4095rpm) 0 to 16383 (0rpm/% to 1280rpm/%) 0 to 15 (0.4% to 6.4%) 6[7:0] 7[7:4] STARTRPM[11:0] 8[7:0] 9[7:2] SPEEDSLOP [13:0] 7[3:0] MAXDUTYHYS [3:0] Equation Calculation example Start Duty × 512 0.20 × 512 =102 Stop Duty × 256 0.18 × 256 = 46 Max Duty × 512 – 257 0.90 × 512 – 257 = 204 Start rotation count 1500 64×(Max RPM – Start RPM) / (MAXDUTY –STARTDUTY + 257) (Max duty hysteresis [%] / 0.4) – 1 (15000-1500)/(204 – 102 + 257) × 64 = 2407 4 / 0.4 – 1=9 Option (2): NOSTOP, MAXOFF setting According to the setting, the operation of which SPD command is start Duty or less, is as follows. Table 8.42 Operation of which SPD command is start Duty or less, in Closed loop control Register setting 9[1] MAXOPEN 0 1 Target speed 0% < SPD duty ≤ Stop Duty Register setting 2[7] NOSTOP Register setting 9[0] MAXOFF 0 0 0 0 0 1 Max rotation count 0 1 0 Start rotation count Start rotation count Start rotation count 1 1 Max rotation count Max rotation count Start rotation count 0 0 0 0 0 1 100% Output 0 1 0 Start rotation count Start rotation count Start rotation count 1 1 100% Output 100% Output Start rotation count SPD duty =0% 31 Stop Duty < SPD duty ≤ Stat duty Duty up: 0 Duty down: Start rotation count Duty up: 0 Duty down: Start rotation count Duty up: 0 Duty down: Start rotation count Duty up: 0 Duty down: Start rotation count 2021-09-17 Speed Speed(RPM) (rpm) Speed Speed(RPM) (rpm) TC78B009FTG 0% SPD input duty (%) 100% 0% 0% SPD input duty (%) 100% NOSTOP=0, MAXOFF=1 Speed(rpm) (RPM) Speed Speed(rpm) (RPM) Speed NOSTOP=0, MAXOFF=0 SPD input duty (%) 100% 0% NOSTOP=1, MAXOFF=0 SPD input duty (%) 100% NOSTOP=1, MAXOFF=1 0% Speed (RPM) Speed (rpm) Speed (RPM) Speed (rpm) Figure 8.13 Example of Closed loop speed curve (option (2)) (MAXOPEN=0) SPD input duty (%) 100% 0% Speed (RPM) Speed (rpm) 0% SPD input duty (%) 100% NOSTOP=0, MAXOFF=1 Speed(rpm) (RPM) Speed NOSTOP=0, MAXOFF=0 SPD input duty (%) 100% 0% NOSTOP=1, MAXOFF=0 SPD input duty (%) 100% NOSTOP=1, MAXOFF=1 Figure 8.14 Example of Closed loop speed curve (option (2)) (MAXOPEN=1) 32 2021-09-17 TC78B009FTG Option (3): Addition of change duty point (5) ⑤ Speed (RPM) (rpm) Speed (9) ⑨ (6) ⑥ (4) ④ 0% (2) ② SPD input duty (%) (1) ① (8) ⑧ (3) ③ 100% Figure 8.15 Example of Closed loop speed curve (option (3)) Table 8.43 List of Closed loop setting for option (3) Description Setting range Setting method Resolution (1) Start Duty 0 to 49.8% STARTDUTY / 512 0.2% (2) Stop Duty 0 to 49.6% STOPDUTY × 2 / 512 0.4% (3) Max Duty 50.2 to 100% (MAXDUTY + 257) / 512 0.2% (4) Start rotation count (Start RPM) 0 to 4095 STARTRPM 1rpm (5) Max rotation count (Max RPM) Depending on (1), (3), and (6) N/A (6) Speed Slope 1 0 to 1280 rpm/% SPEEDSLOP × 0.08 (8) Change Duty 0.4 to 99.6% CHANGEDUTY × 2 / 512 (9) Speed Slope 2 0 to 1280 rpm/% SPEEDSLOP2 × 0.08 N/A 0.08rpm/% 0.4% 0.08rpm/% When the change Duty point is used, the change Duty should be set between start Duty and max. Duty. When the change Duty is not used, CHANGEDUTY should be set to 0. 33 2021-09-17 TC78B009FTG Example of parameter setting: Setting target: Start Duty=20%, Stop Duty=18%, Max Duty=90% Start RPM=1500rpm, 50%Duty RPM=5000rpm, Max RPM=15000rpm Table 8.44 Example of Closed loop parameter setting for option (3) Register address 3[7:0] 2[6:0] 5[7:0] 4[7:0] Register name Setting range STARTDUTY [7:0] STOPDUTY [6:0] MAXDUTY [7:0] CHANGEDUTY [7:0] 0 to 255 (0% to 49.8%) 0 to 127 (0% to 49.6%) 0 to 255 (50.2% to 100%) 1 to 255 (0.4% to 99.6%) 0 to 4095 (0rpm to 4095rpm) 6[7:0] 7[7:4] STARTRPM[11:0] 8[7:0] 9[7:2] SPEEDSLOP [13:0] 0 to 16383 (0rpm/% to 1280rpm/%) 10[7:0] 11[7:2] SPEEDSLOP2 [13:0] 0 to 16383 (0rpm/% to 1280rpm/%) Equation Calculation example Start Duty × 512 0.20 × 512 = 102 Stop Duty × 256 0.18 × 256 = 46 Max Duty × 512 – 257 0.90 × 512 – 257 = 204 Change Duty × 256 0.50 × 256 = 128 Start RPM 1500 64×(Change Duty RPM – Start RPM) / (CHANGEDUTY × 2 – STARTDUTY) 64×(Max RPM – Change Duty RPM) / (MAXDUTY + 257 – CHANGEDUTY × 2) (5000-1500) / (128×2102) × 64 = 1455 (15000 - 5000) / (204 + 257 – 128 × 2) × 64 = 3122 Addition of change duty can be used with option (1) and (2). 34 2021-09-17 TC78B009FTG Limitation of the Rotation Count Change By limiting the change amount in case of decreasing the rotation count, the motor avoids stopping when the rotation count of the motor is lowered rapidly. Table 8.45 Limitation setting of the rotation count change Register setting 18[7:5] RPMLIMIT Rotation count change (rpm) 000 No limitation 001 512 010 2200 011 3800 100 5400 101 7000 110 8600 111 10240 Rotation count of motor Actual rotation count of motor Rotation count change Rotation count change Rotation count change Target rotation count of motor Rotation count change Time Figure 8.16 Image until actual rotation count reaches target count 35 2021-09-17 TC78B009FTG Open Loop Speed Control Output Peak Duty (%) (5) ⑤ (6) ⑥ (4) ④ 0% (2) ② (1) ① SPD input duty (%) (3) ③ 100% Figure 8.17 Speed curve example in Open loop speed control Table 8.46 List of Open loop setting Description Setting range Setting method Resolution (1) Start Duty 0 to 49.8% STARTDUTY / 512 0.2% (2) Stop Duty 0 to 49.6% STOPDUTY × 2 / 512 0.4% (3) Max Duty 50.2 to 100% (MAXDUTY + 257) / 512 0.2% (4) Min output 0 to 49.8% STARTRPM[11:4] / 512 0.2% (5) Max output Depending on (1), (3), and (6) N/A (6) Speed Slope 0 to 16 output %/ input % SPEEDSLOP / 1024 N/A 1/1024 output %/ input % The maximum resolution is 9 bit for the SPD signal. • When the SPD signal is an analog voltage signal, the resolution is 9 bit to the voltage between VVSP(L) and VVSP(H). • In the PWM Duty input, when the frequency of Duty signal is in the range of 1 kHz to 20 kHz, the resolution is 9 bit. When the frequency is 20 kHz or more, the resolution is lowered. For example, in case of 40 kHz, the resolution is 8 bit, and in case of 100 kHz, that is 7 bit. When the output PWM frequency is 23.4 kHz, the output PWM resolution is 9 bit. If the output PWM frequency is high, the output resolution is lowered. 36 2021-09-17 TC78B009FTG Example of parameter setting: Setting target: Start Duty=20%, Stop Duty=18%, Max Duty=90% Min output Duty=10%, Max output Duty=95% Table 8.47 Example of Open loop parameter setting Register address 3[7:0] 2[6:0] Register name Setting range STARTDUTY [7:0] STOPDUTY [6:0] 0 to 255 (0% to 49.8%) 0 to 127 (0% to 49.6%) 0 to 255 (50.2% to 100%) 0 to 255 (0% to 49.8%) 5[7:0] MAXDUTY[7:0] 6[7:0] STARTRPM[11:4] 8[7:0] 9[7:2] SPEEDSLOP [13:0] 0 to 16383 (0 output / input % to16 output / input %) Equation Calculation example Start Duty × 512 0.20 × 512 =102 Stop Duty × 256 0.18 × 256 = 46 Max Duty × 512 – 257 0.90 × 512 – 257 = 204 Min output Duty × 512 0.10 × 512 = 51 1024 × (Max output Duty × 512 – STARTRPM)/(MAXDUTY – STARTDUTY + 257) (0.95 × 512 – 51)/(204 + 257 – 102) × 1024 = 1241 Option (1): Max Duty or more, Output Duty=Input Duty If it is enabled, MAXOPEN should be set to 1. The hysteresis to the change Duty can be set in MAXDUTYHYS. Option (2): NOSTOP, MAXOFF setting According to the setting, the operation of which SPD command is start Duty or less, is as follows. According to MAXOPEN, NOSTOP, and MAXOFF settings, the operation of which Duty is start Duty or less, is as follows. Table 8.48 List of MAXOPEN, NOSTOP, and MAXOFF settings Register setting 9[1] MAXOPEN 0 1 Target speed 0% < SPD duty ≤ Stop Duty Register setting 2[7] NOSTOP Register setting 9[0] MAXOFF 0 0 0 0 0 1 Max Output 0 1 0 Min Output Min Output Min Output 1 1 Max Output Max Output Min Output 0 0 0 0 0 1 100% Output 0 1 0 Min Output Min Output Min Output 1 1 100% Output 100% Output Min Output SPD duty =0% 37 Stop Duty < SPD duty ≤ Stat duty Duty up: 0 Duty down: Min Output Duty up: 0 Duty down: Min Output Duty up: 0 Duty down: Min Output Duty up: 0 Duty down: Min Output 2021-09-17 TC78B009FTG NOSTOP=0, MAXOFF=0 NOSTOP=0, MAXOFF=1 NOSTOP=1, MAXOFF=0 NOSTOP=1, MAXOFF=1 Figure 8.18 Example of Open loop speed curve (option (2)) (MAXOPEN = 0) NOSTOP=0, MAXOFF=0 NOSTOP=0, MAXOFF=1 NOSTOP=1, MAXOFF=0 NOSTOP=1, MAXOFF=1 Figure 8.19 Example of Open loop speed curve (option (2)) (MAXOPEN = 1) 38 2021-09-17 TC78B009FTG Option (3): Addition of change duty point Output Peak Duty (%) (5) ⑤ (9) ⑨ (6) ⑥ (4) ④ 0% (2) ② (1) ① (8) ⑧ SPD input duty (%) (3) ③ 100% Figure 8.20 Example of Open loop speed curve (option (3)) Table 8.49 List of Open loop settings for opstion (3) Description Setting range Setting method Resolution (1) Start Duty 0 to 49.8% STARTDUTY / 512 0.2% (2) Stop Duty 0 to 49.6% STOPDUTY × 2 / 512 0.4% (3) Max Duty 50.2 to 100% (MAXDUTY + 257) / 512 0.2% (4) Min output 0 to 49.8% STARTRPM[11:4] / 512 0.2% (5) Max output Depending on (1), (3), and (6) N/A (6) Speed Slope 1 0 to 16output % / input % SPEEDSLOP / 1024 (8) Change Duty 0.4 to 99.6% CHANGEDUTY × 2 / 512 (9) Speed Slope 2 0 to 16output % / input % SPEEDSLOP2 / 1024 N/A 1/1024 output %/ input % 0.4% 1/1024 output %/ input % When the change Duty point is used, the change Duty should be set between start Duty and max. Duty. When the change Duty is not used, CHANGEDUTY should be set to 0. 39 2021-09-17 TC78B009FTG Example of parameter setting: Setting target: Start Duty=20%, Stop Duty=18%, Max Duty=90%, Change Duty=50% Start output Duty =10%, 50% Change Duty output=40%, Max output Duty=95% Table 8.50 Example of Open loop parameter setting for option (3) Register address Register name Setting range STARTDUTY [7:0] STOPDUTY [6:0] MAXDUTY [7:0] CHANGEDUTY [7:0] STARTRPM [11:4] 0 to 255 (0% to 49.8%) 0 to 127 (0% to 49.6%) 0 to 255 (50.2% to 100%) 1 to 255 (0.4% to 99.6%) 0 to 255 (0% to 49.8%) 8[7:0] 9[7:2] SPEEDSLOP [13:0] 0 to 16383 (0 output % / input % to 16 output % / input %) 10[7:0] 11[7:2] SPEEDSLOP2 [13:0] 0 to 16383 (0output %/ input % to 16 output % / input %) 3[7:0] 2[6:0] 5[7:0] 4[7:0] 6[7:0] Equation Calculation example Start Duty × 512 0.20 × 512 = 102 Stop Duty × 256 0.18 × 256 = 46 Max Duty × 512 – 257 0.90 × 512 – 257 = 204 Change Duty × 256 0.50 × 256 = 128 Min output Duty × 512 0.10 × 512 = 51 1024 × (Output Duty at Change Duty × 512 – STARTRPM) / (CHANGEDUTY × 2 – STARTDUTY + 257) 1024 × (Max output Duty × 512 – Output duty at Change Duty) / (MAXDUTY – CHANGEDUTY × 2 + 257) (0.40 × 512 – 51) / (128 × 2 – 102) × 1024 = 1022 (0.95 × 512 – 0.40 × 512) / (204 + 257 – 128 × 2) × 1024 = 1404 Addition of change duty can be used with option (1) and (2). 40 2021-09-17 TC78B009FTG 8.3. I2C and NVM Data of internal registers can be communicated via I2C. Each setting parameter is read from non-volatile memory (NVM), and is stored to the register. I2C communication SDA SDA SCL ST SP Start condition SCL End condition SDA change area SDA fixed area Figure 8.21 Start condition, stop condition, and data communication • Write procedure of I2C communication (1) Start condition (2) Slave address of I2C + Write (3) Register address (4) Write control data (5) Stop condition Table 8.51 I2C communication: SDA minimum data control S I2C Slave Address A6 A5 A4 A3 A A2 A1 A0 R/W Register Address A7 A6 A5 A4 A A3 A2 A1 A0 Control Data D7 D6 D5 A D4 D3 D2 D1 D0 • S : Start condition • A : Acknowledge • P : Stop condition • Read procedure of I2C communication (1) Start condition (2) Slave address of I2C + Write (3) Register address (4) Start condition (5) Slave address of I2C + Read (6) Read control data (7) Stop condition 41 2021-09-17 P TC78B009FTG NVM Setting Slave address can be set with ID2 pin and ID1 pin. When both ID2 pin and ID1 pin are set to Low, the slave address can be changed by writing the predetermined slave address to the register. Table 8.52 Slave address setting ID2 pin ID1 pin Slave address Note Low Low 0101001 (Initial value) Register 25[7:1]:SLAVE_ADRS It can be stored to NVM. Low High 0101001 ― High Low 0101101 ― High High 0110010 ― • How to read and write to NVM is as follows. • Read procedure of NVM (1) 8’b0000_0000 should be written to the register address:86. (2) When 8’b0000_0001 should be written to the register address:87, NVM is started to read. (3) Waiting time (4) Register address:87 should be read and 8’b0000_0000 is confirmed. • Write procedure of NVM (1) 8’b0000_0001 should be written to the register address:86 (2) When 8’b0000_0001 should be written to the register address:87, NVM is started to read. (3) Waiting time (4) Register address:87 should be read and 8’b0000_0000 is confirmed. * If the write operation is not completed for a certain period, (5) 8’b0000_0000 should be written to the register address:87, and the write operation of NVM is forced to end. Figure 8.22 Write flow of NVM 42 2021-09-17 TC78B009FTG Normal Register Table 8.53 Register map ADDR ESS Bit 0 7:6 0 Name Description NVM Read:R Write:W Initial value ― ― ― R 0 5 CP_LOW Error state of charge pump voltage drop (0: Normal, 1: Error) ― R 0 0 4 TSD Error state of temperature (0: Normal, 1: Error) ― R 0 0 3 ISD Error state of over current (0: Normal, 1: Error) ― R 0 0 2 OV_SPD Error state of maximum rotation number (0: Normal, 1: Error) ― R 0 0 1 UD_SPD Error state of minimum rotation number (0: Normal, 1: Error) ― R 0 0 0 ST_FAIL Error state of startup (0: Normal, 1: Error) ― R 0 1 7:0 USERID Free R/W 0 2 7 NOSTOP No stop mode (0: disable, 1: enable) R/W 0 2 6:0 STOPDUTY Stop Duty R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ✓ 0 R/W 0 ✓ R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 7:0 STARTDUTY Start Duty Duty of inflection point 5 7:0 MAXDUTY Max Duty 6 7:0 STARTRPM Start rotation number 7 7:4 STARTRPM Start rotation number 7 3:0 MAXDUTYHYS Hysteresis of recovery from Open loop to Closed loop 8 7:0 SPEEDSLOP Curve slope 9 7:2 SPEEDSLOP Curve slope 9 1 MAXOPEN OPEN control of Max Duty or more (0: disable, 1: enable) 9 0 MAXOFF Full speed at SPD command OFF (0: disable, 1: enable) 10 7:0 SPEEDSLOP2 Curve slope after inflection point 11 7:2 SPEEDSLOP2 Curve slope after inflection point 11 1 VCP_MASK Low voltage detection of charge pump (0: enable, 1: disable) 11 0 OPENLOOP OPEN LOOP/CLOSEDLOOP (0: Closed loop, 1: Open loop) 12 7 KIX KI x 8 (0:1 x, 1:8 x) 12 6:0 KI KI (0 to 127) 13 7 6:0 KPX ✓ ✓ ✓ KP (0 to 127) Standby mode 6 DIR Polarity of rotation direction of CWCCW pin (0: positive, 1: negative) 14 5:3 POLEPAIR Pole pair number 14 2:1 MAXSPEED Max speed setting to determine Initial output duty, when the motor rotates from idling. 14 0 FG_ON FG pin control 15 7:5 FGSEL Pulse number of FG pin 15 4 TSPSEL Selection of SPD pin input signal (0: Analog voltage, 1:PWM Duty) 15 3 SPDINV SPD input polarity (0: positive, 1: negative) 15 2 LATCH Abnormality detection (0: Auto restart, 1: Latch) 15 1:0 OCPMASK OCP filter setting 6:4 DUTYCHGLIMIT ✓ ✓ ✓ ✓ ✓ ✓ 14 16 ✓ ✓ 7 LOCKDIS ✓ ✓ 14 7 ✓ ✓ STBY_MODE 16 ✓ ✓ KP x 8 x (0:1 x, 1:8 x) KP ✓ ✓ CHANGEDUTY 13 ✓ ✓ 7:0 4 ✓ ✓ ✓ ✓ Forced commutation protection (0: enable, 1: disable) Limitation of Duty change 43 ✓ ✓ ✓ ✓ ✓ ✓ 2021-09-17 TC78B009FTG ADDR ESS Bit 16 3:1 16 0 17 Name Description STARTCURRENT Limitation of start current OCPDIS Limitation function of output current (0: enable, 1: disable) 7:6 SS_ADD_SEL Current limitation setting when start current limitation moves to normal current limitation 17 5:4 SS_UP_SEL Setting of current limitation increasing per 320 ms in SS_ADD_SEL 17 3:1 SS_DUTYCHGLIMIT Duty limitation at soft start 17 0 18 DUTY_UP_TIME Up time of Duty change (0:2.7ms , 1:10.8ms) 7:5 RPMLIMIT Limitation setting of target rotation number change 18 4 BRK_INV Polarity setting of BRAKE pin (0: positive, 1: negative) 18 3 isd_mask Over current detection (0: enable, 1: disable) 18 2:1 RS_SEL Input filter setting of RSA pin 18 0 ANTITHROUGH Auto Dead time control (0: enable, 1: disable) 19 7:5 WAIT_TIME Time setting of brake sequence 19 4 WAIT_MODE Output FET state of brake sequence 19 3 WAIT_CON Moving state after brake sequence 19 2 LOCK_BRK Short brake setting at lock protection (0: OFF, 1: Short brake) 1 alertinv Polarity of ALERT pin (0: High=Error, 1: Low=Error) 19 0 tsd_mask Thermal shutdown (0: enable, 1: disable) 20 7:5 TRE Restart time setting 20 4:3 PreTIP Setting the first DC excitation time 20 2:0 TIP Setting the second DC excitation time 21 7:4 LA Lead angle setting 21 3:2 FMAX Setting of detection rotation number of maximum rotation speed error 21 1:0 FST Setting forced commutation frequency 22 7 SLOP Soft switching setting 22 6:5 LAP Setting conduction angle 22 4:2 FPWM Output PWM frequency setting 22 1:0 DEADTIME Dead time setting 23 7 ISD_LVL ISD threshold setting (0:1V, 1:0.5V) 23 6 OCP_LVL Gain settings of output current limitation threshold and output current monitor function 23 5:3 SOURCE Source current setting of predriver 23 2:0 SINK Sink current setting of predriver 24 7:6 COMP_HYS Hysteresis voltage setting of position detection comparator 24 5:0 ― ― SLAVE_ADRS I2 C 19 NVM Read:R Write:W Initial value ✓ R/W 0 R/W 0 ✓ ✓ R/W ✓ R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ R/W ✓ R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ✓ ✓ ✓ ✓ ✓ 0 ✓ R/W ✓ R/W 0 R/W 0 R/W 0 R/W 0 R/W 0x29 R/W 0 ✓ ✓ ✓ ✓ Slave address 0 0 25 7:1 25 0 ― ― 26 7:0 ― ― ― R/W 0 27 7:0 SPD Setting of speed command ― R/W 0 28 7:6 SPD Setting of speed command ― R/W 0 ― ― R/W 0 R 0 28 5:0 ― ✓ 7:0 hz_cnt Rotation frequency ― 30 7:0 hz_cnt Rotation frequency ― R 0 86 7:1 ― ― ― R/W 0 29 44 2021-09-17 TC78B009FTG ADDR ESS Bit 86 0 87 7:1 87 0 Name Description NVM Read:R Write:W Initial value NVM_W/R READ/WRITE or NVM (0:READ enable,1:WRITE enable) ― R/W 0 ― ― ― R/W 0 NVM_ST NVM processing (0: Processing end, 1: Processing start) ― R/W 0 8.4. Abnormality Detection (Error Mode) Various Abnormality Detection The abnormality detection functions include power supply low voltage detection, output over current detection, charge pump low voltage detection, thermal shutdown, over maximum speed detection, under minimum speed error detection, and startup failure detection. When the abnormality state is detected, the IC enters to the error mode. The IC stops operation when power supply low voltage is detected. The output FETs are all off in cases of output over current detection, charge pump low voltage detection, thermal shutdown, and over maximum speed detection. Output FETs are all OFF or short brake depending on the register setting in cases of under minimum speed error detection and startup failure detection. The abnormal detection signal is output with ALART pin. In error mode, which abnormality detection works can be read from the register by I2C, except UVLO. Table 8.54 Abnormal detection Power supply low voltage (UVLO) Output over current (ISD) Charge pump low voltage (CPVSD) Thermal shutdown (TSD) Abnormality detection Read register ― ISD 0[3] CP_LOW 0[5] TSD 0[4] Detect condition Release condition VM < 3.9V or VREG < 3.7V VM > 4.2 and VREG > 4.0V Output current > ISD threshold ・ Output current < ISD threshold AND ・ Auto restart after TRE OR Release operate ・ VCP-VM > 4.0V AND VCP - VM < 3.7V ・ Auto restart after TRE OR Release operate ・Tj < 130°C AND Tj > 170°C ・ Auto restart after TRE OR Release operate Over maximum speed (FMAX ERROR) OV_SPD 0[2] FMAX setting < Current frequency FMAX:0.75kHz/1.5kHz/3kHz/disable ・ Auto restart after TRE OR Release operate Under minimum speed (FMIN ERROR) UD_SPD 0[1] FST setting > current frequency FST:1.6Hz/3.2Hz/6.4Hz/12.8Hz ・ Auto restart after TRE OR Release operate Startup failure (STARTUP FAIL) ST_FAIL 0[0] Cannot move to sensorless drive mode after force commutation 4 rounds ・ Auto restart after TRE OR Release operate 45 2021-09-17 TC78B009FTG Recovery from Abnormality Detection When the abnormality states except UVLO are detected and the IC moves to the error mode, the recovery operation can be selected among auto recovery and latch. In the auto recovery, IC resumes after moving to the error mode, and restart time elapse. Also, IC resumes with the release operation. In the latch method, the IC does not resume until the release operation is performed. ● Release operation ▪ Speed control command is zero-input. ▪ IC moves to standby mode. ▪ Power OFF Table 8.55 Recovery operation setting Register setting 15[2] LATCH Recovery operation 0 Auto recovery 1 Latch Table 8.56 Restart time setting Register setting 20[7:5] TRE Restart time (s) 000 0 001 0.5 010 1 011 1.5 100 2 101 4 110 7 111 10 ALERT The ALERT pin is an open drain type output pin. When an abnormal state is detected, this pin outputs. Output polarity of the ALERT pin can be set. Table 8.57 Abnormal state polarity setting of ALERT pin Register setting 19[1] alertinv Abnormal state 0 High 1 Low 46 2021-09-17 TC78B009FTG TSD/ISD/CPVSD FMAX/FMIN/STARTUP FAIL Detect error Release error Restart time START Operation mode Normal mode STOP Error mode Startup Sensorless mode ALERT (Polarity:positve:0) ALERT (Polarity: negative:1) Each error signal in register GHU/GHV/GHW Normal operation Normal operation GLU/GLV/GLW Normal operation (When FMIN and Startup fail set OFF.) Normal operation GLU/GLV/GLW Normal operation (When FMIN and Startup fail set short brake.) Normal operation Figure 8.23 Timing chart example of error mode by auto recovery SPD=0 SPD=ON TSD/ISD/CPVSD FMAX/FMIN/STARTUP FAIL Detect error Operation mode Normal mode Release error Error mode Idle mode Startup Sensorless mode ALERT (Polarity:positve:0) ALERT (Polarity: negative:1) Each error signal in register GHU/GHV/GHW Normal operation Normal operation GLU/GLV/GLW (When FMIN and Startup fail set OFF.) Normal operation Normal operation GLU/GLV/GLW (When FMIN and Startup fail set short brake.) Normal operation Normal operation Figure 8.24 Timing chart example of speed command release in error mode by latch method 47 2021-09-17 TC78B009FTG Standby mode:ON Power supply:OFF TSD/ISD/CPVSD FMAX/FMIN/STARTUP FAIL Detect error Operation mode Normal mode Standby mode:OFF Power supply:ON Release error Error mode Standby mode/ Power supply off Normal mode ALERT (Polarity:positve:0) ALERT (Polarity: negative:1) Each error signal in register X GHU/GHV/GHW Normal operation Hi-Z Normal operation GLU/GLV/GLW (When FMIN and Startup fail set OFF.) Normal operation Hi-Z Normal operation GLU/GLV/GLW (When FMIN and Startup fail set short brake.) Normal operation Hi-Z Normal operation Figure 8.25 Timing chart example of standby mode / power off release in error mode by latch method 48 2021-09-17 TC78B009FTG Max Rotation Count Error, Minimum Rotation Count Error, and Start Error In the max rotation count error, when the motor rotation count reaches the maximum rotation frequency setting or more, the IC moves to the error mode, and external FET outputs are all turned off. In the minimum rotation count error, when the rotation count of the motor falls to below the forced commutation frequency, the IC moves to the error mode. The operation at detecting can be selected among external FETs all OFF, and short brake setting. In the start error, if the motor rotates four times with forced commutation, and the IC does not move to the sensorless drive, it moves to error mode. The operation at detecting can be selected among all off setting of the external FETs and the short brake setting. When the motor is locked, the motor cannot be rotated. Therefore, the IC detects the minimum rotation count error or start error, and moves to the error mode. Table 8.58 Max rotation frequency (max rotation count or more) setting Register setting 21[3:2] FMAX Max rotation frequency 00 0.75 kHz 01 1.5 kHz 10 3 kHz 11 None Table 8.59 Forced commutation frequency (minimum rotation count error) setting • Register setting 21[1:0] FST Electrical angle frequency Idling detection time (electrical angle frequency) 00 1.6 Hz 200 ms (5 Hz) 01 3.2 Hz 100 ms (10 Hz) 10 6.4 Hz 50 ms (20 Hz) 11 12.8 Hz 25 ms (40 Hz) The forced commutation frequency is same as the detection frequency of minimum rotation count error, and changes with idling detection time. Table 8.60 Operation settings of minimum rotation count error and start error detection Register setting 19[2] LOCK_BRK Operation 0 Output FET all OFF 1 Output FET short brake Table 8.61 Enable / disable setting of start error function Register setting 16[7] LOCKDIS Start error function 0 Enable 1 Disable 49 2021-09-17 TC78B009FTG Under Voltage Lockout Detection (UVLO) When the power supply voltage is less than the IC operation voltage, this function turns off the IC operation to avoid malfunction. It monitors both VM voltage and VREG voltage. When VM voltage is 3.9 V (typ.) or less, or VREG voltage is 3.7 V (typ.) or less, this function is activated. It has a hysteresis of 0.3 V (typ.). IC is resumed to normal operation when VM voltage is over 4.2 V (typ.), and VREG voltage is over 4.0 V (typ.). Figure 8.26 Timing chart example of UVLO operation Output Over Current Detection (ISD) To prevent the IC from flowing over current continuously, the motor current is detected with external shunt resistor. The detected voltage that is input to RSA pin becomes ISD reference voltage VISD or more, the external FET outputs are all OFF. Table 8.62 ISD reference voltage setting Register setting 23[7] ISD_LVL ISD reference voltage VISD 0 1V 1 0.5V Table 8.63 Enable / disable setting of ISD function Register setting 18[3] isd_mask ISD function 0 Enable 1 Disable 50 2021-09-17 TC78B009FTG Low Voltage Detection for Charge Pump (CPVSD) When the voltage between VCP and VM is 3.7 V(typ.) or less, motor outputs are turned off (as high impedance state). It has a hysteresis of 0.3 V (typ.). Motor is resumed to the normal operation when the voltage difference is over 4.0 V (typ.). Table 8.64 Enable / disable setting of CPVSD function Register setting 11[1] VCP_MASK CPVSD function 0 Enable 1 Disable Thermal Shutdown Thermal shutdown (TSD) is incorporated. It operates when IC’s junction temperature (Tj) exceeds 170°C (typ.). All output FETs are turned off. It has a hysteresis of 40°C (typ.). When IC's junction temperature becomes 130°C (typ.) or less, the operation returns automatically. Table 8.65 Enable / disable setting of TSD function Register setting 19[0] tsd_mask TSD function 0 Enable 1 Disable 51 2021-09-17 TC78B009FTG 9. Absolute Maximum Ratings Table 9.1 Absolute Maximum Ratings(Unless otherwise specified, Ta=25°C) Characteristics Symbol Rating Unit Remarks Motor power supply voltage VMvmax 30 V VM 5V reference voltage VREGvmax 6 (Note1) V VREG VCPvmax VM+10 (Note 1) V VCP VCPMvmax VM V CPM VCPPvmax VM+10 V CPP Charge pump voltage Vmaxin1 -0.3 to 6 V STBY/SPD/SEL/ID1/ID2/SCL/SDA/CW CCW/BRAKE/TESTI/TESTO Vmaxin2 30 V OUTU/OUTV/OUTW Vmaxin3 6 V RSA/RSB Vmaxo1 18 V GLU/GLV/GLW Vmaxo2 6 V ALERT/FG/PHBF/PH Vmaxo3 VM+10 V GHU/GHV/GHW Imax1 10 mA ALERT/FG Imax2 -120 mA GHU/GHV/GHW/GLU/GLV/GHW Imax3 240 mA GHU/GHV/GHW/GLU/GLV/GHW Imax4 2 mA PHBF Imax5 30 mA VREG PD 4.1 W Mounted on a board (4-layer board: FR4:76.2 mm x 114.3 mm x 1.6 mm), Rth (j-a) = 30.5°C/W Operating temperature Topr -40 to 105 °C — Storage temperature Tstg -55 to 150 °C — Junction temperature Tjmax 150 °C — Input voltage Output voltage Output current Power dissipation Note 1: VREG and VCP pin voltages are generated in the IC. Do not apply voltage externally. Note 2: Output current may be restricted by ambient temperature and the mounting board. Please design not to exceed the junction temperature. Note: The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating (s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. Please use this IC within the specified operating ranges. 52 2021-09-17 TC78B009FTG 10. Operating Range Table 10.1 Operating range (Unless otherwise specified, Ta=-40 to 105°C) Characteristics VM pin power supply voltage 1 Symbol Min Typ. Max Unit VM(opr1) 9 14.8 27 V Remarks VM pin power supply voltage 2 VM(opr2) 5.5 — 9 V Electrical characteristics are only for reference because the variation of electrical characteristics becomes large VM pin power supply voltage 3 VM(opr3) 10.8 14.8 27 V For NVM writing fTSP 1 — 100 kHz — fSCK — — 400 kHz — Input PWM command frequency Input I2C CLK frequency Table 10.2 NVM characteristics Characteristics Conditions Min Max Unit Program/Erase cycles Tj=0 to 90°C 10 ― Cycle 10.1. Power Dissipation Mounted on a board (4-layer board: FR4:76.2 mm x 114.3 mm x 1.6 mm), Rth (j-a) = 30.5°C/W Figure 10.1 Power dissipation 53 2021-09-17 TC78B009FTG 11. Electrical Characteristics Table 11.1 Electrical Characteristics (Unless otherwise specified, VM = 14.8V, Ta = 25°C) Pin / Circuit VM VREG VCP GHU, GHV, GHW GLU, GLV, GLW OUTU, OUTV, OUTW STBY Characteristics Symbol Condition Min Typ. Max Unit Idle mode — 15 18 mA Power supply current 1 IVM1 Power supply current 2 IVM2STB Standby mode STBY=0V — 0 10 µA UVLO operation voltage VUVOVM In VM falling 3.7 3.9 4.1 V UVLO hysteresis voltage VUVHYVM — — 300 — mV UVLO release voltage VUVRVM In VM rising 4.0 4.2 4.4 V 5V reference voltage VVREG Iout=0mA 4.75 5.0 5.35 V 5V reference voltage output current VIVREG Iout =-10mA 4.75 5.0 5.35 V In VREG falling 3.5 3.7 3.9 V UVLO operation voltage VUVOVREG UVLO hysteresis voltage VUVHYVREG — — 300 — mV UVLO release voltage VUVRVREG 3.8 4.0 4.2 V Charge pump voltage VVCP VM + 8 VM + 8.5 V In VREG rising VM=9V: Idle mode Between VM and VCP pins: 0.1µF, VM + 7.5 Between CPP and CPM pins: 0.01µF CPVSD operation voltage VCPVSDO In the voltage between VM pin and VCP pin falling, VM ≥ 5.5V 3.4 3.7 4.0 V CPVSD hysteresis voltage VCPVSDHY — — 300 — mV CPVSD release voltage VCPVSDR In the voltage between VM pin and VCP pin rising. VM ≥ 5.5V 3.7 4.0 4.3 V Output H voltage VOHGHX Iout = -1mA VCP – 1.5 VCP – 0.3 VCP V Output L voltage VOLGHX Iout = 1mA — 0.3 0.8 V Output source current 1 ISOGHX1 — -12 -10 -8 mA Output source current 2 ISOGHX2 — -120 -100 -80 mA Output sink current 1 ISIGHX1 — 16 20 24 mA Output sink current 2 ISIGHX2 — 160 200 240 mA Output H voltage VOHGLX Iout= -1mA 6.9 7.7 8.5 V Output L voltage VOLGLX Iout = 1mA — 0.05 0.2 V Output source current 1 ISOGLX1 — -12 -10 -8 mA Output source current 2 ISOGLX2 — -120 -100 -80 mA Output sink current 1 ISIGLX1 — 16 20 24 mA Output sink current 2 ISIGLX2 — 160 200 240 mA Comparator offset voltage VCOFSOUTX (Reference value) -1 0 1 mV Comparator hysteresis voltage 1 VCHYOUTX1 (Reference value) ±40 ±100 ±150 mV Comparator hysteresis voltage 2 VCHYOUTX2 (Reference value) ±80 ±200 ±300 mV Comparator hysteresis voltage 3 VCHYOUTX3 (Reference value) ±120 ±300 ±450 mV Input H voltage VIHSTB — 2.0 — 5.5 V Input L voltage VILSTB — -0.3 — 0.8 V Hysteresis voltage VHYSTB — — 200 — mV H input current IIHSTB Vin=5V 17 25 33 µA L input current IILSTB Vin=0V — — 1 µA STBY:H to L 95 100 105 ms Standby mode setting time TSETSTB 54 2021-09-17 TC78B009FTG Pin / Circuit SPD (during digital signal input) Characteristics BRAKE SEL FG ALERT RSA RSB PH Min Typ. Max Unit VIHSPD — 2.0 — 5.5 V Input L voltage VILSPD — -0.3 — 0.8 V Hysteresis voltage VHYSPD — — 200 — mV H input current IIHSPD Vin=5V — — 1 µA L input current IILSPD Vin=0V — — 1 µA Input frequency fISPD — 1 — 100 kHz t100SPD — — 1.5 — ms t0SPD — — 100 — ms ADC = 512 (100%) 3.9 4.0 4.1 V ADC = 0(%) 1.4 1.5 1.6 V 0%Duty detection time CWCCW Condition Input H voltage 100%Duty detection time SPD (during analog voltage input) Symbol 100% input voltage V100SPD 0% input voltage V0SPD Input H voltage VIHCW — 2.0 — 5.5 V Input L voltage VILCW — -0.3 — 0.8 V Hysteresis voltage VHYCW — — 400 — mV H input current IIHCW Vin=5V 70 100 130 µA L input current IILCW Vin=0V — — 1 µA Input H voltage VIHCW — 2.0 — 5.5 V Input L voltage VILCW — -0.3 — 0.8 V Hysteresis voltage VHYCW — — 400 — mV H input current IIHCW Vin=5V 70 100 130 µA L input current IILCW Vin=0V — — 1 µA Input H voltage VIHSEL — 2.0 — 5.5 V Input L voltage VILSEL — -0.3 — 0.8 V Hysteresis voltage VHYSEL — — 400 — mV H input current IIHSEL Vin=5V 70 100 130 µA L input current IILSEL Vin=0V — — 1 µA Output L voltage VLFG Iout=5mA — 0.15 0.30 V ILFG Vout=6V — — 1 µA Output L voltage Output leakage current VLALERT Iout=5mA — 0.15 0.30 V Output leakage current ILALERT Vout=6V — — 1.0 µA Output current limit reference voltage 1 VOCP1 0.25V setting 0.225 0.25 0.275 V Output current limit reference voltage 2 VOCP2 0.125V setting 0.113 0.125 0.137 V Over current reference voltage 1 VISD1 0.5V setting 0.45 0.5 0.55 V Over current reference voltage 2 VISD2 1V setting 0.9 1 1.1 V Input current IIRSA RSA=0V — 0.1 1 µA Input current1 IIRSB1 Vin=5V, Gain=10 35 45 65 µA Input current2 IIRSB2 Vin=5V, Gain=20 18 24 35 µA Output H voltage VOHPH — VREG1.2 VREG0.85 VREG V Output L voltage VOLPH — 0 0 0.1 V Output voltage 1 VOPH1 Gain=10, RSB=0.25V 2.4 2.5 2.6 V Output voltage 2 VOPH2 Gain=20, RSB=0.125V 2.4 2.5 2.6 V 55 2021-09-17 TC78B009FTG Pin / Circuit PHBF Characteristics ID1 ID2 Typ. Max Unit Gain=20, RSB=0.125V, PH=2.4V 400 840 1400 µA Output L output current IOPH2 Gain=20, RSB=0.125V, PH=2.6V 0 0 1.0 µA — VREG1.2 VREG0.85 VREG V 0 0 0.1 V Output H voltage VOHPHBF Output L voltage VOLPHBF — Output voltage 1 VOPHBF1 Gain=10, RSB=0.25V 2.4 2.5 2.6 V Output voltage 2 VOPHBF2 Gain=20, RSB=0.125V 2.4 2.5 2.6 V Output voltage 3 VOPHBF3 Gain=20, RSB=0.125V, PHBF=2mA 2.4 2.53 2.75 V Output voltage 4 VOPHBF4 Gain=20, RSB=0.125V, PHBF=-2mA 2.25 2.48 2.6 V — 11.64 12.00 12.36 MHz fOSC Output PWM frequency 1 fOPWM1 FPWM = 000 — 23.4 — kHz Output PWM frequency 2 fOPWM2 FPWM = 011 — 187.5 — kHz In rising temperature (Reference value) — 170 — °C TTSD Release hysteresis temperature THYTSD (Reference value) — 40 — °C Shutdown release temperature TRTSD In falling temperature (Reference value) — 130 — °C Input H voltage VIHIDX — 2.0 — 5.5 V Input L voltage VILIDX — -0.3 — 0.8 V Hysteresis voltage VHYIDX — — 400 — mV H input current IIHIDX — 70 100 130 µA L input current IILIDX — — — 1 µA Input H voltage VIHI2C — 2.0 — 5.5 V Input L voltage VILI2C — -0.3 — 0.8 V Hysteresis voltage VIHYI2C — — 400 — mV Vin=0V to 5V -5 1 5 µA VOLSDA Iout=6mA — — 0.4 V SDA Output leakage current ILSDA Vout=6V — — 1 µA SCL clock frequency fSCL — — — 400 kHz 0.6 — — µs 0.6 — — µs Input current SDA Output L voltage SDA SCL Min IOPH1 Shutdown temperature TSD Condition Output H output current OSC frequency Internal circuit Symbol III2C Hold time Start condition tHDSTA Setup time Start condition tSUSTA — — SCL clock Low period tLOW — 1.3 — — µs SCL clock High period tHIGH — 0.6 — — µs Data hold time tHDDAT — 0 — — ns Data setup time tSUDAT — 100 — Setup time Stop condition tSUSTO 0.6 — — µs 1.3 — — µs Bus free time Stop / start condition tBUF — — ns Reference value: It means a design value. The test before shipment has not been performed. 56 2021-09-17 TC78B009FTG Figure 11.1 Electrical characteristics of I2C timing chart 57 2021-09-17 TC78B009FTG 12. Example of Application Circuit Note: Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. I2C Note: As for the external FET, the specification whose gate threshold voltage is minimum 1.0V at Ta 25 °C is recommended. 58 2021-09-17 TC78B009FTG 13. Package Dimensions Figure 13.1 Package Dimensions 59 2021-09-17 TC78B009FTG Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. required, especially at the mass production design stage. Thorough evaluation is Providing these application circuit examples does not grant a license for industrial property rights. IC Usage Considerations Notes on handling of ICs (1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. (2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. (4) Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. 60 2021-09-17 TC78B009FTG Points to remember on handling of ICs (1) Over current Protection Circuit Over current protection circuits (referred to as current limiter circuits) do not necessarily protect ICs under all circumstances. If the Over current protection circuits operate against the over current, clear the over current status immediately. Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the over current protection circuit to not operate properly or IC breakdown before operation. In addition, depending on the method of use and usage conditions, if over current continues to flow for a long time after operation, the IC may generate heat resulting in breakdown. (2) Thermal Shutdown Circuit Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation. (3) Heat Radiation Design In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (Tj) at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation with peripheral components. (4) Back-EMF When a motor reverses the rotation direction, stops or slows down abruptly, a current flow back to the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power supply and output pins might be exposed to conditions beyond absolute maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. 61 2021-09-17 TC78B009FTG RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. Hardware, software and systems described in this document are collectively referred to as “Product”. • TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. • Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. 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