POWER DRIVER FOR STEPPER MOTORS
INTEGRATED CIRCUITS
TMC2041 DATASHEET
Dual step/direction driver for up to two 2-phase bipolar stepper motors. stallGuard for sensorless
homing. SPI, UART (single wire) Configuration and Diagnostics Interface.
APPLICATIONS
Office Automation
Antenna Positioning
3D printers
Battery powered applications
Printer and Scanner
Pumps and Valves
Medical Applications
Office and Laboratory equipment
FEATURES
AND
BENEFITS
DESCRIPTION
Two 2-phase stepper motors
Drive Capability up to 2x 1.1A coil current (2x 1.5A peak)
Parallel Option for one motor at 2.2A (3A peak)
Voltage Range 4.75… 26V DC
SPI & Single Wire UART for configuration and diagnostics
Highest Resolution up to 256 microsteps per full step
microPlyer™ microstep interpolation
spreadCycle™ highly dynamic motor control chopper
stallGuard2™ high precision sensorless motor load detection
coolStep™ current control for energy savings up to 75%
Full Protection & Diagnostics
Compact Size 7x7mm2 QFN48 package
The TMC2041 is a compact, dual stepper
motor driver IC with serial interfaces for
configuration and diagnostics. It is pin
compatible to the fully featured TMC5041
and TMC5072 drivers with internal motion controller. The TMC2041 is intended
for all applications, where an internal
motion controller is not desired, and
ramping is done in a microcontroller.
Based on TRINAMICs high-performance
spreadCycle chopper, the driver allows
precise and smooth motor operation. It
offers coolStep for energy savings and
stallGuard for sensorless stall detection.
The complete set of protection and
diagnostic functionality ensures reliable
operation. High integration, high energy
efficiency and a small form factor enable
miniaturized and scalable systems for
cost effective solutions.
BLOCK DIAGRAM
Step/Dir
Power
Supply
TMC2041
Motor 1
Charge
Pump
SPI
UART
256 µStep
Sequencer
UART / SPI
configuration&
diagnostics
DRIVER 1
Protection
& Diagnostics
Protection
& Diagnostics
Motor 2
DRIVER 2
256 µStep
Sequencer
stallGuard2
Enable
Step/Dir
TRINAMIC Motion Control GmbH & Co. KG
Hamburg, Germany
coolStep
TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
2
APPLICATION EXAMPLES: HIGH FLEXIBILITY – MULTIPURPOSE USE
The TMC2041 scores with power density and sensorless homing. It features serial interfaces for advanced
monitoring and configuration options. The small form factor keeps costs down and allows for miniaturized
layouts. Extensive support at the chip, board, and software levels enables rapid design cycles and fast timeto-market with competitive products. High energy efficiency and reliability deliver cost savings in related
systems such as power supplies and cooling.
STEP/DIR
FOR UP TO TWO
STEPPER MOTORS
Step/Dir
High-Level
Interface
STEP/DIR
CPU
FOR UP TO TWO
SPI or UART
M
TMC2041
STEPPER MOTORS
Step/Dir
High-Level
Interface
CPU
SPI or UART
Step/Dir
M
TMC2041
M
The stepper motor driver
outputs are switched in
parallel. This way, up to
2.2A RMS motors can be
driven.
In this application, a single
CPU controls two motors
using a Step and Direction
interface per motor. It
initially
configures
the
drivers by programming
current
settings
and
chopper, and run and hold
current using either the 4
wire SPI interface, or the
single wire UART interface.
During
operation
the
interface allows access to
status
information
like
stallGuard sensorless load
measurement.
TMC2041-EVAL EVALUATION BOARD
EVALUATION & DEVELOPMENT PLATFORM
The TMC2041-EVAL is part of TRINAMICs universal
Layout for Evaluation
evaluation board system which provides a
convenient handling of the hardware as well as a
user-friendly software tool for evaluation. The
TMC2041 evaluation board system consists of three
parts: STARTRAMPE (base board), ESELSBRÜCKE
(connector board including several test points), and
TMC2041-EVAL.
ORDER CODES
Order code
TMC2041-LA
TMC2041-EVAL
STARTRAMPE
ESELSBRÜCKE
www.trinamic.com
Description
Dual axis step/dir driver, QFN-48
Evaluation board for TMC2041
Baseboard for TMC2041-EVAL and further evaluation boards
Connector board for plug-in evaluation board system
Size [mm2]
7x7
85 x 55
85 x 55
61 x 38
TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
3
TABLE OF CONTENTS
1
PRINCIPLES OF OPERATION
1.1
1.2
1.3
1.4
1.5
2
KEY CONCEPTS
4
CONTROL INTERFACES
4
MOVING AND CONTROLLING THE MOTOR
5
STALLGUARD2 – MECHANICAL LOAD SENSING 5
COOLSTEP – LOAD ADAPTIVE CURRENT CONTROL 5
PIN ASSIGNMENTS
2.1
2.2
3
PACKAGE OUTLINE
SIGNAL DESCRIPTIONS
SAMPLE CIRCUITS
3.1
3.2
3.3
3.4
3.5
3.6
4
STANDARD APPLICATION CIRCUIT
5 V ONLY SUPPLY
ONE MOTOR WITH HIGH CURRENT
EXTERNAL 5V POWER SUPPLY
OPTIMIZING ANALOG PRECISION
DRIVER PROTECTION AND EME CIRCUITRY
SPI INTERFACE
4.1
4.2
4.3
5
DATAGRAM STRUCTURE
CRC CALCULATION
UART SIGNALS
ADDRESSING MULTIPLE SLAVES
GENERAL CONFIGURATION REGISTERS
CURRENT SETTING
MOTOR DRIVER REGISTERS
15
18
20
20
21
24
26
27
32
SENSE RESISTORS
33
8.1
8.2
8.3
SPREADCYCLE
CHOPPER
CLASSIC CONSTANT OFF TIME CHOPPER
RANDOM OFF TIME
34
35
38
39
DRIVER DIAGNOSTIC FLAGS
40
TEMPERATURE MEASUREMENT
SHORT TO GND PROTECTION
OPEN LOAD DIAGNOSTICS
40
40
40
9.1
9.2
9.3
STALLGUARD2 LOAD MEASUREMENT
10.1
10.2
TUNING STALLGUARD2 THRESHOLD SGT
STALLGUARD2 UPDATE RATE AND FILTER
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10.3
10.4
10.5
11
11.1
11.2
11.3
12
DETECTING A MOTOR STALL
HOMING WITH STALLGUARD
LIMITS OF STALLGUARD2 OPERATION
COOLSTEP OPERATION
USER BENEFITS
SETTING UP FOR COOLSTEP
TUNING COOLSTEP
STEP/DIR INTERFACE
12.1
12.2
12.3
44
44
44
45
45
45
47
48
TIMING
48
CHANGING RESOLUTION
49
MICROPLYER STEP INTERPOLATOR AND STAND
STILL DETECTION
49
13
QUICK CONFIGURATION GUIDE
51
14
GETTING STARTED
53
14.1
INITIALIZATION EXAMPLES
53
15
EXTERNAL RESET
54
16
CLOCK OSCILLATOR AND CLOCK INPUT
54
16.1
16.2
16.3
USING THE INTERNAL CLOCK
USING AN EXTERNAL CLOCK
CONSIDERATIONS ON THE FREQUENCY
54
54
54
17
ABSOLUTE MAXIMUM RATINGS
55
18
ELECTRICAL CHARACTERISTICS
55
18.1
18.2
23
CURRENT SETTING
SPREADCYCLE AND CLASSIC CHOPPER
10
10
11
12
12
13
13
18
7.1
9
10
UART SINGLE WIRE INTERFACE
6.1
6.2
6.3
8
7
7
15
16
17
REGISTER MAPPING
7
7
SPI DATAGRAM STRUCTURE
SPI SIGNALS
TIMING
5.1
5.2
5.3
5.4
6
4
18.3
19
LAYOUT CONSIDERATIONS
19.1
19.2
19.3
19.4
19.5
20
OPERATIONAL RANGE
DC CHARACTERISTICS AND TIMING
CHARACTERISTICS
THERMAL CHARACTERISTICS
EXPOSED DIE PAD
WIRING GND
SUPPLY FILTERING
SINGLE DRIVER CONNECTION
LAYOUT EXAMPLE
PACKAGE MECHANICAL DATA
20.1
20.2
DIMENSIONAL DRAWINGS
PACKAGE CODES
55
56
59
60
60
60
60
60
61
62
62
62
21
DISCLAIMER
63
22
ESD SENSITIVE DEVICE
63
23
TABLE OF FIGURES
64
41
24
REVISION HISTORY
65
42
44
25
REFERENCES
65
TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
+VM
VS
+VM
VCP
charge pump
100n
VSA
5VOUT
100n
4.7µ
Step/Dir interface
100n
DRV_ENN
Optional use lower
voltage down to 6V
DIR1
CPI
22n
STEP1
Principles of Operation
CPO
1
4
O1A1
Full Bridge A
5V Voltage
regulator
O1A2
Sequencer &
Microplyer
2R2
VCC
Driver 1
+VIO
stepper
motor #1
N
stepper
motor #2
O1B2
R1A
BR1B
R1B
TMC2041
VS
Single wire
interface
+VM
SWIOP
N
BR1A
SPI interface
NEXTADDR
SWION
S
O1B1
Full Bridge B
470n
CSN/IO0
SCK/IO1
SDI/IO2
SDO
100µF
100n
O2A1
Full Bridge A
SW_SEL
O2A2
Sequencer &
Microplyer
Driver 2
O2B1
Full Bridge B
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
S
O2B2
CLK_IN
BR2A
Step/Dir interface
R2A
VCC_IO
BR2B
R2B
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
DIR2
STEP2
TST_MODE
Figure 1.1 Basic application and block diagram
The TMC2041 driver chip is a highly integrated step & direction stepper driver for two stepper motors.
The driver, chopper logic, and a 256 microstep sequencer are integrated into the TMC2041. It is pin
compatible to the TMC5041 and TMC5072, which provide internal ramping. The TMC2041 offers a
number of unique enhancements over similar products. It features automatic standstill current
reduction and coolStep for enhanced motor efficiency and provides stallGuard2 for sensorless homing.
1.1 Key Concepts
The TMC2041 implements several advanced features which are exclusive to TRINAMIC products. These
features contribute toward greater precision, greater energy efficiency, higher reliability, smoother
motion, and cooler operation in many stepper motor applications.
spreadCycle™
High-precision chopper algorithm available as an alternative to the traditional
constant off-time algorithm.
stallGuard2™
High-precision load measurement using the back EMF on the motor coils.
coolStep™
Load-adaptive current control which reduces energy consumption by as much as
75%.
In addition to these performance enhancements, TRINAMIC motor drivers offer safeguards to detect
and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage
conditions for enhancing safety and recovery from equipment malfunctions.
1.2 Control Interfaces
The TMC2041 supports both, an SPI and a UART based single wire interface with CRC checking.
Selection of the actual interface is done via the configuration pin SW_SEL, which can be hardwired to
GND or VCC_IO depending on the desired interface. From a software point of view the TMC2041 is a
peripheral with a number of control and status registers. Most of them can either be written only or
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
5
read only. Some of the registers allow both read and write access. In case read-modify-write access is
desired for a write only register, a shadow register can be realized in master software.
1.2.1
SPI Interface
The SPI interface is a bit-serial interface synchronous to a bus clock. For every bit sent from the bus
master to the bus slave another bit is sent simultaneously from the slave to the master.
Communication between an SPI master and the TMC2041 slave always consists of sending one 40-bit
command word and receiving one 40-bit status word.
The SPI command rate typically is a few commands per complete motor motion.
1.2.2
UART Interface
The single wire interface allows differential operation similar to RS485 (using SWIOP and SWION) or
single wire interfacing (leaving open SWION). It can be driven by any standard UART. No baud rate
configuration is required. An optional ring mode allows chaining of slaves to optimize interfacing for
applications with regularly distributed drives.
1.3 Moving and Controlling the Motor
1.3.1
STEP/DIR Interface
Each motor is controlled by a step and direction input. Active edges on the STEP input can be rising
edges or both rising and falling edges as controlled by another mode bit (DEDGE). Using both edges
cuts the toggle rate of the STEP signal in half, which is useful for communication over slow interfaces
such as optically isolated interfaces. On each active edge, the state sampled from the DIR input
determines whether to step forward or back. Each step can be a fullstep or a microstep, in which
there are 2, 4, 8, 16, 32, 64, 128, or 256 microsteps per fullstep. During microstepping, a step impulse
with a low state on DIR increases the microstep counter and a high decreases the counter by an
amount controlled by the microstep resolution. An internal table translates the counter value into the
sine and cosine values which control the motor current for microstepping.
1.4 stallGuard2 – Mechanical Load Sensing
stallGuard2 provides an accurate measurement of the load on the motor. It can be used for stall
detection as well as other uses at loads below those which stall the motor, such as coolStep loadadaptive current reduction. This gives more information on the drive allowing functions like
sensorless homing and diagnostics of the drive mechanics.
1.5 coolStep – Load Adaptive Current Control
coolStep drives the motor at the optimum current. It uses the stallGuard2 load measurement
information to adjust the motor current to the minimum amount required in the actual load situation.
This saves energy and keeps the components cool.
Benefits are:
- Energy efficiency
- Motor generates less heat
- Less or no cooling
- Use of smaller motor
power consumption decreased up to 75%
improved mechanical precision
improved reliability
less torque reserve required → cheaper motor does the job
Figure 1.2 shows the efficiency gain of a 42mm stepper motor when using coolStep compared to
standard operation with 50% of torque reserve. coolStep is enabled above 60RPM in the example.
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
6
0,9
Efficiency with coolStep
0,8
Efficiency with 50% torque reserve
0,7
0,6
0,5
Efficiency
0,4
0,3
0,2
0,1
0
0
50
100
150
200
250
300
350
Velocity [RPM]
Figure 1.2 Energy efficiency with coolStep (example)
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
2
7
Pin Assignments
TST_MODE
O1A1
BR1A
O1A2
VS
GNDP
VS
O1B1
BR1B
O1B2
-
VCP
48
47
46
45
44
43
42
41
40
39
38
37
2.1 Package Outline
GND
1
36
CPI
GND
2
35
CSN
3
34
CPO
GND
SCK
4
33
VCC
SDI
5
32
5VOUT
GND
6
31
GNDA
VCC_IO
7
30
VSA
SDO
8
29
DRV_ENN
SWIOP
9
28
STEP1
SWION
10
27
DIR1
CLK
11
26
STEP2
SWSEL
12
25
DIR2
17
18
19
20
21
22
23
24
VS
GNDP
VS
O2B1
BR2B
O2B2
-
NEXTADDR
15
BR2A
O2A2
14
O2A1
16
13
-
TMC 2041-LA
QFN48 7mm x 7mm
0.5 pitch
Figure 2.1 TMC2041 pin assignments.
2.2 Signal Descriptions
Pin
GND
VCC_IO
VSA
Number
6, 34
7
30
Type
GND
GNDA
5VOUT
31
32
GND
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Function
Digital ground pin for IO pins and digital circuitry.
3.3V or 5V I/O supply voltage pin for all digital pins.
Analog supply voltage for 5V regulator – typically supplied with
driver supply voltage. An additional 100nF capacitor to GND (GND
plane) is recommended for best performance.
Analog GND. Tie to GND plane.
Output of internal 5V regulator. Attach 2.2µF or larger ceramic
capacitor to GNDA near to pin for best performance. Use to supply
VCC of chip.
TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
Pin
VCC
Number
33
Type
DIE_PAD
-
GND
8
Function
5V supply input for digital circuitry within chip and charge pump.
Attach 470nF capacitor to GND (GND plane). Typically supplied by
5VOUT. A 2.2Ω resistor is recommended for decoupling noise from
5VOUT. When using an external supply, make sure, that VCC comes
up before or in parallel to 5VOUT or VCC_IO, whichever comes up
later!
Connect the exposed die pad to a GND plane. Provide as many as
possible vias for heat transfer to GND plane.
Table 2.1 Low voltage digital and analog power supply pins
Pin
CPO
Number
35
Type
O(VCC)
CPI
36
I(VCP)
VCP
37
Function
Charge pump driver output. Outputs 5V (GND to VCC) square wave
with 1/16 of internal oscillator frequency.
Charge pump capacitor input: Provide external 22nF or 33nF / 50 V
capacitor to CPO.
Output of charge pump. Provide external 100nF capacitor to VS.
Table 2.2 Charge pump pins
Pin
GND
GND
CSN/IO0
SCK/IO1
SDI/IO2
SDO
Number
1
2
3
4
5
8
Type
I
I
I/O
I/O
I/O
I/O
SWIOP
9
I/O
SWION
10
I/O
CLK
11
I
SWSEL
12
I
NEXTADDR
24
I
DIR2
25
I
STEP2
26
I
DIR1
27
I
STEP1
28
I
DRV_ENN
29
I
TST_MODE
-
48
I
13, 23, 38 N.C.
Function
unused input, tie to GND
unused input, tie to GND
Chip select input of SPI interface, programmable IO in UART mode
Serial clock input of SPI interface, programmable IO in UART mode
Data input of SPI interface, programmable IO in UART mode
Data output of SPI interface (Tristate, enabled with CSN=0), mode
configuration input in UART mode (0 = Normal mode, 1 = Single wire
ring mode – SWIO_P is input, SWIO_N is output)
Single wire I/O (positive). Serial input in ring mode. Multi-purpose
input in SPI mode or encoder 1 N input.
Single wire I/O (negative) for differential mode. Leave open in nondifferential mode when operating at 5V IO voltage or tie to desired
threshold voltage. Serial output in ring mode. Multi-purpose input in
SPI mode or encoder 2 N input.
Clock input. Tie to GND using short wire for internal clock or supply
external clock. The first high signal disables the internal oscillator
until power down.
Interface selection input. Tie to GND for SPI mode, tie to VCC_IO for
single wire (UART) interface mode.
Address increment (if tied high) for single wire (UART) mode. General
purpose input in SPI mode
Right reference switch input for motor 2, optional DIR input for
STEP/DIR operation of motor 2 or encoder 2 B input
Left reference switch input for motor 2, optional STEP input for
STEP/DIR operation of motor 2
Right reference switch input for motor 1, optional DIR input for
STEP/DIR operation of motor 1 or encoder 2 A input
Left reference switch input for motor 1, optional STEP input for
STEP/DIR operation of motor 1
Enable input for motor drivers. The power stage becomes switched
off (all motor outputs floating) when this pin becomes driven to a
high level. Tie to GND for normal operation.
Test mode input. Tie to GND using short wire.
Unused pins – no internal electrical connection. Leave open or tie to
GND for compatibility with future devices.
Table 2.3 Digital I/O pins (all related to VCC_IO supply)
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
Pin
O2A1
BR2A
Number
14
15
Type
O (VS)
O2A2
VS
16
17, 19
O (VS)
GNDP
O2B1
BR2B
18
20
21
GND
O (VS)
O2B2
O1B2
BR1B
22
39
40
O (VS)
O (VS)
O1B1
VS
41
42, 44
O (VS)
GNDP
O1A2
BR1A
43
45
46
GND
O (VS)
O1A1
47
O (VS)
Table 2.4 Power driver pins
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9
Function
Motor 2 coil A output 1
Sense resistor connection for motor 2 coil A. Place sense resistor to
GND near pin.
Motor 2 coil A output 2
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
Power GND. Connect to GND plane near pin.
Motor 2 coil B output 1
Sense resistor connection for motor 2 coil B. Place sense resistor to
GND near pin.
Motor 2 coil B output 2
Motor 1 coil B output 2
Sense resistor connection for motor 1 coil B. Place sense resistor to
GND near pin.
Motor 1 coil B output 1
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
Power GND. Connect to GND plane near pin.
Motor 1 coil A output 2
Sense resistor connection for motor 1 coil A. Place sense resistor to
GND near pin.
Motor 1 coil A output 1
TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
3
10
Sample Circuits
The sample circuits show the connection of the external components in different operation and
supply modes. The connection of the bus interface and further digital signals is left out for clarity.
DIR1
+VM
VS
+VM
VCP
charge pump
100n
VSA
5VOUT
100n
4.7µ
Step/Dir interface
100n
DRV_ENN
Optional use lower
voltage down to 6V
STEP1
CPI
22n
CPO
3.1 Standard Application Circuit
O1A1
Full Bridge A
5V Voltage
regulator
O1A2
Sequencer &
Microplyer
2R2
VCC
Driver 1
+VIO
stepper
motor #1
N
stepper
motor #2
O1B2
R1A
BR1B
SPI interface
R1B
TMC2041
VS
Single wire
interface
+VM
SWIOP
N
BR1A
NEXTADDR
SWION
S
O1B1
Full Bridge B
470n
CSN/IO0
SCK/IO1
SDI/IO2
SDO
100µF
100n
O2A1
Full Bridge A
SW_SEL
O2A2
Sequencer &
Microplyer
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
Driver 2
S
O2B1
Full Bridge B
O2B2
CLK_IN
BR2A
Step/Dir interface
R2A
VCC_IO
BR2B
R2B
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
DIR2
STEP2
TST_MODE
Figure 3.1 Standard application circuit
The standard application circuit uses a minimum set of additional components in order to operate the
motor. Use low ESR capacitors for filtering the power supply which are capable to cope with the
current ripple. The current ripple often depends on the power supply and cable length. The VCC_IO
voltage can be supplied from 5VOUT, or from an external source, e.g. a low drop 3.3V regulator. In
order to minimize linear voltage regulator power dissipation of the internal 5V voltage regulator in
applications where VM is high, a different (lower) supply voltage can be used for VSA, if available. For
example, many applications provide a 12V supply in addition to a higher supply voltage like 24V.
Using the 12V supply for VSA will reduce the power dissipation of the internal 5V regulator to about
37% of the dissipation caused by supply with the full motor voltage. For best motor chopper
performance, an optional R/C-filter de-couples 5VOUT from digital noise cause by power drawn from
VCC.
Basic layout hints
Place sense resistors and all filter capacitors as close as possible to the related IC pins. Use a solid
common GND for all GND connections, also for sense resistor GND. Connect 5VOUT filtering capacitor
directly to 5VOUT and GNDA pin. See layout hints for more details. Low ESR electrolytic capacitors are
recommended for VS filtering.
Attention
In case VSA is supplied by a different voltage source, make sure that VSA does not exceed VS by
more than one diode drop upon power up or power down.
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
11
DIR1
STEP1
CPI
22n
CPO
3.2 5 V Only Supply
+5V
VS
+5V
5VOUT
100n
O1A1
Full Bridge A
5V Voltage
regulator
O1A2
Sequencer &
Microplyer
4.7µ
VCC
Driver 1
SWION
+VIO
stepper
motor #1
BR1A
BR1B
SPI interface
TMC2041
VS
Single wire
interface
N
stepper
motor #2
+5V
SWIOP
N
O1B2
470n
NEXTADDR
S
O1B1
Full Bridge B
CSN/IO0
SCK/IO1
SDI/IO2
SDO
100µF
RS1A
VSA
Step/Dir interface
RS1B
charge pump
DRV_ENN
VCP
100n
100n
O2A1
Full Bridge A
SW_SEL
PP
INT & position
pulse output
Driver 2
O2B1
Full Bridge B
O2B2
CLK_IN
BR2A
VCC_IO
5V
Step/Dir interface
BR2B
VCC_IO
RS2A
INT
Sequencer &
Microplyer
S
RS2B
Optional external
clock 12-16MHz
O2A2
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
DIR2
STEP2
TST_MODE
VCC_IO 3.3V
Figure 3.2 5V only operation
While the standard application circuit is limited to roughly 5.5 V lower supply voltage, a 5 V only
application lets the IC run from a normal 5 V +/-5% supply. In this application, linear regulator drop
must be minimized. Therefore, the major 5 V load is removed by supplying VCC directly from the
external supply. In order to keep supply ripple away from the analog voltage reference, 5VOUT should
have an own filtering capacity and the 5VOUT pin does not become bridged to the 5V supply.
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
12
3.3 One Motor with High Current
DIR1
STEP1
CPI
22n
CPO
The TMC2041 supports double motor current for a single driver by paralleling both power stages. In
order to operate in this mode, activate the flag single_driver in the global configuration register
GCONF. This register can be locked for subsequent write access.
+VM
VS
+VM
100n
100n
O1A1
Full Bridge A
5V Voltage
regulator
O1A2
Sequencer &
Microplyer
4.7µ
VCC
Driver 1
+VIO
SWION
BR1B
SPI interface
TMC2041
VS
Single wire
interface
100n
O2A1
Full Bridge A
SW_SEL
ENC1A/INT
ENC1B/PP
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
high current
stepper motor
+VM
SWIOP
N
O1B2
BR1A
NEXTADDR
S
O1B1
Full Bridge B
CSN/IO0
SCK/IO1
SDI/IO2
SDO
100µF
RS1A
VSA
5VOUT
Step/Dir interface
RS1B
charge pump
DRV_ENN
VCP
100n
O2A2
INT & position
pulse output
Sequencer &
Microplyer
Driver 2
O2B1
Full Bridge B
O2B2
CLK_IN
BR2A
Step/Dir interface
VCC_IO
BR2B
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
DIR2
STEP2
TST_MODE
Figure 3.3 Driving a single motor with high current
3.4 External 5V Power Supply
When an external 5V power supply is available, the power dissipation caused by the internal linear
regulator can be eliminated. This especially is beneficial in high voltage applications, and when
thermal conditions are critical.
3.4.1
Internal Regulator Bridged
In case a clean external 5V supply is available, it can be used for complete supply of analog and
digital part (Figure 3.4). The circuit will benefit from a well regulated supply, e.g. when using a +/-1%
regulator. A precise supply guarantees increased motor current precision, because the voltage at
5VOUT directly is the reference voltage for all internal units of the driver, especially for motor current
control. For best performance, the power supply should have low ripple to give a precise and stable
supply at 5VOUT pin with remaining ripple well below 5mV. Some switching regulators have a higher
remaining ripple, or different loads on the supply may cause lower frequency ripple. In this case,
increase capacity attached to 5VOUT. In case the external supply voltage has poor stability or low
frequency ripple, this would affect the precision of the motor current regulation as well as add
chopper noise.
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
13
Well-regulated, stable
supply, better than +-5%
+5V
VSA
5V Voltage
regulator
5VOUT
4.7µ
10R
VCC
470n
Figure 3.4 Using an external 5V supply to bypass internal regulator
3.5 Optimizing Analog Precision
CPI
22n
CPO
The 5VOUT pin is used as an analog reference for operation of the TMC2041. Performance will degrade
when there is voltage ripple on this pin. Most of the high frequency ripple in a TMC2041 design
results from the operation of the internal digital logic. The digital logic switches with each edge of
the clock signal. Further, ripple results from operation of the charge pump, which operates with
roughly 1 MHz and draws current from the VCC pin. In order to keep this ripple as low as possible, an
additional filtering capacitor can be put directly next to the VCC pin with vias to the GND plane giving
a short connection to the digital GND pins (pin 6 and pin 34). Analog performance is best, when this
ripple is kept away from the analog supply pin 5VOUT, using an additional series resistor of 2.2 Ω. The
voltage drop on this resistor will be roughly 100 mV (IVCC * R).
+VM
VCP
charge pump
100n
VSA
5VOUT
100n
5V Voltage
regulator
GNDA
4.7µ
2R2
VCC
470n
Figure 3.5 RC-Filter on VCC for reduced ripple
3.6 Driver Protection and EME Circuitry
Some applications have to cope with ESD events caused by motor operation or external influence.
Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset
or even a destruction of the motor driver, depending on their energy. Especially plastic housings and
belt drive systems tend to cause ESD events. It is best practice to avoid ESD events by attaching all
conductive parts, especially the motors themselves to PCB ground, or to apply electrically conductive
plastic parts. In addition, the driver can be protected up to a certain degree against ESD events or live
plugging / pulling the motor, which also causes high voltages and high currents into the motor
connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the dV/dt caused
by ESD events. Larger capacitors will bring more benefit concerning ESD suppression, but cause
additional current flow in each chopper cycle, and thus increase driver power dissipation, especially at
high supply voltages. The values shown are example values – they might be varied between 100pF
and 1nF. The capacitors also dampen high frequency noise injected from digital parts of the circuit
and thus reduce electromagnetic emission. A more elaborate scheme uses LC filters to de-couple the
driver outputs from the motor connector. Varistors in between of the coil terminals eliminate coil
overvoltage caused by live plugging. Optionally protect all outputs by a varistor against ESD voltage.
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
14
470pF
100V
OA1
Full Bridge A
OA1
OA2
S
N
stepper
motor
Full Bridge A
50Ohm @
100MHz
V1A
V1
OA2
50Ohm @
100MHz
470pF
100V
BRA
Driver
RSA
470pF
100V
S
N
stepper
motor
V1B
470pF
100V
Driver
100nF
16V
470pF
100V
OB1
Full Bridge B
OB1
Full Bridge B
OB2
50Ohm @
100MHz
V2A
V2
OB2
50Ohm @
100MHz
470pF
100V
BRB
RSB
100nF
16V
470pF
100V
Fit varistors to supply voltage
rating. SMD inductivities
conduct full motor coil
current.
Figure 3.6 Simple ESD enhancement and more elaborate motor output protection
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V2B
470pF
100V
Varistors V1 and V2 protect
against inductive motor coil
overvoltage.
V1A, V1B, V2A, V2B:
Optional position for varistors
in case of heavy ESD events.
TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
4
15
SPI Interface
4.1 SPI Datagram Structure
The TMC2041 uses 40 bit SPI™ (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams
for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are
typically able to communicate using integer multiples of 8 bit. The NCS line of the TMC2041 must be
handled in a way, that it stays active (low) for the complete duration of the datagram transmission.
Each datagram sent to the device is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set. Each register is accessed via 32
data bits even if it uses less than 32 data bits.
For simplification, each register is specified by a one byte address:
- For a read access the most significant bit of the address byte is 0.
- For a write access the most significant bit of the address byte is 1.
Most registers are write only registers, some can be read additionally, and there are also some read
only registers.
SPI DATAGRAM STRUCTURE
MSB (transmitted first)
40 bit
39 ...
8 bit address
8 bit SPI status
... 0
32 bit data
39 ... 32
to TMC2041:
RW + 7 bit address
from TMC2041:
8 bit SPI status
W
39 / 38 ... 32
38...32
LSB (transmitted last)
31 ... 0
8 bit data
8 bit data
31 ... 24
31...28
27...24
23 ... 16
23...20
19...16
8 bit data
8 bit data
15 ... 8
15...12
7 ... 0
11...8
7...4
3...0
3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
4.1.1
Selection of Write / Read (WRITE_notREAD)
The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI
datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a
WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to
be added to the address for a write access. The SPI interface always delivers data back to the master,
independent of the W bit. The data transferred back is the data read from the address which was
transmitted with the previous datagram, if the previous access was a read access. If the previous
access was a write access, then the data read back mirrors the previously received write data. So, the
difference between a read and a write access is that the read access does not transfer data to the
addressed register but it transfers the address only and its 32 data bits are dummies, and, further the
following read or write access delivers back the data read from the address transmitted in the
preceding read cycle.
A read access request datagram uses dummy write data. Read data is transferred back to the master
with the subsequent read or write access. Hence, reading multiple registers can be done in a
pipelined fashion.
Whenever data is read from or written to the TMC2041, the MSBs delivered back contain the SPI
status, SPI_STATUS, a number of eight selected status bits.
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
16
Example:
For a read access to the register (XACTUAL) with the address 0x21, the address byte has to
be set to 0x21 in the access preceding the read access. For a write access to the register
(VACTUAL), the address byte has to be set to 0x80 + 0x22 = 0xA2. For read access, the data
bit might have any value (-). So, one can set them to 0.
action
data sent to TMC2041
read CHOPCONF1
0x6C00000000
read CHOPCONF1
0x6C00000000
write CHOPCONF1:= 0x00ABCDEF 0xEC00ABCDEF
write CHOPCONF1:= 0x00123456 0xEC00123456
data received from TMC2041
0xSS & unused data
0xSS & CHOPCONF1
0xSS & CHOPCONF1
0xSS00ABCDEF
*)S: is a placeholder for the status bits SPI_STATUS
4.1.2
SPI Status Bits Transferred with Each Datagram Read Back
New status information becomes latched at the end of each access and is available with the next SPI
transfer.
SPI_STATUS – status flags transmitted with each SPI access in bits 39 to 32
Bit
7
6
5
4
3
2
1
0
Name
Comment
driver_error(2)
driver_error(1)
reset_flag
reserved (0)
reserved (0)
reserved (0)
reserved (0)
reserved (0)
GSTAT[2] – 1: Signals driver 2 driver error (clear by reading GSTAT)
GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT)
GSTAT[0] – 1: Signals, that a reset has occurred (clear by reading GSTAT)
4.1.3
Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values, some represent integer
values (signed) as two’s complement numbers, single bits or groups of bits are represented as single
bits respectively as integer groups.
4.2 SPI Signals
The SPI bus on the TMC2041 has four signals:
- SCK – bus clock input
- SDI – serial data input
- SDO – serial data output
- CSN – chip select input (active low)
The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 40 SCK clock cycles is required for a bus transaction with the TMC2041.
If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a
40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge
of CSN are recognized as the command.
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
17
4.3 Timing
The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to
half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.
CSN
tCC
tCL
tCH
tCH
tCC
SCK
tDU
SDI
bit39
tDH
bit38
bit0
tDO
SDO
tZC
bit39
bit38
bit0
Figure 4.1 SPI timing
Hint
Usually this SPI timing is referred to as SPI MODE 3
SPI interface timing
Parameter
SCK valid before or after change
of CSN
AC-Characteristics
clock period: tCLK
Symbol
tCC
fSCK
fSCK
assumes
synchronous CLK
tCSH
SCK low time
tCL
SCK high time
tCH
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Min
Typ
Max
10
*) Min time is for
synchronous CLK
with SCK high one
tCH before CSN high
only
*) Min time is for
synchronous CLK
only
*) Min time is for
synchronous CLK
only
assumes minimum
OSC frequency
CSN high time
SCK frequency using internal
clock
SCK frequency using external
16MHz clock
SDI setup time before rising
edge of SCK
SDI hold time after rising edge
of SCK
Data out valid time after falling
SCK clock edge
SDI, SCK and CSN filter delay
time
Conditions
Unit
ns
tCLK*)
>2tCLK+10
ns
tCLK*)
>tCLK+10
ns
tCLK*)
>tCLK+10
ns
4
MHz
8
MHz
tDU
10
ns
tDH
10
ns
tDO
no capacitive load
on SDO
tFILT
rising and falling
edge
12
20
tFILT+5
ns
30
ns
TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
5
18
UART Single Wire Interface
The UART single wire interface allows the control of the TMC2041 with any microcontroller UART. It
shares transmit and receive line like an RS485 based interface. Data transmission is secured using a
cyclic redundancy check, so that increased interface distances (e.g. over cables between two PCBs) can
be bridged without the danger of wrong or missed commands even in the event of electro-magnetic
disturbance. The automatic baud rate detection and an advanced addressing scheme make this
interface easy and flexible to use.
5.1 Datagram Structure
5.1.1
Write Access
UART WRITE ACCESS DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
0 … 63
8 bit slave
RW + 7 bit
sync + reserved
32 bit data
address
register addr.
56…63
63
…
CRC
56
55
…
24…55
data bytes 3, 2, 1, 0
(high to low byte)
24
1
23
…
16…23
register
address
16
15
3
…
2
SLAVEADDR
8
1
7
0
6
1
5
0
8…15
Reserved (don’t cares
but included in CRC)
4
1
0
0…7
CRC
A sync nibble precedes each transmission to and from the TMC2041 and is embedded into the first
transmitted byte, followed by an addressing byte. Each transmission allows a synchronization of the
internal baud rate divider to the master clock. The actual baud rate is adapted and variations of the
internal clock frequency are compensated. Thus, the baud rate can be freely chosen within the valid
range. Each transmitted byte starts with a start bit (logic 0, low level on SWIOP) and ends with a stop
bit (logic 1, high level on SWIOP). The bit time is calculated by measuring the time from the
beginning of start bit (1 to 0 transition) to the end of the sync frame (1 to 0 transition from bit 2 to
bit 3). All data is transmitted byte wise. The 32 bit data words are transmitted with the highest byte
first.
A minimum baud rate of 9000 baud is permissible, assuming 20 MHz clock (worst case for low baud
rate). Maximum baud rate is fCLK/16 due to the required stability of the baud clock.
The slave address is determined by the register SLAVEADDR. If the external address pin NEXTADDR is
set, the slave address becomes incremented by one.
The communication becomes reset if a pause time of longer than 63 bit times between the start bits
of two successive bytes occurs. This timing is based on the last correctly received datagram. In this
case, the transmission needs to be restarted after a failure recovery time of minimum 12 bit times of
bus idle time. This scheme allows the master to reset communication in case of transmission errors.
Any pulse on an idle data line below 16 clock cycles will be treated as a glitch and leads to a timeout
of 12 bit times, for which the data line must be idle. Other errors like wrong CRC are also treated the
same way. This allows a safe re-synchronization of the transmission after any error conditions.
Remark, that due to this mechanism, an abrupt reduction of the baud rate to less than 15 percent of
the previous value is not possible.
Each accepted write datagram becomes acknowledged by the receiver by incrementing an internal
cyclic datagram counter (8 bit). Reading out the datagram counter allows the master to check the
success of an initialization sequence or single write accesses. Read accesses do not modify the
counter.
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
5.1.2
19
Read Access
UART READ ACCESS REQUEST DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
sync + reserved
8 bit slave address
RW + 7 bit register
address
CRC
0...7
8…15
16…23
24…31
31
…
CRC
24
0
23
…
16
register address
15
3
…
2
SLAVEADDR
8
1
7
0
6
1
5
0
4
1
0
Reserved (don’t cares
but included in CRC)
The read access request datagram structure is identical to the write access datagram structure, but
uses a lower number of user bits. Its function is the addressing of the slave and the transmission of
the desired register address for the read access. The TMC2041 responds with the same baud rate as
the master uses for the read request.
In order to ensure a clean bus transition from the master to the slave, the TMC2041 does not
immediately send the reply to a read access, but it uses a programmable delay time after which the
first reply byte becomes sent following a read request. This delay time can be set in multiples of
eight bit times using SENDDELAY time setting (default=8 bit times) according to the needs of the
master. In a multi-slave system, set SENDDELAY to min. 2 for all slaves. Otherwise a non-addressed
slave might detect a transmission error upon read access to a different slave.
UART READ ACCESS REPLY DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
24…55
data bytes 3, 2, 1, 0
(high to low byte)
56…63
…
CRC
56
55
CRC
…
32 bit data
24
0
23
…
15
3
…
2
16…23
register
address
0xFF
8
1
reserved (0)
7
0
6
1
5
0
8…15
4
1
0
0…7
16
sync + reserved
63
0 ...... 63
8 bit slave
RW + 7 bit
address
register addr.
The read response is sent to the master using address code %1111. The transmitter becomes switched
inactive four bit times after the last bit is sent.
Address %11111111 is reserved for read accesses going to the master. A slave cannot use this
address.
ERRATA IN READ ACCESS
A known bug in the UART interface implementation affects read access to registers that change during
the access. While the SPI interface takes a snapshot of the read register before transmission, the UART
interface transfers the register directly MSB to LSB without taking a snapshot. This may lead to
inconsistent data when reading out a register that changes during the transmission. Further, the CRC
sent from the driver may be incorrect in this case (but must not), which will lead to the master
repeating the read access. As a workaround, it is advised not to read out quickly changing registers
like XACTUAL, MSCNT or X_ENC during a motion, but instead first stop the motor or check the
position_reached flag to become active, and read out these values afterwards. If possible, use
X_LATCH and ENC_LATCH for a safe readout during motion (e.g. for homing). As the encoder cannot be
guaranteed to stand still during motor stop, only a dual read access and check for identical result
ensures correct X_ENC read data. Therefore it is advised to use the latching function instead. Use the
vzero and velocity_reached flag rather than reading VACTUAL.
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TMC2041 DATASHEET (Rev. 1.02 / 2017-MAY-16)
20
5.2 CRC Calculation
An 8 bit CRC polynomial is used for checking both read and write access. It allows detection of up to
eight single bit errors. The CRC8-ATM polynomial with an initial value of zero is applied LSB to MSB,
including the sync- and addressing byte. The sync nibble is assumed to always be correct. The
TMC2041 responds only to correctly transmitted datagrams containing its own slave address. It
increases its datagram counter for each correctly received write access datagram.
𝐶𝑅𝐶 = 𝑥 8 + 𝑥 2 + 𝑥 1 + 𝑥 0
SERIAL CALCULATION EXAMPLE
CRC = (CRC
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