X3211

UTC X3211 LINEAR INTEGRATED CIRCUIT FET BIAS CONTROLLER WITH POLARISATION SWITCH AND TONE DETECTION DESCRIPTION The UTC X3211 is designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs, PMR, cellular telephones etc. with a minimum of external components. SSOP20(150mil) FEATURES * Provides bias for GaAs and HEMT FETs * Drives up to three FETs * Dynamic FET protection * Drain current set by external resistor * Polarisation switch for LNBs –supporting zero volt gate switching topology. * 22kHz tone detection for band switching APPLICATIONS *Satellite receiver LNBs * Private mobile radio (PMR) * Cellular telephones PIN CONFIGURATION G1 D1 G2 D2 G3 D3 G ND CNB1 CNB2 N/ C 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC RCAL VPOL FIN N/ C FOUT LOV HB LB CS UB UTC UNISONIC TECHNOLOGIES CO., LTD. 1 QW-R122-004,C UTC X3211 PARAMETER LINEAR INTEGRATED CIRCUIT SYMBOL Vcc ICC ID VIN Topr TStg PD ABSOLUTE MAXIMUM RATINGS VALUE -0.6~12 100 0~15 25 continuous -40~70 -50~85 500 Supply Voltage Supply Current Drain Current (per FET) (set by RCAL ) Input Voltage (VPOL) Operating Temperature Storage Temperature Power Disspation(Ta=25°C) UNIT V mA mA V °C °C mW ELECTRICAL CHARACTERISTICS (Ta = 25 °C,Vcc=5V,ID=10mA, RCAL =33kΩUnless otherwise specified) PARAMETER Supply Voltage Supply Current SYMBOL Vcc ICC TEST CONDITIONS ID1 to ID3=0 ID1 =0, ID2 to ID3=10mA,VPOL=14V ID2=0, ID1 to ID3=10mA,VPOL=15.5V ID1 to ID3=0,ILB=10mA ID1 to ID3=0,IHB=10mA (Internally generated) ISUB =0 ISUB = -200µA CG=4.7nF,CD=10nF CG=4.7nF,CD=10nF MIN 5 TYP 6 25 25 16 16 -3 MAX 10 15 35 35 25 25 -2.5 -2.4 0.02 0.005 800 UNIT V mA mA mA mA mA V V Vpkpk Vpkpk kHz Substrate Voltage Output Noise Drain Voltage Gate Voltage Oscillator Freq VSUB -3.5 END ENG fO 200 350 GATE CHARACTERISTICS PARAMETER Output Current Range Output Voltage Gate 1 Off Low High Output Voltage Gate 2 Off Low High Output Voltage Gate 3 Low High SYMBOL IGO VG1O VG1L VG1H VG2O VG2L VG2H VG3L VG3H TEST CONDITIONS MIN -30 TYP MAX 2000 UNIT µA ID1=0mA, VPOL=14V, IGO1=0µA ID1=12mA, VPOL=15.5V, IGO1=-10µA ID1=8mA, VPOL=15.5V, IGO1=0µA ID2=0mA, VPOL=15.5V, IGO2=0µA ID2=12mA, VPOL=14V, IGO2=-10µA ID2=8mA, VPOL=14V, IGO2=0µA ID3=12mA, IGO3=-10µA ID3=8mA, IGO3=0µA -0.05 -2.7 0.4 -0.05 -2.7 0.4 -3.5 0.4 0 -2.4 0.75 0 -2.4 0.75 -2.9 0.75 0.05 -2 1.0 0.05 -2 1.0 -2 1.0 V V V UTC UNISONIC TECHNOLOGIES CO., LTD. 2 QW-R122-004,C UTC X3211 PARAMETER Current Current Change With Vcc With Tj Drain 1 Change : High Drain 2 Change : High Drain 3 Change : High Voltage Change With Vcc With Tj Leakage Current Drain 1 Drain 2 LINEAR INTEGRATED CIRCUIT SYMBOL ID ΔIDV ΔIDT VD1 VD2 VD3 ΔVDV ΔVDT IL1 IL2 Vcc=5 to12V Tj= -40 to +70°C ID1 =10mA VPOL=15.5V ID2 =10mA VPOL=14V ID3 =10mA Vcc=5 to10V Tj= -40 to +70°C VD1=0.5V, VPOL=14V VD2=0.5V, VPOL=15.5V DRAIN CHARACTERISTICS TEST CONDITIONS MIN 8 TYP 10 0.5 0.05 2.0 2.0 2.0 0.5 50 MAX 12 UNIT mA %/V %/°C V V V %/V ppm 1.8 1.8 1.8 2.2 2.2 2.2 10 10 µA TONE DETECTION CHARACTERISTICS PARAMETER Filter Amplifier Input Bias Current Output Voltage 5 Output Current 5 Voltage Gain Rejection Frequency V Threshold 5 Output Stage Lov Volt.Range Lov Bias Current LB Output Low LB Output High HB Output Low HB Output High SYMBOL TEST CONDITIONS MIN TYP MAX UNIT µA IB VOUT IOUT Gv fR FVT VLOV ILOV VLBL VLBH VHBL VHBH RF1=150kΩ RF1=150kΩ VOUT=1.96V, VFIN=2.1V f=22kHz, VIN=1mV V(AC)IN=1V p/p sq.w6 0.02 1.75 400 1.0 100 -0.5 0.02 -3.5 -0.01 -0.025 2.9 -3.5 -0.01 -0.025 2.9 0.07 1.95 520 46 7.5 0.25 2.05 650 350 Vcc-1.8 1.0 -2.5 0.01 0.025 3.1 -2.5 0.01 0.025 3.1 V µA dB kHz mV p/p V µA V V V V V V V V IL=50mA(LB or HB) VLOV=0 VLOV=0, IL= -10µA, Enable 6 VLOV=3V, IL=0, Enable 7 VLOV=0, IL=10 mA, Disable 6 VLOV=3V, IL=50mA, Disable 7 VLOV=0, IL= -10μA, Disable 6 VLOV=3V, IL=0, Disable 7 VLOV=0, IL=10mA, Enable 6 VLOV=3V, IL=50mA, Enable 7 0.15 -2.75 0 0 3.0 -2.75 0 0 3.0 POLY SWITCH CHARACTERISTICS PARAMETER Input Current Threshold Voltage Switching Speed SYMBOL IPOL VTPOL TSPOL TEST CONDITIONS VPOL=25V (Applied via RPOL=10kΩ) VPOL=25V (Applied via RPOL=10kΩ) VPOL=25V (Applied via RPOL=10kΩ) MIN 10 14 TYP 20 14.75 MAX 40 15.5 100 UNIT µA V ms UTC UNISONIC TECHNOLOGIES CO., LTD. 3 QW-R122-004,C UTC X3211 NOTES: 1. 2. 3. 4. 5. 6. 7. LINEAR INTEGRATED CIRCUIT The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, CNB and CsuB of 47nFare required for this purpose. The characteristics are measured using an external reference resistors RCAL of value 33kΩ wired from pins RCAL to ground. Noise voltage is not measured in production. Noise voltage measurement is made with FETs and gate drain capacitors in place on all outputs. CG,4.7nF,are connected between gate outputs and ground,CD,10nF,are connected between drain outputs and ground. These parameters are linearly related to Vcc These parameters are measured using Test Circuit 1 These parameters are measured using Test Circuit 2 TEST CIRCUIT 1 Vcc + V1 5V DC VPOL FIN Lov FOUT RCAL RCAL 33K R3 150K R2 CF1 470pF CF2 68pF 10K GND CNB1 CNB 47nF V2 + - CNB2 CSUB CSUB 47nF V2 Type Frequency Voltage Characteristics AC source 22kHz 350mV p/p enabled 100mV p/P disabled UTC UNISONIC TECHNOLOGIES CO., LTD. 4 QW-R122-004,C UTC X3211 TEST CIRCUIT 2 LINEAR INTEGRATED CIRCUIT Vcc + V1 5V DC VPOL FIN Lov FOUT RCAL R5 2.0K CF1 470pF CF2 68pF R2 10K R3 150K GND CNB1 CNB 47nF V2 + - CNB2 CSUB CSUB 47nF RCAL 33K V2 Type Frequency Voltage Characteristics AC source 22kHz 350mV p/p enabled 100mV p/P disabled TYPICAL CHARACTERISTICS Vsub v External Load Vcc =5V -0.0 -0.5 Vsub (V) -1.0 -1.5 -2.0 -2.5 -3.0 20 40 60 Rcal (k) 80 100 0 0.2 Vcc =8V Vcc =10V 1.0 Vcc =5V Vcc =6V Note :Operation with load>200μA is not guranteed. JFET Drain Current v Rcal 16 14 Drain Current (mA) 12 10 8 6 4 2 0 0 0.4 0.6 0.8 External Vsub Load (mA) UTC UNISONIC TECHNOLOGIES CO., LTD. 5 QW-R122-004,C UTC X3211 2.2 LINEAR INTEGRATED CIRCUIT 70 60 Open Loop Gain v Frequency Vcc =5V JFET Drain Voltage v Drain Current Drain Voltage (V) 2.1 Open Loop Gain (dB) Vcc =10V 50 40 30 20 10 0 2.0 Vcc =5V Vcc =6V Vcc =8V 1.9 1.8 2 4 6 8 10 12 14 16 100 1k 10k 100k Frequency (Hz) 1M 10M LB/HB Offset Voltage v Load Current Vcc =5V VLOV=0V Open Loop Phase(o) Tamb=70℃ Open Loop Phase v Frequency Vcc =5V 180 150 120 90 60 30 0 50 100 1k 10k 100k Frequency (Hz) 1M 10M 4 LB/HB Offset Voltage (mV) 2 0 -2 -4 -6 -8 0 10 20 Tamb= -40℃ Tamb=25℃ 30 40 Load Current (mA) LB/HB Dropout Voltage v Load Current 2.0 1.9 LB/HB Dropout Voltage (V) 1.8 Tamb= -40℃ 1.7 1.6 1.5 1.4 1.3 1.2 0 10 20 30 Load Current (mA) 40 50 Tamb=70℃ Tamb=25℃ Vcc =5V Fout Voltage (Vpkpk) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 100 1k Filter Response 10k 100k Frequency (Hz) 1M UTC UNISONIC TECHNOLOGIES CO., LTD. 6 QW-R122-004,C UTC X3211 FUNCTIONAL DIAGRAM LINEAR INTEGRATED CIRCUIT + DN ON GN + 20μ A CSUB Negative Supply Gen. + I D Set ID Sense VD Set + - Vcc RCAL RCAL SetS ID GND CSUB CNB1 CNB2 CNB FUNCTIONAL DESCRIPTION The X3211 provides all the bias requirements for external FETs, including the generation of the negative supply required for gate biasing, from the single supply voltage. It contains 3 such stages. The negative rail generator is common to all devices. The drain voltage of the external FET QN is set by the X3211 device to its normal operating voltage. This is determined by the on board VD Set reference, the X3211 provides nominally 2 volts . The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier driving the gate of the FET adjusts the gate voltage of QN so that the drain current taken matches the current called for by an external resistor RCAL. Since the FET is a depletion mode transistor, it is usually necessary to drive its gate negative with respect to ground to obtain the required drain current. To provide this capability powered from a single positive supply, the device includes a low current negative supply generator. This generator uses an internal oscillator and two external capacitors, CNB and CSUB. The following schematic shows the function of the Vpol input. Only one of the two external FETs numberd Q1 and Q2 are powered at any one time, their selection is controlled by the input Vpol. This input is designed to be wired to UTC UNISONIC TECHNOLOGIES CO., LTD. 7 QW-R122-004,C UTC X3211 applied to Vpol. LINEAR INTEGRATED CIRCUIT the power input of the LNB via a high value (10k) resistor. With th input voltage of the LNB set at or below 14V.FET Q2 will be enabled. With the input voltage at or above 15.5V,FET Q1 will be enabled.The disabled FET has its gate driven to 0V and its drain terminal is switched open circuit.FET number Q3 is always active regardless of the voltage D1 Q1 G1 Drain voltage& Current Controller VPOL Input Enable + 20μ A VSUB D2 Q2 G2 Drain voltage& Current Controller 14.75V Reference Enable 20μA VSUB D3 Q3 G3 Drain voltage& Current Controller Enable 20μA VSUB Control input switch function INPUT SENSE