SI91871

Si91871 Vishay Siliconix 300-mA Ultra Low-Noise LDO Regulator With Discharge Option FEATURES D D D D D D D D D D D D D Ultra Low Dropout—300 mV at 300-mA Load Ultra Low Noise—30 mVRMS (10-Hz to 100-kHz) Shutdown Control 130-mA Ground Current at 300-mA Load 1.5% Guaranteed Output Voltage Accuracy 400-mA Peak Output Current Capability Uses Low ESR Ceramic Capacitors Fast Start-Up (50 ms) Fast Line and Load Transient Response (v 30 ms) 1-mA Maximum Shutdown Current Output Current Limit Reverse Battery Protection Built-in Short Circuit and Thermal Protection D Output, Auto-Discharge In Shutdown Mode D Fixed 1.2, 1.8, 2.5, 2.6, 2.8, 3.0, 3.3, 5.0-V Output Voltage Options D MLP33-5 PowerPAKr Package Available APPLICATIONS D Cellular Phones, Wireless Handsets D Noise-Sensitive Electronic Systems, Laptop and Palmtop Computers D PDAs D Pagers D Digital Cameras D MP3 Player D Wireless Modem DESCRIPTION The Si91871 is a 300-mA CMOS LDO (low dropout) voltage regulator. It is the perfect choice for low voltage, low power applications. An ultra low ground current makes this part attractive for battery operated power systems. The Si91871 also offers ultra low dropout voltage to prolong battery life in portable electronics. Systems requiring a quiet voltage source, such as RF applications, will benefit from the Si91871’s ultra low output noise. An external noise bypass capacitor connected to the device’s BP pin can further reduce the noise level. The Si91871 is designed to maintain regulation while delivering 400-mA peak current, making it ideal for systems that have a high surge current upon turn-on. For better transient response and regulation, an active pull-down circuit is built into the Si91871 to clamp the output voltage when it rises beyond normal regulation. The Si91871 automatically discharges the output voltage by connecting the output to ground through a 100-W n-channel MOSFET when the device is put in shutdown mode. The Si91871 features reverse battery protection to limit reverse current flow to approximately 1-mA in the event reversed battery is applied at the input, thus preventing damage to the IC. The Si91871 is available in both the standard and lead (Pb)-free 5-pin MLP33 PowerPAK packages and is specified to operate over the industrial temperature range of −40_C to 85_. TYPICAL APPLICATION CIRCUIT Si91871 VIN 2.2 mF SD SD VIN VOUT VOUT 2.2 mF GND BP 10 nF MLP33-5 Document Number: 72012 S-51147—Rev. F, 20-Jun-05 www.vishay.com 1 Si91871 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings Input Voltage, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −6.0 to 6.5 V VSD (See Detailed Description) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VIN Output Current, IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected Output Voltage, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VIN + 0.3 V Package Power Dissipation, (Pd)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 W Thermal Resistance (qJA)a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55_C/W R(qJA)a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8_C/W Maximum Junction Temperature, TJ(max) . . . . . . . . . . . . . . . . . . . . . . . 150_C Storage Temperature, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 20 mW/_C above TA = 25_C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to 6 V Input Voltage, VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VIN Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 300 mA CIN, COUTa (Ceramic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 mF CEB (Ceramic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.01 mF Operating Ambient Temperature, TA . . . . . . . . . . . . . . . . . . . . −40_C to 85_C Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . −40_C to 125_C Notes a. Maximum ESR of COUT: 0.2 W. SPECIFICATIONS Test Conditions Unless Specified TA = 25_C, VIN = VOUT(nom) + 1 V ( ) IOUT = 1 mA, CIN = 2 mF, COUT = 2.0 mF VSD = 1.5 V Limits −40 to 85_C Parameter Start-Up BP Current Input Voltage Range Symbol IOUT VIN Tempa Room Full Minb Typc 1 Maxb Unit mA ON/OFF = High 2 −2.0 −3.0 −2.5 −3.5 −0.06 0 0 1 45 50 300 65 400 100 130 110 150 400 1 1 1 1 6 2.0 3.0 2.5 3.5 0.18 0.3 0.4 V VOUT w 1.8 V 8 Output Voltage Accuracy 1 mA v IOUT v 300 mA VOUT = 1.2 V, 1.5 V 2V 15 Line Regulation (VOUT v 3 V) Line Regulation (3.0 V < VOUT v3.6 V) Line Regulation (5-V Version) DVIN DVOUT 100 From VIN = VOUT(nom) + 1 V to VOUT(nom) + 2 V VOUT(nom) From VIN = 5.5 V to 6 V IOUT = 1 mA d, Dropout V lt D t Voltaged g (V (VOUT(nom) w 2.6 V) .6 V) Room Full Room Full Full Full Full Room Room Full Room Full Room Full Room Full Room Full Room Full Room Full Room Full Full % %/V IOUT = 50 mA IOUT = 300 mA IOUT = 50 mA IOUT = 300 mA IOUT = 0 mA IOUT = 300 mA IGND IOUT = 0 mA IOUT = 300 mA IO(peak) VOUT w 0.95 x VOUT(nom). tPW = 2 ms 80 90 350 415 100 120 520 570 150 180 200 330 170 200 225 275 mA Document Number: 72012 S-51147—Rev. F, 20-Jun-05 mA mV VIN − VOUT Dropout Voltaged, g (VOUT( 6V OUT(nom) t 2.6 V, VIN w ) 2 V) Ground Pin (VOUT(nom) v 3 V) Currente, g Ground Pin Currente (VOUT(nom) u 3 V) Peak Output current www.vishay.com 2 Si91871 Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified TA = 25_C, VIN = VOUT(nom) + 1 V IOUT = 1 mA, CIN = 2 mF, COUT = 2.0 mF VSD = 1.5 V Limits −40 to 85_C Parameter Symbol Tempa Minb Typc Maxb Unit Output Noise Voltage eN VNOM = 2.6 V, BW = 10 Hz to 100 kHz, 0 mA t IOUT t 300 mA, CNOISE = 0.01 mF f = 1 kHz IOUT = 300 mA f = 10 kHz f = 100 kHz Room Room Room Room Room Room Room Room 30 60 40 30 20 20 150 20 1 700 mV(rms) Ripple Rejection pp j DVOUT/DVIN dB Dynamic Line Regulation Dynamic Load Regulation Thermal Shutdown Junction Temperature Thermal Hysteresis Reverse current Short Circuit Current DVO(line) DVO(load) TJ(S/D) THYST IR ISC VIN : VOUT(nom) + 1 V to VOUT(nom) + 2 V tr/tf = 2 ms, IOUT = 300 mA IOUT : 1 mA to 300 mA, tr/tf = 2 ms mV _C mA mA VIN = −6.0 V VOUT = 0 V Room Room Shutdown Shutdown Supply Current SD Pin Input Voltage Auto Discharge Resistance SD Pin Input Currentf SD Hysteresis VOUT Turn-On Time ICC(off) VSD R_DIS IIN(SD) VHYST(SD) tON VSD (See Figure 1), ILOAD = 100 nA VSD = 1.5 V, VIN = 6 V VSD = 0 V High = Regulator ON (Rising) Low = Regulator OFF (Falling) Room Full Full Room Room Full 100 0.7 150 50 1.5 0.1 1 VIN 0.4 mA V W mA mV ms Notes a. Room = 25_C, Full = −40 to 85_C. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typical values for dropout voltage at VOUT w 2 V are measured at VOUT = 3.3 V, while typical values for dropout voltage at VOUT < 2 V are measured at VOUT = 1.8 V. d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V differential, provided that VIN does not not drop below 2.0 V. e. Ground current is specified for normal operation as well as “drop-out” operation. f. The device’s shutdown pin includes a typical 2-MW internal pull-down resistor connected to ground. g. VOUT(nom) is VOUT when measured with a 1-V differential to VIN. TIMING WAVEFORMS VIN VSD tr v 1 ms 0V tON VNOM 0.95 VNOM VOUT FIGURE 1. Timing Diagram for Power-Up Document Number: 72012 S-51147—Rev. F, 20-Jun-05 www.vishay.com 3 Si91871 Vishay Siliconix PIN CONFIGURATION MLP33-5 PowerPAK SD BP VIN VOUT 2 1 GND GND 5 5 GND GND 1 2 3 4 3 4 Top View Bottom View PIN DESCRIPTION Pin Number 1 2 3 4 5 Name SD BP VIN VOUT GND Function By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to VIN if unused Noise bypass pin. For low noise applications, a 0.01 mF ceramic capacitor should be connected from this pin to ground. Input supply pin. Bypass this pin with a 1-mF ceramic or tantalum capacitor to ground Output voltage. Connect COUT between this pin and ground. Ground pin. For better thermal capability, directly connected to large ground plane ORDERING INFORMATION Standard Part Number Si91871DMP-12-T1 Si91871DMP-18-T1 Si91871DMP-25-T1 Si91871DMP-26-T1 Si91871DMP-28-T1 Si91871DMP-30-T1 Si91871DMP-33-T1 Si91871DMP-50-T1 Lead (Pb)-Free Part Number Si91871DMP-12-E3 Si91871DMP-18-E3 Si91871DMP-25-E3 Si91871DMP-26-E3 Si91871DMP-28-E3 Si91871DMP-30-E3 Si91871DMP-33-E3 Si91871DMP-50-E3 Marking 7112 7118 7125 7126 7128 7130 7133 7150 Voltage 1.2 1.8 2.5 2.6 2.8 3.0 3.3 5.0 Temp. Range Pkg. −40 to 85_C MLP33-5 MLP33 5 www.vishay.com 4 Document Number: 72012 S-51147—Rev. F, 20-Jun-05 Si91871 Vishay Siliconix TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED) 0.30 0.15 0.00 −0.15 −0.30 −0.45 −0.60 −0.75 0 50 100 150 200 250 300 Load Current (mA) V OUT (%) Normalized Output Voltage vs. Load Current VIN = VOUT(nom) + 1 V 0.4 0.2 Normalized VOUT vs. Temperature VIN = VOUT(nom) + 1 V IOUT = 0 mA Output Voltage (%) −0.0 −0.2 −0.4 −0.6 −0.8 −1.0 −40 IOUT = 75 mA IOUT = 150 mA IOUT = 300 mA −15 10 35 60 85 Ambient Temperature (_C) 150 GND Current vs. Load Current VOUT = 3.0 V VIN = 4.0 V 85_C 300 250 No Load GND Pin Current vs. Input Voltage 125 25_C I GND ( m A) I GND ( m A) 100 200 150 100 75 50 50 0 50 100 150 200 250 300 Load Current (mA) 0 2 3 4 5 6 7 Input Voltage (V) −40_C 85_C 25_C −40_C 0 Power Supply Rejection CIN = 1 mF COUT = 1 mF ILOAD = 150 mA VOUT = 3.0 V I SC (mA) 750 725 700 Output Short Circuit Current vs. Temperature VOUT = 2.6 V −20 Gain (dB) −40 675 650 −60 625 −80 10 600 −40 100 1000 10000 100000 1000000 −15 10 35 60 85 Frequency (Hz) Document Number: 72012 S-51147—Rev. F, 20-Jun-05 AmbientTemperature (_C) www.vishay.com 5 Si91871 Vishay Siliconix TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED) 350 300 250 V DROP (mV) 200 150 100 50 0 0 60 120 180 240 300 ILOAD (mA) V OUT (V) Dropout Voltage vs. Load Current VOUT = 3.0 V 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 VIN − VOUT Transfer Characteristic VOUT = 3.0 V 1 2 3 VIN (V) 4 5 6 350 300 250 V DROP (mV) 200 150 100 50 0 −50 Dropout Voltage vs. Temperature VOUT = 3.0 V IOUT = 300 mA Dropout Voltage (mV) 400 350 300 250 200 150 100 50 IOUT = 10 mA IOUT = 0 mA 0 1.0 Dropout Voltage vs. VOUT IOUT = 300 mA IOUT = 150 mA IOUT = 75 mA IOUT = 75 mA IOUT = 150 mA IOUT = 10 mA 1.5 2.0 2.5 3.0 VOUT 3.5 4.0 4.5 5.0 −25 0 25 50 75 100 125 150 Junction Temperature (_C) www.vishay.com 6 Document Number: 72012 S-51147—Rev. F, 20-Jun-05 Si91871 Vishay Siliconix TYPICAL WAVEFORMS Load Transient Response-1 Load Transient Response-2 VOUT 10 mV/div VOUT 10 mV/div ILOAD 100 mA/div ILOAD 100 mA/div 20 ms/div VOUT = 3.0 V COUT = 1 mF ILOAD = 1 to 150 mA trise = 2 msec 20 ms/div VOUT = 3.0 V COUT = 1 mF ILOAD = 150 to 1 mA tfall = 2 msec LineTransient Response-1 LineTransient Respons-2 VOUT 10 mV/div VOUT 10 mV/div VIN 2 V/div VIN 2 V/div 20 ms/div VINSTEP = 4 to 5 V VOUT = 3 V COUT = 1 mF CIN = 1 mF ILOAD = 150 mA trise = 5 msec 20 ms/div VINSTEP = 5 to 4 V VOUT = 3 V COUT = 1 mF CIN = 1 mF ILOAD = 150 mA tfall = 5 msec Document Number: 72012 S-51147—Rev. F, 20-Jun-05 www.vishay.com 7 Si91871 Vishay Siliconix TYPICAL WAVEFORMS Output Noise 10 Noise Spectrum VOUT 200 mV/div Output Spectral Noise Density mV Hz 0.01 4 ms/div VIN = 4 V VOUT = 3 V IOUT = 150 mA CNOISE = 0.01 mF BW = 10 Hz to 100 kHz 10 Hz VIN = 4 V VOUT = 3 V ILOAD = 150 mA CNOISE = 0.01 mF 1 MHz FUNCTIONAL BLOCK DIAGRAM Si91871 VIN Reverse Polarity Protection BP Reference − + VOUT Thermal Sensor Current Limit SD Shutdown Control GND www.vishay.com 8 Document Number: 72012 S-51147—Rev. F, 20-Jun-05 Si91871 Vishay Siliconix DETAILED DESCRIPTION The Si91871 is a low-noise, low drop-out and low quiescent current linear voltage regulator, packaged in a small footprint MLP33-5 package. The Si91871 can supply loads up to 300 mA. As shown in the block diagram, the circuit consists of a bandgap reference error, amplifier, p-channel pass transistor and feedback resistor string. An external bypass capacitor connected to the BP pin reduces noise at the output. Additional blocks, not shown in the block diagram, include a precise current limiter, reverse battery and current protection and thermal sensor. Thermal Overload Protection The thermal overload protection limits the total power dissipation and protects the device from being damaged. When the junction temperature exceeds 150_C, the device turns the p-channel pass transistor off. Reverse Battery Protection The Si91871 has a battery reverse protection circuitry that disconnects the internal circuitry when VIN drops below the GND voltage. There is no current drawn in such an event. When the SD pin is hardwired to VIN, the user must connect the SD pin to VIN via a 100-kW resistor if reverse battery protection is desired. Hardwiring the SD pin directly to the VIN pin is allowed when reverse battery protection is not desired. Noise Reduction An external 10-nF bypass capacitor at BP is used to create a low pass filter for noise reduction. The start-up time is fast, since a power-on circuit pre-charges the bypass capacitor. After the power-up sequence the pre-charge circuit is switched to standby mode in order to save current. It is therefore not recommended to use larger bypass capacitor values than 50 nF. When the circuit is used without a capacitor, stable operation is guaranteed. Auto-Discharge The Si91871 VOUT has an internal 100-W (typ.) discharge path to ground when the SD pin is low. Stability The circuit is stable with only a small output capacitor equal to 6 nF/mA (= 2 mF @ 300 mA). Since the bandwidth of the error amplifier is around 1−3 MHz and the dominant pole is at the output node, the capacitor should be capacitive in this range, i.e., for 150-mA load current, an ESR