VSC8115YA

VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8115 Features • Performs clock and data recovery for 622.08Mb/s (STS-12/OC-12/STM-4) or 155.52Mb/s (STS-3/OC-3/STM-1) NRZ data • Meets Bellcore, ITU and ANSI Specifications for Jitter Performance • 19.44MHz reference frequency LVTTL Input • Lock Detect output pin monitors data run length and frequency drift from the reference clock • Data is Retimed at the Output • Active High Signal Detect LVPECL Input STS-12/STS-3 Multi Rate Clock and Data Recovery Unit • Low-jitter high speed outputs can be configured as either LVPECL or low power LVDS • Low power - 0.188 Watts Typical Power • +3.3V Power Supply • 20 Pin TSSOP Package • Requires One External Capacitor • PLL bypass operation facilitates the board debug process General Description The VSC8115 functions as a clock and data recovery unit for SONET/SDH-based equipment to derive high speed timing signals. The VSC8115 recovers the clock from the scrambled NRZ data operating at 622.08Mb/s (STS-12/OC-12/STM-4) or 155.52Mb/s (STS-3/OC-3/STM-1). After the clock is recovered, the data is retimed using an output flip-flop. Both recovered clock and retimed data outputs can be configured as LVDS or LVPECL signals to facilitate a low-jitter and low power interface. VSC8115 Block Diagram STS12 Divider CAP+ CAPVCO BYPASS DATAIN+/SD LOCKREFN REFCLK 0 1 2 2 Phase/ Freq Detector Loop Filter 2 LOCKDET DATAOUT+/- CLKOUT+/-± G52272-0, Rev. 1.1 9/29/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Target Specification VSC8115 Functional Description The VSC8115 contains an on-chip PLL consisting of a phase/frequency detector, a loop filter using one external capacitor, a LC-based voltage-controlled oscillator (VCO), and a programmable frequency divider. The phase/frequency detector compares the phase relationship between the VCO output and an external 19.44MHz LVTTL reference clock to make coarse adjustment to the VCO block so that its output is held within +500ppm of the reference clock. The use of reference clock minimizes the PLL lock time during power up and provides a stable output clock source in the absence of serial input data. The phase/frequency detector also compares the phase relationship between the VCO output and the serial data input to make fine adjustment to the VCO block. The loop filter converts the phase detector output into a smooth DC voltage. This DC voltage is used as the input to the VCO block whose output frequency is a function of the input voltage. A programmable frequency divider down converts the VCO output signal and provides two modes of operation: 622.08Mb/s mode if STS12 is HIGH, or 155.52Mb/s mode if STS12 is LOW. Lock Detection The VSC8115 features a lock detection for the PLL. The lock detect (LOCKDET) output goes HIGH to indicate that the PLL is locked to the serial data inputs and that valid data and clock are present at the high speed differential outputs. If LOCKDET output is LOW, then either the PLL is forced to lock to the REFCLK input or the VCO has drifted away from the local reference clock by more than 500 ppm. Signal Detection The VSC8115 has a signal detect (SD) input and a lock-to-reference (LOCKREFN) input. The SD pin is a LVPECL input, and the LOCKREFN pin is a LVTTL input. These two control pins are used to indicate a loss of signal condition and they are connected inside the part as shown in Figure 1. If either one of these two inputs goes LOW and BYPASS is LOW, the VSC8115 will enter the loss of signal (LOS) state, and it will hold the DATAOUT+/- output at logic LOW state. During the LOS state, the VSC8115 also will hold the output clock CLKOUT+/- to within +500ppm of the REFCLK. See Table 1. Most of the optical module has a signal detect output. This signal detect output indicates that there is sufficient optical power, and it is typically active HIGH. If the signal detect output on the optical module is LVPECL, it should be connected directly to the SD input on the VSC8115, and the LOCKREFN input needs to be tied HIGH. If the signal detect output is LVTTL, it should be connected directly to the LOCKREFN input, and the SD input needs to be tied HIGH. The SD and LOCKREFN inputs also can be used for other applications when the users need to hold the CLKOUT+/- output to within +500ppm of the reference clock and to force the DATAOUT+/- output to the logic LOW state. PLL Bypass Operation The BYPASS pin is intended for use in production test, and it should be set at logic LOW in the normal operation. If both BYPASS and MODE pins are set at logic HIGH, the VSC8115 will bypass the PLL and will present an inverted version of the REFCLK to the clock output CLKOUT+/-. The REFCLK’s rising edge is used to capture data at DATAIN+/- and transmit data at DATAOUT+/-. This bypass operation can be used to facilitate the board debug process. Page 2 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52272-0, Rev. 1.1 9/29/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8115 STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Figure 1: Control Diagram for Signal Detection and PLL Bypass Operation 2 2 DATAIN+/- DATAOUT+/- PLL Clock (on-chip) REFCLK STS12 BYPASS 0 1 2 CLKOUT+/-± LOCKREFN SD LOS (on-chip) Table 1: Signal Detection and PLL Bypass Operation Control STS12 1 1 1 1 1 0 0 0 0 0 BYPASS 0 0 0 0 1 0 0 0 0 1 LOCKREFN 1 1 0 0 X 1 1 0 0 X SD 1 0 1 0 X 1 0 1 0 X LOS 0 1 1 1 0 0 1 1 1 0 DATAOUT DATIN LOW LOW LOW DATIN DATIN LOW LOW LOW Not Allowed CLKOUT PLL Clock PLL Clock PLL Clock PLL Clock REFCLK PLL Clock PLL Clock PLL Clock PLL Clock Not Allowed G52272-0, Rev. 1.1 9/29/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Target Specification VSC8115 AC Characteristics Table 2: Performance Specifications Parameters VCO Center Frequency CRU’s Reference Clock Frequency Tolerance OC-12/STS12 Capture Range Clock Output Duty Cycle Acquisition Lock Time OC-12/STS-12 LVDS Output Rise & Fall Times CLKOUT+/- Jitter Generation OC-12/STS-12 Jitter Tolerance Min — -250 — 45 — — — Typ 622.08 — ± 500 — — — 0.005 Max — +250 — 55 16 600 0.01 Units MHz ppm ppm % of UI µs ps U.I. Conditions With respect to the fixed reference frequency 20% Minimum transition density Valid REFCLK and device already powered up 10% to 90%, with 100Ω & 5pF capacitive equivalent load No more than 14ps rms jitter on DATAIN+/Sinusoidal input jitter of DATAIN+/- from 250KHz to 5MHz 0.5 — — U.I. Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52272-0, Rev. 1.1 9/29/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8115 STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Jitter Tolerance Jitter Tolerance is the ability of the Clock and Data Recovery Unit to track timing variation in the received data stream. The Bellcore and ITU specifications allow the received optical data to contain jitter. The amount that must be tolerated is a function of the frequency of the jitter. At high frequencies the specifications do not require the VSC8115 to tolerate large amounts, whereas at low frequencies many unit intervals (bit times) of jitter have to be tolerated. Jitter tolerance is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STSN signal versus frequency. The VSC8115 is designed to tolerate this jitter with margin over the specification limits, see Figure 2. The VSC8115 obtains and maintains lock based on the data transition information. When there is no transition on the data stream, the recovered clock frequency will be held to within +500ppm of the reference clock. The VSC8115 can maintain lock over 1000 bits of no switching on data stream. Figure 2: Input Jitter Tolerance Specification JITTER(UI P-P) 150 Bellcore Requirement 24 VSC8115 Typical Jitter Tolerance 15 2.4 1.5 0.6 0.15 10 30 300 25K 250K 1M 2.5M JITTER FREQ(HZ) Jitter Generation Jitter generation is defined as the jitter of the serial clock and serial data outputs while rms jitter is presented to the serial data inputs. Maximum jitter generation is 0.01 U.I. when rms jitter of less than 14ps (OC-12) or 56ps (OC-3) is presented to the serial data inputs. G52272-0, Rev. 1.1 9/29/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Target Specification VSC8115 Retimed Data and Clock Outputs AC Specification As indicated in figure 3, it is recommended that the retimed data output be captured with the rising edge of the clock output. Data valid time is larger for OC-3/STS-3 mode of operation than that of OC-12/STS-12. Data valid time before the output clock’s rising edge is the available setup time (tsu) while the data valid time after the clock’s rising edge is the available hold time (th). Figure 3: Retimed Data and Clock Outputs Timing Diagram DATAOUT+/- CLKOUT+ tsu th Table 3: Retimed Data and Clock Outputs Timing Parameters tsu th Description Minimum Available Setup Time Minimum Available Hold Time STS-12 Operation (622.08MHz) 450 pS 650 pS STS-3 Operation (155.52MHz) 2.0 nS 3.0 nS High Speed Outputs The high speed output buffers, DATAOUT+/- and CLKOUT+/-, can be terminated as either LVDS or LVPECL outputs. If used as LVDS outputs, the transmission lines should be routed with 100-ohm differential impedance, and they need to be terminated at the receive end with a 100-ohm resistor across the differential pair. If used as LVPECL outputs, the transmission line should be 50-ohm terminated with 50-ohm pull down resistors near the receiving end. Page 6 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52272-0, Rev. 1.1 9/29/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8115 DC Characteristics Table 4: LVPECL Single-ended Inputs and Outputs Parameters VIH VIL IIH IIL VOL VOH Description Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Output LOW voltage Output HIGH voltage Min VDD - 1.125 VDD - 2.0 -0.5 -0.5 VDD - 2.0 VDD - 1.25 STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Typ — — — — — — Max VDD - 0.5 VDD - 1.5 10 10 VDD - 1.8 VDD - 0.67 Units V V µA µA V V Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VIN = VDD - 0.5V VIN = VDD - 2.0V 50Ω to (VDD - 2V) 50Ω to (VDD - 2V) Table 5: LVPECL Differential Inputs Parameters VIH VIL ∆VIN Description Input HIGH voltage Input LOW voltage Differential Input Voltage Input HIGH current Input LOW current Min VDD - 1.75 VDD - 2.0 250 -0.5 -0.5 Typ — — — — — Max VDD - 0.45 VDD - 0.7 — 10 10 Units V V mV µA µA Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage — ∆VIN = 0.5V ∆VIN = 0.5V IIH IIL G52272-0, Rev. 1.1 9/29/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Table 6: LVDS Differential Outputs Parameters VOCM ∆VOUT Target Specification VSC8115 Description Common Mode voltage Differential Output Swing Min 1.0 350 Typ 1.35 500 Max 1.7 750 Units V mV Conditions 100Ω PAD to PADN 100Ω PAD to PADN Table 7: LVPECL Differential Outputs Parameters VOCM ∆VOUT Description Common Mode voltage Differential Output Swing Min 1.12 400 Typ - Max 2.0 800 Units V mV Conditions 50Ω to (VDD - 2V) 50Ω to (VDD - 2V) Table 8: LVTTL Inputs Parameters VIH VIL IIH IIL Description Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Min 2.0 0 -50 -50 Typ — — ----- Max VDD 0.8 50 50 Units V V µA µA Conditions — — VIN = 2.7V, VDD=MAX VIN = 0.5V, VDD=MAX Power Dissipation Table 9: Power Supply Currents Parameter IDD PD Power dissipation Description Power supply current from VDD (Typ) 57 188.1 (Max) 80 277 Units mA mW Page 8 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52272-0, Rev. 1.1 9/29/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8115 Absolute Maximum Ratings(1) STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Power Supply Voltage (VDD) Potential to GND.................................................................................-0.5V to +4V DC Input Voltage (LVPECL Inputs)..................................................................................... -0.5V to VDD + 0.5V DC Input Voltage (LVTTL Inputs) ....................................................................................... -0.5V to VDD + 0.5V Output Current (LVDS or LVPECL Outputs).......................................................................................... +/-50mA Case Temperature Under Bias.........................................................................................................-55o to +125oC Storage Temperature .................................................................................................................... -65oC to +150oC Maximum Input ESD (Human Body Model) High Speed Outputs (pins 11, 12, 13, & 14) .................................................................................... 500V All Other Pins ................................................................................................................................. 1500V Note: Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage (VDD)................................................................................................................+3.3V ± 5 % Industrial Operating Ambient Temperature Range under Bias ......................................................... -40o to 85oC Commercial Operating Ambient Temperature Range under Bias ....................................................... 0o to 70oC Package Pin Descriptions Figure 4: Pin Diagram VDDA DATAIN+ DATAINVSSA LOCKDET STS12 REFCLK LOCKREFN VSS VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDA VSSA CAP+ CAPBYPASS SD DATAOUT+ DATAOUTCLKOUT+ CLKOUT- G52272-0, Rev. 1.1 9/29/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Table 10: Pin Identification Signal DATAIN+/DATAOUT+/- Target Specification VSC8115 I/O I O Level LVPECL LVDS/LVPECL Pin Description Receive data in. The high speed output clock (CLKOUT+/-) is recovered from this high speed differential input data. High speed differential data out. This is the retimed version of the receive data input (DATAIN+/-). Can be configured as either LVDS or LVPECL signal. High speed differential clock out This clock is recovered from the receive data input (DATAIN+/-). Can be configured as either LVDS or LVPECL signal. STS-12 or STS-3 mode selection. Set HIGH to select the STS-12 operation. Set LOW to select the STS-3 operation. Lock to REFCLK input. When set LOW, it holds the CLKOUT+/output to within +500ppm of the REFCLK input, and it forces the DATAOUT+/- output to the LOW state. Signal Detect. SD should be connected to the SD output on the optical module. SD is active HIGH. When SD is set HIGH, it means that there is sufficient optical power. When SD is set LOW to indicate loss of signal condition, the CLKOUT+/- output signal will be held to within +500ppm of the REFCLK input; in additions, the DATAOUT+/- will be held in the LOW state. 19.44 MHz local reference clock input for the CRU. REFCLK is used for the PLL phase adjustment during power up, and it also serves as a stable clock source in the absence of serial input data. Active HIGH to indicate that PLL is locked to serial data input, and valid clock and data are present at the serial outputs (DATAOUT+/and CLKOUT+/-). The LOCKDET will go inactive under the following conditions: (1). If SD is set LOW. (2). If LOCKREFN is set LOW. (3). If the VCO has drifted away from the local reference clock REFCLK by more than 500 ppm. Used for production test. Set to VSS for normal operation. External loop filter pins. The loop filter capacitor should be connected to these pins. The capacitor value should be 1.0uF +10% tolerance. +3.3V Power Supply for low speed I/O’s and on-chip digital CMOS blocks. Ground pin for low speed I/O’s and on-chip digital CMOS blocks +3.3V Power Supply for high speed I/O’s and on-chip PLL blocks. Ground pins for high speed I/O’s and on-chip PLL blocks. CLKOUT+/STS12 LOCKREFN O I I LVDS/LVPECL LVTTL LVTTL SD I LVPECL REFCLK I LVTTL LOCKDET O LVPECL BYPASS CAP+/CAPVDD VSS VDDA VSSA I I LVTTL Analog +3.3V GND +3.3V GND Page 10 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52272-0, Rev. 1.1 9/29/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8115 Package Information TSSOP Package Drawings Key A A1 A2 aaa b b1 bbb c c1 E1 e E L θ STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Min Nom Max 1.10 0.15 0.95 0.30 0.25 0.20 0.16 4.50 − 0.05 0.85 0.19 0.19 0.09 0.09 4.30 − − 0.90 0.076 − 0.22 0.10 − 0.127 4.40 0.65 BSC 6.40 BSC 0.50 0° 0.60 − 0.70 8° G52272-0, Rev. 1.1 9/29/00 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION STS-12/STS-3 Multi Rate Clock and Data Recovery Unit Target Specification VSC8115 Package Thermal Characteristics The VSC8115 is packaged in a Thin Shrink Small Outline Package (TSSOP). This package conforms to JEDEC package outline standards. It has hi-conductivity copper lead frames and a very low-stress mold compound. The junction to case thermal resistance is 80oC/W for multi-layer PCB applications and 126oC/W for single-layer PCB applications. The air flow versus thermal resistance relationship for multi-layer PCB applications is shown in Table 11. Table 11: Theta Case to Ambient versus Air Velocity Case to Air Thermal Resistance (oC/W) 55.0 52.0 49.0 46.0 Ta (Ambient Temperature) Range (oC) YA (0oC to 75oC ) Tcase 15.4 14.6 13.7 12.9 to to to to 59.6 60.4 61.3 62.1 Air Velocity (LFPM) 0 100 200 400 YA1 (0oC to 103oC ) Tcase 15.4 14.6 13.7 12.9 to to to to 87.6 88.4 89.3 90.1 YA2 (-40oC to 85oC ) Tcase -55.4 -54.6 -53.7 -52.9 to to to to 69.6 70.4 71.3 72.1 Ordering Information The order number for this product are: Part Number VSC8115YA: VSC8115YA1 VSC8115YA2 Device Type STS-12/STS-3 Multi-Rate Clock and Data Recovery Unit in a 20 Pin TSSOP Commercial Temperature, 0°C ambient to 70°C case STS-12/STS-3 Multi-Rate Clock and Data Recovery Unit in a 20 Pin TSSOP Extended Temperature, 0°C ambient to 110°C case STS-12/STS-3 Multi-Rate Clock and Data Recovery Unit in a 20 Pin TSSOP Industrial Temperature, -40°C ambient to 85°C case Notice This document contains information about a proposed product during its design phase of development and is subject to change without notice at any time. All features and specification are design goals only. Please contact Vitesse Semiconductor to obtain the latest product status and most recent versions of this specification. Warning Vitesse Semiconductor Corporation’s product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. Page 12 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 G52272-0, Rev. 1.1 9/29/00