W83792AD/D W83792AG/G Winbond H/W Monitoring IC (CSB Version)
Date :2006 Apr. Revision: 0.9
W83792AD/AG/D/G
W83792AD/D Data Sheet Revision History
PAGES DATES VERSION WEB VERSION MAIN CONTENTS
1 2 3 4 5 6 7 11 20 39 45 48 5-6 11 70-72 12-34
Aug-27-2003 Aug-27-2003 Sep-12-2003 Sep-16-2003 Nov-06-2003 Jan-05-2004 Dec-13-2004 0.6 0.6.1. 0.7 0.82 0.83
N/A N/A N/A N/A N/A N/A N/A
Move Low Bit I/II to AEh and AFh Add Description of ASF Severity/Offset Update register Update Application circuit Add the part of “Function Description” Combining with W83792D and W83792AD in one datasheet. Move Low Bit I/II to 3Eh and 3Fh Add description on Voltage translation. The Deletion of Vin4 4.096V(Voltage mode) Modify Monitor negative voltage Update voltage convert formula Modify Device Version ID 13h for C version. Modify Temperature Offset Attribute R/W Modify the W83792AD/D pin outputs define for BSA version. PIN25 and PIN26 pins are High active for Thermtrip. PIN35 is VCOREB/VIN4. Modify the PIN35 descriptions. VCOREB input detect range is 0~2.048V and Vin4 is 0~4.096V. Added the PIN37 VREF reference voltage is equal to 3.6V. Modify the monitor the negative voltage for VREF equals 3.6V. Modify Device Version ID 11h for B version CR [49h] and Pin control register. CR [4Bh] bit7 Modify Diode Selection Register CR[59h] power on value. Modify Low Bit I/II to AEh and AFh. The voltage Calculation with Low Bit I/II to AEh and AFh Modify top marking for the BSA version. Updated application circuits.
8
Mar-01-2005
0.85
N/A
20 9 45 47 39 88 90-97 Nov-10-2005 0.86 N/A
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Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
W83792AD/D Data Sheet Revision History, continued
PAGES
DATES
VERSION
WEB VERSION
MAIN CONTENTS
5~6
10 10 10 40 35 83-90 Apr-26-2006 0.9 N/A
Modify the W83792AD/D pin outputs define for CSB version. PIN25 and PIN26 pins are low active for Thermtrip. PIN35 is VCOREB. Modify the PIN35 descriptions. VCOREB input detect range is 0~2.048V and Vin4 is deleted. Added the PIN37 VREF description. Reference voltage is equal to 2.048V. Modify Device Version ID 13h for C version. Modify Low Bit I/II to 3Eh and 3Fh. Updated application circuits. Add Pb-free package
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W83792AD/AG/D/G
Table of Contents1. 2. GENERAL DESCRIPTION .............................................................................................................. 1 FEATURES...................................................................................................................................... 2 2.1 2.2 2.3 2.4 2.5 2.6 3. 4. 5. VCORE Monitoring Items ...................................................................................................... 2 Monitoring Items .................................................................................................................... 2 Address Resolution Protocol (ARP) and Alert-Standard Format (ASF 2.0).......................... 2 Actions Enabling.................................................................................................................... 2 General.................................................................................................................................. 2 Package................................................................................................................................. 3
KEY SPECIFICAITON ..................................................................................................................... 3 BLOCK DIAGRAM........................................................................................................................... 4 PIN CONFIGURATION.................................................................................................................... 5 5.1 5.2 W83792AD/AG ...................................................................................................................... 5 W83792D/G........................................................................................................................... 6 Pin Type Description ............................................................................................................. 7 Pin Description List................................................................................................................ 7 General Description............................................................................................................. 12 Access Interface .................................................................................................................. 12 The first serial bus access timing ........................................................................................ 12 Address Resolution Protocol (ARP) Introduction ................................................................ 13 ASF (Alert Standard Format) Introduction........................................................................... 15
7.5.1 Platform Event Trap (PET) ................................................................................................... 16 Monitor over 4.096V voltage:................................................................................................ 18 Monitor negative voltage: ..................................................................................................... 19 Fan speed count................................................................................................................... 20 Fan speed control................................................................................................................. 21 Smart FanTM I Control ......................................................................................................... 23 Smart FanTM II Control ........................................................................................................ 24 SMI# interrupt for W83792D/G Voltage ................................................................................ 26 SMI# interrupt for W83792D/G Fan...................................................................................... 26 SMI# interrupt for W83792D/G temperature sensor 1/2/3 .................................................... 26 Over-Temperature (OVT#) for W83792D temperature sensor 1/2/3 .................................... 27
6.
PIN DESCRIPTION ......................................................................................................................... 7 6.1 6.2
7.
FUNCTION DECRIPPTION........................................................................................................... 12 7.1 7.2 7.3 7.4 7.5 7.6
Analog Inputs....................................................................................................................... 18
7.6.1 7.6.2
7.7
FAN Speed Count and FAN Speed Control ........................................................................ 20
7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7 7.7.8
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Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
8. CONTROL AND STATUS REGISTER.......................................................................................... 29 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Watch Dog Timer Registers --- Index 01h-04h ................................................................... 29 VRM Tolerance Registers ⎯ Index 12h-13h (Bank 0)........................................................ 30 VID Control/Status Registers ⎯ Index 14h-18h (Bank 0) ................................................... 31 GPIO Control/Status Register ⎯ Index 1A~1Eh (Bank 0) .................................................. 33 VRM Output Control ---- Index 1F(Bank 0).......................................................................... 34 Value RAM ⎯ Index 20h- 2Ah AEh AFh (Bank 0) .............................................................. 35 Limit RAM ⎯ Index 2Bh- 2Dh (Bank 0)............................................................................... 36 Configuration Register ⎯ Index 40h (Bank 0)..................................................................... 37 Interrupt Status Registers ⎯ Index 41h 42h 9Bh(Bank 0) .................................................. 38
8.10 SMI#/IRQ Mask Registers ⎯ Index 43h~45h 9Ch 9Dh(Bank 0) ........................................ 38 8.11 Realtime Status Registers ⎯ Index A9h~ABh(Bank 0) ...................................................... 39 8.12 Serial Bus Address Registers ⎯ Index 48h 4A(Bank 0) ..................................................... 39 8.13 ID, Bank Select Registers-- Index 49h 4Eh 4Fh 58h (Bank 0)............................................ 40 8.14 Pin Control Register -- Index4Bh (Bank 0) .......................................................................... 40 8.15 SMI#/OVT# Property Select -- Index 4Ch (Bank 0) ............................................................ 41 8.16 Diode Selection Register -- Index 59h (Bank 0)................................................................. 43 8.17 FANIN Divisor Control Registers -- Index 47h 5Bh 5Ch(Bank 0)....................................... 44 8.18 VBAT Monitor Control Register -- Index 5Dh (Bank 0) ....................................................... 45 8.19 FAN Pre-Scale Registers-- Index 80h 82h 93h A0h A1h A2h(Bank 0).............................. 46 8.20 FAN Duty Cycle Select Register--81h 83h 94h A3h A4h A5h(Bank 0)............................... 47 8.21 FAN 1/2 Configuration Register-- Index 84h (Bank 0) ........................................................ 49 8.22 Fan 1 Target Temperature Registers -- Index 85h 86h 96h(Bank 0).................................. 49 8.23 Tolerance of Fan1/2 Target Temperature Register -- Index 87h 97h(Bank0).................... 50 8.24 Fan Stop/Start Duty Cycle/DC Level Registers -- Index 88h 89h 98h(Bank 0)................... 51 8.25 Fan Stop Time Register -- Index 8Ch 8Dh 9Ah(Bank 0)..................................................... 51 8.26 Fan Step Down/Up Time Register -- Index 8Eh 8Fh(Bank 0) ............................................. 52 8.27 Fan 1/2/3 Smart Fan II Temperature/ Duty Cycle setups -- Index E0h~EBh 5Fh(Bank 0) 52 8.28 Value RAM 2⎯ Index B0h B1h B8h ~ BAh (BANK 0) ........................................................ 54 8.29 Limit RAM 2--- Index B4h~B7h BBh~BDh (BANK0) ........................................................... 55 8.30 Temperature Sensor 2 (First LM75) .................................................................................... 55 8.31 Temperature (High Byte) Register - Index C0h (Bank 0) .................................................... 56 8.32 Temperature Sensor 2 Temperature (Low Byte) Register - Index C1h (Bank 0)................ 56 8.33 Temperature Sensor 2 Configuration Register - Index C2h (Bank 0) ................................. 56 8.34 Temperature Sensor 2 Hysteresis (High Byte) Register - Index C3h (Bank 0)................... 56 8.35 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index C4h (Bank 0) ................... 56 - IV -
W83792AD/AG/D/G
8.36 Temperature Sensor 2 Over-temperature (High Byte) Register -Index C5h (Bank 0) ........ 57 8.37 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index C6h(Bank 0)......... 57 8.38 Temperature Sensor 3 (Second LM75)............................................................................... 57 8.39 Temperature Sensor 3 Hysteresis (High Byte) Register - Index CBh (Bank 0) .................. 57 8.40 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index CCh (Bank 0)................... 58 8.41 Temperature Sensor 3 Over-temperature (High Byte) Register - Index CDh (Bank 0) ...... 58 8.42 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index CEh(Bank 0) ........ 58 9. ARP (ADDRESS RESOLUTION PROTOCOL) REGISTERS...................................................... 59 9.1 Unique Device Identifier (UDID) -- 20h-2Fh (Bank 1) ......................................................... 59
10. ASF SENSOR ENVIRONMENTAL EVENT .................................................................................. 61 10.1 Temperature: Get Event Data message.............................................................................. 61 10.2 Voltage: Get Event Data message ...................................................................................... 65 10.3 Fan: Get Event Data message ............................................................................................ 67 10.4 Case Intrusion: Get Event Data message ........................................................................... 70 10.5 Thermal Trip: Get Event Data message.............................................................................. 71 10.6 ASF Response Registers -- 40h-7Fh (Bank 1) ................................................................... 73
10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 ASF Critical/non-critical Temperature Registers:.................................................................. 73 Sensor device: (SMBus Address, Read/Write)..................................................................... 73 Relative Entity ID Table ........................................................................................................ 73 Entity Instance Register........................................................................................................ 75 Remote Control Configuration Registers .............................................................................. 76
11. ELECTRICAL CHARACTERISTICS ............................................................................................. 77 11.1 Absolute Maximum Ratings................................................................................................. 77 11.2 DC Characteristics............................................................................................................... 77 11.3 AC Characteristics............................................................................................................... 79
11.3.1 11.3.2 Serial Bus Timing Diagram................................................................................................... 79 VID Input Skew..................................................................................................................... 79
12. THE TOP MARKING ..................................................................................................................... 80 13. ACKAGE SPECIFICATION ........................................................................................................... 82 14. W83792AD/AG APPLICATION CIRCUIT...................................................................................... 83 15. W83792D/G APPLICATION CIRCUIT .......................................................................................... 87
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Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
1 . GENERAL DESCRIPTION
W83792AD/AG and W8392D/G are two parts support single and dual CPU application, the former is for single CPU application which provides 1 set thermal trip and 1 set of VID controlling; the latter is for dual CPU application which provides dual CPU VID controlling and 2 sets of thermal trip. Other functions are all the same without difference except thermal trip and VID controlling numbers. W83792D/G is an evolving version of the W83791D --- Winbond's most popular hardware status monitoring IC. Besides the conventional functions of W83791D, W83792D/G uniquely provides several innovative features such as support dual CPU VID controlling, VRM9.0 and VRD10.0 specifications supported, ASF 2.0 specification compliant, SMBus 2.0 ARP command compatible, 2 sets of Thermal trip, 12 VID control, 6 sets of Smart fan TM, VID table selection trapping. Conventionally, W83792D/G can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system, such as server, workstation…etc, working very stably and efficiently. A 10-bit analog-to-digital converter (ADC) was built inside W83792D/G. W83792D/G can simultaneously monitor 9 analog voltage inputs (including power VDD/5VSB monitoring), 6 fan tachometer inputs, 3 remote temperatures, and Watch Dog Timer function. The sense of remote temperature can be performed by thermistors, or directly from IntelTM CPU with thermal diode output. W83792D/G provides 6 PWM (pulse width modulation)/DC fan output modes for smart fan control mode and Smart FanTM II mode. Under Thermal CruiseTM mode, Thermal CruiseTM temperatures of CPU and the system can be maintained within specific programmable ranges under the hardware control. As Smart Fan TM II, which provides 4 sets of temperatures point each could control fan’s duty cycle, depends on this construction, fan could be operated at the lowest possible speed so that the acoustic noise could be avoided. As for warning mechanism, W83792D/G provides SMI#, OVT#, IRQ signals for system protection events. Additionally, 12 VID inputs are provided to read 2 sets of VID for CPU (i.e. PentiumTM III/4). These VID inputs provide the information of Vcore voltage that CPU expects. W83792D/G also has 2 specific pins to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2C interface. W83792D/G can uniquely serve as an ASF sensor to respond to ASF master’s request for the implementation of network management in OS-absent status. Through W83792D/G’s compliance with ASF2.0 sensor specification, network server is able to monitor the environmental status of each client in OS-absent state by PET (Platform Event Trip) frame values returned from W83792D/G, such as temperatures, voltages, fan speed, thermal trip, and case open. Moreover, W83792D/G supports SMBus 2.0 ARP command to solve the problem of address conflicts by dynamically assigning a new unique address for W83792D/G ASF Function after W83792D/G’s UDID is sent. Through the application software or BIOS, the users can read all the monitored parameters of the system from time to time. A pop-up warning can also be activated when the monitored item is out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, IntelTM LDCM (LanDesk Client Management), or other management application software. Besides, the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and activate one programmable and maskable interrupts.
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Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
2 . FEATURES
2.1 VCORE Monitoring Items
Support dual CPU VID reading. VRM9.0 / VRD10.0 compliant to monitor dual CPU voltage. 2 sets of thermal trip latch mechanism to protect CPU from over temperature.
2.2
Monitoring Items
Monitoring 9 voltage inputs. 6 DC / PWM Fan outputs for fan speed control and 6 Fan speed inputs for monitoring --- Total up to 6 sets of fan speed monitoring and controlling 3 temperature inputs from remote thermistor and PentiumTM II/III/4 (Deschutes) thermal diode output 6 sets Smart FanTM could control the most fitting speed automatically by temperature. Case open detection input 2 sets of CPU thermal management:2 Thermal Trip signals latch up and generate VRM_EN signal to PWM for removing CPU power. Programmable hysteresis and setting points (alarm thresholds) for all monitored items
2.3
Address Resolution Protocol (ARP) and Alert-Standard Format (ASF 2.0)
Support System Management Bus (SMBus) version 2.0 specification Comply with hardware sensor slave ARP (Address Resolution Protocol) Response ASF 2.0 command --- Get Event Data, Get Event Status, Device Type Poll Comply with ASF 2.0 sensors (Power on/off remote control, Monitoring fan speed, voltage, temperature, thermal trip and case open) Support Remote Control subset: Remote Power-on/ Power-off/ Reset.
2.4
Actions Enabling
Issue SMI#, OVT#, IRQ signals to activate system protection Warning signal pop-up in application.
2.5
General
I2C serial bus interface Support 2 sets of 6bit VID monitoring for dual processors application Watch Dog Timer function with pin: RESET#, SYSRST_IN. 16 GPIOs 2 pins (A0, A1) to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2C interface
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W83792AD/AG/D/G
Winbond hardware monitoring application software (Hardware DoctorTM) support, for both Windows 95/98/2000/XP and Windows NT 4.0/5.0/2000 5V VSB operation
2.6
Package
48-pin LQFP
3 . KEY SPECIFICAITON
Voltage monitoring accuracy Intel VRM 9.x/VRD10.0 Voltage monitoring accuracy Temperature Sensor Accuracy Remote Diode Sensor Accuracy Resolution Supply Voltage Operating Supply Current ADC Resolution ± 3°C(Max) 0.5 ℃ 5V 5 mA typ. 10 Bits ±1% (Max) ±1% (Max)
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Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
4 . BLOCK DIAGRAM
ADDR 1:2 SDA SCL
VID A 0:5 VID register * 2 VID B 0:5
SMBus Address Selection
Serial Bus Interface
FAN Mode FAN IN/OUT 1:6 Smart FanTM II Thermal Cruise Manual Mode
SMBus Control ARP Control
ASF2.0 Commend Decoder VRM_EN PWRBTN# VID 90_10 CASEOPEN SMI#/IRQ OVT#
W83792D
Control Logic & Register
THERMALTRIP# 1:2
Thermal Protection
WDTRST# SYSRTIN#
Watch Dog Timer
10 Bits ADC
Band Gap Reference
VREF
GPIOs
GPIO
Temp. Sensor
Voltage Sensor
VBAT GND
CLK
VTIN 1:3
VIN 1:7 VDD
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W83792AD/AG/D/G
5 . PIN CONFIGURATION
5.1 W83792AD/AG
VREF VTIN3 VTIN2 VTIN1 SMI# / IRQ OVT# FAN_OUT4 / GPIOA0 FANIN4 / GPIOA1 FAN_OUT5 / GPIOA2 FANIN5 / GPIOA3 WDTRST# / FAN_OUT6 SYSRSTIN# / FANIN6
333333322222 654321098765 37 24 38 23
39 40 41 42 43 44 45 46 47 48 22 21 20
VCOREA VCOREB VIN0 VIN1 VIN2 VIN3 VBAT CASEOPEN VRM_EN GND
NC THERMTRIP1 #
+5VSB PWRBTN# SDA SCL FANIN1 FANIN2 FANIN3
CLK
W83792AD
Version C
19 18 17 16 15 14
FAN_OUT1/A0 FAN_OUT2/A1 FAN_OUT3/VID90_10 VDD
13 111 123456789 012
VIDA0 / GPIOA4 VIDA1 / GPIOA5 VIDA2 / GPIOA6 VIDA3 / GPIOA7 VIDA4 / GPIOB0 VIDA5 / GPIOB1 GPIOB2 GPIOB3 GPIOB4 GPIOB5 GPIOB6 GPIOB7
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Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
5.2 W83792D/G
VRE F VTIN 3 VTIN 2 VTIN 1 SMI# / IRQ OVT# FAN_OUT4 / GPIOA0 FANIN4 / GPIOA1 FAN_OUT5 / GPIOA2 FANIN5 / GPIOA3 WDTRST# / FAN_OUT6 SYSRSTIN# / FANIN6
333333322222 654321098765 37 24 38 23
39 40 41 42 43 44 45 46 47 48 22
VIN3 VBAT CASEOPEN VRM_EN / FAN_OUT7 GND THERMTRIP2 THERMTRIP1/ FAN_IN7
VCOREA VCOREB / VIN4 VIN0 VIN1 VIN2
+5VS B PWRBTN# SDA SC L FANIN 1 FANIN 2 FANIN 3 CLK FAN_OUT1/A0 FAN_OUT2/A1 FAN_OUT3/VID90_10 VDD
W83792D Version C
21 20 19 18 17 16 15 14
13 111 123456789 012
VIDA0 / GPIOA4 VIDA1 / GPIOA5 VIDA2 / GPIOA6 VIDA3 / GPIOA7 VIDA4 / GPIOB0 VIDA5 / GPIOB1 VIDB0 / GPIOB2 VIDB1 / GPIOB3 VIDB2 / GPIOB4 VIDB3 / GPIOB5 VIDB4 / GPIOB6 VIDB5 / GPIOB7
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W83792AD/AG/D/G
6 . PIN DESCRIPTION
6.1 Pin Type Description
I/O12t I/O12ts I/O8ts I/O6ts I/OD12ts OUT12 OD12 AOUT INt INts AIN TTL level bi-directional pin with 12 mA source-sink capability TTL level and schmitt trigger with 12 mA source-sink capability TTL level and schmitt trigger with 8 mA source-sink capability TTL level and schmitt trigger with 6 mA source-sink capability TTL level and schmitt trigger open drain output with 12 mA sink capability Output pin with 12 mA source-sink capability Open-drain output pin with 12 mA sink capability Output pin (Analog) TTL level input pin TTL level input pin and schmitt trigger Input pin(Analog)
6.2
Pin Description List
PIN NAME PIN NO. POWER PLANE TYPE DESCRIPTION
VIDA0 1 GPIOA4 VIDA1 2 GPIOA5 VIDA2 3 GPIOA6 VIDA3 4 GPIOA7 VIDA4 5 GPIOB0 5VSB 5VSB 5VSB 5VSB 5VSB
INts I/O D12ts
Voltage Supply readouts bit 0 from CPU A. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 1 from CPU A. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 2 from CPU A. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 3 from CPU A. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 4 from CPU A. After programming, this pin can be VID output or GPIO.
INts I/O D12ts
INts I/O D12ts
INts I/O D12ts
INts I/O D12ts
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Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
Pin Description List, continued
PIN NAME
PIN NO.
POWER PLANE
TYPE
DESCRIPTION
VIDA5 6 GPIOB1 VIDB0 7 GPIOB2 VIDB1 8 GPIOB3 VIDB2 9 GPIOB4 VIDB3 10 GPIOB5 VIDB4 11 GPIOB6 VIDB5 12 GPIOB7 5VSB 5VSB 5VSB 5VSB 5VSB 5VSB 5VSB
INts I/O D12ts
Voltage Supply readouts bit 5 from CPU A. Only used in VRD10.0. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 0 from CPU B. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 1 from CPU B. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 2 from CPU B. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 3 from CPU B. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 4 from CPU B. After programming, this pin can be VID output or GPIO. Voltage Supply readouts bit 5 from CPU B. Only used in VRD10.0. After programming, this pin can be VID output or GPIO. +5V VDD power. Bypass with the parallel combination of 10μF (electrolytic or tantalum) and 0.1μF (ceramic) bypass capacitors. Fan speed control PWM/DC output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. At 5VSB power on, this pin is used to select Internal VRM 9 or 10 table. Detect 1, Select VRM9, Detect 0, selects VRM10.
INts I/O D12ts
INts I/O D12ts
INts I/O D12ts
INts I/O D12ts
INts I/O D12ts
INts I/O D12ts
VDD
13
-
POWE R
FAN_OUT3 14 VID9_10 5VSB
OUT1 2
INt s
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W83792AD/AG/D/G
Pin Description List, continued
PIN NAME
PIN NO.
POWER PLANE
TYPE
DESCRIPTION
FAN_OUT2 15 A1 5VSB
OUT12
Fan speed control PWM/DC output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. I2C device address bit 1 trapping during 5VSB power on. Fan speed control PWM/DC output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. I2C device address bit 0 trapping during 5VSB power on. 14.318MHz System clock while VCC5V powered up. 0V to +5V amplitude fan tachometer input 0V to +5V amplitude fan tachometer input 0V to +5V amplitude fan tachometer input Serial Bus Clock. Serial Bus bi-directional data. Power Button output for enable/disable power supply.
INts
FAN_OUT1 16 A0 CLK FANIN3 FANIN2 FANIN1 SCL SDA PWRBTN# 17 18 19 20 21 22 23 VDD VDD VDD VDD 5VSB 5VSB 5VSB 5VSB
I/O12t
INts INts INts INts INts INts I/OD12ts OD12
+5VSB
24
-
This pin is power for W83792D/G. Bypass with the POWER parallel combination of 10μF (electrolytic or tantalum) and 0.1μF (ceramic) bypass capacitors. Thermal Trip signal from CPU A. Low Active.
THERMTRIP1# 25 FANIN7 THERMTRIP2# 26 5VSB INts 5VSB INts
0~+5V FANIN 7 tachometer. Thermal Trip signal from CPU B. Low Active.
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W83792AD/AG/D/G
Pin Description List, continued
PIN NAME
PIN NO.
POWER PLANE
TYPE
DESCRIPTION
GND VRM_EN
27
-
POWER System Ground. OD12 Any assertion of thermal trip after VDD power good will disable Voltage Regulator Module. Fan speed control PWM output. By default it’s high. The power of this pin is supplied by VSB 5V. CASE OPEN detection. An active high input from an external device when case is Intruded. This signal can be latched in external circuit which power is supplied by VBAT, even if W83792D is power off.
28 FAN_OUT7
5VSB OUT12
CASEOPEN
29
VBAT
INts
VBAT
30
-
VBAT supplies power for CASEOPEN, POWER THERMALTRIP. Besides, it is also a voltage monitor channel.
VIN3VIN0 VCOREB VCOREA VREF
31 34 35 36 37 AIN AIN AOUT CPU B Core Voltage Input. Detect range is 0~2.048V. CPU A Core Voltage Input. Detect range is 0~2.048V. Reference voltage and is equal to 2.048V Thermistor 3 terminal input.(Default). AIN 0V to 4.096V Analog Voltage Monitor Inputs.
VTIN3
38
AIN
PentiumTM 4 diode 3 input. This multi-functional pin is programmable. Thermistor 2 terminal input. (Default).
VTIN2
39
AIN
PentiumTM 4 diode 2 inputs. This multi-functional pin is programmable. Thermistor 1 terminal input. (Default).
VTIN1
40
AIN
PentiumTM 4 diode 1 inputs. This multi-functional pin is programmable.
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W83792AD/AG/D/G
Pin Description List, continued
PIN NAME
PIN NO.
POWER PLANE
TYPE
DESCRIPTION
IRQ / 41 SMI# OVT# FAN_OUT4 43 GPIOA0 FANIN4 44 GPIOA1 5VSB 5VSB 42 VDD VDD
OUT12 OD12 OD12 OUT12 I/O12ts INts I/O12ts
Interrupt request. System Management Interrupt (open drain). Over temperature Shutdown Output for temperature sensor 1-3. Fan speed control PWM/DC output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. After programming, this pin can be GPIO. 0V to +5V amplitude fan tachometer input After programming, this pin can be GPIO. Fan speed control PWM output. When the power of VDD is 0v, this pin will drive logic 0. The power of this pin is supplied by VSB 5V. After programming, this pin can be GPIO. 0V to +5V amplitude fan tachometer input After programming, this pin can be GPIO. Fan speed control PWM output. By default it’s high. The power of this pin is supplied by VSB 5V. Low active System RESET. If triggered, this pin will send out 100ms low pulse for system reset. 0V to +5V amplitude fan tachometer input System reset input, used to control WDT.
FAN_OUT5 45 GPIOA2 FANIN5 46 GPIOA3 5VSB 5VSB
OUT12
I/O12ts INts I/O12ts
FAN_OUT6 47 RESET# 5VSB
OUT12
OD12
FANIN6 48 SYSRSTIN# 5VSB
INts INts
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Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
7 . FUNCTION DECRIPPTION
7.1 General Description
The W83792D/G provides 9 analog voltage inputs, 7 fan speed inputs and output controls which support both of PWM (Pulse Width Modulation) control and DC (Direct Current) fan control, all of them are implemented with Smart FANTM I and Smart FANTM II. 3 sets of thermal inputs for remote thermistor or PentiumTM 4 thermal diode outputs, and case open detection also supported in W83792D/G. Further more, W83792D/G provides several innovative and practical functions to make the whole system manage more efficiently and compliant with future trend of network management, such as ASF2.0 sensor compliant, which could remote Power on/off control the system, report the status of thermal trip, fan, and temperature limitation. Also, it is SMBus 2.0 ARP command compatible. VID table could be selected by hardware trapping for VRM9.0 and VRD 10 specifications. 2 sets of 6 bits of VID input/output control for dual processors and 2 sets of thermal Trip input for disable VRM module, and for the more, once the monitoring function of W83792D/G is enabled, the watch dog will monitor every function and store the values to registers for comparison with preset ranges. If the monitoring value exceeds the limit value, the interrupt status will be set to 1 and W83792D/G will issue interrupt signals such as SMI# and IRQ if they are not masked off. W83792D/G also provides software and hardware Watch Dog Timer to avoid system hang on.
7.2
Access Interface
The W83792D/G provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83792D/G, there are three serial bus addresses. Through the fi The first serial bus address of W83792D/G has 2 hardware setting bits set by Pin15-16. The address is 01011[pin15][pin16]X. Hence, the content of CR [48h] would be 00101110 if pin15=1 and pin16=0. The read/write of the CPUT1/CPUT2 temperature sensor registers can be implemented through the second address (defined at CR [4Ah] bit2-0 10011[IA1][IA0]X) and the third address (defined at CR[4Ah] bit6-4 10010[IA1][IA0]X).rst address defined at CR[48h], all the registers can be read and written.
7.3
The first serial bus access timing
0 SCL SDA
Start By Master
(a) Serial bus writes to internal address register followed by the data byte
7 8 0 7 8
0
1
0
1
1
0
1
R/W
Ack by 792D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 792D
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte 7 8
SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0
Ack Ack by 792D 784R Stop by Master
Frame 3 Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
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W83792AD/AG/D/G
(b) Serial bus read from a register
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
0
1
R/W
Ack by 792D
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 792D
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
0
7
8
0
7
8
0
Repeat start by Master
1
0
1
1
0
1
R/W
Ack by 792D
D7
D6
D5
D4
D3
D2
D1
D0
Nak by Master Stop by Master
Frame 3 Serial Bus Address Byte 0
Frame 4 Data Byte
Figure 2. Serial Bus Read from Internal Address Register
7.4
Address Resolution Protocol (ARP) Introduction
As the W8792D/G is a slave device existing on the System Management Bus, it must have a unique address to prevent itself from conflicting with the other devices existing on the same bus. In order to solve the problem of address conflicts, SMBus version 2.0 introduces the concept of dynamically assigned address called Address Resolution Protocol (ARP). By such mechanism, each device existing on the SMBus will be given with an unique slave address if it is a ARP-capable device. Thus, to meet the new spec, W83792D/G uniquely provides ARP compliant function to acquire an unique slave address. The typical process of ARP contains several steps, including Prepare to ARP, Reset Device, Get UDID, Assign Address, and so on. Whenever the slave device accepts the command of ARP master, it must reply an Acknowledgement to the ARP master, thus the ARP master is able to carry on the next step. In order to provide a mechanism to isolate device for the purpose of address assignment, each device must implement a unique device identifier (UDID). The UDID is a 128-bit number comprised of several field, including Device Capabilities, Version Revision, Vendor ID, Device ID, Interface, Subsystem Vendor ID, Subsystem Device ID, and Vendor Specific ID. After the UDID of the device is sent to the ARP master, the ARP master will then assign an address not in the Used Address Pool to the device. Generally speaking, there are eleven possible commands to read /write the data of SMBus device, and a slave device may use any or all of the eleven protocols to communicate. These protocols are Quick Command, Send Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read word, Process Call, Block Write, and Block Write-Block Read Process Call. W83792D/G itself supports the Block Write-Block Read Process with PEC to communicate with ARP Master. Following is a description of the SMBus packet protocol diagrams element key. Not all protocol elements will be present in every command, that is, not all packets are required to include the Packet Error Code.
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1-bit S S Sr Rd Wr A
7 Slave Address
1
1
8 Command
1 A
8 PEC
1 A
1-bit P
Wr A
Start Condition Repeated Start Condition Read (bit value of 1) Write (bit value of 0) Acknowledge (this bit position may be ‘0’ for an ACK or ‘1’ for a NACK)
P PEC
Stop Condition Packet Error Code Master-to-Slave Slave-to-Master
Relative command list:
SLAVE ADDRESS COMMAND DESCRIPTION
C2h C2h C2h C2h C2h C2h C2h
01h 02h 03h 04h Slave_Addr | 1 Slave_Addr | 0 05h-1Fh
Prepare to ARP Reset device (general) Get UDID (general) Assign address Direct Get UDID Direct Reset Reserved.
Following is an example of the Block Write-Block Read Process Call. The Block Write-Block Read Process Call is a two-part message. It begins with a salve address and a write condition. After the command code the host issues a write count M that describes how many more bytes will be written in the first part of the message. The second part of the message is a block of read data beginning with a repeat start condition followed by the salve address and a Read Bit. The next read byte count N indicates how many more data will be read in the second part of the message. Note that the combined data payload must not exceed 32bytes. Besides, W83792D/G also provides packet error code (PEC) to ensure the accuracy during data transmission.
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W83792AD/AG/D/G
1 S
7 Slave Address
1 Wr
1 A
8
1
8 Byte Count=M
1 A
8 Data Byte 1
1 A …
Command Code A
8 Data Byte 2 1 Sr 7 8 1 1
1 A 1 … … 8 8
… …
8 Data Byte M 1 1 8 8
1 A … 1 1 1 P 1 …
Slave Address Rd A Data Byte 2 A
Byte Count=N A Data Byte N A
Data Byte 1 A PEC A
7.5
ASF (Alert Standard Format) Introduction
In order to implement network management in OS-absent, W83792D/G provides ASF Response Registers to meet ASF sensor spec. As a result, the network server is able to monitor several environmental status of the client in OS-absent by PET frame values returned from W83792D/G, including temperature, voltage, fan speed, and case open. In below is the ASF diagram: Alert Message LAN on Card
Management Server Polling (PET Subset) Motherboard PCI Bus LAN on Board SMBus Chipset 792D Slave
Figure 3. ASF Block Diagram
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7.5.1 Platform Event Trap (PET) PET is the ASF transmit protocol used to provide common fields for trap regardless of trap source. The variable bindings fields in a PET frame contain the system and sensor information for an event, such as event sensor type, event type, event offset, event source type, sensor device, sensor number, entity ID, entity instance, event status index, event status, and event severity. Each field has its definition and is described in the following table.
PET VARIABLE BINDING FIELD DESCRIPTION
Event Sensor Type Event Type Event Offset Event source Type Sensor Device Sensor Number Entity ID Entity Instance Event Status Index
The Event Sensor Type field indicates what types of events the sensor is monitoring. E.g. temperature, voltage, fan, etc. The Event Type indicates what type of transition/state change triggered the trap. The Event Offset indicates which particular event occurred for a given Even Type. The Event Source Type describes the originator of the event. It is ASF2.0(68h) for all PET frames defined by this specification. The Sensor Device is the SMBus address of the sensor that caused the event for the PET frame. The Sensor Number is used to identify a given instance of a sensor relative to the Sensor Device. The Entity ID indicates the platform entity the event is associated with. E.g. processor, system board, etc. The Entity Instance indicates which instance of the Entity the event is for. E.g. processor 1 or processor 2. The Event Status Index identifies a unique event monitored by the ASF-sensor. It is zero-based, sequential, continuous, and ranging form 0-37h. The Event Status indicates the event state of the ASF-sensor device associated with the message’s Event Status Index. The Event Severity gives the management station an indication of the severity of the event in the PET frame. Typical values are Monitor (0x01), Non Critical (0x08), or Critical Condition (0x10).
Event Status Event Severity
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Following is the illustration of ASF SMBus command for Get Event Data. 1 S 7 Slave Address ASF-sensor Address 1 Wr 0 1 A 0 8 Command Sensor Device 0000 0001 1 A 0 8 Wr Data 2 Version Number 0001 0000 1 A 0 8 Wr Data 3 Event Index 00ii iiii 1 A Status 0 8 Wr Data 4 Reserved 0000 0000 1 A… 0 1 A 0 8 Wr Byte Count 0000 0100 1 A 0 …
8 Wr Data 1 Sub Command Get Event Data 0001 0001
1 Sr
7 Slave Address ASF-sensor Address
1 R 1
1 A 0
8 Rd Byte Count 0000 1010 to0000 1111 1 A 8 Rd Data 3 Event Type 1 A 8 Rd Data 7 Sensor Device 1 A 0
1 A 0 …
1 A 0 8
8 Rd Data 1 Status 1 A 8
1 A 0
8 Rd Data 2
…
Event Sensor Type 0 1 A 8 Rd Data 6
1 A 0 …
Rd Data 4
Rd Data 5
Event Offset 0
Event Source 0 Type 8 Rd Data 9 Entity 1 A 0
Event Severity 0
8 Rd Data 8 Sensor Number
1 A 0
8 Rd Data 10 Entity Instance
1 A 0 …
8 … PEC From zero to five bytes of Event Data [data dependent]
1 A 1
1 P
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7.6 Analog Inputs
The maximum input voltage of the analog pin is 4.096V because the 10-bit ADC has a 4mv LSB. Actually, the application of the PC monitoring would most often be connected to power supply. The CPU V-core voltage, +3.3V and battery voltage can directly connect to these analog inputs. The – 5V, –12V and +12V inputs should be reduced a factor with external resistors to meet the input range. As Figure 4 shows. *PS : VCORE channel resolution = 2mv VIN0-4 channel resolution = 4mv
VcoreA Positive Inputs VcoreB +3.3VIN VBAT
Pin 36 Pin 35 Pin 34 Pin 30 Pin 32 10-bit ADC with 4mV LSB
V1 Positive Input
R1
12VIN R2
Negative Input
V3 V4 R7
R5
N12VIN N5VIN
Pin 31 Pin 33
R8 R 10K, 1% VREF VTIN3 Typical Thermister Connection R THM 10K, 25 C VTIN2 VTIN1 Pin 38 Pin 39 Pin 40
R6 Pin 37
**The Connections of VTIN1 and VTIN2 are same as VTIN3
Figure 4.
7.6.1
Monitor over 4.096V voltage:
The input voltage +12VIN can be expressed as the following equation.
12VIN = V1 ×
R2 R1 + R2
The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node voltage of +12VIN should be subject to under 4.096V for the maximum input range of the 8-bit ADC. The pin 13 and pin 29 are discretely connected to the power supply +5V and 5VSB . There are two functions in these pins with 5V. The first function is to supply internal analog power in the W83792D and the second one is that these voltages are all connected to internal serial resistors to monitor the +5V and 5VSB voltage.
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W83792AD/AG/D/G
7.6.2 Monitor negative voltage: The negative voltage should be connected to two series resistors and a positive voltage VREF (equal to 2.048V). In the Figure 11, the voltage V3 and V4 are two negative voltages and are -12V and -5V respectively. The voltage V3 is connected to two serial resistors as well as another positive terminal VREF. Therefore, the voltage node N12VIN would be a positive voltage if the scale of the two serial resistors are carefully selected. It is recommended from Winbond that the scale of the two serial resistors are R5=232K ohms and R6=10K ohm. The input voltage of node -12VIN can be calculated by the following equation.
N12VIN = (VREF + V5 ) × (
where VREF is equal to 2.048V.
232 KΩ ) + V5 232 KΩ + 10 KΩ
If the V5 is equal to -12V then the voltage is equal to 1.467V and the converted hexdecimal data is set to 60h by the 8-bit ADC with 8mV-LSB.This monitored value should be converted to the real negative voltage and the express equation is shown as follows.
V5 =
Where
N12VIN − VREF × β 1− β
β
is 232K/(232K+10K). If the N2VIN is 1.467 then the V5 is approximately equal to -12V.
The other negative voltage input V6 (approximate -5V) can also be evaluated by the similar method and the serial resistors can be R7=120K ohms and R8=10K ohms by the Winbond recommended. The expression equation of V6 With -5V voltage is shown as follows.
V6 =
N 5VIN − VREF × γ 1− γ
Where the γ is set to 120K/(120K+10K). If the monitored ADC value in the N5VIN channel is 1.505, VREF=2.048V and the parameter γ is 0.923, then the negative voltage of V6 can be evaluated -5V.
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7.7 FAN Speed Count and FAN Speed Control
7.7.1 Fan speed count W83792D/G support 6 sets of fan counting. Fan inputs are provided for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and the maximum input voltage should not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to meet the input specification. The normal circuit and trimming circuits are shown as Figure 8.
Determine the fan counter according to:
1.35 × 10 6 Count = RPM × Divisor
In other words, if the fan speed counter has been read from register CR [28], CR [29], CR [2A], CR [B8], CR [B9] or CR [BA] , then the fan speed can be evaluated by the following equation.
RPM =
1.35 × 10 6 Count × Divisor
The default divisor is 2 and defined at CR47, CR5B, and CR5C which are three bits for divisor. This provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, RPM, and count.
DIVISOR NOMINAL RPM TIME PER REVOLUTION COUNTS
1 2 (default) 4 8 16 32 64 128
8800 4400 2200 1100 550 275 137 68
Table 2.
6.82 ms 13.64 ms 27.27 ms 54.54 ms 109.08 ms 218.16 ms 436.32 ms 872.64 ms
153 153 153 153 153 153 153 153
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W83792AD/AG/D/G
+12V +5V Pull-up resister 4.7K Ohms +12V Pull-up resister 4.7K Ohms
+12V FAN Out GND Fan Input Pin 18/19/20
+12V FAN Out GND
14K~39K
Fan Input
Pin 18/19/20
FAN Connector
W83792D
FAN Connector
10K
W83792D
Figure 5-1. Fan with Tach Pull-Up to +5V
Figure 5-2. Fan with Tach Pull-Up to +12V, or Totem-Pole Output and Register Attenuator
+12V
+12V
Pull-up resister > 1K +12V FAN Out GND Fan Input Pin 18/19/20 +12V FAN Out GND
Pull-up resister < 1K or totem-pole output > 1K
Fan Input
Pin 18/19/20
3.9V Zener
FAN Connector
W83792D
3.9V Zener
FAN Connector Figure 5-4. Fan with Tach Pull-Up to +12V, or Totem-Pole Putput and Zener Clamp
W83792D
Figure 5-3. Fan with Tach Pull-Up to +12V and Zener Clamp
7.7.2 Fan speed control The W83792D/G provides six sets both of PWM and DC mode for fan speed control. The duty cycle of PWM can be programmed by a 4-bit registers defined in the Bank0 CR[81], CR[83], CR[94], CR[A3],CR[A4] and CR[A5] . The default duty cycle is set to 100%, that is, the default 4-bit register is set to 0x8Fh. The expression of duty cycle can be represented as follows.
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7.7.2.1. PWM mode :
Duty − cycle(%) =
Programmed 8 - bit Register Value × 100% 255
+12V
R1 R2 G D NMOS S + PNP Transistor
PWM Clock Input
C
FAN
Figure 6.
7.7.2.2. DC mode: W83792D/G has a 4-bit DAC, which produces 0 to 5 volts DC output that provides maximum 3 sets for fan speed control. The analog output can be programmed in the Bank0 CR[81], CR[83], CR[94], CR[A3],CR[A4] and CR[A5]. That is default output value is 5 V. The expression of output voltage can be represented as follow, OUTPUT VOLTAGE
= AVCC ×
Programmed 4 - bit Register Value 16
IO+12V
The application circuit is shown as follow,
IO+12V
Q1 R1
FANOUT 0 3 2 NPN 4 + LM358 1
C1
0.1U
Tachometer output
11 IO-12V
R3
47K FAN
3 2 1
R4
33K
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W83792AD/AG/D/G
Must be take care when choosing the OP-AMP and the transistor. The OP-AMP is used for amplify the 5V range of the DC output up to 12V. The transistor should has a suitable β value to avoid its base current pulling down the OP-AMP ’s output and gain the common current to operate the fan at fully speed. (For more cost and effort efficiently solution please refer to W8339TS/QS –which is the DC fan pre-driver and it could provide up to 24V gate voltage for external N-channel MOSFET with lower cost and better performance)
7.7.3
Smart FanTM I Control
W83792D/G supports two Smart Fan function and mapping to temp1 (FAN1, PWMOUT1), temp2 (FAN2, PWMOUT2), temp3 ( FAN3, PWMOUT3) .Smart Fan Control provides two mechanisms. One is Thermal Cruise mode and the other is Smart FanTM II mode. 7.7.3.1. Thermal Cruise mode At this mode, W83792D/G provides the Smart Fan system to automatically control fan speed to keep the temperatures of CPU and the system within specific range. At first a wanted temperature and interval must be set (ex. 55 °C ± 3 °C) by BIOS and the fan speed will be lowered as long as the current temperature remains below the setting value. Once the temperature exceeds the high limit (58°C), the fan will be turned on with a specific speed set by BIOS (ex: 80% duty cycle) and automatically controlled its PWM duty cycle with the temperature varying. Three conditions may occur: (1) If the temperature still exceeds the high limit (ex: 58°C), PWM duty cycle will increase slowly. If the fan has been operating in its full speed but the temperature still exceeds the high limit (ex: 58°C), a warning message will be issued to protect the system. (2) If the temperature goes below the high limit (ex: 58°C), but still above the low limit (ex: 52°C), the fan speed will be fixed at the current speed because the temperature is in the target range (ex: 52 °C ~ 58°C). (3) If the temperature goes below the low limit (ex: 52°C), PWM duty cycle will decrease slowly to 0 or a preset stop value until the temperature exceeds the low limit. Figure 7-1, 7-2 gives an illustration of Thermal Cruise Mode.
A 58`C 55`C 52`C 100 50 0
Figure 7-1.
Fan Start = 20%
B
C
D
PWM Duty Cycle
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W83792AD/AG/D/G
D
A 58`C 55`C 52`C 100 50 0
B
C
PWM Duty Cycle
Fan Start = 20%
Fan Stop = 10%
Fan Start = 20%
Figure 7-2.
Of course, Smart Fan control system can be disabled and the fan speed control algorithm can be programmed by BIOS or application software.
7.7.4
Smart FanTM II Control
W83792D/G provide 4 temperature point each can auto control PWM or DC fan mode. Each Temp maps Different fan out level, the relationship is shown as follow:
Fan Duty Cycle Temp. Tolerance
Fan Duty Cycle 100% Fan Duty Cycle Level 3 Fan Duty Cycle Level 2 Fan Duty Cycle Level 1 Non-Stop Duty Cycle
Temp. 1
Temp.2
Temp.3
Temp.4
Temperature
Figure 8. Smart Fan II behavior
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W83792AD/AG/D/G
7.7.4.1. Temperature Measurement Machine The temperature data format is 8-bit two-complement for sensor 1 and 9-bit two-complement for sensor 2/3. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the bank0 CR[C0/ C8h] and the LSB from the bank0 CR[C1/C9h] bit 7. The format of the temperature data is show in Table 3.
TEMPERATURE 8-BIT DIGITAL OUTPUT 8-BIT BINARY 8-BIT HEX 9-BIT DIGITAL OUTPUT 9-BIT BINARY 9-BIT HEX
+125°C +25°C +1°C +0.5°C +0°C
0111,1101 0001,1001 0000,0001 0000,0000
7Dh 19h 01h 00h
Table 3.
0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000
0FAh 032h 002h 001h 000h
7.7.4.2. Monitor temperature from thermistor: The W83792D/G can be connected three thermistors to measure three different environmental temperatures. The specification of thermistor should be considered to (1) β value is 3435K, (2) resistor value is 10K ohms at 25°C. In the Figure 11, the thermistor is connected by a serial resistor with 10K Ohms(1% error), then connect to VREF (Pin 37). 7.7.4.3. Monitor temperature from Pentium IVTM thermal diode or bipolar transistor 2N3904 The W83792D/G can alternate the thermistor to Pentium IVTM thermal diode interface or transistor 2N3904 and the circuit connection is shown as Figure 11. The pin of Pentium IVTM D- is connected to power supply ground (GND) and the pin D+ is connected to pin VTINx in the W83792D/G. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base (B) and Collector (C) in the 2N3904 should be tied together to act as a thermal diode.
VREF R =1 5K , 1%
B ipolar T ransistor T em perature S en sor
P IV T D x C = 3300p F
B
C 2 N 3904 E R =15 K , 1%
W 83792D
OR
P entium IV CPU
T herm inal D iode
D+ C =33 00pF D-
P IV T D x
F igure 9.
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7.7.5 SMI# interrupt for W83792D/G Voltage
SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 10-1.)
7.7.6
SMI# interrupt for W83792D/G Fan
SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 10-2.)
High limit
Low limit
Fan Count limit
SMI#
*
*
*
*
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 10-1. Voltage SMI# Mode
Figure 10-2. Fan SMI# Mode
7.7.7
SMI# interrupt for W83792D/G temperature sensor 1/2/3
(1) Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO but has not been reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. (Figure 10-3.) (2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 10-4.) (3) One-Time interrupt mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will not cause an interrupt. Once an interrupt event has occurred by exceeding TO, then going below THYST, an interrupt will not occur again until the temperature exceeding TO. (Figure 10-5.)
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W83792AD/AG/D/G
TI O
T OI
T YST H
T HYST
SMI#
*
*
*
*
*
SMI#
*
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 10-3. Comparator Interrupt Mode
TI O
Figure 10-4. Two-Times Interrupt Mode
T YST H
SMI#
*
*
*Interrupt Reset when Interrupt Status Registers are read
Figure 10-5. One-Time Interrupt Mode
Note. The IRQ interrupt action like SMI# , but the IRQ is level signal.
7.7.8
Over-Temperature (OVT#) for W83792D temperature sensor 1/2/3
7.7.8.1. Comparator Mode: Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. (Figure 13) 7.7.8.2. Interrupt Mode: Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor 1 or sensor 2 or sensor 3 registers. Temperature exceeding TO, then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor 1 or sensor 2 or sensor 3 registers. Once the OVT# is activated by exceeding TO, then reset, if the temperature remains above THYST, the OVT# will not be activated again.( Figure 11)
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7.7.8.3. ACPI Mode At this mode, temperature exceeding one level of temperature separation, starting from 0 degree, causes the OVT# output activated. OVT# will be activated again once temperature exceeds the next level. OVT# output will act the same manner when temperature goes down. (Figure 11-1). The granularity of temperature separation between each OVT# output signal can be programmed at Bank0 CR[4Ch] bit 4-5.
To
T YST H
O VT#
( Comparator Mode; default)
OVT#
(Interrupt Mode)
*
*
*
*Interrupt Reset when Temperature 1/2/3 is read
Figure 11 Over-Temperature Response Diagram
( 'C) 1 00 90 80 70 60 50 40 30 20 10 0 O VT#
C urrent Temperature
Figure 11-1. ACPI Mode
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W83792AD/AG/D/G
8 . CONTROL AND STATUS REGISTER
8.1 Watch Dog Timer Registers --- Index 01h-04h
BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 0 0 0 0 1 2 3 4 WO RO R/W R/W Reserve 0Reserve 0 0 Timeout Time 00h (Unit in min) Unlock Code HARD 0 0 SOFT 0 0 BIT 1 BIT 0 MNEMONIC LOCK Watch Dog Watch Dog Enable Watch Dog Status Watch Dog Timer
WDT Stage HARD_TO SOFT_TO
Reset Condition: Resume reset Two kinds of watchdog timer function are supported by W83792D/G. One is so-called Soft Watch Dog Timer, and the other is Hard Watch Dog Timer. Hard Watch Dog timer if enabled which will start a 4 minutes WDT after completion of system reset. (A Low to High transition on SYSRSTIN# pin). BIOS need to write a 00 into Watch Dog Timer Register (04h) to disable timer within 4 minutes, otherwise pin 47 WDTRST# will assert to reset system. Soft Watch Dog Timer will start to down counting whenever Timeout Time is set and Soft Watch Dog Timer is enabled. A WDTRST# will be issued while the timer timeouts. Soft Watch Dog Timer will be disabled automatically after received a SYSRSTIN_N low signal. To write these registers requires CR40[4]/ENWDT being asserted. CR01 LOCK Watch Dog
BIT NAME ATTRIBUTE DESCRIPTION
7~0
Unlock Code
WO
Write 55h, Enable Soft Watch Dog Timer. Wire AAh, Disable Soft Watch Dog Timer. Write 33h, Enable Hard Watch Dog Timer. Write CCh, Disable Hard Watch Dog Timer.
CR02 Watch Dog Enable
BIT NAME ATTRIBUTE DESCRIPTION
7~2 1 0
reserve HARD SOFT
RO RO RO
reserve 1 indicates the Hard Watch Dog is enabled; 0, Hard Watch Dog is disabled. 1 indicates the Soft Watch Dog is enabled; 0, Soft Watch Dog is disabled.
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W83792AD/AG/D/G
CR03 Watch Dog Status
BIT NAME ATTRIBUTE DESCRIPTION
7~4 3~2
reserve WDT Stage HARD_TO SOFT_TO
R/W R/W
Reserve. Default 0, these 2 bits record last WDT stage for BIOS readout. The information is used to help BIOS to identify WDT timeout issue. 1: a hard timeout occurs. This bit will be cleared while reading. 1: a soft timeout occurs. This bit will be cleared while reading.
1 0
RO RO
CR04 Watch Dog Timer
BIT NAME ATTRIBUTE DESCRIPTION
7~0
Watch Dog Timer
R/W
Time to issue WDTRST#. Unit in minutes. Write 00h will disable the timer.
8.2
VRM Tolerance Registers ⎯ Index 12h-13h (Bank 0)
MNEMONIC
BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Vcore High Tolerance (2mV unit) Vcore High Tolerance 0 12 RW 64h(0.2V) Vcore Low Tolerance (2mV unit) Vcore Low Tolerance 0 13 RW 64h(0.2V) Vcore Offset (12.5mV/LSB, 2s complement) VRM Offset 0 FD RW 0 RESET Condition: Resume Reset, INIT(CR40.7), or both VID detect no CPU. Writing Tolerance register will force VCORE Limit Generator generate new voltage limit for VCORE. For example, writing CR[FDh] with 01 in VRM 10.1 mode will result in VCORE limit registers CR[2B/2C/2D/2E] become Voltage(VID) +/- Tolerance + 12.5mV.
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W83792AD/AG/D/G
8.3 VID Control/Status Registers ⎯ Index 14h-18h (Bank 0)
Mnemonic
VID IN A VID Control A Entry/Disable VID Output VID IN B VID Control B
Bank Index Attr
0 0 0 0 0 14 15 16 17 18 RO RW RW RO RW
BIT 7
VRD10 RW EN_VIDO 0 ENTRYOK 0 RW 0 EN_VIDO 0
BIT 6
VRM_CK RO VIDCHG RO
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
VIDIN5 VIDIN4 VIDIN3 VIDIN2 VIDIN1 VIDIN0 RO VID5 0 VID4 0 VID3 0 VID2 0 VID1 0 0 RO VID5 0 VID4 0 VID3 0 VID2 0 VID1 0 VID0 0 VID0 0 0
ENTRY_ST Write pattern/ Read 00h 1 RW VIDCHG RO
EN_VIDTG AUTOUPD VIDIN5 VIDIN4 VIDIN3 VIDIN2 VIDIN1 VIDIN0
RESET Condition: Both VID detects no CPU, Resume Reset, INIT(CR40.7), These registers are used to control 12 VID Pins. When power on, system can strap Pin14 to decide which VRM table will be used later. This information is shown at CR14.VRM_CK. In VRM9, power on value will be shown at VIDIN. When system wants to program VID pins, it must program a sequence to CR16 first, the sequence is 5A, 73, B2, E0. After this, one can set EN_VIDO, and write VID to output. To disable, write CR16 with A5, 4C, D9, 8A. In this way, the W83792D/G will lock its latest status. CR14/CR17 VID IN 7.VRD10 Set to enable VRD10 table translation, clear to enable VRM9 table translation. Default value is Inversion of VRM_CK. Power on strapping value of Pin14, this will determine default value of VRD10 (bit 7).
6.VRM_CK
6.AUTOUPD
Auto-update for VRD10.0 VID. In auto-update mode, VID is automatically update and SMBus to modify upper/lower limit of vcore is not applicable. If programming High/Low limit is required with VRD10=1, this bit must be cleared as 0.
5~0.VIDIN
Power-on value of VID pins(VRM9 mode) or current VID value on pins(VRM10 mode).
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W83792AD/AG/D/G
CR15/CR18 VID Control 7.EN_VIDO 6.VIDCHG 5~0.VID Set to enable VID output. VID on the fly. (Read only) Use to indicate VID have been changed in last 1ms~2ms. The desired VID to output to pin. (ENTRY OK must be 1 to write this register)
CR16 Entry/Disable VID Output 7.ENTRYOK Read only. An one means entry pattern all successfully received, and programming VID function is valid. Read only. These 2 bits indicate how many patterns have been written into CR16.
1~0. ENTRY_ST 7~0 Pattern
Write 8-bit to input patterns for writing VID output privilege. Entrance: 5A(Entry_ST=1), 73(Entry_ST=2), B2(Entry_ST=3), E0(ENTRY_OK=1). Exit: A5(Entry_ST=2), 4C(Entry_ST=1), D9(Entry_ST=0), 8A(ENTRY_OK=0). The pattern must be sequentially input without other writes interrupt, otherwise, the current input sequence is considered as in-effective.
Note. Programming VID for output and using VID pins as GPIO are different. Programming VID output will activate VID translation, but GPIO will not. Writing VID should be separated into 2 steps at the first time after VID Entry is enabled. One for set EN_VIDOUT, the other for set the wanted VID. These actions are used to inform VID Limit Generator generate new VCORE Limits for written VID. If writing EN_VIDOUT/VIDOUT in the same SMBus transaction, VID will be output to port but will not update internal Vcore Limits. VIDIN latches external pin value, and will not affect by VIDOUTDATA. VID on the fly flag is only used in VRM10 mode. User should not assume its value under VRM9 value.
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W83792AD/AG/D/G
8.4 GPIO Control/Status Register ⎯ Index 1A~1Eh (Bank 0)
Mnemonic
GPIO Enable
Bank Index Attr BIT 7
0 1A RW
0 GPA7 0 GPA7 0 GPB7 0 GPB7 0
BIT 6
0 GPA6 0 GPA6 0 GPB6 0 GPB6 0
BIT 5
0 GPA5 0 GPA5 0 GPB5 0 GPB5 0
BIT 4
0 GPA4 0 GPA4 0 GPB4 0 GPB4 0
BIT 3 BIT 2 BIT 1 BIT 0
0 GPA3 0 GPA3 0 GPB3 0 GPB3 0 0 GPA2 0 GPA2 0 GPB2 0 GPB2 0 0 GPA1 0 GPA1 0 GPB1 0 GPB1 0 0 GPA0 0 GPA0 0 GPB0 0 GPB0 0
reserve GPA0_1 GPA2_3 GPA4_B0 GPB1 GPB2_6 GPB_7 reserve
GPIOA Output Control
0
1B
RW
GPIOA Data/Status
0
1C
RW
GPIOB Output Control
0
1D
RW
GPIOB Data/Status
0
1E
RW
Reset Condition: Resume Reset, INIT. 16 GPIO pins are provided in W83792D. Three kinds of registers are used to control GPIO mechanism. GPIO Enable enables GPIO function, Output Control determines direction of the GPIO pin, and Data/status put/get data from the pin. CR1A GPIO Enable
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1
reserve GPA0_1 GPA2_4 GPA4_B0 GPB1 GPB2_6 GPB7
RO R/W R/W R/W R/W R/W R/W
Reserved. Enable GPIO function for GPA0 and GPA1. Enable GPIO function for GPA2 and GPA3. Enable GPIO function for GPA4, GPA5, GPA6, GPA7 and GPB0. Enable GPIO function for GPB. Enable GPIO function for GPB2, GPB3, GPB4, GPB5 and GPB6. Enable GPIO function for GPB7.
CR1B/CR1D GPIO Output Control These bits control the direction of each GPIO pins. Write 0, GPIO serves as input. Write 1, GPIO serves as output. Default is input. CR1C/CR1E GPIO Data/Status Write these bits, the data will response to GPIO, set to output mode. If read this register, will return this pin data that can input or output in this pin.
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W83792AD/AG/D/G
8.5 VRM Output Control ---- Index 1F(Bank 0)
Bank Index Attr BIT 7 BIT 6 BIT 5
0 1F RW
VRM_EN 1 DIR 0 RO
Mnemonic
VRM Output Control
BIT 4
1
BIT 3 BIT 2
0 0
BIT 1
1
BIT 0
1
VRMSTS VRMOPV reserve reserve TTRIP2_N TTRIP1_N
Reset Condition: Resume Reset, INIT. W83792D have the ability to control VRM(Voltage Regulator Module) enable. At normal power on, VRM is always enabled. But once TTRIP1_N(Thermal Trip1) or TTRIP2_N is asserted, all VRM will be disabled until resume reset, no matter TTRIP_N is written 1 again or not. CR1F VRM Output Control
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4
VRM_EN DIR VRMSTS VRMOPV
R/W R/W RO R/W
Set to 1 will enable VRM Enable control. Clear to 0 enable GPIO function. Pin direction when VRM_EN. Set to 1, serves as output ; 0 will change into input mode. Current value on pin VRM_EN. For GPIO use VRM_EN Output Value. When Thermal Trip occurs, this bit will reset to 0 also. In GPIO mode, write this bit will force the value output to pin. Thermal Trip input 1. This bit is powered by 5VSB. It will latch a 0 once THERMTRIP1 goes high. It can be reset to 1 by 5VDD Power on and resume reset. Thermal Trip input 0. This bit is powered by 5VSB. It will latch a 0 once THERMTRIP0 goes high. It can be reset to 1 by 5VDD Power on and resume reset.
1
TTRIP2_N
RO
0
TTRIP1_N
RO
TTRIP2_N and TTRIP1_N, any of these two bits cleared as 0 means thermal trip shutdown is happening. If VRM_EN is set, a zero will be outputted at pin 28 to shut down voltage regulator.
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W83792AD/AG/D/G
8.6 Value RAM ⎯ Index 20h- 2Ah AEh AFh (Bank 0)
MNEMONIC Vcore A Readout Vcore B Readout VIN0 Readout VIN1 Readout VIN2 Readout VIN3 Readout 5VCC Readout Temperature 1 Readout FAN 1 Count FAN 2 Count FAN 3 Count LOW BITS I LOW BITS II BANK INDEX ATTR 0 0 0 0 0 0 0 0 0 0 0 0 0 20 21 22 23 24 25 26 27 28 29 2A 3E 3F RO RO RO RO RO RO RO RO RO RO RO RO RO VIN1 TEMP1 EN_HLD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Vcore A Voltage Vcore B(VIN4) Voltage VIN0 Voltage VIN1 Voltage VIN2 Voltage VIN3 Voltage 5VCC Voltage Temperature Sensor 1 FAN 1 Count Readout FAN 2 Count Readout FAN 3 Count Readout VIN0 5VCC VCOREB VIN3 VCOREA VIN2
Value RAM stores the latest sensed system parameter. Each data will refresh automatically after the channel input converted. EN_HLD bit(Writable, default is 0) of AFh is capable of turn on Sample and Hold mechanism. VcoreA Calculation Vcore A Voltage = (CR[20]*4 + CR[3E]&0x03) * 0.002; VcoreB Calculation VcoreB Voltage = (CR[21]*4 + CR[3E]&0x0C/4) * 0.002; VIN0~VIN3 Calculation VIN0 Voltage = (CR[22]*4 + CR[3E]&0x30/16) * 0.004; VIN1 Voltage = (CR[23]*4 + CR[3E]&0xC0/16) * 0.004; VIN2 Voltage = (CR[24]*4 + CR[3F]&0x03) * 0.004; VIN3 Voltage = (CR[25]*4 + CR[3F]&0x0C/4) * 0.004; 5VCC Calculation 5VCC Voltage = (CR[26]*4 + CR[3F]&0x30/16) * 0.006;
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Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
8.7 Limit RAM ⎯ Index 2Bh- 2Dh (Bank 0)
MNEMONIC Vcore 1 High Limit MNEMONIC Vcore 1 Low Limit Vcore 2 High Limit Vcore 2 Low Limit VIN0 High Limit VIN0 Low Limit VIN1 High Limit VIN1 Low Limit VIN2 High Limit VIN2 Low Limit VIN3 High Limit VIN3 Low Limit 5VCC High Limit 5VCC Low Limit Temperature 1 High Limit Temperature 1 Low Limit FAN 1 Count High Limit FAN 2 Count High Limit FAN 3 Count High Limit BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Vcore A Voltage High Limit (unit 8mV) 0 2B RW DEPENDS ON VID BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Vcore A Voltage Low Limit 0 2C RW DEPENDS ON VID Vcore B Voltage High Limit 0 2D RW DEPENDS ON VID Vcore B Voltage Low Limit 0 2E RW DEPENDS ON VID VIN0 Voltage High Limit 0 2F RW FFh VIN0 Voltage Low Limit 0 30 RW 00h VIN1 Voltage High Limit 0 31 RW FFh VIN1 Voltagez 0 32 RW 00h VIN2 Voltage High Limit 0 33 RW FFh VIN2 Voltage Low Limit 0 34 RW 00h VIN3 Voltage High Limit 0 35 RW FFh VIN3 Voltage Low Limit 0 36 RW 00h 5VCC Voltage High Limit 0 37 RW FFh 5VCC Voltage Low Limit 0 38 RW 00h Temperature Sensor 1 High Limit 0 39 RW 7Fh Temperature Sensor 1 Low/Hysteresis Limit 0 3A RW 00h FAN 1 Count High Limit 0 3B RW FFh FAN 2 Count High Limit 0 3C RW FFh FAN 3 Count High Limit 0 3D RW FFh
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W83792AD/AG/D/G
Limit RAM setups the high/low limit for each channel in Value RAM. While exceeding these limits, system will take certain action determined by prior setups. FAN Count high limits should be the limit for lowest fan speed. This is because the slower the fan is, the more the internal clock will be counted by internal clock. Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupt will never be generated except the case when voltages go below the low limits. VcoreA Limit Setup CR[2B/2C] = [Desired Voltage]/0.008; VcoreB Limint Setup CR[2D/2E] = [Desired Voltage]/0.008; VIN0~VIN3 Limit Setup CR[2F~36] = [Desired Voltage] / 0.016; 5VCC Limit Setup CR[37/38] = [Desired Voltage] / 0.024;
8.8
Configuration Register ⎯ Index 40h (Bank 0)
MNEMONIC BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 INIT IRQEDGE IRQPOL ENWDT INT_CLR EN_IRQ EN_SMI START Configuration 0 40 RW 0 0 0 0 0 0 0 1
Reset Condition: Resume Reset, INIT. Configuration Register controls the system reset, stop, power down and warning output mode.
BIT NAME ATTRIBUTE DESCRIPTION
7
Initialization
R/W
6 5 4 3
IRQ output IRQ Polarity ENWDT INT_Clear
R/W R/W R/W R/W
Set one restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero. Set 0 , IRQ output level signal . Set 1, output 200 us pulse signal. Default is 0. When set to 0, IRQ active high. Set to 1, IRQ active low. Default is 0. Set this bit to 1 will enable Watch Dog Timer function. Watch dog timer function will reset system(pin 47) while it timeouts. A one disables the SMI# and IRQ# outputs without affecting the contents of Interrupt Status Registers. The device will stop monitoring at last channel. It will resume upon clearing of this bit. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit.
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W83792AD/AG/D/G
Continued.
BIT
NAME
ATTRIBUTE
DESCRIPTION
2 1 0
EN_IRQ EN_SMI# START
R/W R/W R/W
A one enables the IRQ Interrupt output. A one enables the SMI# Interrupt output. If EN_SMI# and EN_IRQ are both set to 1, SMI# will override the IRQ output. A one enables startup of monitoring operations; a zero puts the analog part in Power-down mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit.
8.9
Interrupt Status Registers ⎯ Index 41h 42h 9Bh(Bank 0)
BANK INDEX ATTR BIT 7 0 0 0 41 42 9B RO RO RO FAN3 BIT 6 FAN2 BIT 5 FAN1 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TEMP3 TEMP2 TEMP1 VcoreB VcoreA VIN3 VSB VIN2 VIN1 VIN0
MNEMONIC Interrupt Status 1 Interrupt Status 2 Interrupt Status 3
FAN7 VIDCHG Chassis 5VCC FAN6 FAN5 FAN4 VBAT
TART3 TART2 TART1
An one represents corresponding channel have been exceed its limit. TART will assert while target temperature cannot be achieved after 3 minutes full speed of corresponding FAN. Read Interrupt Status will clear the interrupt flag.
8.10 SMI#/IRQ Mask Registers ⎯ Index 43h~45h 9Ch 9Dh(Bank 0)
MNEMONIC SMI/IRQ Mask 1 BANK INDEX ATTR 0 43 RW BIT 7 FAN3 0 BIT 6 FAN2 0 BIT 5 FAN1 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TEMP3 TEMP2 TEMP1 VcoreB VcoreA 0 VDD 0 VBAT 0 0 VIN3 0 VSB 0 0 VIN2 0 0 VIN1 0 0 VIN0 0
SMI/IRQ Mask 2
0
44
RW
CLR_CHS VIDCHG Chassis 0 FAN6 0 0 FAN5 0 0 FAN4 0
SMI/IRQ Mask 3
0
9C
RW
TART3 TART2 TART1 0 0 0
These are SMI/IRQ mask registers. Set to one will disable the corresponding interrupt sources. Clear to 0 will enable that interrupt source. SMI Mask 2 bit 7 is CLR_CHS(Clear Chassis), write this bit with an one will clear internal caseopen latch, and after latch is clear, CLR_CHS will be reset to 0 itself.
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W83792AD/AG/D/G
8.11 Realtime Status Registers ⎯ Index A9h~ABh(Bank 0)
MNEMONIC Realtime status 1 Realtime status 2 Realtime status 3 BANK INDEX ATTR BIT 7 0 0 0 A9 AA AB RO RO RO FAN3 BIT 6 FAN2 BIT 5 FAN1 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TEMP3 TEMP2 TEMP1 VcoreB VcoreA VDD VBAT VIN3 VSB VIN2 VIN1 VIN0
FAN7 VIDCHG Chassis FAN6 FAN5 FAN4
TART3 TART2 TART1
Realtime status registers show the related channel exceeding limit or not at the polling moment. Return 1 represents related channel have exceeded the limit defined in limit RAM.
8.12 Serial Bus Address Registers ⎯ Index 48h 4A(Bank 0)
MNEMONIC SMBus Address BANK INDEX ATTR 0 48 RW BIT 7 reserve 0 DIS_T3 0 1 0 1 T3 Address IA[1] IA[0] BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SMBus address 0 1 DIS_T2 0 0 1 IA[1] IA[0]
TEMP2/3 Address
0
4A
RW
T2 Address IA[1] IA[0]
Reset Condition: Resume Reset W83792D provides 2 power on strapping pin for default SMBus address. With these 2 pins, 4 kinds of default address setups are possible. CR48 SMBus Address
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
Reserved SMBADDR1
RO R/W
Reserved. Serial Bus Address for general index registers. The address bit 0 and bit 1 are trapped by the pin 10 and pin 11, respectively.
CR4A Temperature 2 and Temperature 3 Serial Bus Address Register
BIT NAME ATTRIBUTE DESCRIPTION
7
DIS_T3
R/W
Set to 1, disable temperature 3 sensor accessing from Temperature 3 Serial Bus Address. Still can access from Bank 0 Cxh. Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. Set to 1, disable temperature Sensor accessing from Temperature 2 Serial Bus Address. Still can access from Bank 0 Cxh. Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits.
6-4 3
I2CADDR3 DIS_T2
R/W R/W
2-0
I2CADDR2
R/W
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W83792AD/AG/D/G
8.13 ID, Bank Select Registers-- Index 49h 4Eh 4Fh 58h (Bank 0)
MNEMONIC Device Version ID Bank Select Winbond vendor ID(Toggle) Winbond Chip ID BANK INDEX ATTR 0 x 0 0 49 4E 4F 58 RO RW RO RO HBACS 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 13h for CSB version. Reserved 0 RO BANK Select 0 0 0
Return 5Ch(if HBACS=1); return A3h(if HBACS=0) 7Ah
CR4E Bank Select Register (Reset Condition: Resume Reset)
BIT NAME ATTRIBUTE DESCRIPTION
7 2-0
HBACS Bank Select
R/W R/W
High Byte Access of Winbond Vendor ID. Set to 1, read 4Fh will get 5Ch ; Clear as 0, read 4Fh will return A3h. Bank select is to change current indexed bank. Available banks are 0,1, and 7.
8.14 Pin Control Register -- Index4Bh (Bank 0)
MNEMONIC BANK INDEX ATTR Pin Control 0 4B RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TT Level 0 VIDLevel FAN6/WDT SELVIDA SELVIDB reserve EnFAN7 VRM10 0 0 0 0 0
Reset Condition: Resume Reset Pin Controls enables different pin/clock selections.
BIT NAME ATTRIBUTE DESCRIPTION
7
VID Level
R/W
6
FAN6/WDT
R/W
5 4 3 2 1-0
SELVIDA SELVIDB reserve FAN7 Enable Thermal Trip Level
R/W R/W R/W R/W R/W
Set this bit enables VID with 0.8/0.4V level. Clear this bit makes VID in input mode with TTL level. Default value is set by VRM10 power-on trapping. Set this bit enables FAN6 Functionality. Default is Watch Dog Timer Function. Clear this bit to 0 will perform Watch Dog Functionality on Pin 47/48. Set to enable VIDA with offset output at VID port B. Clear to disable this function. Set to enable VIDB with offset output at VID port A. Clear to disable this function. reserved Set to enable FAN7 function and disable Thermaltrip/VRM_EN pin function. Thermal Trip Level Selector. These two bits select the input level for ThermalTrip 1/2. 11b is 1.0Vref GTLP. 10b enables 0.8Vref GTL. 00b set these 2 pins to TTL.
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W83792AD/AG/D/G
8.15 SMI#/OVT# Property Select -- Index 4Ch (Bank 0)
MNEMONIC BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TEMP_SMI_MD OVT_MD EN_OVT3 EN_OVT2 EN_OVT1 OVTPOL 0 0 0 1
IRQ/OVT Polarity
0
4C
RW
0(Comp Interrupt) 0(Comparator) reserve
DIFFREG (ACPI Increment Difference) 5
ACPI Difference
0
5E
RW
0
Reset Condition: Resume Reset. Register 4Ch selects SMI modes, OVT modes, OVT sources and OVT polarity. If OVT_MD selects ACPI mode, register 5Eh determines the temperature interval between each OVT is issued. Default sets to 5, that is, every time temperature reaches 5*n degree, an OVT will be issued.
BIT NAME ATTRIBUTE DESCRIPTION
7-6
TEMP_SMI_MD [1:0]
R/W
Temperature SMI# Mode Select. - Comparator Interrupt Mode:(Default) Temperature 1/2/3 exceeds TO (Over-temperature) limit causes and interrupt and this interrupt will be reset by reading all the Interrupt Status. - Two Time Interrupt Mode: This bit use in temperature sensor 1/2/3 interrupt mode with hysteresis type. Temperature exceeding TO, causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST. - One Time Interrupt Mode: This bit use in temperature sensor 1/2/3 interrupt mode with hysteresis type. Temperature exceeding TO (Over-temperature, defined in Bank 1/2) causes an interrupt and then temperature going below THYST (Hysteresis temperature, defined in Bank 1/2) will not cause an interrupt. Once an interrupt event has occurred by exceeding TO, then going below THYST, and interrupt will not occur again until the temperature exceeding TO.
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W83792AD/AG/D/G
Continued.
BIT
NAME
ATTRIBUTE
DESCRIPTION
5-4
OVT_MD[1:0]
R/W
OVT# Mode Select. There are three OVT# signal output type. - Comparator Mode: (Default) Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. - Interrupt Mode: Setting temperature exceeding TO causes the OVT# output activated indefinitely until reset reading temperature sensor 1/2/3 registers. Temperature exceeding TO, then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor 1/2/3(reading interrupt status). Once the OVT# will not be activated by exceeding TO, then reset, if the temperature remains above THYST, the OVT# will not be activated again. - ACPI Mode: If set to 1 then enable ACPI OVT# output. Which is always send an OVT# pulse signal (22us, if not a suddenly temperature jump)when the temperature over the ACPI temperature increment value defined at Index 5Eh.
3
EN_OVT3
R/W
Enable temperature sensor 3 over-temperature (OVT) output if set to 1. Default 0, disable OVT2 output through pin OVT#. The pin OVT# is wire OR with OVT1 and OVT2. Enable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, disable OVT2 output through pin OVT#. The pin OVT# is wire OR with OVT1 and OVT3. Enable temperature sensor 1 over-temperature (OVT) output .if set to 1. Default 0, disable OVT1 output through pin OVT#. The pin OVT# is wire OR with OVT2 and OVT3. Over-Temperature Polarity. Write 0, OVT# active high. Write 1, OVT# active low. Default is 1 .
2
EN_OVT2
R/W
1
EN_OVT1
R/W
0
OVTPOL
R/W
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W83792AD/AG/D/G
8.16 Diode Selection Register -- Index 59h (Bank 0)
Mnemonic Bank Index Attr BIT 7 0 reserve 0 BIT 6 1 BIT 5 1 BIT 4 0 BIT 3 0 BIT 2 0 OFFSET1 00h OFFSET2 0 OFFSET3 00h BIT 1 0 BIT 0 0
Thermal Diode Select
0
59
RW
reserve TDSEL3 TDSEL2 TDSEL1 K8SEL1 NVSEL1 K8SEL23 NVSEL23
Temperature 1 Offset
0
90
RW
Temperature 2 Offset
0
91
RW
reserve 0 reserve
Temperature 3 Offset
0
92
RW
0
Reset Condition: Resume Reset, INIT. CR59h Thermal Diode Select
BIT NAME ATTRIBUTE DESCRIPTION
7 6
Reserved TDSEL3
RO R/W
Reserved. Temperature sensor 3 diode mode. When set to 1, select Pentium IV compatible Diode. Set to 0 to select Thermistor mode Temperature sensor 2 diode mode. When set to 1, select Pentium IV compatible Diode. Set to 0 to select Thermistor mode Temperature sensor 1 diode mode. When set to 1, select Pentium IV compatible Diode. Set to 0 to select Thermistor mode Set to select K8 Temperature Table for VTIN1. Set to select nVidia NV34 Temperature Table for VTIN1. Set to select K8 Temperature Table for VTIN2/3. Set to select nVidia NV34 Temperature Table for VTIN2/3.
5
TDSEL2
R/W
4
TDSEL1
R/W
3 2 1 0
K8SEL1 NVSEL1 K8SEL23 NVSEL23
R/W R/W R/W R/W
K8 and NV34 GPU table is also supported in W83792D. VTIN2, VTIN3 should be always in the same mode since they will decide the VID mapping. There is only one exception, that is, thermistor mode. VTIN2 and VTIN3 can choose one in thermistor mode and another in other modes. VTIN1 is separately set up in this configuration. Configuration these bits have priority as… Thermistor mode > K8 diode mode > NVIDIA diode mode > P4 mode.
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W83792AD/AG/D/G
CR90h-92h Temperature Offset
BIT NAME ATTRIBUTE DESCRIPTION
7-6 5-0
Reserved Temperature Offset
RO R/W
Reserved. Related temperature channel base temperature. The temperature is added by both monitor value and offset value. 01,1111 => +31 degree C 01,1110 => +30 degree C : 00,0001 => +1 degree C 00,0000 => +0 degree C 11,1111 => -1 degree C 11,1110 => -2 degree C : 10,0000 => -32 degree C
8.17 FANIN Divisor Control Registers -- Index 47h 5Bh 5Ch(Bank 0)
MNEMONIC BANK INDEX ATTR BIT 7 FAN2_OB 0 FAN4_OB 0 FAN6_OB 0 Manual BIT 6 BIT 5 BIT 4 BIT 3 FAN1_OB 0 FAN3_OB 0 FAN5_OB 0 BIT 2 BIT 1 BIT 0 FAN 1 Divisor 1 FAN 3 Divisor 1 FAN 5 Divisor 1 FAN 7 Divisor 1 FAN 2 Divisor 1 FAN 4 Divisor 1 FAN 6 Divisor 1
FAN Divisor 1
0
47
RW
FAN Divisor 2
0
5B
RW
FAN Divisor 3
0
5C
RW
Trigger Mask Reserve FAN7_OB 0 0 0 0
FAN 7 Divisor and Control
0
9E
RW
0
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W83792AD/AG/D/G
Reset Condition: Resume Reset, INIT, 5VDD posedge
BIT NAME ATTRIBUTE DESCRIPTION
Enable Fan as Output Buffer. Set to 1, FANOUT can drive logical high or logical low. 6-4, FAN_DIV R/W FAN PWM Input Divisor. 2-0 000 - divided by 1; 001 - divided by 2(Default); 010 - divided by 4; 011 - divided by 8; 100 - divided by 16; 101 - divided by 32; 110 - divided by 64; 111 - divided by 128. W83792D supports different FAN power on time. The FAN will power on one by one after 5VDD is ready. (At sequence FAN6-2-3-1-4-5) Fan Divisor also determines the FAN power on time. Under power-on-default setting(divisor = 2), to power on all FAN will take 71.5ms. If divisor is change, the timing will be different.
7,3
FAN_OB
R/W
CR9E FAN 7 Divisor and Control
BIT NAME ATTRIBUTE DESCRIPTION
7
Manual
R/W
Fan7 Automatic/Manual Mode Selection. Clear to 0, always polling FAN7 automatically; Set to 1, only polling once while Trigger is set to 1. Fan7 count trigger. Once set, W83792D will count FANIN7 in Auto Mode. After FAN count write back, this bit will be clear to 0. Interrupt/SMI mask for FAN7.
6
Trigger
R/W
5
Mask
R/W
8.18 VBAT Monitor Control Register -- Index 5Dh (Bank 0)
OLARIT BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 TT1 TT2 RO reserve 0 BIT 3 CLR_TT1 0 BIT 2 BIT 1 BIT 0 EN_VBAT 0 CLR_TT2 reserve 0 0
VBAT Monitor Control
0
5D
RW
RO
Reset Condition: Resume Reset .
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W83792AD/AG/D/G
BIT
NAME
ATTRIBUTE
DESCRIPTION
7 6 5-4,1 3 2 0
TT1 TT2 reserve CLR_TT1 CLR_TT2 EN_VBAT_MNT
RO RO RO R/W R/W R/W
Thermal Trip 1 event log. Powered by VBAT. Thermal Trip 2 event log. Powered by VBAT. Reserved. Set this bit to 1 will reset TT1 to 0, after bit 7 reset, CLR_TT1 will deassert automatically. Set this bit to 1 will reset TT2 to 0, after bit 6 reset, CLR_TT2 will deassert automatically. Write 1, enable battery voltage monitor. Write 0, disable battery voltage monitor. If enable this bit, the monitor value is valid after one monitor cycle.
TT1, TT2, 2 thermal trip event log bits powered by VBAT. They will never cleared by all reset. To clear it must set CLR_TT1 and CLR_TT2 to 1. For real time status of Thermal trip, please refer to CR[1F].
8.19 FAN Pre-Scale Registers-- Index 80h 82h 93h A0h A1h A2h(Bank 0)
OLARIT BANK INDEX ATTR BIT 7 CLKSEL 0 CLKSEL 0 CLKSEL 0 CLKSEL 0 CLKSEL 0 CLKSEL 0 CLKSEL BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PRE_SCALE1 01h (divider equals PRE_SCALE1 + 1) PRE_SCALE2 01h (divider equals PRE_SCALE2 + 1) PRE_SCALE3 01h PRE_SCALE4 01h PRE_SCALE5 01h PRE_SCALE6 01h PRE_SCALE7 01h
PWM1 Prescalar
0
80
RW
PWM 2 Prescalar
0
82
RW
FAN 3 Prescalar
0
93
RW
FAN 4 Prescalar
0
A0
RW
FAN 5 Prescalar
0
A1
RW
FAN 6 Prescalar
0
A2
RW
FAN 7 Prescalar
0
9D
RW
0
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W83792AD/AG/D/G
Reset Condition: Resume Reset, INIT, 5VDD posedge.
BIT NAME ATTRIBUTE DESCRIPTION
7
PWM_CLK_SEL
R/W
PWM Input Clock Select. This bit select Fan input clock to pre-scale divider. 0: 14.318MHz(External) 1: 1MHz(Internal) Fan PWMOUT Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : :
6-0
PRE_SCALE[6:0]
R/W
PWM frequency = (Input clock / pre-scale ) / 16
8.20 FAN Duty Cycle Select Register--81h 83h 94h A3h A4h A5h(Bank 0)
MNEMONIC BANK INDEX ATTR BIT 7 PWM/DC 1 PWM/DC 1 PWM/DC 1 PWM/DC 1 PWM/DC 1 PWM/DC 1 PWM/DC BIT 6 BIT 5 reserve 0 reserve 0 reserve 0 RO SYNC T1/2/3 0(Stand alone) SYNC T1/2/3 0 SYNC T1/2/3 0 SYNC T1/2/3 0 reserve 0 reserve 0 reserve 0 reserve 0 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PRGVAL1 Fh PRGVAL2 Fh PRGVAL3 Fh PRGVAL4 Fh PRGVAL5 Fh PRGVAL6 Fh PRGVAL7 Fh
FAN 1 Duty Cycle
0
81
RW
FAN 2 Duty Cycle
0
83
RW
FAN 3 Duty Cycle
0
94
RW
FAN 4 Duty Cycle
0
A3
RW
FAN 5 Duty Cycle
0
A4
RW
FAN 6 Duty Cycle
0
A5
RW
FAN 7 Duty Cycle
0
A6
RW
1
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W83792AD/AG/D/G
Reset Condition: Resume Reset, INIT.
BIT NAME ATTRIBUTE DESCRIPTION
7
PWM/DC
R/W
PWM/DC FAN Config. Set 1, FANOUT is configured as PWM output. Clear to 0, FANOUT is configured as DC output.
6-5
SYNC T1/2/3
R/W
Sync with Temp Sensor. 00: Stand alone, does not sync with any temperature sensor 01: Sync with Temp1. 10: Sync with Temp2. 11: Sync with Temp3.
4 3-0
Reserve
FAN_DC[3:0]
RO R/W
Reserved Fan Duty Cycle. This 4-bit register determines the number of input clock cycles, out of 16-cycle period, during which the PWM output is high. During smart fan control mode, read this register will return smart fan duty cycle. In Manual mode, write this register to control the output PWM Duty cycle. 0h: PWM output is always logical Low. Fh: PWM output is always logical High. Xh: PWM output logical High percentage is (X/16*100%) during one cycle.
Notice. To use SYNC T1/2/3 function, the corresponding FAN1, FAN2, or FAN3 must be enabled with temperature cruise mode. Otherwise, only 2 DC output is available. One is full speed when exceeding flag raised, and the other is start speed when not exceeding temperature limit. User may not read out PRGVAL with 0xF when system power up, because the FAN will sequentially powered on one by one. The order of FAN power on is followed the sequence 6-2-3-1-4-5. At DC FAN mode, the output level and corresponding programmed value have the relation as following table.
PRGVAL OUTPUT LEVEL (VOLT) PRGVAL OUTPUT LEVEL (VOLT)
0000 0001 0010 0011 0100 0101 0110 0111
0 0.31 0.62 0.94 1.25 1.56 1.87 2.19
1000 1001 1010 1011 1100 1101 1110 1111
2.50 2.81 3.12 3.44 3.75 4.06 4.37 4.69
For Fan1, Fan2, and Fan 3, the output value will be affected by power-on-strap resistor. In the case of using 100K resistor, the output drifts about 0.15V with normal value.
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W83792AD/AG/D/G
8.21 FAN 1/2 Configuration Register-- Index 84h (Bank 0)
MNEMONIC FAN Configuration BANK INDEX ATTR BIT 7 BIT 6 0 84 RW reserve 0h BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FAN3_TYPE 0 FAN2_TYPE 0 FAN1_TYPE 0
Reset Condition: Resume Reset, INIT, 5VDD posedge.
BIT NAME ATTRIBUTE DESCRIPTION
7-6 5-4
Reserved FAN3_TYPE
R/W
3-2
FAN2_TYPE
R/W
1-0
FAN1_TYPE
R/W
Reserved FAN 3 PWM Control Type. 00 - Manual PWM/DC Control Mode. (Default) 01 - Thermal Cruise mode. (Corresponding to VTIN3) 10/11 – Smart FAN II mode. (Corresponding to VTIN3) FAN 2 PWM Control Type. 00 - Manual PWM/DC Control Mode. (Default) 01 - Thermal Cruise mode. (Corresponding to VTIN2) 10/11 – Smart FAN II mode. (Corresponding to VTIN2) FAN 1 PWM Control Type. 00 - Manual PWM/DC Control Mode. (Default) 01 - Thermal Cruise mode. (Corresponding to VTIN1) 10/11 – Smart FAN II mode. (Corresponding to VTIN1)
8.22 Fan 1 Target Temperature Registers -- Index 85h 86h 96h(Bank 0)
MNEMONIC FAN 1 Target Temperature BANK INDEX ATTR 0 85 RW BIT 7 reserve 0 reserve 0 reserve 0 RO BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FAN_TAR_T1 00h FAN_TAR_T2 00h FAN_TAR_T3 00h
FAN 2 Target Temperature
0
86
RW
FAN 3 Target Temperature
0
96
RW
Reset Condition: Resume Reset, INIT, 5VDD posedge.
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W83792AD/AG/D/G
VTIN target temperature register for Thermal Cruise mode.
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
Reserved FAN_TAR_T R/W
Reserved. Fan Target Temperature. / Temperature Point 1 For Thermal Cruise mode. When the sensed temperature is over the target temperature with tolerance, the smart fan duty cycle will go up until the duty cycle reach FFh. For Smart Fan II Mode, this temperature is used to distinguish the FANOUT between Fan Duty Cycle Level 1 and Non-stop Duty Cycle.
8.23 Tolerance of Fan1/2 Target Temperature Register -- Index 87h 97h(Bank0)
MNEMONIC FAN Tolerance BANK 0 INDEX 87 ATTR RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TOL_TEMP2 0h reserve 0 RO TOL_TEMP1 0h TOL_TEMP3 0h
FAN 3 Tolerance
0
97
RW
Reset Condition: Resume Reset, INIT, 5VDD posedge. Tolerance of Fan1/2 target temperature register.
BIT NAME ATTRIBUTE DESCRIPTION
7-4 3-0
TOL_T2[3:0] TOL_T1[3:0]
R/W R/W
Tolerance of Fan 2 Target Temperature. Only for Thermal Cruise mode and Smart Fan II mode. Tolerance of Fan 1 Target Temperature. Only for Thermal Cruise mode and Smart Fan II mode.
Tolerance of Fan 3 target temperature register.
BIT NAME ATTRIBUTE DESCRIPTION
7-4 3-0
reserved TOL_T3[3:0]
R/W R/W
reserved Tolerance of Fan 3 Target Temperature. Only for Thermal Cruise mode and Smart Fan II mode.
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W83792AD/AG/D/G
8.24 Fan Stop/Start Duty Cycle/DC Level Registers -- Index 88h 89h 98h(Bank 0)
MNEMONIC BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 START_DC1 01h START_DC2 01h START_DC3 MIN_NOSTOP_DC1 01h MIN_NOSTOP_DC2 01h MIN_NOSTOP_DC3 01h
FAN 1 Nonstop/Start
0
88
RW
FAN 2 Nonstop/Start
0
89
RW
FAN 3 Nonstop/Start
0
98
RW
01h
Reset Condition: Resume Reset, INIT, 5VDD posedge.
BIT NAME ATTRIBUTE DESCRIPTION
7-4
START_DC
R/W
In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. This register should be written a fan start-up duty cycle. At Smart Fan II mode. This register is used as Fan Duty Cycle Level 1.
3-0
STOP_DC
R/W In Thermal Cruise mode, PWM duty will be 0 if it decreases to under this value. This register should be written a non-zero minimum PWM stop duty cycle.
8.25 Fan Stop Time Register -- Index 8Ch 8Dh 9Ah(Bank 0)
MNEMONIC FAN 1 Stop Time BANK 0 INDEX 8C ATTR RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STOP_TIME1 3Ch (6 sec) STOP_TIME2 3Ch (6 sec) STOP_TIME3 3Ch (6 sec)
FAN 2 Stop Time
0
8D
RW
FAN 3 Stop Time
0
9A
RW
Reset Condition: Resume Reset, INIT, 5VDD posedge.
BIT NAME ATTRIBUTE DESCRIPTION
7-0
STOP_TIME
R/W
In Thermal Cruise mode, this register determines the time of which PWM duty/DC Level is from stop duty cycle/DC level to 0. The unit of this register is 0.1 second. Set Stop Time to 0 implies never stop FANs. The default value is 6 seconds.
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W83792AD/AG/D/G
8.26 Fan Step Down/Up Time Register -- Index 8Eh 8Fh(Bank 0)
MNEMONIC FAN Step Up Time BANK 0 INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 8E RW UPTIME 0Ah (1 sec) DOWNTIME 0Ah (1 sec)
FAN Step Down Time
0
8F
RW
Reset Condition: Resume Reset, INIT, 5VDD posedge. FAN Step Up Time
BIT NAME ATTRIBUTE DESCRIPTION
7-0
STEP_DOWN_T
R/W
The time interval, which is 0.1 second unit, to decrease PWM duty in Thermal Cruise mode.
FAN Step Down Time
BIT NAME ATTRIBUTE DESCRIPTION
7-0
STEP_UP_T
R/W
The time interval, which is 0.1 second unit, to increase PWM duty in Thermal Cruise mode.
8.27 Fan 1/2/3 Smart Fan II Temperature/ Duty Cycle setups -- Index E0h~EBh 5Fh(Bank 0)
Mnemonic Bank Index Attr BIT 7 BIT 6 8h Fan Duty Cycle Level 2 8h Fan Duty Cycle Level 2 8h reserve 0 reserve 0 reserve 0 reserve 0 reserve 0 reserve 0 Temperature Point 2 28h Temperature Point 3 3Ch Temperature Point 4 50h Temperature Point 2 28h Temperature Point 3 3Ch Temperature Point 4 50h BIT 5 BIT 4 BIT 3 BIT 2 Bh Fan Duty Cycle Level 3 Bh Fan Duty Cycle Level 3 Bh BIT 1 BIT 0
FAN 1 Duty Cycle Level FAN 2 Duty Cycle Level FAN 3 Duty Cycle Level FAN 1 Temperature Point 2 FAN 1 Temperature Point 3 FAN 1 Temperature Point 4 FAN 2 Temperature Point 2 FAN 2 Temperature Point 3 FAN 2 Temperature Point 4
0 0 0 0 0 0 0 0 0
E0 E1 E2 E3 E4 E5 E6 E7 E8
RW RW RW RW RW RW RW RW RW
Fan Duty Cycle Level 2
Fan Duty Cycle Level 3
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W83792AD/AG/D/G
Fan 1/2/3 Smart Fan II Temperature/ Duty Cycle setups -- Index E0h~EBh 5Fh(Bank 0), continued.
Mnemonic Bank Index Attr BIT 7 reserve 0 reserve 0 reserve 0 reserve 0 BIT 6 BIT 5 BIT 4 BIT 3 28h Temperature Point 3 3Ch Temperature Point 4 50h Temperature point above this will turn all FAN to full speed 7Fh BIT 2 BIT 1 BIT 0 Temperature Point 2
FAN 3 Temperature Point 2 FAN 3 Temperature Point 3 FAN 3 Temperature Point 4 All FAN on Temperature Point
0 0 0
E9 EA EB
RW RW RW
0
5F
RW
Reset Condition: Resume Reset, INIT. W83792D also provides a special mode for FAN. It’s called Smart Fan II mode. In this mode, W83792D will output fix cycles when related temperature sensors detects the temperature in preset temperature region. Their relation looks like the following figure. 5Fh specifies a temperature point, if any temperature sensor is sensed above this, all FAN will be push to full speed. Default is 127 degree, that means, this is disabled, since no temperature can higher than 127 degree in W83792D.
Fan Duty Cycle Temp. Tolerance
Fan Duty Cycle 100% Fan Duty Cycle Level 3 Fan Duty Cycle Level 2 Fan Duty Cycle Level 1 Non-Stop Duty Cycle
Temp. 1
Temp.2
Temp.3
Temp.4
Temperature
In Register E0h-EBh defines the relationship of temperature and duty cycle. Also previous Target Temperature and Non-Stop Duty Cycle are used as Temperature Point 1 and minimum duty cycle. To prevent FAN Duty Cycle from throttling at Temperature Point, Temperature Tolerances(87h, 97h) are used to provide a hysterisis mechanism. When temperature is going up (Blue Line), duty cycle changes only when temperature reaches Temperature Point + Tolerance. On the contrary, when temperature is going low (Green Line), duty cycle changes only when sensor temperature down to Temperature Point – Tolerance.
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W83792AD/AG/D/G
FAN Duty Cycle Level
BIT NAME ATTRIBUTE DESCRIPTION
7-4 3-0
Duty Cycle Level 2 Duty Cycle Level 3
R/W R/W
For Smart Fan II mode. The output duty cycle when temperature is between Temperature point 2 and 3. For Smart Fan II mode. The output duty cycle when temperature is between Temperature 3 and 4.
FAN Temperature Point
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
Reserved Temperature
RO R/W
reserved For Smart Fan II mode. Specifies each temperature point at which the output duty cycle changes.
8.28 Value RAM 2⎯ Index B0h B1h B8h ~ BAh (BANK 0)
MNEMONIC 5VSB Readout VBAT Readout FAN4 Readout FAN5 Readout FAN6 Readout FAN7 Readout BANK 0 0 0 0 0 0 INDEX B0 B1 B8 B9 BA BE ATTR RO RO RO RO RO RO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 5VSB Voltage Readout VBAT Voltage Readout FAN 4 Count Reading FAN 5 Count Reading FAN 6 Count Reading FAN 7 Count Reading
5VSB Calculation 5VSB Voltage = CR[B0] * 0.024; VBAT Calculation VBAT Voltage = CR[B1] * 0.016;
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W83792AD/AG/D/G
8.29 Limit RAM 2--- Index B4h~B7h BBh~BDh (BANK0)
MNEMONIC BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 5VSB Voltage High Limit FFh 5VSB Voltage Low Limit 00h VBAT Voltage High Limit FFh VBAT Voltage Low Limit 00h FAN 4 Count Low Limit FFh FAN 5 Count Low Limit FFh FAN 6 Count Low Limit FFh FAN 7 Count Low Limit
5VSB High Limit
0
B4
RO
5VSB Low Limit
0
B5
RO
VBAT High Limit
0
B6
RO
VBAT Low Limit
0
B7
RW
FAN4 Limit
0
BB
RW
FAN5 Limit
0
BC
RW
FAN6 Limit
0
BD
RW
FAN7 Limit
0
BF
RW
FFh
5VSB Limit Setup CR[B4/B5] = [Desired Voltage] / 0.024; VBAT Limit Setup CR[B6/B7] = [Desired Voltage] / 0.016;
8.30 Temperature Sensor 2 (First LM75)
MNEMONIC Temperature 2 Readout Temperature 2 Readout Temperature 2 Config BANK INDEX ATTR 0 0 0 C0 C1 C2 RO RO RW 0.5deg reserve 0 #of faults 0 reserve 0 STOP 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Temperature 2
Temperature 2 Thyst High
0
C3
RW 0.5deg 0
Temperature 2 Thryst 4Bh Reserve 0
Temperature 2 Thyst Low
0
C4
RW
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W83792AD/AG/D/G
Temperature Sensor 2 (First LM75), continued.
MNEMONIC
BANK
INDEX
ATTR
BIT 7 0
BIT 6 C5
BIT 5 RW
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Temperature 2 Over High
Temperature 2 Over Limit 50h 0.5deg 0 reserve 0
Temperature 2 Over Low
0
C6
RW
8.31 Temperature (High Byte) Register - Index C0h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7-0
TEMP2
Read Only
Temperature of VTIN 2, which is high byte.
8.32 Temperature Sensor 2 Temperature (Low Byte) Register - Index C1h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
TEMP2 Reserved
Read Only Read Only
Temperature of VTIN2, which is low byte. Read 0.
8.33 Temperature Sensor 2 Configuration Register - Index C2h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7-5 4-3 2:1 0
Reserved FAULT Reserved STOP2
RO R/W
Reserved Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Reserved When set to 1 the sensor will stop monitor.
R/W
8.34 Temperature Sensor 2 Hysteresis (High Byte) Register - Index C3h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7-0
THYST2
R/W
Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
8.35 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index C4h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
THYST2 Reserved
R/W Read Only
Temperature hysteresis bit 0, which is low Byte. Read 0
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W83792AD/AG/D/G
8.36 Temperature Sensor 2 Over-temperature (High Byte) Register -Index C5h (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7-0
TOVF2
R/W
Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
8.37 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index C6h(Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
TOVF2 Reserved
R/W Read Only
Over-temperature bit 0, which is low Byte. Read 0
8.38 Temperature Sensor 3 (Second LM75)
MNEMONIC Temperature 3 Readout Temperature 3 Readout Temperature 3 Config BANK INDEX ATTR 0 0 0 C8 C9 CA RO RO RW 0.5deg reserve 0 #of faults 0 reserve 0 STOP 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Temperature 3
Temperature 3 Thyst High
0
CB
RW 0.5deg 0
Temperature 3 Thryst 4Bh Reserve 0 Temperature 3 Over Limit 50h 0.5deg 0 Reserve 0
Temperature 3 Thyst Low
0
CC
RW
Temperature 3 Over High
0
CD
RW
Temperature 3 Over Low
0
CE
RW
8.39 Temperature Sensor 3 Hysteresis (High Byte) Register - Index CBh (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7-0
THYST3
R/W
Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.
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W83792AD/AG/D/G
8.40 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index CCh (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
6-0 7
Reserved THYST3
Read Only R/W
Read 0 Temperature hysteresis bit 0, which is low Byte.
8.41 Temperature Sensor 3 Over-temperature (High Byte) Register - Index CDh (Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7-0
OVTF3
R/W
Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.
8.42 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index CEh(Bank 0)
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
OVTF3 Reserved
R/W
Over-temperature bit 0, which is low Byte. Reserved
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W83792AD/AG/D/G
9 . ARP (ADDRESS RESOLUTION PROTOCOL) REGISTERS
9.1 Unique Device Identifier (UDID) -- 20h-2Fh (Bank 1)
In order to provide a mechanism to isolate each device for the purpose of address assignment each device must implement a unique device identifier (UDID).
MNEMONIC Device Capability BANK INDEX ATTR 1 20 RO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PEC 0 0 1
Random Number 1 1 0 0
RESERVED 0
Version/Revision
1
21
RO
RESERVED 0 0
SMBUS 2.0 SUPPORT SILICON REVISION 0 0 1 0 1 1
Vendor ID
1
22-23
RO
WINBOND PCI SIG VENDOR ID 1050h DEVICE ID assigned by Manufacturer 0100h ASF protocol layer interface over SMBus. 0024h SUBSYSTEM VENDOR 0000h SUBSYSTEM 0000h VENDOR SPEC Random Number
Device ID
1
24-25
RW
Interface
1
26-27
RW
Subsystem Vendor ID
1
28-29
RW
Subsystem Device ID
1
2A-2B
RW
Vendor specific ID
1
2C-2F
RW
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W83792AD/AG/D/G
NAME
DESCRIPTIONS
Device Capabilities Version/Rev ision Vendor ID Device ID Interface Subsystem Vendor ID
Describes the device’s capabilities. See detail SMBus 2.0. UDID version number and silicon revision identification. See detail SMBus2.0. The device manufacturer’s ID as assigned by the SBS Implementers’ Forum or the PCI SIG. The device ID as assigned by the device manufacturer (identified by the Vendor ID field). Identifies the protocol layer interfaces supported over the SMBus connection by the device. For example, ASF and IPMI. This field may hold a value derived from any of several sources: 1. The device manufacturer’s ID as assigned by the SBS Implementers’ Forum or the PCI SIG. 2. The device OEM’s ID as assigned by the SBS Implementers’ Forum or the PCI SIG. 3. A value that, in combination with the Subsystem Device ID, can be used to identify an organization or industry group that has defined a particular common device interface specification.
Subsystem Device ID Vendor Specific ID
The subsystem ID identifies a specific interface, implementation, or device. The part identified by the Subsystem Vendor ID field defines the subsystem ID. A unique number per device. See detail SMBus 2.0.
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W83792AD/AG/D/G
1 0. ASF SENSOR ENVIRONMENTAL EVENT
10.1 Temperature: Get Event Data message
In the W83792D, it has three temperatures for monitoring System Board, CPU1, and CPU2. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET DATA TEMPERATURE 1
Event sensor type Event type Event offset
0x01 (Temperature sensor) Threshold-based: 0x01h.
Event Status: 011b (Asserted, Send) (iii) Upper Temp. 0x01:Threshold-based 0x09: Upper critical going Event Status: 011b (Asserted, Send) (v) (iv) 0x01:Threshold-based 0x08: Upper Critical, going (Reserved)
(ii)
0x01:Threshold-based 0x07: Upper non-critical going Lower Temp
0x01:Threshold-based 0x06 : Upper Non-critical, going low.
0x01:Threshold-based (i) 0x01:Threshold-based 0x01: Lower Non-critical Going (Reserved) (vi) 0x00: Lower non-critical, going
Event Status: 010b (Deasserted, Send)
Event sensor type: 0x01 Event Type: 0x01
Event source type Sensor device The W83792D is complying ASF 2.0.I specification and the value is 0x68.
The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83792D is ARP assigned address. VCOREA). Sensor number Temperature 1: 0Dh (Don’t use 00h and FFh. Therefore 01h Temperature 2: 0Eh Temperature 3: 0Fh Entity ID Temperature 1: 07h (System board) Temperature 2/3: 03h (Processor) These are defined in Table 6 of PET v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device.
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Temperature: Get Event Data message, continued.
ASF PACKET DATA
TEMPERATURE 1
Entity instance Temperature 1: 01h (main system board). Temperature 2: 01h (Processor 1) Temperature 3: 02h (Processor 2) These are programmable. Event status index Temperature 1: 0Ch (zero-based) Temperature 2: 0Dh Temperature 3: 0Eh Event status Status Value Status type Description Byte Count for GetEventStatus 0Ah
0000_0010b Deasserted (send) Refer as above figure. 0000_0011b Asserted (send) 0000_0111b Event Status End
W83792D will respond all 0Ah relative information. When event status index 02h is more than 14h, the machine will be ended the transmission.
Event Severity Monitor (0x01): That is represented the monitored temperature is under the lower temperature. Non Critical (0x08): that is represented the temperature is located between the lower and upper temperature. Critical Condition (0x10): that is represented the monitored temperature is over the upper temperature.
Critical Condition (0x10) Upper Temp. Non Critical (0x08) Lower Temp. Monitor (0x01)
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Event Offset, Type and Severity
DESCRIPTION SENSOR TYPE EVENT TYPE EVENT OFFSET STATUS EVENT SEVERITY
TEMPERATURE SENSORS Upper-Critical Going High Upper-Critical Going Low Upper-Non-critical Going High Upper-Non-critical Going Low Lower-Non-critical Going High Lower-Non-critical Going Low Generic Over Voltage Problem Normal Voltage Generic Under Voltage Problem Normal FAN Speed Generic FAN Failure 07h 02h Voltage GenericSeverity 01h Temperature 01h ThresholdBased 09h 08h 3h 07h 06h 01h 00h VOLTAGE SENSORS 02h 07h 02h FAN SENSORS 04h Fan 07h CASEOPEN Case Intruded Case Normal 05h Physical Security 6Fh Sensor Specific 00h 80h 3h 2h 10h 01h 07h 02h 2h 3h 01h 10h 3h 2h 3h 10h 01h 10h 2h Deassert 01h Monitor Assert 08h Non-critical 10h Critical
THERMAL TRIP SENSORS Thermal Trip Occurs No Thermal Trip 07h Processor 01h 6Fh 81h 2h 01h 3h 10h
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Entity ID and Instance (Default):
ENTITY ID ENTITY INSTANCE SENSOR IN W83792D EVENT STATUS INDEX EVENT NUMBER EVENT SENSOR TYPE
(PROGRAMMABLE) (PROGRAMMABLE)
01h 02h 03h 04h 05h 07h (System Board) 06h 07h 01h 02h 03h 04h 01h 01h 01h 01h 02h 02h 02h 01h 02h 01h
VIN0 VIN1 VIN2 VIN3 5VDD VSB VBAT FAN1 FAN4 FAN5 FAN6 Temperature1 VCOREA FAN2 Temperature 2 VCOREB FAN3 Temperature 3 Thermal Trip 1 Thermal Trip 2 Case Intrusion
02h 03h 04h 05h 06h 07h 08h 09h 0Fh 10h 11h 0Ch 00h 0Ah 0Dh 01h 0Bh 0Eh 12h 13h 14h
03h 04h 05h 06h 07h 08h 09h 0Ah 10h 11h 12h 0Dh 01h 0Bh 0Eh 02h 0Ch 0Fh 13h 14h 15h
02h (Voltage) 02h 02h 02h 02h 02h 02h 04h (Fan) 04h 04h 04h 01h (Temperature) 02h 04h 01h 02h 04h 01h 07h (Processor) 07h (Processor) 05h (Physical Security)
03h (Processor)
23h (System Chassis)
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10.2 Voltage: Get Event Data message
In the W83792D, it has nine voltage inputs for monitoring System Board, CPU1, and CPU2. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET DATA VOLTAGE INPUT
Event sensor type 02h (Voltage sensor) Event type Event offset Discrete (Generic Severity): 07h
(i) 07h: Discrete (Generic Severity) 02h: Transition to Critical from less severe Event Status: 011b (Asserted, send) High voltage 07h: Discrete (Generic Severity) 07h: Monitor Low voltage Event Status: 010b (Deasserted, send) 07h: Discrete (Generic Severity) (ii) 02h: Transition to Critical from less severe Event Status: 011b (Asserted, send)
Event sensor type: 02h (Voltage) Event Type: 07h (Discrete, Generic Severity)
Event source type The W83792D is complying ASF 2.0.I specification and the value is 0x68. Sensor device The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83792D is ARP assigned address. The number is shown as following: Voltage Sensor VCOREA VCOREB VIN0 VIN1 VIN2 VIN3 5VDD VSB VBAT Sensor Number 01h 02h 03h 04h 05h 06h 07h 08h 09h
Sensor number
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Voltage: Get Event Data message, continued.
ASF PACKET DATA
VOLTAGE INPUT
Entity ID
The Entity ID is shown as following. Voltage Sensor VCOREA VCOREB VIN0 VIN1 VIN2 VIN3 5VDD VSB VBAT These ID are defined in Table 6 of PET v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. 07h (System board) Entity ID 03h (Processor)
Entity instance
The Entity Instance is shown as following. Sensor VCOREA VCOREB VIN0 VIN1 VIN2 VIN3 5VDD VSB VBAT Entity Instance 01h 02h 01h 02h 03h 04h 05h 06h 07h
Event status index VCOREA: 00h VCOREB: 01h VIN0: 02h VIN1: 03h VIN2: 04h VIN3: 05h 5VDD: 06h VSB: 07h VBAT: 08h
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Voltage: Get Event Data message, continued.
ASF PACKET DATA
VOLTAGE INPUT
Event status
Event Severity
W83792D will respond all relative information. 0000_0111b Event Status End When event status index 02h is more than 0Fh, the machine will be ended the transmission. Monitor (0x01): That is represented the monitored voltage is during the limit value. Critical Condition (0x10): that is represented the monitored voltage is over the limit value.
Critical Condition (0x10) Upper Volt. Monitor (0x01) Lower Volt. Critical Condition (0x10)
Status Value 0000_0010b 0000_0011b
Status type Desserted (send) Asserted (send)
Description
Byte Count 0Ah 0Ah
10.3 Fan: Get Event Data message
In the W83792D, it has Six Fan tachometers for monitoring System Board, CPU1, and CPU2. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET DATA FAN CLOCK INPUT
Event sensor type 04h (Fan speed sensor) Event type Discrete (Generic Severity): 07h
07h: Discrete 07h: Monitoring Event Status: 010b (Deasserted, send) High Speed (Low Count) Fan Limit Lower Speed (High Count) Event Status: 011b (Asserted, send) 07h: Discrete 02h: Transition from less severe to critical
Event sensor type: 04h Event Type: 07h Discrete
Publication Release Date: April 26, 2006 Revision 0.9
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Fan: Get Event Data message, continued.
ASF PACKET DATA
FAN CLOCK INPUT
Event source type The W83792D is complying ASF 2.0.I specification and the value is 0x68. Sensor device The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83792D is ARP assigned address. The number is shown as following: Fan Sensor FAN 1 FAN 2 FAN 3 FAN 4 FAN 5 FAN 6 Entity ID The Entity ID is shown as following. Voltage Sensor FAN 1 FAN 2 FAN 3 FAN 4 FAN 5 FAN 6 These ID are defined in Table 6 of PET v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. Entity instance The Entity Instance is shown as following. Fan Sensor FAN 1 FAN 2 FAN 3 FAN 4 FAN 5 FAN 6 Entity Instance (default) 01h (Main system board) 01h (Processor 1) 02h (Processor 2) 02h (Main system board) 03h (Main system board) 04h (Main system board) 07h Entity ID (default) 07h (System board) 03h (Processor) Sensor Number 0Ah 0Bh 0Ch 11h 12h 13h
Sensor number
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Fan: Get Event Data message, continued.
ASF PACKET DATA
FAN CLOCK INPUT
Event index
status FAN1 : 0Ah FAN2 : 0Bh FAN3 : 0Ch Status Value 0000_0010b Deasserted (send) Status type Description Byte Count 0Ah
Event status
0000_0011b Asserted (send) 0000_0100b Disabled
W83792D will respond all 0Ah relative information. FAN 6 also supports Watch Dog Timer function. ASF return disabled when the pin switch to Watch Dog Function. 02h
0000_0111b Event Status End When event status index is more than 0Fh, the machine will be ended the transmission.
02h
Event Severity
Monitor (0x01): That is represented the monitored fan count is under the limit count. Critical Condition (0x10): that is represented the monitored fan count is over the limit count.
Monitor (0x01) Upper Speed Fan Speed Lower Speed Critical Condition (0x10)
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10.4 Case Intrusion: Get Event Data message
In the W83792D, it has one chassis intrusion monitoring for System Board. The listed table shows the entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET DATA CASE INTRUSION INPUT
Event sensor type 05h (Chassis Intrusion) Event type Sensor Specific : 6Fh
Logic High Event type: 6Fh Event offset: 80h (Deassert) Event Status: 010b (Deasserted, send) Logic Low Event type: 6Fh Event offset: 00h (Asserted) Event Status: 011b (Asserted, send)
Event sensor type: 05h (Physical security) Event Type: 6Fh ( Sensor specific)
Event source type The W83792D is complying ASF 2.0.I specification and the value is 0x68. Sensor device The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83792D is ARP assigned address. Sensor number The sensor number for case intrusion is 15h Entity ID The Entity ID is 23h for case intruded These ID are defined in Table 28-11 of IPMI v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. Entity instance The Entity Instance is 01h for (Main system board) Event status 0x14 (W83792D sensor index) index Event status Status Status type Description Byte Value Count 0000_0010b Deasserted (send) 0Ah 0000_0011b Asserted (send) W83792D will respond all 0Ah relative information. 0000_0111b Event Status End When event status index 02h is more than 0Fh, the machine will be ended the transmission.
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Case Intrusion: Get Event Data message, continued.
ASF PACKET DATA
CASE INTRUSION INPUT
Event Severity
Monitor (0x01): That is represented the monitored CASEOPEN is logic Low Critical Condition (0x10): that is represented the monitored CASEOPEN is logic High.
Logic High
Monitor (0x01) Critical Condition (0x10) Logic Low
Case Intruded Input Pin
10.5 Thermal Trip: Get Event Data message
In the W83792D, it has two thermal trip monitoring for System Board. The listed table shows the entity ID, entity instance, event source type, event type, event offset, and so on.
ASF PACKET DATA THERMAL TRIP INPUT
Event sensor type 07h (Processor related event) Event type Sensor Specific : 6Fh
Logic High Event type: 6Fh Event offset: 81h (Deassert) Event Status: 010b (Deasserted, send) Logic Low Event type: 6Fh Event offset: 01h (Asserted) Event Status: 011b (Asserted, send)
Event sensor type: 07h (Processor) Event Type: 6Fh ( Sensor specific)
Event source type The W83792D is complying ASF 2.0.I specification and the value is 0x68. Sensor device The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83792D is ARP assigned address. The sensor number for thermal trip 1 is 13h ; 14h for thermal trip 2. The Entity ID is 3h for thermal trip. These ID are defined in Table 6 of PET v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device.
Sensor number Entity ID
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Thermal Trip: Get Event Data message, continued.
ASF PACKET DATA
THERMAL TRIP INPUT
Entity instance Event index
The Entity Instance is 01h for Thermal Trip 1. 02h for thermal trip 2. 0x13 (Thermal Trip 2) Status Value 0000_0010b Deasserted (send) Status type Description Byte Count 0Ah
status 0x12 (Thermal Trip 1)
Event status
0000_0011b Asserted (send) 0000_0111b Event Status End
W83792D will respond all 0Ah relative information. 02h When event status index is more than 0Fh, the machine will be ended the transmission.
Event Severity
Monitor (0x01): That is represented the monitored Thermal trip is logic Low Critical Condition (0x10): that is represented the monitored Thermal Trip has been logic High.
Logic High
Monitor (0x01) Critical Condition (0x10) Logic Low
Case Intruded Input Pin
Once W83792D detects thermal trip event, it will report to host polling. Thermal Trip event can only be cleared by CLR_TT, the event itself is latched by VBAT power.
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W83792AD/AG/D/G
10.6 ASF Response Registers -- 40h-7Fh (Bank 1)
10.6.1 ASF Critical/non-critical Temperature Registers:
These registers shall never assign negative temperature. Generic/Upper/Under temperature
MNEMONIC Temp 1 Noncritical BANK 1 INDEX 40 ATTR RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Temp 1 Noncritical 4Bh Temp 1 Critical 50h Temp 2 Noncritical 4Bh Temp 2 Critical 50h Temp 3 Noncritical 4Bh (75 DEGREE) Temp 3 Critical 50h (80 DEGREE)
Temp 1 Critical
1
41
RW
Temp 2 Noncritical
1
42
RW
Temp 2 Critical
1
43
RW
Temp 3 Noncritical
1
44
RW
Temp 3 Critical
1
45
RW
10.6.2 Sensor device: (SMBus Address, Read/Write)
MNEMONIC ASF Address BANK 1 INDEX 4F ATTR RO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SMBus address assigned by ARP 00h
10.6.3 Relative Entity ID Table
MNEMONIC Vcore A Entity ID BANK 1 INDEX 50 ATTR RW BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Vcore A Entity ID 3(CPU) Vcore B Entity ID 3(CPU) VIN0 Entity ID 7(System) VIN1 Entity ID 7(System)
Vcore B Entity ID
1
51
RW
VIN0 Entity ID
1
52
RW
VIN1 Entity ID
1
53
RW
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Relative Entity ID Table, continued
MNEMONIC VIN2 Entity ID VIN3 Entity ID 5VCC Entity ID VSB Entity ID VBAT Entity ID FAN 1 Entity ID FAN 2 Entity ID FAN 3 Entity ID FAN 4 Entity ID FAN 5 Entity ID FAN 6 Entity ID Chassis Entity ID Temp 1 Entity ID Temp 2 Entity ID Temp 3 Entity ID FAN7 Entity ID
BANK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
INDEX 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63
ATTR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
BIT 7
BIT 6
BIT 5
BIT 4 BIT 3 BIT 2 VIN2 Entity ID 7(System) VIN3 Entity ID 7(System) 5VCC Entity ID 7(System) VSB Entity ID 7(System) VBAT Entity ID 7(System) FAN 1 Entity ID 7(System) FAN 2 Entity ID 3(CPU) FAN 3 Entity ID 3(CPU) FAN 4 Entity ID 7(SYSTEM) FAN 5 Entity ID 7(SYSTEM) FAN 6 Entity ID 7(SYSTEM) Chassis Entity ID 23(Chassis) Temp 1 Entity ID 7(SYSTEM) Temp 2 Entity ID 3(CPU) Temp 3 Entity ID 3(CPU) FAN7 Entity ID 7(SYSTEM)
BIT 1
BIT 0
Table of Entity ID defined in PET 1.0 or IPMI 1.0
ENTITY DEFINITION ENTITY ID
CPU System Memory module System Chassis Fan/Cooling device Memory device
3 7 8 23 29 32
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10.6.4 Entity Instance Register Maximum number of instance is 15
MNEMONIC ENTITY INSTANCE I ENTITY INSTANCE II ENTITY INSTANCE III ENTITY INSTANCE IV ENTITY INSTANCE V ENTITY INSTANCE VI ENTITY INSTANCE VII ENTITY INSTANCE VIII ENTITY INSTANCE IX ENTITY INSTANCE X ENTITY INSTANCE XI BANK INDEX ATTR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Vcore B Vcore A 1 70 RW 2 (CPU B) 1 (CPU A) VIN1 VIN0 1 71 RW 2 (SYSTEM 1) 1 (SYSTEM 1) VIN3 VIN2 1 72 RW 4 (SYSTEM 1) 3(SYSTEM 1) VSB 5VCC 1 73 RW 6(SYSTEM 1) 5 (SYSTEM 1) FAN1 VBAT 1 74 RW 1 (SYSTEM 1) 7 (SYSTEM 1) FAN3 FAN2 1 75 RW 2 (CPU B) 1 (CPU A) TEMP2 TEMP1 1 76 RW 1 (CPU A) 1 (SYSTEM 1) FAN4 TEMP3 1 77 RW 2 (SYSTEM 1) 2 (CPU B) FAN6 FAN5 1 78 RW 4 (SYSTEM 1) 3(SYSTEM 1) FAN7 CHASSIS 1 79 RW 5(SYSTEM 1) 1 (SYSTEM Chassis) THERMALTRIP2 THERMALTRIP1 1 7A RW 2 1
The Entity for a given event varies according to what entity the environmental sensor is monitoring. For example, a typical managed system board can have temperature monitoring associated with the system board and with the main processor. Thus, the Entity IDs and Entity Instance values for these would be Entity ID=7, Entity Instance=1 for ‘main system board’ and Entity ID=3, Entity Instance=1 for ‘processor 1’, respectively.
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10.6.5 Remote Control Configuration Registers
MNEMONIC Remote Power On Command Remote Power Down Command Remote Reset Command Remote Power on Control BANK INDEX ATTR BIT 7 BIT 6 BIT 5 1 1 1 1 7D 7E 7F 7C RW RW RW RW AV 0 BIT 4 11h 12h 10h AR ASF_TM DIS_RMC 0 0 0 PWR1T 0 BIT 3 BIT 2 BIT 1 BIT 0
Reset Condition: Resume Reset These registers define the Remote control command for each remote control function. When Remote Power on command received by W83792D, PWRBTN# will be asserted for 100ms every 1sec if PWR1T is clear to 0, the process will continue until 5VCC is detected as high. If PWR1T is set to 1, PWRBTN# will be asserted only once, no matter 5VCC is high or low. ASF_TM is ASF test mode in production test. We strongly recommend you not to use this in normal operation. Notice: User should avoid continuously sending Remote Control Command. If last Remote Command execution is not complete, and next remote command comes in. W83792D ignores (blocks) next remote command, and complete the first one only.
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W83792AD/AG/D/G
1 1. ELECTRICAL CHARACTERISTICS
11.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage(Storage) Power Supply Voltage(Operate) Input Voltage Operating Temperature Storage Temperature
-0.5 to 7.0 4.5 to 5.5 -0.5 to VDD+0.5 0 to +70 -55 to +150
V V V °C °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
11.2 DC Characteristics
(Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)
PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V μA μA IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V μA μA VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V
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DC Characteristics, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA
OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage VOL 0.4 V IOL = 8 mA
OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 V IOL = 12 mA
OD48 - Open-drain output pin with sink capability of 48 mA Output Low Voltage VOL 0.4 V IOL = 48 mA
INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V μA μA VIN = VDD VIN = 0 V
- TTL level Schmitt-triggered input pin VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V μA μA VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V
Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage
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W83792AD/AG/D/G
11.3 AC Characteristics
11.3.1 Serial Bus Timing Diagram
t SCL t R R
t
SCL
t HD;SDA
t SU;DAT t SU;STO
SDA IN
VALID DATA
t HD;DAT
SDA OUT Serial Bus Timing Diagram
Serial Bus Timing
PARAMETER SYMBOL MIN. MAX. UNIT
SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time
t SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF
-
10 4.7 4.7 120 5 1.0 300
uS uS uS nS nS uS nS
11.3.2 VID Input Skew
t skew
t hold
VIDA[5:0]/VIDB[5:0]
VALID VID
VALID VID
VID Input Timing
PARAMETER SYMBOL MIN. MAX. UNIT
VID Input Unstable Time VID Valid Input Hold Time
t Skew t-hold 4
-
0.8
uS uS
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1 2. THE TOP MARKING
The top marking of W83792D
inbond
W83792D 2326952Z - 91 333GCSB
First Line Second Line Third Line Fourth Line Winbond Logo. The chip part number: W83792D, D means LQFP package. Serial number Tracking Code: 3 33 G C SB For Package information Package was made in 2003 3 33 G C SB Week: 33 Assembly house ID; G means Greatek; A means ASE; O means OSE The IC version The Mask version
The top marking of W83792G
inbond
W83792G 2326952Z - 91 333GCSB
First Line Second Line Third Line Fourth Line Winbond Logo. The chip part number: W83792G, G means Pb-free package. Serial number Tracking Code: 3 33 G C SB For Package information Package was made in 2003 3 33 G C SB Week: 33 Assembly house ID; G means Greatek; A means ASE; O means OSE The IC version The Mask version
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W83792AD/AG/D/G
The top marking of W83792AD
inbond
W83792AD 2326952Z - 91 333GCSB
First Line Second Line Third Line Fourth Line Winbond Logo. The chip part number: W83792AD, D means LQFP package. Serial number Tracking Code: 3 33 G C SB For Package information 3 33 G C SB Package was made in 2003 Week: 33 Assembly house ID; G means Greatek; A means ASE; O means OSE The IC version The Mask version
The top marking of W83792AG
inbond
W83792AG 2326952Z - 91 333GCSB
First Line Second Line Third Line Fourth Line Winbond Logo. The chip part number: W83792AG, G means Pb-free package. Serial number Tracking Code: 3 33 G C SB For Package information 3 33 G C SB Package was made in 2003 Week: 33 Assembly house ID; G means Greatek; A means ASE; O means OSE The IC version The Mask version
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W83792AD/AG/D/G
1 3. ACKAGE SPECIFICATION
(48-pin LQFP)
HD D
36 25
Symbol
Dimension in inch Min. Nom. Max.
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2 A1 y
A
Seating Plane
See Detail F
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
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W83792AD/AG/D/G
1 4. W83792AD/AG APPLICATION CIRCUIT
5VSB 3.3VSB R1 4.7K R3 4.7K R4 SDA SCL R6 100k FANOUT3 R7 100k F ANOUT3 R8 10K VCOREA VCOREB VIN0 VIN1 VIN2 VIN3 VABT CASEOPEN CPUA_TTP# 5VSB VRM_EN R5 330 330 R2 4.7K SMSDA SMCLK
Select VID Table
5VSB
5VCC 5VSB R10 100k FAN_OUT1 R13 100k FAN_OUT2 SMI# OVT# R11 4.7K R12 4.7K VREF VTIN3 VTIN2 VTIN1 FANOUT4 FANIN4 FANOUT5 FANIN5 FANOUT6 FANIN6 37 38 39 40 41 42 43 44 45 46 47 48 VREF VTIN3 VTIN2 VTIN1 SMI#/IRQ OVT# FAN_OUT4/GPIOA0 FANIN4/GPIOA1 FAN_OUT5/GPIOA2 FANIN5/GPIOA3 WDTRST#/FAN_OUT6 SY SRSTIN#/FANIN6
VCOREA VCOREB VIN0 VIN1 VIN2 VIN3 VBAT CASEOPEN VRM_EN GND NC THERMTRIP1#
36 35 34 33 32 31 30 29 28 27 26 25
Select I2C ADD
CPUD-
Pull High : Old table(VRM9.X) Pull Low : New table(VRD10.0)
3VSB
R9 4.7K
CSB Version
VIDA0/GPOA4 VIDA1/GPOA5 VIDA2/GPOA6 VIDA3/GPOA7 VIDA4/GPOB0 VIDA5/GPOB1 GPOB2 GPOB3 GPOB4 GPOB5 GPOB6 GPOB7
W 83792AD
+5VSB PWRBTN# SDA SCL FANIN1 FANIN2 FANIN3 CLK FAN_OUT1/A0 FAN_OUT2/A1 FAN_OUT3/VID90_10 VDD
24 23 22 21 20 19 18 17 16 15 14 13
5VSB SDA SCL FANIN1 FANIN2 FANIN3 14.318CLK FANOUT1 FANOUT2 FANOUT3 PWRBTN# C1 10u/16V C2 0.1u CPUDL1 5VCC INDUCTOR C3 10u/16V C4 0.1u
FAN_OUT2(A1=0)
FAN_OUT2(A1=1)
FAN_OUT1(A0=1)
792D(0X5A) T2(0x92) T3(0x9A)
792D(0X5E) T2(0x96) T3(0x9E)
L2 CPUDINDUCTOR
1 2 3 4 5 6 7 8 9 10 11 12
FAN_OUT1(A0=0)
792D(0X58) T2(0x90) T3(0x98)
792D(0X5C) T2(0x94) T3(0x9C)
CPUD-
VIDA0 VIDA1 VIDA2 VIDA3 VIDA4 VIDA5
Y1 OUT 8 14.318CLK
14.318M hz
Title Size Date:
W83792AD Application Circuit Document Number Thursday , Nov ember 10, 2005 Sheet 1 of 4 Rev 0.6
- 83 -
Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
VREF
R14
RT1
T
Temperature Sensing
10K 1% R17 10K 1% R19 10K 1% VTIN1 VTIN2 VTIN3
Voltage Sensing
10K 1%
(for system)
R15 CPUA CPUB R16
10K 10K
THERMISTOR RT2
VCOREA VCOREB
T
10K 1%
(for cpu1) (for cpu2)
THERMISTOR RT3
T
10K 1%
+3.3V
R18
10K 1%
VIN0
THERMISTOR +5V C PUDVIN1 R20 34K 1% R21 50K 1%
CPUD-
Case Open Circuits
VBAT S1 CASEOPEN CASEOPEN SW R24
Measuring CPU temperature by either thermistor or diode.
R22 10K 1% R23 232K 1% -12V VIN2 D+ 3300p CPUDC5 DVREF
VREF VTIN2
R25 15K 1%
10M R26 10K 1% R27 120K 1%
(from CPU)
-5V VIN3
VID Circuit
CPUAVID5 CPUAVID4 CPUAVID3 CPUAVID2 CPUAVID1 CPUAVID0 R28 R29 R30 R31 R32 R33 1K 1K 1K 1K 1K 1K VIDA5 VIDA4 VIDA3 VIDA2 VIDA1 VIDA0
(From CPUA)
Title Size Date:
W83792AD H/W Sensing Circuit Document Number Thursday , Nov ember 10, 2005 Sheet 2 of 4 Rev 0.6
- 84 -
W83792AD/AG/D/G
+12V R34 R35 4.7K 1K Q1 PNP 3906
PWM FAN OUTPUT
FANOUT1 LM358 U2A
+12V
DC FAN OUTPUT
3
PWMOUT1 +
R36
470K 2 Q3 P DGS TO-1
R38 R 39 6.49K +12V R40 R41 4.7K 1K Q3 PNP 3906 PWMOUT2 Q4 MOSFET N 2N7002 C7 10u + FANOUT2 LM358
10K
1
FANOUT1
R37
510
Q2 MOSFET N 2N7002
C6 10u
FANOUT2
R43 470K
2 Q7 P DGS TO-1
U3A R44 R45 6.49K 10K 1
3
R42
510
+3.3V DCOUT1 R46 0 D1 1N4148 PWMOUT1 R48 0 JP1 3 2 1 HEADER 3 FANIN1 R47 4.7K
R63, R66 FOR DC FAN R65, R68 FOR PWM FAN
DCOUT2 R49 0 D2 1N4148
+3.3V
R50 4.7K
PWMOUT2
R51
0
JP2 3 2 1 HEADER 3 FANIN2
- 85 -
+ +
DCOUT1
+12V
DCOUT2
Title Size Date:
W83792AD FAN OUTPUT CIRCUIT Document Number Thursday , Nov ember 10, 2005 Sheet 3 of 4 Rev 0.6
Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
R59 FANOUT1 VCC12 100K C8 0.1U R60 FANOUT2 VCC12 100K C11 0.1U C13 0.1U C12 0.1U 2 3 4 5 6 C15 0.1U 7 1 U6 FAN1_IN FAN2_IN VCC12 C1 C2 CHRPMP GND FAN1_DRV FAN1_SEN FAN2_DRV FAN2_SEN FAN3_DRV FAN3_SEN FAN3_IN W83391TS 14 13 12 11 10 9 8 R64 6.49K C16 VCC12 1 470u 2 C14 10n 3 R62 6.49K C10 VCC12 1 470u C9 10n 2 R61 10K DCOUT1 3 1 Q6 N DGS TO-252
Q7 N DGS TO-252
R63 10K DCOUT2
R65 F ANOUT3 100K C18 0.1U R66 10K 2 C17 10n 3
Q8 N DGS TO-252
DCOUT3 R67 6.49K C19 470u
Title Size B Date:
W83792D with W83391TS FAN OUTPUT CIRCUIT Document Number Thursday , Nov ember 17, 2005 Sheet 4 of 4 Rev 0.6
- 86 -
W83792AD/AG/D/G
1 5. W83792D/G APPLICATION CIRCUIT
5VSB R1 R2 4.7K SMSDA SMCLK R4 330
Select VID Table
5VSB R5 100k FANOUT3 R7 100k FANOUT3 VRM_EN CPUDCPUB_TTP# CPUA_TTP# VCOREA VCOREB VIN0 VIN1 VIN2 VIN3 VABT CASEOPEN R6 4.7K 3.3VSB
4.7K R3 SDA SCL 330
Pull High : Old table(VRM9.X) Pull Low : New table(VRD10.0)
5VCC 5VSB R9 100k FAN_OUT1 R12 100k FAN_OUT2 SMI# OVT# R10 4.7K R11 4.7K VREF VTIN3 VTIN2 VTIN1 FANOUT4 FANIN4 FANOUT5 FANIN5 FANOUT6 FANIN6 37 38 39 40 41 42 43 44 45 46 47 48 VREF VTIN3 VTIN2 VTIN1 SMI#/IRQ OVT# FAN_OUT4/GPIOA0 FANIN4/GPIOA1 FAN_OUT5/GPIOA2 FANIN5/GPIOA3 WDTRST#/FAN_OUT6 SY SRSTIN#/FANIN6
VCOREA VCOREB VIN0 VIN1 VIN2 VIN3 VBAT CASEOPEN VRM_EN/FANOUT7 GND THERMTRIP2# THERMTRIP1#/FANIN7
36 35 34 33 32 31 30 29 28 27 26 25
Select I2C ADD
3VSB
R8 4.7K
CSB Version
VIDA0/GPOA4 VIDA1/GPOA5 VIDA2/GPOA6 VIDA3/GPOA7 VIDA4/GPOB0 VIDA5/GPOB1 VIDB0/GPOB2 VIDB1/GPOB3 VIDB2/GPOB4 VIDB3/GPOB5 VIDB4/GPOB6 VIDB5/GPOB7
W83792D
+5VSB PWRBTN# SDA SCL FANIN1 FANIN2 FANIN3 CLK FAN_OUT1/A0 FAN_OUT2/A1 FAN_OUT3/VID90_10 VDD
24 23 22 21 20 19 18 17 16 15 14 13
5VSB SDA SCL FANIN1 FANIN2 FANIN3 14.318CLK FANOUT1 FANOUT2 FANOUT3 PWRBTN# C1 10u/16V C2 0.1u CPUDL1 5VCC INDUCTOR C3 10u/16V C4 0.1u
FAN_OUT2(A1=0)
FAN_OUT2(A1=1)
FAN_OUT1(A0=1)
792D(0X5A) T2(0x92) T3(0x9A)
792D(0X5E) T2(0x96) T3(0x9E)
L2 CPUDINDUCTOR
1 2 3 4 5 6 7 8 9 10 11 12
FAN_OUT1(A0=0)
792D(0X58) T2(0x90) T3(0x98)
792D(0X5C) T2(0x94) T3(0x9C)
CPUD-
VIDA0 VIDA1 VIDA2 VIDA3 VIDA4 VIDA5 VIDB0 VIDB1 VIDB2 VIDB3 VIDB4 VIDB5
Y1 OUT 8 14.318CLK
14.318M hz
Title Size Date:
W83792D Application Circuit Document Number Thursday , Nov ember 10, 2005 Sheet 1 of 4 Rev 0.6
- 87 -
Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
VREF
R13
T
Temperature Sensing
10K 1% R16 10K 1% R18 10K 1% VTIN1 VTIN2 VTIN3
Voltage Sensing
RT1 10K 1%
(for system)
THERMISTOR RT2
C PUA CPUB
R14 R15
10K 10K
VCOREA VCOREB
T
10K 1%
(for cpu1)
THERMISTOR RT3
T
10K 1%
(for cpu2)
+3.3V
R17
10K 1%
VIN0
THERMISTOR +5V CPUDVIN1 R19 34K 1% R20 50K 1%
CPUD-
Case Open Circuits
VBAT S1 CASEOPEN CASEOPEN SW R23
Measuring CPU temperature by either thermistor or diode.
R21 10K 1% R22 232K 1% -12V VIN2
VREF VTIN2
R24 15K 1% 3300p D+ VREF
10M R25 10K 1% R26 120K 1%
(from CPU)
D-
CPUD-
C5
-5V VIN3
VID Circuit
CPUAVID5 CPUAVID4 CPUAVID3 CPUAVID2 CPUAVID1 CPUAVID0 R27 R29 R31 R33 R35 R37 1K 1K 1K 1K 1K 1K VIDA5 VIDA4 VIDA3 VIDA2 VIDA1 VIDA0 CPUBVID5 CPUBVID4 CPUBVID3 CPUBVID2 CPUBVID1 CPUBVID0 R28 R30 R32 R34 R36 R38 1K 1K 1K 1K 1K 1K VIDB5 VIDB4 VIDB3 VIDB2 VIDB1 VIDB0
(From CPUA)
(From CPUB)
Title Size Date:
W83792D H/W Sensing Circuit Document Number Thursday , Nov ember 10, 2005 Sheet 2 of 4 Rev 0.6
- 88 -
W83792AD/AG/D/G
+12V R39 R40 4.7K 1K Q1 PNP 3906
PWM FAN OUTPUT
FANOUT1 LM358 U2A
+12V
DC FAN OUTPUT
3
PWMOUT1 +
R41
470K 2 Q3 P DGS TO-1
R43 R44 6.49K +12V R45 R46 4.7K 1K Q3 PNP 3906 PWMOUT2 Q4 MOSFET N 2N7002 C7 10u + FANOUT2 LM358
10K
1
FANOUT1
R42
510
Q2 MOSFET N 2N7002
C6 10u
FANOUT2
R47
510
R48 470K 2
3
1
R50 6.49K
+3.3V DCOUT1 R51 0 D1 1N4148 PWMOUT1 R53 0 JP1 3 2 1 HEADER 3 FANIN1 R52 4.7K
R63, R66 FOR DC FAN R65, R68 FOR PWM FAN
DCOUT2 R54 0 D2 1N4148
+3.3V
R55 4.7K
PWMOUT2
R56
0
JP2 3 2 1 HEADER 3 Title Size Date: FANIN2
- 89 -
+ +
DCOUT1
+12V
Q7 P DGS TO-1 U3A R49 10K DCOUT2
W83792D FAN OUTPUT CIRCUIT Document Number Thursday , Nov ember 10, 2005 Sheet 3 of 4 Rev 0.6
Publication Release Date: April 26, 2006 Revision 0.9
W83792AD/AG/D/G
R57 FANOUT1 100K C8 0.1U R58 FANOUT2 100K C11 0.1U C13 0.1U VCC12 C12 0.1U 1 2 3 4 5 6 C15 0.1U 7 U4 FAN1_IN FAN2_IN VCC12 C1 C2 CHRPMP GND FAN1_DRV FAN1_SEN FAN2_DRV FAN2_SEN FAN3_DRV FAN3_SEN FAN3_IN W83391TS R60 6.49K VCC12 1 C10 470u C9 10n 2 R59 10K DCOUT1 3 VCC12 1
Q5 N DGS TO-252
14 13 12 11 10 9 8
2 C14 10n 3
Q6 N DGS TO-252
R61 10K DCOUT2 R62 6.49K C16 VCC12 1 470u
R63 FANOUT3 100K C18 0.1U 2 C17 10n R64 10K 3
Q7 N DGS TO-252
DCOUT3 R65 6.49K C19 470u
Title
W83792D with W83391TS FAN OUTPUT CIRCUIT Rev 0.6 Sheet 4 of 4
Size Document Number Custom Date: Thursday , Nov ember 17, 2005
- 90 -
W83792AD/AG/D/G
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
- 91 -
Publication Release Date: April 26, 2006 Revision 0.9
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