74LVC2G04GV,165

74LVC2G04 Dual inverter Rev. 9 — 12 December 2016 Product data sheet 1. General description The 74LVC2G04 provides the dual inverting buffer. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits             Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C. 74LVC2G04 Nexperia Dual inverter 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G04GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC2G04GV 40 C to +125 C TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC2G04GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1  1.45  0.5 mm 74LVC2G04GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1  1  0.5 mm 74LVC2G04GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm SOT1115 74LVC2G04GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm SOT1202 74LVC2G04GX 40 C to +125 C X2SON6 plastic thermal extremely thin small outline package; no leads; 6 terminals; body 1  0.8  0.35 mm SOT1255 4. Marking Table 2. Marking Type number Marking code[1] 74LVC2G04GW V4 74LVC2G04GV V04 74LVC2G04GM V4 74LVC2G04GF V4 74LVC2G04GN V4 74LVC2G04GS V4 74LVC2G04GX V4 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram  $ <   $ <    Logic symbol 74LVC2G04 Product data sheet    < $ PQE PQE Fig 1.  Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 9 — 12 December 2016 PQD Fig 3. Logic diagram (one gate) © Nexperia B.V. 2017. All rights reserved 2 of 18 74LVC2G04 Nexperia Dual inverter 6. Pinning information 6.1 Pinning /9&* /9&* $    VCC or VO < 0 V output voltage VO Min VO = 0 V to VCC Tamb = 40 C to +125 C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. mA For X2SON6 and XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate Active mode Power-down mode; VCC = 0 V 74LVC2G04 Product data sheet Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V 0 - VCC V 0 - 5.5 V 40 - +125 C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 9 — 12 December 2016 © Nexperia B.V. 2017. All rights reserved 4 of 18 74LVC2G04 Nexperia Dual inverter 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH 40 C to +85 C Conditions VCC = 1.65 V to 1.95 V VOH HIGH-level output voltage LOW-level output voltage Max Min Max 0.65VCC - - 0.65VCC - V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V - - 0.35VCC - - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V VCC  0.1 - - VCC  0.1 - V 1.2 - - 0.95 - V 0.35VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V VOL Min Unit VCC = 2.3 V to 2.7 V LOW-level input VCC = 1.65 V to 1.95 V voltage VCC = 2.3 V to 2.7 V VIL 40 C to +125 C Typ[1] IO = 8 mA; VCC = 2.3 V 1.9 - - 1.7 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 1.9 - V IO = 24 mA; VCC = 3.0 V 2.3 - - 2.0 - V IO = 32 mA; VCC = 4.5 V 3.8 - - 3.4 - V IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.10 - 0.10 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.30 - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.40 - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V - 0.1 1 - 1 A II input leakage current IOFF power-off VCC = 0 V; VI or VO = 5.5 V leakage current - 0.1 2 - 2 A ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 4 - 4 A ICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC  0.6 V; IO = 0 A - 5 500 - 500 A CI input capacitance VCC = 3.3 V; VI = GND to VCC - 2.5 - - - pF [1] VI = 5.5 V or GND; VCC = 0 V to 5.5 V All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 74LVC2G04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 12 December 2016 © Nexperia B.V. 2017. All rights reserved 5 of 18 74LVC2G04 Nexperia Dual inverter 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9. Symbol Parameter 40 C to +85 C Conditions power dissipation capacitance CPD Unit Min Max Min Max VCC = 1.65 V to 1.95 V 1.0 3.5 8.0 1.0 9.5 ns VCC = 2.3 V to 2.7 V 1.0 2.2 4.4 1.0 5.4 ns VCC = 2.7 V 1.0 2.7 5.2 1.0 7.0 ns VCC = 3.0 V to 3.6 V 0.5 2.7 4.1 0.5 5.5 ns VCC = 4.5 V to 5.5 V 1.0 1.9 3.2 1.0 3.8 ns - 13.5 - - - pF [2] propagation delay nA to nY; see Figure 8 tpd 40 C to +125 C Typ[1] [3] VI = GND to VCC; VCC = 3.3 V [1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 12. AC waveforms 9, 90 Q$LQSXW 90 *1' W 3+/ W 3/+ 92+ 90 Q