74LVC1G10GV,125

74LVC1G10 Single 3-input NAND gate Rev. 5 — 28 November 2016 Product data sheet 1. General description The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 1.65 V to 5.5 V  High noise immunity  Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8-B/JESD36 (2.7 V to 3.6 V).  24 mA output drive (VCC = 3.0 V)  CMOS low power consumption  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C 74LVC1G10 Nexperia Single 3-input NAND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G10GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC1G10GV 40 C to +125 C SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC1G10GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.5 mm SOT886 74LVC1G10GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1  0.5 mm SOT891 74LVC1G10GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm SOT1115 74LVC1G10GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm SOT1202 4. Marking Table 2. Marking Type number Marking code[1] 74LVC1G10GW YM 74LVC1G10GV YM 74LVC1G10GM YM 74LVC1G10GF YM 74LVC1G10GN YM 74LVC1G10GS YM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram $ % &  $   <     DDJ Fig 1. Logic symbol 74LVC1G10 Product data sheet % & DDJ Fig 2. <  IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2016 Fig 3. DDJ Logic diagram © Nexperia B.V. 2017. All rights reserved 2 of 17 74LVC1G10 Nexperia Single 3-input NAND gate 6. Pinning information 6.1 Pinning /9&* /9&* $   & *1'   9&& %   < $   & *1'   9&& %  $   & *1'   9&& %   < < DDJ DDJ 7UDQVSDUHQWWRSYLHZ 7UDQVSDUHQWWRSYLHZ DDJ Fig 4.  /9&* Pin configuration SOT363 and SOT457 Fig 5. Pin configuration SOT886 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3. Pin description Symbol Pin Description A 1 data input GND 2 ground (0 V) B 3 data input Y 4 data output VCC 5 supply voltage C 6 data input 7. Functional description Table 4. Function table[1] Input Output A B C Y H H H L L X X H X L X H X X L H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 74LVC1G10 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2016 © Nexperia B.V. 2017. All rights reserved 3 of 17 74LVC1G10 Nexperia Single 3-input NAND gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VI < 0 V [1] IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Min Max Unit 0.5 +6.5 V 50 - 0.5 +6.5 V mA mA - 50 Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA - 100 mA 100 - mA - 250 mW 65 +150 C VO > VCC or VO < 0 V output voltage VO [1] Conditions VO = 0 V to VCC Tamb = 40 C to +125 C [3] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For SC-88 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Tamb ambient temperature t/V input transition rise and fall rate 74LVC1G10 Product data sheet Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V Active mode 0 - VCC V Power-down mode; VCC = 0 V 0 - 5.5 V 40 - +125 C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2016 © Nexperia B.V. 2017. All rights reserved 4 of 17 74LVC1G10 Nexperia Single 3-input NAND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL 40 C to +85 C Conditions VCC = 1.65 V to 1.95 V 40 C to +125 C Min Typ[1] Max Min Unit Max 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.35VCC V 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V VCC  0.1 - - VCC  0.1 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 0.95 - V IO = 8 mA; VCC = 2.3 V 1.9 - - 1.7 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 1.9 - V IO = 24 mA; VCC = 3.0 V 2.3 - - 2.0 - V IO = 32 mA; VCC = 4.5 V 3.8 - - 3.4 - V IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.10 - 0.10 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.30 - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.40 - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - 0.1 1 - 1 A IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 2 - 2 A ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 4 - 4 A ICC additional supply VI = VCC  0.6 V; IO = 0 A; current VCC = 2.3 V to 5.5 V; per pin - 5 500 - 500 A CI input capacitance - 3 - - - pF [1] VCC = 3.3 V; VI = GND to VCC All typical values are measured at Tamb = 25 C. 74LVC1G10 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 November 2016 © Nexperia B.V. 2017. All rights reserved 5 of 17 74LVC1G10 Nexperia Single 3-input NAND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.5 4.7 18.0 1.5 21.5 ns VCC = 2.3 V to 2.7 V 1.0 3.0 6.5 1.0 7.8 ns VCC = 2.7 V 1.0 3.0 6.0 1.0 7.5 ns VCC = 3.0 V to 3.6 V 1.0 2.6 5.0 1.0 6.2 ns VCC = 4.5 V to 5.5 V 1.0 1.9 3.6 1.0 4.4 ns - 12 - - - pF propagation delay A, B and C to Y; see Figure 7 tpd power dissipation capacitance CPD 40 C to +125 C Unit Typ[1] VI = GND to VCC; VCC = 3.3 V [2] [3] [1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. 12. Waveforms 9, $%& LQSXW *1' 92+ 90 W3/+ W3+/ 90