74LVC2G02DC,125

74LVC2G02 Dual 2-input NOR gate Rev. 13 — 20 April 2018 1 Product data sheet General description The 74LVC2G02 provides a 2-input NOR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2 Features and benefits • • • • • • • • • • • • Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8-B/JESD36 (2.7 V to 3.6 V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V ESD protection: – HBM JESD22-A114F exceeds 2000 V – MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C 74LVC2G02 Nexperia Dual 2-input NOR gate 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G02DP -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G02DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 74LVC2G02GT -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 x 1.95 x 0.5 mm 74LVC2G02GF -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 74LVC2G02GM -40 °C to +125 °C XQFN8 plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2 74LVC2G02GN -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116 74LVC2G02GS -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 4 Marking Table 2. Marking codes [1] Type number Marking code 74LVC2G02DP V02 74LVC2G02DC V02 74LVC2G02GT V02 74LVC2G02GF VB 74LVC2G02GM V02 74LVC2G02GN VB 74LVC2G02GS VB [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 2 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate 5 Functional diagram 1 1A 1Y 1B 2A 2B 001aah780 Y A 001aah781 Figure 1.  Logic symbol 6 B 1 2Y Figure 2.  IEC logic symbol mna105 Figure 3.  Logic diagram (one gate) Pinning information 6.1 Pinning 74LVC2G02 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 74LVC2G02 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aab643 Transparent top view 001aab642 Figure 4.  Pin configuration SOT505-2 and SOT765-1 Figure 5.  Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 74LVC2G02 1Y 1 2B 2A 8 VCC terminal 1 index area 1A 2 6 1B 3 5 2Y GND 4 7 001aae971 Transparent top view Figure 6.  Pin configuration SOT902-2 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 3 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate 6.2 Pin description Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT1116 and SOT1203 SOT902-2 1A, 2A 1, 5 7, 3 data input 1B, 2B 2, 6 6, 2 data input GND 4 4 ground (0 V) 1Y, 2Y 7, 3 1, 5 data output VCC 8 8 supply voltage 7 Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Input Output nA nB nY L L H X H L H X L 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 4 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate 8 Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Max Unit -0.5 +6.5 V [1] -0.5 +6.5 V Active mode [1] -0.5 VCC + 0.5 V Power-down mode; VCC = 0 V [1] -0.5 +6.5 V -50 - mA IIK input clamping current VI < 0 V IOK output clamping current VO < 0 V or VO > VCC - ±50 mA IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 300 mW Tamb = -40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. For XSON8 and XQFN8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9 Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Tamb ambient temperature Δt/ΔV input transition rise and fall rate 74LVC2G02 Product data sheet Min Max Unit 1.65 5.5 V 0 5.5 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 5.5 V -40 +125 °C VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 5 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate 10 Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ [1] Max Unit Tamb = -40 °C to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - VCC - 0.1 - - V IO = -4 mA; VCC = 1.65 V 1.2 1.53 - V IO = -8 mA; VCC = 2.3 V 1.9 2.13 - V IO = -12 mA; VCC = 2.7 V 2.2 2.50 - V IO = -24 mA; VCC = 3.0 V 2.3 2.60 - V IO = -32 mA; VCC = 4.5 V 3.8 4.10 - V IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - 0.08 0.45 V IO = 8 mA; VCC = 2.3 V - 0.14 0.3 V IO = 12 mA; VCC = 2.7 V - 0.19 0.4 V IO = 24 mA; VCC = 3.0 V - 0.37 0.55 V IO = 32 mA; VCC = 4.5 V - 0.43 0.55 V - ±0.1 ±1 μA 0.3 × VCC V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 5.5 V VOL 0.35 × VCC V LOW-level output voltage VI = VIH or VIL II input leakage current IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±2 μA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 4 μA ΔICC additional supply current per pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 μA CI input capacitance - 2.5 - pF 74LVC2G02 Product data sheet VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 6 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate Symbol Parameter Conditions Min Typ [1] Max Unit Tamb = -40 °C to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - VCC - 0.1 - - V IO = -4 mA; VCC = 1.65 V 0.95 - - V IO = -8 mA; VCC = 2.3 V 1.7 - - V IO = -12 mA; VCC = 2.7 V 1.9 - - V IO = -24 mA; VCC = 3.0 V 2.0 - - V IO = -32 mA; VCC = 4.5 V 3.4 - - V IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V - - ±1 μA 0.3 × VCC V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 5.5 V VOL 0.35 × VCC V LOW-level output voltage VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - ±2 μA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 4 μA ΔICC additional supply current per pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 500 μA [1] All typical values are measured at Tamb = 25 °C. 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 7 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate 11 Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 8. Symbol Parameter tpd Conditions -40 °C to +85 °C Unit Min Typ Max Min Max VCC = 1.65 V to 1.95 V 1.2 3.8 8.9 1.2 11.2 ns VCC = 2.3 V to 2.7 V 0.8 2.4 5.4 0.8 6.8 ns VCC = 2.7 V 0.8 3.2 6.0 0.8 7.5 ns VCC = 3.0 V to 3.6 V 0.6 2.4 4.9 0.6 6.2 ns 0.6 1.8 4.3 0.6 5.5 ns - 14 - - - pF propagation delay nA, nB to nY; see Figure 7 power dissipation capacitance -40 °C to +125 °C [2] VCC = 4.5 V to 5.5 V CPD [1] [3] per gate; VI = GND to VCC [1] Typical values are measured at nominal VCC and at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of outputs. 11.1 Waveforms and test circuit VI VM nA, nB input GND t PHL t PLH VOH nY output VM 001aae972 VOL Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Figure 7.  Input (nA, nB) to output (nY) propagation delays 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 8 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 x VCC 0.5 x VCC 2.3 V to 2.7 V 0.5 x VCC 0.5 x VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 x VCC 0.5 x VCC VI negative pulse tW 90 % VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 10. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Figure 8.  Test circuit for measuring switching times Table 10. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open 74LVC2G02 Product data sheet VEXT Load All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 9 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate 12 Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 pin 1 index (A3) A1 θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Figure 9.  Package outline SOT505-2 (TSSOP8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 10 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D SOT765-1 E A X c y HE v A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 detail X 4 e L w bp 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A max. max nom min 1 A1 A2 0.15 0.85 0.00 0.60 A3 0.12 D(1) E(2) 0.27 0.23 2.1 2.4 0.17 0.08 1.9 2.2 bp c e HE 0.5 3.2 3.0 L 0.4 Lp Q 0.40 0.21 0.15 0.19 v 0.2 w 0.08 y 0.1 Z(1) θ 0.4 8° 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Outline version SOT765-1 References IEC JEDEC JEITA sot765-1_po European projection Issue date 07-06-02 16-05-31 MO-187 Figure 10.  Package outline SOT765-1 (VSSOP8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 11 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Figure 11.  Package outline SOT833-1 (XSON8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 12 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.04 0.20 1.40 1.05 0.35 0.40 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 sot1089_po References IEC JEDEC JEITA European projection Issue date 10-04-09 10-04-12 MO-252 Figure 12.  Package outline SOT1089 (XSON8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 13 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2 X D B A terminal 1 index area E A A1 detail X e v w b 4 3 C C A B C y1 C y 5 e1 terminal 1 index area 2 6 L 1 7 k 8 L2 L k metal area not for soldering L3 L1 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A 0.5 A1 b D E e e1 0.05 0.25 1.65 1.65 0.20 1.60 1.60 0.55 0.00 0.15 1.55 1.55 0.5 k 0.2 L L1 L2 L3 0.35 0.15 0.25 0.35 0.30 0.10 0.20 0.30 0.25 0.05 0.15 0.25 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT902-2 --- MO-255 --- sot902-2_po European projection Issue date 16-07-14 16-11-08 Figure 13.  Package outline SOT902-2 (XQFN8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 14 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 e1 6 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1116_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1116 Figure 14.  Package outline SOT1116 (XSON8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 15 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 1 2 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1203_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1203 Figure 15.  Package outline SOT1203 (XSON8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 16 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate 13 Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14 Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G02 v.13 20180420 Product data sheet - 74LVC2G02 v.12 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. • Type number 74LVC2G02GD (SOT996-2) removed. 74LVC2G02 v.12 20161212 Modifications: • Table 7: The maximum limits for leakage current and supply current have changed. 74LVC2G02 v.11 20130408 Modifications: • For type number 74LVC2G02GD XSON8U has changed to XSON8. 74LVC2G02 v.10 20120622 Modifications: • For type number 74LVC2G02GM the SOT code has changed to SOT902-2. 74LVC2G02 v.9 20111130 Modifications: • Legal pages updated. 74LVC2G02 v.8 20101020 74LVC2G02 v.7 Product data sheet Product data sheet Product data sheet - - 74LVC2G02 v.11 74LVC2G02 v.10 74LVC2G02 v.9 - 74LVC2G02 v.8 Product data sheet - 74LVC2G02 v.7 20080606 Product data sheet - 74LVC2G02 v.6 74LVC2G02 v.6 20080222 Product data sheet - 74LVC2G02 v.5 74LVC2G02 v.5 20070904 Product data sheet - 74LVC2G02 v.4 74LVC2G02 v.4 20060515 Product data sheet - 74LVC2G02 v.3 74LVC2G02 v.3 20050201 Product specification - 74LVC2G02 v.2 74LVC2G02 v.2 20040915 Product specification - 74LVC2G02 v.1 74LVC2G02 v.1 20031015 Product specification - - 74LVC2G02 Product data sheet Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 17 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate 15 Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74LVC2G02 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 18 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74LVC2G02 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 13 — 20 April 2018 © Nexperia B.V. 2018. All rights reserved. 19 / 20 74LVC2G02 Nexperia Dual 2-input NOR gate Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 11.1 12 13 14 15 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 2 Marking .................................................................2 Functional diagram ............................................. 3 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 4 Functional description ........................................4 Limiting values .................................................... 5 Recommended operating conditions ................ 5 Static characteristics .......................................... 6 Dynamic characteristics .....................................8 Waveforms and test circuit ................................ 8 Package outline .................................................10 Abbreviations .................................................... 17 Revision history ................................................ 17 Legal information .............................................. 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2018. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 20 April 2018 Document identifier: 74LVC2G02 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: 74LVC2G02GD,125 74LVC2G02GN,115 74LVC2G02GS,115 74LVC2G02DC,125 74LVC2G02DP,125 74LVC2G02GM,125 74LVC2G02GT,115 74LVC2G02GF,115