XD74LS76

XD74LS76 DIP16 Pin Arrangement 1CK 1 1PR 2 1CLR 3 1J VCC 2CK 16 1K 15 1Q 14 1Q 4 13 GND 5 12 2K 11 2Q 10 2Q 9 2J 6 2PR 7 2CLR 8 J CK K PR CLR Q Q K CK J CLR PR Q Q (Top view) Function Table Inputs Outputs Preset L Clear H Clock X J X K X Q H Q L H L L L X X X X X X L H* H H* H H H H ↓ ↓ L H L L Q0 H Q0 L H H H H ↓ ↓ L H H H L H Toggle H H H X X Q0 Q0 H; high level, L; low level, X; irrelevant, ↓; transition from high to low level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established. Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓. * This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level. Block Diagram (1/2) Q Q Clear Preset K J Clock 1 XD74LS76 DIP16 Absolute Maximum Ratings Item Supply voltage Symbol VCC Ratings 7 Unit V VIN PT 7 400 V mW Tstg –65 to +150 °C Input voltage Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Symbol VCC Min 4.75 Typ 5.00 Max 5.25 Unit V IOH IOL — — — — –400 8 µA mA Topr fclock –20 0 25 — 75 30 °C MHz Output current Operating temperature Clock frequency Pulse width Clock High Clear Preset Low tw tw 20 25 — — — — ns Setup time “H” Data “L” Data tsu tsu 20↓ 20↓ — — — — ns th 0↓ — — ns Hold time Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH min. 2.0 typ.* — max. — Unit V VIL — — 0.8 V VOH 2.7 — — V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA VOL — — — — 0.5 0.4 V IOL = 8 mA IOL = 4 mA — — — — 20 60 — — — — 60 80 µA VCC = 5.25 V, VI = 2.7 V — — — — –0.4 –0.8 — — — — –0.8 –0.8 mA VCC = 5.25 V, VI = 0.4 V — — — — 0.1 0.3 — — — — 0.3 0.4 mA VCC = 5.25 V, VI = 7 V IOS –20 — –100 mA VCC = 5.25 V ICC — 4 6 mA VCC = 5.25 V Output voltage J, K Clear Preset Clock Input current J, K Clear Preset Clock J, K Clear Preset Clock Short-circuit output current Supply current*** IIH IIL** II Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** IIL should not be measured when preset and clear inputs are low at same time. *** With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded. 2 XD74LS76 DIP16 Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Symbol Maximum clock frequency fmax tPLH Propagation delay time Inputs Outputs Clear Preset Clock tPHL Q, Q min. typ. max. Unit 30 — 45 15 20 MHz ns — 15 20 ns Condition CL = 15 pF, RL = 2 kΩ Timing Definition tw 3V 1.3 V 1.3 V 1.3 V Clock tsu th tsu 0V th 3V 1.3 V 1.3 V 1.3 V J, K 0V "H" Data "L" Data Testing Method Test Circuit 1. ƒmax, tPLH, tPHL, (Clock→Q, Q) VCC Output Q Input 4.5V RL J P.G. Zout=50Ω PR Load circuit 1 Q CL CK Output Q K CLR Notes: Q 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). 3 Same as Load Circuit 1. XD74LS76 DIP16 2. tPHL, tPLH (Clear, Preset→ Q, Q) VCC Input Output Q P.G. Zout=50Ω RL PR Load circuit 1 Q J CL 4.5V CK Input Output Q K Q CLR Same as Load Circuit 1. P.G. Zout=50Ω Notes: 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). Waveforms 1 tTLH tTHL tw(L) 90% 90% 1.3 V 1.3 V Clock 10% 3V 1.3 V 1.3 V 10% 0V tw(H) tPLH tPHL VOH 1.3 V Q tPHL 1.3 V VOL tPLH Q VOH 1.3 V 1.3 V VOL Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax., tTLH = tTHL ≤ 2.5 ns 4 XD74LS76 DIP16 Waveforms 2 tTHL Clear tTLH 90% 1.3V 10% 3V 90% 1.3V 10% tw (CLR) 0V tTHL tTLH 90% 1.3V 10% Preset 90% 1.3V 10% tw (PR) 3V 0V tPHL tPLH 1.3V Q VOH 1.3V tPLH VOL VOH Q Note: 1.3V 1.3V tPHL Crear and preset input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, DIP 5 VOL