SIT9387AE-2B1-33E300.000000G

SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Features ◼ ◼ ◼ ◼ ◼ ◼ Applications AEC-Q100 Grade 2 temperature range (-40°C to 105°C). Grade 3 and Grade 4 also available Any frequency between 220.000001 MHz and 725 MHz, accurate to 6 decimal places. For HCSL output signaling, maximum frequency is 500 MHz – contact SiTime for higher frequency options. For frequency between 1 and 220 MHz, see SiT9386 LVPECL, LVDS and HCSL output signaling Frequency stability as low as ±10 ppm – contact SiTime 0.23 ps RMS (typ) phase jitter (random, 12 kHz to 20 MHz) Industry-standard packages: 3.2 x 2.5, 7.0 x 5.0 mm. Contact SiTime for 5.0 x 3.2 mm package ◼ ◼ 100 Gbps Ethernet, SONET, SATA, SAS, Fibre Channel Telecom, networking, instrumentation, storage, servers Electrical Characteristics Table 1. Electrical Characteristics – Common to LVPECL, LVDS and HCSL All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage wi th standard output termination show in the termination diagrams. Typical values are at 25°C and nominal supply voltage. Parameter Symbol Min. Typ. Max. Unit Condition Frequency Range Output Frequency Range f 220.000001 – 725 MHz Accurate to 6 decimal places Frequency Stability Frequency Stability First Year Aging F_aging1 -10 – +10 ppm Inclusive of initial tolerance, operating temperature, rated power supply voltage and load variations. Contact SiTime for ±10 ppm -20 – +20 ppm -25 – +25 ppm Inclusive of initial tolerance, operating temperature, rated power supply voltage and load variations -50 – +50 ppm – ±1 – ppm At 25°C Temperature Range Operating Temperature Range T_use -20 – +70 °C AEC-Q100 Grade 4 -40 – +85 °C AEC-Q100 Grade 3 -40 – +105 °C AEC-Q100 Grade 2 Supply Voltage Supply Voltage Vdd 2.97 3.30 3.63 V 2.70 3.00 3.30 V 2.52 2.80 3.08 V 2.25 2.50 2.75 V Input Characteristics Input Voltage High VIH 70% – – Vdd Pin 1, OE Input Voltage Low VIL – – 30% Vdd Pin 1, OE Input Pull-up Impedance Z_in – 100 - kΩ Pin 1, OE logic high or logic low Output Characteristics Duty Cycle DC 45 – 55 % Startup and OE Timing Startup Time OE Enable/Disable Time Rev 1.01 T_start – – T_oe – – 3.0 ms Measured from the time Vdd reaches its rated minimum value 3.8 µs F = 322.265625 MHz. Measured from the time OE pin reaches rated VIH and VIL to the time clock pins reach 90% of swing and high-Z. See Figure 6 and Figure 7 9 March 2021 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Table 2. Electrical Characteristics – LVPECL Specific Parameter Symbol Min. Typ. Max. Unit Condition Current Consumption Idd – – 94 mA Excluding Load Termination Current, Vdd = 3.3 V or 2.5 V OE Disable Supply Current I_OE – – 63 mA OE = Low Output Disable Leakage Current I_leak – 0.15 – A OE = Low I_driver – – 33 mA Maximum average current drawn from OUT+ or OUT- Current Consumption Maximum Output Current Output Characteristics Output High Voltage VOH Vdd-1.15 – Vdd-0.7 V See Figure 2 Output Low Voltage VOL Vdd-2.0 – Vdd-1.5 V See Figure 2 V_Swing 1.2 1.6 2.0 V See Figure 3 Tr, Tf – 225 330 ps 20% to 80%, see Figure 3 Output Differential Voltage Swing Rise/Fall Time Jitter – 7.0 x 5.0 mm package RMS Period Jitter[1] T_jitt – 1.0 1.6 ps f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V RMS Phase Jitter (random) T_phj – 0.220 0.270 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -40 to 85ºC – 0.220 0.300 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature range -40 to 105ºC – 0.1 – ps f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask integration bandwidth = 1.875 MHz to 20 MHz, includes spurs, all Vdd levels Jitter – 3.2 x 2.5 mm package RMS Period Jitter T_jitt – 1.0 1.6 ps f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V T_phj – 0.225 0.282 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -40 to 85ºC – 0.225 0.315 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature range -40 to 105ºC – 0.1 – ps f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask integration bandwidth = 1.875 MHz to 20 MHz, Includes spurs, all Vdd levels [1] RMS Phase Jitter (random) Notes: 1. Measured according to JESD65B. Rev 1.01 Page 2 of 12 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Table 3. Electrical Characteristics – LVDS Specific Parameter Symbol Min. Typ. Max. Unit Condition Current Consumption Current Consumption Idd – – 85 mA Excluding Load Termination Current, Vdd = 3.3 V or 2.5 V OE Disable Supply Current I_OE – – 63 mA OE = Low Output Disable Leakage Current I_leak – 0.15 – A OE = Low Output Characteristics VOD 250 – 530 mV See Figure 4 ΔVOD – – 50 mV See Figure 4 VOS 1.125 – 1.375 V See Figure 4 VOS Magnitude Change ΔVOS – – 50 mV See Figure 4 Rise/Fall Time Tr, Tf – 370 505 ps Measured with 2 pF capacitive loading to GND, 20% to 80%, see Figure 5 RMS Period Jitter[2] T_jitt – 0.92 1.6 ps f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V RMS Phase Jitter (random) T_phj – 0.215 0.265 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -40 to 85ºC – 0.215 0.280 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature range -40 to 105ºC – 0.1 – ps f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask integration bandwidth = 1.875 MHz to 20 MHz, Includes spurs, all Vdd levels Differential Output Voltage VOD Magnitude Change Offset Voltage Jitter – 7.0 x 5.0 mm package Jitter – 3.2 x 2.5 mm package RMS Period Jitter[2] T_jitt – 0.92 1.6 ps f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V RMS Phase Jitter (random) T_phj – 0.235 0.282 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -40 to 85ºC. – 0.235 0.310 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature range -40 to 105ºC – 0.1 – ps f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask integration bandwidth = 1.875 MHz to 20 MHz, Includes spurs, all Vdd levels Notes: 2. Measured according to JESD65B. Rev 1.01 Page 2 of 12 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Table 4. Electrical Characteristics – HCSL Specific Parameter Symbol Min. Typ. Max. Unit Condition Current Consumption Current Consumption Idd – – 97 mA Excluding Load Termination Current, Vdd = 3.3 V or 2.5 V OE Disable Supply Current I_OE – – 63 mA OE = Low Output Disable Leakage Current I_leak – 0.15 – A OE = Low I_driver – – 35 mA Maximum average current drawn from OUT+ or OUT- Maximum Output Current Output Characteristics Output High Voltage VOH 0.60 – 0.90 V See Figure 2 Output Low Voltage VOL -0.05 – 0.08 V See Figure 2 V_Swing 1.2 1.4 1.9 V See Figure 3 Rise/Fall Time Tr, Tf – 360 505 ps Measured with 2 pF capacitive loading to GND, 20% to 80%, see Figure 3 RMS Period Jitter[3] T_jitt – 1.0 1.6 ps f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V RMS Phase Jitter (random) T_phj – 0.215 0.265 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -40-85ºC – 0.215 0.282 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature range -40 to 105ºC – 0.1 – ps f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask integration bandwidth = 1.875 MHz to 20 MHz, Includes spurs, all Vdd levels Output Differential Voltage Swing Jitter – 7.0 x 5.0 mm package Jitter – 3.2 x 2.5 mm package RMS Period Jitter[3] T_jitt – 1.0 1.6 T_phj – 0.235 0.282 ps ps f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V RMS Phase Jitter (random) – 0.235 0.305 ps f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature range -40 to 105ºC – 0.1 – ps f = 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask integration bandwidth = 1.875 MHz to 20 MHz, Includes spurs, all Vdd levels f = 322.265625 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -40 to 85ºC. Notes: 3. Measured according to JESD65. Rev 1.01 Page 3 of 12 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Table 5. Pin Description Pin 1 Map Top View Functionality OE/NC [4] Output Enable (OE) H : specified frequency output L: output is high impedance Non Connect (NC) H or L or Open: No effect on output frequency or other device functions OE/NC 1 6 VDD NC 2 5 OUT- GND 3 4 OUT+ No Connect; Leave it floating or connect to GND for better heat dissipation 2 NC NA 3 GND Power Vdd Power Supply Ground 4 OUT+ Output Oscillator output 5 OUT- Output Complementary oscillator output 6 Vdd Power Power supply voltage[5] Figure 1. Pin Assignments Notes: 4. In OE mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. 5. A capacitor of value 0.1 µF or higher between Vdd and GND is required. An additional 10 µF capacitor between Vdd and GND is required for the best phase jitter performance. Table 6. Absolute Maximum Ratings Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Parameter Min. Max. Unit -0.5 4.0 V Vdd + 0.3V V 150 ºC Maximum Junction Temperature 130 ºC Soldering Temperature (follow standard Pb-free soldering guidelines) 260 ºC Vdd VIH VIL -0.3 Storage Temperature -65 V Table 7. Thermal Considerations[6] Package JA, 4 Layer Board (°C/W) JC, Bottom (°C/W) 3225, 6-pin 80 30 7050, 6-pin 52 19 Notes: 6. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table. Table 8. Maximum Operating Junction Temperature[7] Max Operating Temperature (ambient) Maximum Operating Junction Temperature 70°C 95°C 85°C 110°C 105°C 130°C Notes: 7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature. Table 9. Environmental Compliance Test Conditions Value Unit Mechanical Shock Resistance Parameter MIL-STD-883F, Method 2002 10,000 g Mechanical Vibration Resistance MIL-STD-883F, Method 2007 70 g Soldering Temperature (follow standard Pb free soldering guidelines) MIL-STD-883F, Method 2003 260 °C Moisture Sensitivity Level MSL1 @ 260°C Electrostatic Discharge (HBM) HBM, JESD22-A114 2,000 V Charge-Device Model ESD Protection JESD220C101 750 V Latch-up Tolerance Rev 1.01 JESD78 Compliant Page 4 of 12 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Waveform Diagrams OUT- VOH OUT+ VOL GND Figure 2. LVPECL/HCSL Voltage Levels per Differential Pin (OUT+/OUT-) V 80% 80% V_ Swing 0V t 20% 20% Tr Tf Figure 3. LVPECL/HCSL Voltage Levels across Differential Pair Rev 1.01 Page 5 of 12 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Waveform Diagrams (continued) OUT- VOD OUT+ VOS GND Figure 4. LVDS Voltage Levels per Differential Pin (OUT+/OUT-) V 80% 80% 0V t 20% 20% Tr Tf Figure 5. LVDS Differential Waveform Timing Diagrams Vdd OE Voltage Vdd VIH VIL T_oe_hw OE Voltage T_oe_hw OUT- OUT- 90% HZ HZ OUT+ OUT+ GND GND Figure 6. Hardware OE Enable Timing Rev 1.01 Figure 7. Hardware OE Disable Timing Page 6 of 12 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Termination Diagrams LVPECL OUT+ Shunt Bias Termination network 0.1μF Zo = 50Ω D+ OUT- Zo = 50Ω D- LVPECL 0.1μF RB RB VDD 50 Ω 50 Ω RB 3.3 V 100 Ω VT 2.5 V 48.7 Ω Figure 8. LVPECL with AC-coupled termination VDD Thevenin-equivalent Termination network R1 LVPECL R1 OUT+ Zo = 50Ω D+ OUT- Zo = 50Ω D- VDD R1 R2 R2 3.3 V 127 Ω 82.5 Ω 2.5 V 250 Ω 62.5 Ω R2 Figure 9. LVPECL DC-coupled load termination with Thevenin equivalent network Y-Bias Termination network LVPECL OUT+ Zo = 50Ω D+ OUT- Zo = 50Ω D- R1 VDD R1 R2 R3 3.3 V 50 Ω 50 Ω 50 Ω 2.5 V 50 Ω 50 Ω 18 Ω C1 0.1μF R2 R3 Figure 10. LVPECL with Y-Bias termination OUT+ Shunt Bias Termination network Zo = 50Ω D+ OUT- Zo = 50Ω D- LVPECL 50 Ω 50 Ω VT=VDD-2V Figure 11. LVPECL with DC-coupled parallel shunt load termination Rev 1.01 Page 7 of 12 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Termination Diagrams (continued) LVDS LVDS Zo = 50Ω OUT+ OUT+ 100 Ω Zo = 50Ω OUT- OUT- Figure 12. LVDS single DC termination at the load LVDS 0.1μF Zo = 50Ω OUT+ OUT+ 100 Ω 100 Ω 0.1μF Zo = 50Ω OUT- OUT- Figure 13. LVDS double AC termination with capacitor close to the load LVDS Zo = 50Ω OUT+ OUT+ 100 Ω 100 Ω Zo = 50Ω OUT- OUT- Figure 14. LVDS double DC termination HCSL R1 OUT+ OUT- Zo = 50Ω D+ Zo = 50Ω D- R2 50Ω 50Ω R1 = R2 = 33 Ω Figure 15. HCSL interface termination Rev 1.01 Page 8 of 12 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Dimensions and Patterns Package Size – Dimensions (Unit: mm)[8] Recommended Land Pattern (Unit: mm)[9] 3.2 x 2.5 x 0.85 mm 3.2 x 2.5 x 0.85 mm 1.00 1.6 2.25 0.65 7.0 x 5.0 x 0.85 mm[10] 1.05 7.0 x 5.0 x 0.85 mm[10] Notes: 8. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device. 9. A capacitor of value 0.1 µF or higher between Vdd and GND is required. An additional 10 µF capacitor between Vdd and GND is required for the best phase jitter performance 10. The center pad has no electrical function. Soldering down the center pad to the GND is recommended for best thermal dissipation, but is optional. Rev 1.01 Page 9 of 12 www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Ordering Information SiT9387AC - 1B1-33E 322.265625T Packaging Part Family “T”, “Y”, “D” or “E” Refer to table below for packing method [13] Leave Blank for Bulk “SiT9387” Revision Letter “A” is the revision of Silicon Frequency 220.000001 to 725 MHZ for LVDS and LVPECL output drivers Temperature Range 220.000001 to 500 MHz for HCSL driver “C”: Extended Commercial, -20 to 70°C “I”: Industrial, -40 to 85°C “E”: Extended Industrial, -40 to 105°C [14] Feature Pin “N”: No Connect “E”: Output Enable Signalling Type “1”: LVPECL “2”: LVDS “4”: HCSL Voltage Supply Package Size “25”: 2.5 V ±10% “28”: 2.8 V ±10% “30”: 3.0 V ±10% “33”: 3.3 V ±10% [11] “B”: 3.2 x 2.5 mm “E”: 7.0 x 5.0 mm with center pad Frequency Stability “F”: “1”: “2”: “3”: ±10 ppm ±20 ppm ±25 ppm ±50 ppm [12] Notes: 11. Contact SiTime for 5.0 x 3.2 mm package. 12. Contact SiTime for ±10 ppm option. 13. Bulk is available for sampling only. 14. Contact SiTime for higher frequency HCSL options. Table 10. Ordering Codes for Supported Tape & Reel Packing Method Device Size (mm x mm) 8 mm T&R (3ku) 8 mm T&R (1ku) 12 mm T&R (3ku) 12 mm T&R (1ku) 7.0 x 5.0 — — — — 3.2 x 2.5 D E Rev 1.01 Page 10 of 12 16 mm T&R (3ku) 16 mm T&R (1ku) T Y — — www.sitime.com SiT9387 AEC-Q100, 220 to 725 MHz Ultra-low Jitter Differential Oscillator Table 11. Additional Information Document Description Download Link ECCN #: EAR99 Five character designation used on the commerce Control List (CCL) to identify dual use items for export control purposes. — Part number Generator Tool used to create the part number based on desired features. https://www.sitime.com/part-number-generator Manufacturing Notes Tape & Reel dimension, reflow profile and other manufacturing related info https://www.sitime.com/sites/default/files/gated/Manufacturing-Notes-for-SiTimeProducts.pdf Qualification Reports RoHS report, reliability reports, composition reports http://www.sitime.com/support/quality-and-reliability Performance Reports Additional performance data such as phase noise, current consumption and jitter for selected frequencies http://www.sitime.com/support/performance-measurement-report Termination Techniques Termination design recommendations http://www.sitime.com/support/application-notes Layout Techniques Layout recommendations http://www.sitime.com/support/application-notes Table 12 .Revision History Revision Release Date Change Summary 0.1 11-Mar-2017 Initial draft 0.87 6-Nov-2017 Updated package drawings Corrected tape/reel ordering information Updated Electrical Characteristics based on characterization Added additional information table Corrected formatting issues added temperature range to 105ºC Changed ±10 ppm to “contact SiTime” Updated termination diagrams Lower mechanical shock from 20,000 to 10,000 g 0.90 24-Nov-2017 Ordering information updates and page layout changes 1.0 15-Mar-2019 Updated Electrical Characteristics tables Updated waveform diagrams Added OE enable/disable timing diagrams Updated package dimensions Added an AEC-Q100 Grade 4 temperature option Updated the ordering information 1.01 9-Mar-2021 Updated L1 and Dimple Width package dimensions for 3.2 x 2.5 mm package Updated hyperlinks and changed rev table date format SiTime Corporation, 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA | Phone: +1-408-328-4400 | Fax: +1-408-328-4439 © SiTime Corporation 2017-2021. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress. Disclaimer: SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, either in fact or by operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any SiTime product and any product documentation. Products sold by SiTime are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications where human life may be involved or at stake. All sales are made conditioned upon compliance with the critical uses policy set forth below. CRITICAL USE EXCLUSION POLICY BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE. SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited. Rev 1.01 Page 11 of 12 www.sitime.com