RS768M32LZ4D4ANQ-75BT

200b: x32 LPDDR4 SDRAM Features LPDDR4 SDRAM RS384M32LZ4D2ANP, RS768M32LZ4D4ANQ Features Options Marking • VDD1/VDD2: 1.8V/1.1V • Array configuration – 384 Meg x 32 (2 channels x16 I/O) – 768 Meg x 32 (4 channels x16 I/O) • Device configuration – 384M16 x 2 die in package – 384M16 x 4 die in package • FBGA “green” package – 200-ball WFBGA (10mm x 14.5mm x 0.8mm, Ø0.28 SMD ) – 200-ball VFBGA (10mm x 14.5mm x 0.95mm, Ø0.28 SMD ) – 200-ball WFBGA (10mm x 14.5mm x 0.8mm, Ø0.35 SMD) – 200-ball VFBGA (10mm x 14.5mm x 0.95mm, Ø0.35 SMD) – Speed grade, cycle time – 755ps @ RL = 24/28 – 625ps @ RL = 28/32 – 535ps @ RL = 32/36 • Ultra-low-voltage core and I/O power supplies – VDD1 = 1.70–1.95V; 1.8V nominal – VDD2/VDDQ = 1.06–1.17V; 1.1V nominal • Frequency range – 1866–10 MHz (data rate range: 3733–20 Mb/s/ pin) • 16n prefetch DDR architecture • 1-channel partitioned architecture for low RD/WR energy and low average latency • 8 internal banks per channel for concurrent operation • Single-data-rate CMD/ADR entry • Bidirectional/differential data strobe per byte lane • Programmable READ and WRITE latencies (RL/WL) • Programmable and on-the-fly burst lengths (BL = 16, 32) • Directed per-bank refresh for concurrent bank operation and ease of command scheduling • Up to 7.5 GB/s per die • On-chip temperature sensor to control self refresh rate • Partial-array self refresh (PASR) • Selectable output drive strength (DS) • Clock-stop capability • RoHS-compliant, “green” packaging • Programmable V SS (ODT) termination A 384M32 768M32 D2 D4 NP NQ DS1 DT1 -75 -62 -53 • Operating temperature range – –25°C to +85°C • Revision Table 1: Key Timing Parameters WRITE Latency READ Latency Speed Grade Clock Rate (MHz) Data Rate (Mb/s/pin) Set A Set B -75 1333 2667 12 22 24 28 -62 1600 3200 14 26 28 32 -53 1866 3733 16 30 32 36 1 (DBI Disabled) (DBI Enabled) 200b: x32 LPDDR4 SDRAM Features SDRAM Addressing The table below shows the addressing for the 6Gb die density. All bank, row, and column addresses are shown perdie. Table 2: Device Addressing Configuration 384M32 (12Gb) 768M32 (24Gb) 2 4 Device density (per die) 6Gb 6Gb Device density (per channel) 6Gb 6Gb 48Mb x 16 DQ x 8 banks x 2 channels 96Mb x 16 DQ x 8 banks x 2 channels Number of channels (per die) 1 1 Number of ranks per channel 1 2 Number of banks (per channel) 8 8 256 256 49,152 49,152 Die per package Configuration Array prefetch (bits) (per channel) Number of rows (per bank) Number of columns (fetch boundaries) 64 64 2048 2048 Channel density (bits per channel) 6,442,450,944 6,442,450,944 Total density (bits per die) 6,442,450,944 6,442,450,944 Page size (bytes) Bank address x16 BA[2:0] BA[2:0] Row addresses R[15:0] R[15:0] Column addresses C[9:0] C[9:0] 64-bit 64-bit Burst starting address boundary Notes: 1. The lower two column addresses (C0–C1) are assumed to be zero and are not transmitted on the CA bus. 2. Row and column address values on the CA bus that are not used for a particular density are "Don't Care." 3. For non-binary memory densities, only a quarter of the row address space is invalid. When the MSB address bit is HIGH, then the MSB - 1 address bit must be LOW. 2 200b: x32 LPDDR4 SDRAM Features Part Number Ordering Information Figure 1: Part Number Chart 3 200b: x32 LPDDR4 SDRAM Features Contents General Description ....................................................................................................................................... 16 General Notes ............................................................................................................................................ 16 Package Block Diagrams ................................................................................................................................. 17 Ball Assignments and Descriptions ................................................................................................................. 19 Package Dimensions ....................................................................................................................................... 22 MR0, MR[6:4], MR8, MR13 Readout ................................................................................................................. 26 IDD Parameters ............................................................................................................................................... 27 Functional Description ................................................................................................................................... 31 Monolithic Device Addressing ......................................................................................................................... 32 Simplified Bus Interface State Diagram ............................................................................................................ 36 Power-Up and Initialization ............................................................................................................................ 37 Voltage Ramp ............................................................................................................................................. 38 Reset Initialization with Stable Power .......................................................................................................... 40 Power-Off Sequence ....................................................................................................................................... 41 Controlled Power-Off .................................................................................................................................. 41 Uncontrolled Power-Off .............................................................................................................................. 41 Mode Registers ............................................................................................................................................... 42 Mode Register Assignments and Definitions ................................................................................................ 42 Commands and Timing .................................................................................................................................. 67 Truth Tables ................................................................................................................................................... 67 ACTIVATE Command ..................................................................................................................................... 70 Read and Write Access Modes ......................................................................................................................... 71 Preamble and Postamble ................................................................................................................................ 72 Burst READ Operation .................................................................................................................................... 75 Read Timing ............................................................................................................................................... 77 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ..................................................................................... 77 tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) .................................................... 78 tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) ........................................................ 79 Burst WRITE Operation .................................................................................................................................. 81 Write Timing .............................................................................................................................................. 84 tWPRE Calculation for ATE (Automatic Test Equipment) .............................................................................. 85 tWPST Calculation for ATE (Automatic Test Equipment) ............................................................................... 85 MASK WRITE Operation ................................................................................................................................. 86 Mask Write Timing Constraints for BL16 ...................................................................................................... 88 Data Mask and Data Bus Inversion (DBI [DC]) Function ................................................................................... 90 Preamble and Postamble Behavior .................................................................................................................. 94 Preamble, Postamble Behavior in READ-to-READ Operations ...................................................................... 94 READ-to-READ Operations – Seamless ........................................................................................................ 94 READ-to-READ Operations – Consecutive ................................................................................................... 95 WRITE-to-WRITE Operations – Seamless ................................................................................................... 102 WRITE-to-WRITE Operations – Consecutive ............................................................................................... 105 PRECHARGE Operation ................................................................................................................................. 109 Burst READ Operation Followed by Precharge ............................................................................................ 109 Burst WRITE Followed by Precharge ........................................................................................................... 110 Auto Precharge .............................................................................................................................................. 111 Burst READ With Auto Precharge ............................................................................................................... 111 Burst WRITE With Auto Precharge .............................................................................................................. 112 RAS Lock Function .................................................................................................................................... 116 Delay Time From WRITE-to-READ with Auto Precharge .............................................................................. 117 REFRESH Command ..................................................................................................................................... 118 4 200b: x32 LPDDR4 SDRAM Features Refresh Requirement ..................................................................................................................................... 123 SELF REFRESH Operation .............................................................................................................................. 124 Self Refresh Entry and Exit ......................................................................................................................... 124 Power-Down Entry and Exit During Self Refresh ......................................................................................... 125 Command Input Timing After Power-Down Exit ......................................................................................... 126 Self Refresh Abort ...................................................................................................................................... 127 MRR, MRW, MPC Commands During tXSR, tRFC ........................................................................................ 127 Power-Down Mode ........................................................................................................................................ 130 Power-Down Entry and Exit ....................................................................................................................... 130 Input Clock Stop and Frequency Change ........................................................................................................ 140 Clock Frequency Change – CKE LOW ......................................................................................................... 140 Clock Stop – CKE LOW ............................................................................................................................... 140 Clock Frequency Change – CKE HIGH ........................................................................................................ 140 Clock Stop – CKE HIGH ............................................................................................................................. 141 MODE REGISTER READ Operation ................................................................................................................ 142 MRR After a READ and WRITE Command .................................................................................................. 143 MRR After Power-Down Exit ...................................................................................................................... 145 MODE REGISTER WRITE ............................................................................................................................... 146 Mode Register Write States ......................................................................................................................... 147 VREF Current Generator (VRCG) ..................................................................................................................... 148 VREF Training ................................................................................................................................................. 150 VREF(CA) Training ........................................................................................................................................ 150 VREF(DQ) Training ....................................................................................................................................... 155 Command Bus Training ................................................................................................................................. 160 Command Bus Training Mode .................................................................................................................... 160 Training Sequence for Single-Rank Systems ................................................................................................ 161 Training Sequence for Multiple-Rank Systems ............................................................................................ 162 Relation Between CA Input Pin and DQ Output Pin ..................................................................................... 163 Write Leveling ............................................................................................................................................... 167 Mode Register Write-WR Leveling Mode ..................................................................................................... 167 Write Leveling Procedure ........................................................................................................................... 167 Input Clock Frequency Stop and Change .................................................................................................... 168 MULTIPURPOSE Operation ........................................................................................................................... 171 Read DQ Calibration Training ........................................................................................................................ 176 Read DQ Calibration Training Procedure .................................................................................................... 176 Read DQ Calibration Training Example ...................................................................................................... 178 MPC[READ DQ CALIBRATION] After Power-Down Exit ............................................................................... 179 Write Training ............................................................................................................................................... 179 Internal Interval Timer .............................................................................................................................. 185 DQS Interval Oscillator Matching Error ...................................................................................................... 187 OSC Count Readout Time .......................................................................................................................... 188 Thermal Offset .............................................................................................................................................. 190 Temperature Sensor ...................................................................................................................................... 190 ZQ Calibration ............................................................................................................................................... 191 ZQCAL Reset ............................................................................................................................................. 192 Multichannel Considerations ..................................................................................................................... 193 ZQ External Resistor, Tolerance, and Capacitive Loading ............................................................................. 194 Frequency Set Points ..................................................................................................................................... 195 Frequency Set Point Update Timing ........................................................................................................... 196 Pull-Up and Pull-Down Characteristics and Calibration .................................................................................. 200 On-Die Termination for the Command/Address Bus ....................................................................................... 201 ODT Mode Register and ODT State Table .................................................................................................... 201 5 200b: x32 LPDDR4 SDRAM Features ODT Mode Register and ODT Characteristics ............................................................................................. 202 ODT for CA Update Time ........................................................................................................................... 204 DQ On-Die Termination ................................................................................................................................ 205 Output Driver and Termination Register Temperature and Voltage Sensitivity .............................................. 207 ODT Mode Register ................................................................................................................................... 208 Asynchronous ODT ................................................................................................................................... 208 DQ ODT During Power-Down and Self Refresh Modes ................................................................................ 210 ODT During Write Leveling Mode .............................................................................................................. 210 Target Row Refresh Mode ............................................................................................................................... 211 TRR Mode Operation ................................................................................................................................. 211 Post-Package Repair ...................................................................................................................................... 213 Failed Row Address Repair ......................................................................................................................... 213 Read Preamble Training ................................................................................................................................. 215 Electrical Specifications ................................................................................................................................. 216 Absolute Maximum Ratings ....................................................................................................................... 216 AC and DC Operating Conditions ................................................................................................................... 216 AC and DC Input Measurement Levels ........................................................................................................... 218 Input Levels for CKE .................................................................................................................................. 218 Input Levels for RESET_n and ODT_CA ...................................................................................................... 218 Differential Input Voltage for CK ................................................................................................................ 218 Peak Voltage Calculation Method ............................................................................................................... 219 Single-Ended Input Voltage for Clock ......................................................................................................... 220 Differential Input Slew Rate Definition for Clock ......................................................................................... 221 Differential Input Cross-Point Voltage ........................................................................................................ 222 Differential Input Voltage for DQS .............................................................................................................. 223 Peak Voltage Calculation Method ............................................................................................................... 223 Single-Ended Input Voltage for DQS ........................................................................................................... 224 Differential Input Slew Rate Definition for DQS .......................................................................................... 225 Differential Input Cross-Point Voltage ........................................................................................................ 226 Input Levels for ODT ................................................................................................................................. 227 Output Slew Rate and Overshoot/Undershoot specifications ........................................................................... 227 Single-Ended Output Slew Rate .................................................................................................................. 227 Differential Output Slew Rate ..................................................................................................................... 228 Overshoot and Undershoot Specifications .................................................................................................. 229 Driver Output Timing Reference Load ............................................................................................................ 229 LVSTL I/O System .......................................................................................................................................... 230 Input/Output Capacitance ............................................................................................................................. 231 IDD Specification Parameters and Test Conditions ........................................................................................... 232 IDD Specifications ...................................................................................................................................... 238 AC Timing ..................................................................................................................................................... 240 CA Rx Voltage and Timing .............................................................................................................................. 249 DQ Tx Voltage and Timing ............................................................................................................................. 252 DRAM Data Timing ................................................................................................................................... 252 DQ Rx Voltage and Timing ............................................................................................................................. 253 Clock Specification ........................................................................................................................................ 256 tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 257 Clock Period Jitter .......................................................................................................................................... 257 Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 257 Cycle Time Derating for Core Timing Parameters ........................................................................................ 258 Clock Cycle Derating for Core Timing Parameters ....................................................................................... 258 Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 258 Clock Jitter Effects on READ Timing Parameters .......................................................................................... 258 6 200b: x32 LPDDR4 SDRAM Features Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 259 Revision History ............................................................................................................................................ 260 Rev. D – 3/17 ............................................................................................................................................. 260 Rev. C – 11/16 ............................................................................................................................................ 260 Rev. B – 8/16 .............................................................................................................................................. 260 Rev. A – 5/16 .............................................................................................................................................. 260 7 200b: x32 LPDDR4 SDRAM Features List of Figures Figure 1: Part Number Chart ............................................................................................................................ 3 Figure 2: Dual-Die, Dual-Channel, Single-Rank Package Block Diagram .......................................................... 17 Figure 3: Quad-Die, Dual-Channel, Dual-Rank Package Block Diagram ........................................................... 18 Figure 4: 200-Ball Dual-Channel, Single-Rank Discrete FBGA .......................................................................... 19 Figure 5: 200-Ball Dual-Channel, Dual-Rank Discrete FBGA ............................................................................ 20 Figure 6: 200-Ball WFBGA – 10mm × 14.5mm (Package Code: NP) ................................................................... 22 Figure 7: 200-Ball VFBGA – 10mm × 14.5mm (Package Code: NQ) ................................................................... 23 Figure 8: 200-Ball WFBGA – 10mm × 14.5mm (Package Code: DS) ................................................................... 24 Figure 9: 200-Ball WFBGA – 10mm × 14.5mm (Package Code: DT) ................................................................... 25 Figure 10: Functional Block Diagram ............................................................................................................. 32 Figure 11: Simplified State Diagram ............................................................................................................... 36 Figure 12: Simplified State Diagram ............................................................................................................... 37 Figure 13: Voltage Ramp and Initialization Sequence ...................................................................................... 39 Figure 14: ACTIVATE Command .................................................................................................................... 71 Figure 15: tFAW Timing .................................................................................................................................. 71 Figure 16: DQS Read Preamble and Postamble – Toggling Preamble and 0.5nCK Postamble ............................. 72 Figure 17: DQS Read Preamble and Postamble – Static Preamble and 1.5nCK Postamble .................................. 73 Figure 18: DQS Write Preamble and Postamble – 0.5nCK Postamble ................................................................ 73 Figure 19: DQS Write Preamble and Postamble – 1.5nCK Postamble ................................................................ 74 Figure 20: Burst Read Timing ......................................................................................................................... 75 Figure 21: Burst Read Followed by Burst Write or Burst Mask Write .................................................................. 76 Figure 22: Seamless Burst Read ...................................................................................................................... 76 Figure 23: Read Timing .................................................................................................................................. 77 Figure 24: tLZ(DQS) Method for Calculating Transitions and Endpoint ............................................................ 78 Figure 25: tHZ(DQS) Method for Calculating Transitions and Endpoint ........................................................... 78 Figure 26: tLZ(DQ) Method for Calculating Transitions and Endpoint .............................................................. 79 Figure 27: tHZ(DQ) Method for Calculating Transitions and Endpoint ............................................................. 80 Figure 28: Burst WRITE Operation ................................................................................................................. 82 Figure 29: Burst Write Followed by Burst Read ................................................................................................ 83 Figure 30: Write Timing ................................................................................................................................. 84 Figure 31: Method for Calculating tWPRE Transitions and Endpoints ............................................................... 85 Figure 32: Method for Calculating tWPST Transitions and Endpoints ............................................................... 85 Figure 33: MASK WRITE Command – Same Bank ........................................................................................... 86 Figure 34: MASK WRITE Command – Different Bank ...................................................................................... 87 Figure 35: MASKED WRITE Command with Write DBI Enabled; DM Enabled .................................................. 92 Figure 36: WRITE Command with Write DBI Enabled; DM Disabled ................................................................ 93 Figure 37: READ Operations: tCCD = MIN, Preamble = Toggle, 1.5nCK Postamble ............................................ 94 Figure 38: Seamless READ: tCCD = MIN + 1, Preamble = Toggle, 1.5nCK Postamble .......................................... 95 Figure 39: Consecutive READ: tCCD = MIN + 1, Preamble = Toggle, 0.5nCK Postamble ..................................... 95 Figure 40: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 1.5nCK Postamble ...................................... 96 Figure 41: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 0.5nCK Postamble ...................................... 96 Figure 42: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 1.5nCK Postamble ..................................... 97 Figure 43: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 0.5nCK Postamble ..................................... 98 Figure 44: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 1.5nCK Postamble ...................................... 98 Figure 45: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 0.5nCK Postamble ...................................... 99 Figure 46: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 1.5nCK Postamble .................................... 100 Figure 47: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 0.5nCK Postamble .................................... 100 Figure 48: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 1.5nCK Postamble ..................................... 101 Figure 49: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 0.5nCK Postamble ..................................... 101 Figure 50: Seamless WRITE: tCCD = MIN, 0.5nCK Postamble ......................................................................... 102 8 200b: x32 LPDDR4 SDRAM Features Figure 51: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble, 533 MHz < Clock Frequency ” 800 MHz, ODT Worst Timing Case ..................................................................................................................................... 103 Figure 52: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble ......................................................................... 104 Figure 53: Consecutive WRITE: tCCD = MIN + 1, 0.5nCK Postamble ................................................................ 105 Figure 54: Consecutive WRITE: tCCD = MIN + 1, 1.5nCK Postamble ................................................................ 105 Figure 55: Consecutive WRITE: tCCD = MIN + 2, 0.5nCK Postamble ................................................................ 106 Figure 56: Consecutive WRITE: tCCD = MIN + 2, 1.5nCK Postamble ................................................................ 106 Figure 57: Consecutive WRITE: tCCD = MIN + 3, 0.5nCK Postamble ................................................................ 107 Figure 58: Consecutive WRITE: tCCD = MIN + 3, 1.5nCK Postamble ................................................................ 108 Figure 59: Consecutive WRITE: tCCD = MIN + 4, 1.5nCK Postamble ................................................................ 108 Figure 60: Burst READ Followed by Precharge – BL16, Toggling Preamble, 0.5nCK Postamble .......................... 110 Figure 61: Burst READ Followed by Precharge – BL32, 2tCK, 0.5nCK Postamble ............................................... 110 Figure 62: Burst WRITE Followed by PRECHARGE – BL16, 2nCK Preamble, 0.5nCK Postamble ........................ 111 Figure 63: Burst READ With Auto Precharge – BL16, Non-Toggling Preamble, 0.5nCK Postamble ..................... 112 Figure 64: Burst READ With Auto Precharge – BL32, Toggling Preamble, 1.5nCK Postamble ............................. 112 Figure 65: Burst WRITE With Auto Precharge – BL16, 2 nCK Preamble, 0.5nCK Postamble ................................ 113 Figure 66: Command Input Timing with RAS Lock ......................................................................................... 117 Figure 67: Delay Time From WRITE-to-READ with Auto Precharge ................................................................. 117 Figure 68: All-Bank REFRESH Operation ....................................................................................................... 120 Figure 69: Per Bank REFRESH Operation ....................................................................................................... 121 Figure 70: Postponing REFRESH Commands (Example) ................................................................................. 123 Figure 71: Pulling In REFRESH Commands (Example) ................................................................................... 123 Figure 72: Self Refresh Entry/Exit Timing ...................................................................................................... 125 Figure 73: Self Refresh Entry/Exit Timing with Power-Down Entry/Exit .......................................................... 126 Figure 74: Command Input Timings after Power-Down Exit During Self Refresh ............................................. 127 Figure 75: MRR, MRW, and MPC Commands Issuing Timing During tXSR ....................................................... 128 Figure 76: MRR, MRW, and MPC Commands Issuing Timing During tRFC ...................................................... 129 Figure 77: Basic Power-Down Entry and Exit Timing ...................................................................................... 131 Figure 78: Read and Read with Auto Precharge to Power-Down Entry ............................................................. 132 Figure 79: Write and Mask Write to Power-Down Entry .................................................................................. 133 Figure 80: Write With Auto Precharge and Mask Write With Auto Precharge to Power-Down Entry ................... 134 Figure 81: Refresh Entry to Power-Down Entry .............................................................................................. 135 Figure 82: ACTIVATE Command to Power-Down Entry .................................................................................. 135 Figure 83: PRECHARGE Command to Power-Down Entry .............................................................................. 136 Figure 84: Mode Register Read to Power-Down Entry ..................................................................................... 137 Figure 85: Mode Register Write to Power-Down Entry .................................................................................... 138 Figure 86: MULTI PURPOSE Command for ZQCAL Start to Power-Down Entry ............................................... 139 Figure 87: MODE REGISTER READ Operation ............................................................................................... 143 Figure 88: READ-to-MRR Timing .................................................................................................................. 144 Figure 89: WRITE-to-MRR Timing ................................................................................................................. 145 Figure 90: MRR Following Power-Down ......................................................................................................... 146 Figure 91: MODE REGISTER WRITE Timing .................................................................................................. 146 Figure 92: VRCG Enable Timing .................................................................................................................... 149 Figure 93: VRCG Disable Timing ................................................................................................................... 149 Figure 94: V REF Operating Range (VREF,max, V REF,min) ....................................................................................... 150 Figure 95: V REF Set-Point Tolerance and Step Size .......................................................................................... 151 Figure 96: tVref for Short, Middle, and Long Timing Diagram .......................................................................... 152 Figure 97: V REF(CA) Single-Step Increment ...................................................................................................... 152 Figure 98: V REF(CA) Single-Step Decrement ..................................................................................................... 153 Figure 99: V REF(CA) Full Step from V REF,min to V REF,max ...................................................................................... 153 Figure 100: V REF(CA) Full Step from V REF,max to V REF,min .................................................................................... 153 Figure 101: V REF Operating Range (VREF,max, V REF,min) ..................................................................................... 155 9 200b: x32 LPDDR4 SDRAM Features Figure 102: Figure 103: Figure 104: Figure 105: Figure 106: Figure 107: Figure 108: Figure 109: Figure 110: Figure 111: Figure 112: Figure 113: Figure 114: Figure 115: Figure 116: Figure 117: Figure 118: Figure 119: Figure 120: Figure 121: Figure 122: Figure 123: Figure 124: Figure 125: Figure 126: Figure 127: Figure 128: Figure 129: Figure 130: Figure 131: Figure 132: Figure 133: Figure 134: Figure 135: Figure 136: Figure 137: Figure 138: Figure 139: Figure 140: Figure 141: Figure 142: Figure 143: Figure 144: Figure 145: Figure 146: Figure 147: Figure 148: Figure 149: Figure 150: Figure 151: Figure 152: Figure 153: V REF Set Tolerance and Step Size .................................................................................................. 156 V REF(DQ) Transition Time for Short, Middle, or Long Changes ........................................................ 157 V REF(DQ) Single-Step Size Increment ............................................................................................. 157 V REF(DQ) Single-Step Size Decrement ............................................................................................ 158 V REF(DQ) Full Step from V REF,min to V REF,max ................................................................................... 158 V REF(DQ) Full Step from V REF,max to V REF,min ................................................................................... 158 Command Bus Training Mode Entry – CA Training Pattern I/O with V REF(CA) Value Update ............ 163 Consecutive V REF(CA) Value Update .............................................................................................. 164 Command Bus Training Mode Exit with Valid Command .............................................................. 165 Command Bus Training Mode Exit with Power-Down Entry .......................................................... 166 Write Leveling Timing – tDQSL (MAX) .......................................................................................... 168 Write Leveling Timing – tDQSL (MIN) .......................................................................................... 168 Clock Stop and Timing During Write Leveling .............................................................................. 169 DQS_t/DQS_c to CK_t/CK_c Timings at the Pins Referenced from the Internal Latch .................... 170 WRITE-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK ............................................................................ 172 READ-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK, tRPRE = Toggling, tRPST = 1.5nCK ......................... 173 READ-FIFO – tRPRE = Toggling, tRPST = 1.5nCK ........................................................................... 174 Read DQ Calibration Training Timing: Read-to-Read DQ Calibration ............................................ 177 Read DQ Calibration Training Timing: Read DQ Calibration to Read DQ Calibration/Read ............ 177 MPC[READ DQ CALIBRATION] Following Power-Down State ....................................................... 179 WRITE-to-MPC[WRITE-FIFO] Operation Timing ......................................................................... 181 MPC[WRITE-FIFO]-to-MPC[READ-FIFO] Timing ........................................................................ 182 MPC[READ-FIFO] to Read Timing ............................................................................................... 183 MPC[WRITE-FIFO] with DQ ODT Timing .................................................................................... 184 Power-Down Exit to MPC[WRITE-FIFO] Timing ........................................................................... 185 Interval Oscillator Offset – OSCoffset ............................................................................................. 187 In Case of DQS Interval Oscillator is Stopped by MPC Command .................................................. 188 In Case of DQS Interval Oscillator is Stopped by DQS Interval Timer ............................................. 189 Temperature Sensor Timing ........................................................................................................ 191 ZQCAL Timing ............................................................................................................................ 193 Frequency Set Point Switching Timing ......................................................................................... 197 Training for Two Frequency Set Points ......................................................................................... 199 Example of Switching Between Two Trained Frequency Set Points ................................................ 199 Example of Switching to a Third Trained Frequency Set Point ....................................................... 200 ODT for CA ................................................................................................................................. 201 ODT for CA Setting Update Timing in 4-Clock Cycle Command .................................................... 204 Functional Representation of DQ ODT ........................................................................................ 205 Asynchronous ODTon/ODToff Timing ......................................................................................... 209 Target Row Refresh Mode ............................................................................................................ 212 Post-Package Repair Timing ........................................................................................................ 214 Read Preamble Training .............................................................................................................. 215 Input Timing Definition for CKE .................................................................................................. 218 Input Timing Definition for RESET_n and ODT_CA ...................................................................... 218 CK Differential Input Voltage ....................................................................................................... 219 Definition of Differential Clock Peak Voltage ................................................................................ 220 Clock Single-Ended Input Voltage ................................................................................................ 220 Differential Input Slew Rate Definition for CK_t, CK_c .................................................................. 221 V ix Definition (Clock) .................................................................................................................. 222 DQS Differential Input Voltage .................................................................................................... 223 Definition of Differential DQS Peak Voltage .................................................................................. 224 DQS Single-Ended Input Voltage ................................................................................................. 224 Differential Input Slew Rate Definition for DQS_t, DQS_c ............................................................. 225 10 200b: x32 LPDDR4 SDRAM Features Figure 154: Figure 155: Figure 156: Figure 157: Figure 158: Figure 159: Figure 160: Figure 161: Figure 162: Figure 163: Figure 164: Figure 165: Figure 166: Figure 167: Figure 168: Figure 169: Figure 170: Figure 171: Figure 172: Figure 173: V ix Definition (DQS) .................................................................................................................... 226 Single-Ended Output Slew Rate Definition ................................................................................... 228 Differential Output Slew Rate Definition ...................................................................................... 228 Overshoot and Undershoot Definition ......................................................................................... 229 Driver Output Timing Reference Load ......................................................................................... 230 LVSTL I/O Cell ............................................................................................................................ 230 Pull-Up Calibration ..................................................................................................................... 231 tCMDCKE Timing ....................................................................................................................... 244 tESCKE Timing ........................................................................................................................... 246 CA Receiver (Rx) Mask ................................................................................................................ 249 Across Pin V REF (CA) Voltage Variation ........................................................................................... 249 CA Timings at the DRAM Pins ..................................................................................................... 250 CA tcIPW and SRIN_cIVW Definition (for Each Input Pulse) .......................................................... 250 CA V IHL_AC Definition (for Each Input Pulse) ................................................................................ 250 Read Data Timing Definitions – tQH and tDQSQ Across DQ Signals per DQS Group ....................... 252 DQ Receiver (Rx) Mask ................................................................................................................ 253 Across Pin V REF DQ Voltage Variation ........................................................................................... 253 DQ-to-DQS tDQS2DQ and tDQDQ .............................................................................................. 254 DQ tDIPW and SRIN_dIVW Definition for Each Input Pulse .......................................................... 255 DQ V IHL(AC) Definition (for Each Input Pulse) ............................................................................... 255 11 200b: x32 LPDDR4 SDRAM Features List of Tables Table 1: Key Timing Parameters ....................................................................................................................... 1 Table 2: Device Addressing .............................................................................................................................. 2 Table 3: Ball/Pad Descriptions ....................................................................................................................... 21 Table 4: Mode Register Contents .................................................................................................................... 26 Table 5: IDD Parameters – Single-Die .............................................................................................................. 27 Table 6: IDD6 Full-Array Self Refresh Current ................................................................................................... 28 Table 7: IDD Parameters – Single-Die .............................................................................................................. 28 Table 8: IDD6 Full-Array Self Refresh Current ................................................................................................... 30 Table 9: Monolithic Device Addressing – 2 Channels per Die ........................................................................... 33 Table 10: Monolithic Device Addressing – 1 Channel per Die ........................................................................... 34 Table 11: Mode Register Default Settings ........................................................................................................ 38 Table 12: Voltage Ramp Conditions ................................................................................................................ 38 Table 13: Initialization Timing Parameters ...................................................................................................... 40 Table 14: Reset Timing Parameter .................................................................................................................. 41 Table 15: Power Supply Conditions ................................................................................................................ 41 Table 16: Power-Off Timing ............................................................................................................................ 42 Table 17: Mode Register Assignments ............................................................................................................. 42 Table 18: MR0 Device Feature 0 (MA[7:0] = 00h) .............................................................................................. 43 Table 19: MR0 Op-Code Bit Definitions .......................................................................................................... 43 Table 20: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 44 Table 21: MR1 Op-Code Bit Definitions .......................................................................................................... 44 Table 22: Burst Sequence for Read .................................................................................................................. 46 Table 23: Burst Sequence for Write ................................................................................................................. 46 Table 24: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 47 Table 25: MR2 Op-Code Bit Definitions .......................................................................................................... 47 Table 26: Frequency Ranges for RL, WL, nWR, and nRTP Settings .................................................................... 49 Table 27: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 49 Table 28: MR3 Op-Code Bit Definitions .......................................................................................................... 50 Table 29: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 51 Table 30: MR4 Op-Code Bit Definitions .......................................................................................................... 51 Table 31: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 52 Table 32: MR5 Op-Code Bit Definitions .......................................................................................................... 52 Table 33: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 52 Table 34: MR6 Op-Code Bit Definitions .......................................................................................................... 52 Table 35: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 52 Table 36: MR7 Op-Code Bit Definitions .......................................................................................................... 52 Table 37: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 53 Table 38: MR8 Op-Code Bit Definitions .......................................................................................................... 53 Table 39: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 53 Table 40: MR9 Op-Code Definitions ............................................................................................................... 53 Table 41: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 53 Table 42: MR10 Op-Code Bit Definitions ........................................................................................................ 54 Table 43: MR11 ODT Control (MA[7:0] = 0Bh) ................................................................................................. 54 Table 44: MR11 Op-Code Bit Definitions ........................................................................................................ 54 Table 45: MR12 Register Information (MA[7:0] = 0Ch) ..................................................................................... 55 Table 46: MR12 Op-Code Bit Definitions ........................................................................................................ 55 Table 47: MR13 Register Control (MA[7:0] = 0Dh) ............................................................................................ 55 Table 48: MR13 Op-Code Bit Definition .......................................................................................................... 56 Table 49: Mode Register14 (MA[7:0] = 0Eh) ..................................................................................................... 57 Table 50: MR14 Op-Code Bit Definition .......................................................................................................... 57 12 200b: x32 LPDDR4 SDRAM Features Table 51: V REF Setting for Range[0] and Range[1] ............................................................................................. 58 Table 52: MR15 Register Information (MA[7:0] = 0Fh) ..................................................................................... 59 Table 53: MR15 Op-code Bit Definition .......................................................................................................... 59 Table 54: MR15 Invert Register Pin Mapping ................................................................................................... 59 Table 55: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 59 Table 56: MR16 Op-Code Bit Definitions ........................................................................................................ 59 Table 57: MR17 PASR Segment Mask (MA[7:0] = 11h) ...................................................................................... 60 Table 58: MR17 PASR Segment Mask Definitions ............................................................................................ 60 Table 59: MR17 PASR Segment Mask .............................................................................................................. 60 Table 60: MR18 Register Information (MA[7:0]=12h) ....................................................................................... 61 Table 61: MR18 LSB DQS Oscillator Count ...................................................................................................... 61 Table 62: MR19 Register Information (MA[7:0] = 13h) ..................................................................................... 61 Table 63: MR19 DQS Oscillator Count ............................................................................................................ 61 Table 64: MR20 Register Information (MA[7:0] = 14h) ..................................................................................... 62 Table 65: MR20 Register Information ............................................................................................................. 62 Table 66: MR20 Invert Register Pin Mapping ................................................................................................... 62 Table 67: MR21 Register Information (MA[7:0] = 15h) ..................................................................................... 62 Table 68: MR22 Register Information (MA[7:0] = 16h) ..................................................................................... 62 Table 69: MR22 Register Information ............................................................................................................. 63 Table 70: MR23 Register Information (MA[7:0] = 17h) ..................................................................................... 64 Table 71: MR23 Register Information ............................................................................................................. 64 Table 72: MR24 Register Information (MA[7:0] = 18h) ..................................................................................... 64 Table 73: MR24 Register Information ............................................................................................................. 65 Table 74: MR25 Register Information (MA[7:0] = 19h) ..................................................................................... 65 Table 75: MR25 Register Information ............................................................................................................. 65 Table 76: MR26:31 Register Information (MA[7:0] = 1Ah–1Fh) ......................................................................... 66 Table 77: MR32 Register Information (MA[7:0] = 20h) ..................................................................................... 66 Table 78: MR32 Register Information ............................................................................................................. 66 Table 79: MR33:39 Register Information (MA[7:0] = 21h–27h) .......................................................................... 66 Table 80: MR40 Register Information (MA[7:0] = 28h) ..................................................................................... 66 Table 81: MR40 Register Information ............................................................................................................. 67 Table 82: MR41:47 Register Information (MA[7:0] = 29h–2Fh) .......................................................................... 67 Table 83: MR48:63 Register Information (MA[7:0] = 30h–3Fh) .......................................................................... 67 Table 84: Command Truth Table .................................................................................................................... 68 Table 85: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements ..................................................... 79 Table 86: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements ........................................................ 80 Table 87: Method for Calculating tWPRE Transitions and Endpoints ................................................................ 85 Table 88: Reference Voltage for tWPST Timing Measurements ......................................................................... 86 Table 89: Same Bank (ODT Disabled) ............................................................................................................. 88 Table 90: Different Bank (ODT Disabled) ........................................................................................................ 88 Table 91: Same Bank (ODT Enabled) .............................................................................................................. 89 Table 92: Different Bank (ODT Enabled) ......................................................................................................... 89 Table 93: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations ................. 90 Table 94: Precharge Bank Selection ............................................................................................................... 109 Table 95: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable ................. 113 Table 96: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Enable ................. 116 Table 97: Bank and Refresh Counter Increment Behavior ............................................................................... 118 Table 98: REFRESH Command Timing Constraints ........................................................................................ 120 Table 99: Legacy REFRESH Command Timing Constraints ............................................................................. 122 Table 100: Modified REFRESH Command Timing Constraints ........................................................................ 122 Table 101: Refresh Requirement Parameters .................................................................................................. 123 Table 102: MRR ............................................................................................................................................ 142 13 200b: x32 LPDDR4 SDRAM Features Table 103: Table 104: Table 105: Table 106: Table 107: Table 108: Table 109: Table 110: Table 111: Table 112: Table 113: Table 114: Table 115: Table 116: Table 117: Table 118: Table 119: Table 120: Table 121: Table 122: Table 123: Table 124: Table 125: Table 126: Table 127: Table 128: Table 129: Table 130: Table 131: Table 132: Table 133: Table 134: Table 135: Table 136: Table 137: Table 138: Table 139: Table 140: Table 141: Table 142: Table 143: Table 144: Table 145: Table 146: Table 147: Table 148: Table 149: Table 150: Table 151: Table 152: Table 153: Table 154: Truth Table for MRR and MRW ..................................................................................................... 147 MRR/MRW Timing Constraints: DQ ODT is Disable ...................................................................... 147 MRR/MRW Timing Constraints: DQ ODT is Enable ....................................................................... 148 VRCG Enable/Disable Timing ....................................................................................................... 149 Internal V REF(CA) Specifications ..................................................................................................... 154 Internal V REF(DQ) Specifications .................................................................................................... 159 Mapping MR12 Op Code and DQ Numbers ................................................................................... 161 Mapping of CA Input Pin and DQ Output Pin ................................................................................ 163 Write Leveling Timing Parameters ................................................................................................. 169 Write Leveling Setup and Hold Timing .......................................................................................... 169 MPC Command Definition ........................................................................................................... 171 MPC Commands .......................................................................................................................... 172 Timing Constraints for Training Commands .................................................................................. 174 Invert Mask Assignments .............................................................................................................. 176 Read DQ Calibration Bit Ordering and Inversion Example .............................................................. 178 MR Setting vs. DMI Status ............................................................................................................. 179 MPC[WRITE-FIFO] AC Timing ...................................................................................................... 185 DQS Oscillator Matching Error Specification ................................................................................. 187 DQS Interval Oscillator AC Timing ................................................................................................ 189 Temperature Sensor ..................................................................................................................... 191 ZQ Calibration Parameters ........................................................................................................... 192 Mode Register Function with Two Physical Registers ...................................................................... 195 Relation Between MR Setting and DRAM Operation ...................................................................... 196 Frequency Set Point AC Timing ..................................................................................................... 197 tFC Value Mapping ....................................................................................................................... 197 tFC Value Mapping: Example ........................................................................................................ 198 Pull-Down Driver Characteristics – ZQ Calibration ........................................................................ 200 Pull-Up Characteristics – ZQ Calibration ....................................................................................... 200 Valid Calibration Points ................................................................................................................ 200 Command Bus ODT State ............................................................................................................. 202 ODT DC Electrical Characteristics – up to 3200 Mbps .................................................................... 202 ODT DC Electrical Characteristics – Beyond 3200 Mbps ................................................................. 203 ODT DC Electrical Characteristics – up to 3200 Mbps .................................................................... 205 ODT DC Electrical Characteristics – Beyond 3200 Mbps ................................................................. 206 Output Driver and Termination Register Sensitivity Definition ....................................................... 207 Output Driver and Termination Register Temperature and Voltage Sensitivity ................................. 208 ODTLON and ODTLOFF Latency Values .......................................................................................... 209 Termination State in Write Leveling Mode ..................................................................................... 210 Post-Package Repair Timing Parameters ........................................................................................ 214 Absolute Maximum DC Ratings .................................................................................................... 216 Recommended DC Operating Conditions ..................................................................................... 216 Input Leakage Current .................................................................................................................. 217 Input/Output Leakage Current ..................................................................................................... 217 Operating Temperature Range ...................................................................................................... 217 Input Levels ................................................................................................................................. 218 Input Levels ................................................................................................................................. 218 CK Differential Input Voltage ........................................................................................................ 219 Clock Single-Ended Input Voltage ................................................................................................. 221 Differential Input Slew Rate Definition for CK_t, CK_c ................................................................... 221 Differential Input Level for CK_t, CK_c .......................................................................................... 222 Differential Input Slew Rate for CK_t, CK_c .................................................................................... 222 Cross-Point Voltage for Differential Input Signals (Clock) ............................................................... 223 14 200b: x32 LPDDR4 SDRAM Features Table 155: Table 156: Table 157: Table 158: Table 159: Table 160: Table 161: Table 162: Table 163: Table 164: Table 165: Table 166: Table 167: Table 168: Table 169: Table 170: Table 171: Table 172: Table 173: Table 174: Table 175: Table 176: Table 177: Table 178: Table 179: Table 180: Table 181: Table 182: Table 183: Table 184: Table 185: Table 186: Table 187: Table 188: Table 189: Table 190: DQS Differential Input Voltage ...................................................................................................... 223 DQS Single-Ended Input Voltage ................................................................................................... 225 Differential Input Slew Rate Definition for DQS_t, DQS_c .............................................................. 225 Differential Input Level for DQS_t, DQS_c ..................................................................................... 226 Differential Input Slew Rate for DQS_t, DQS_c ............................................................................... 226 Cross-Point Voltage for Differential Input Signals (DQS) ................................................................ 227 Input Levels ................................................................................................................................. 227 Single-Ended Output Slew Rate .................................................................................................... 227 Differential Output Slew Rate ....................................................................................................... 228 AC Overshoot/Undershoot Specifications ..................................................................................... 229 Overshoot/Undershoot Specification for CKE and RESET .............................................................. 229 Input/Output Capacitance ........................................................................................................... 231 IDD Measurement Conditions ....................................................................................................... 232 CA Pattern for IDD4R ...................................................................................................................... 232 CA Pattern for IDD4W ..................................................................................................................... 233 Data Pattern for IDD4W (DBI Off) ................................................................................................... 233 Data Pattern for IDD4R (DBI Off) .................................................................................................... 234 Data Pattern for IDD4W (DBI On) .................................................................................................... 236 Data Pattern for IDD4R (DBI On) .................................................................................................... 237 IDD Specification Parameters and Operating Conditions ................................................................ 238 Clock Timing ............................................................................................................................... 240 Read Output Timing ..................................................................................................................... 240 Write Voltage and Timing ............................................................................................................. 242 CKE Input Timing ........................................................................................................................ 243 Command Address Input Timing .................................................................................................. 244 Boot Timing Parameters (10–55 MHz) ........................................................................................... 244 Mode Register Timing Parameters ................................................................................................. 245 Core Timing Parameters ............................................................................................................... 245 CA Bus ODT Timing ..................................................................................................................... 247 CA Bus Training Parameters .......................................................................................................... 247 Asynchronous ODT Turn On and Turn Off Timing ......................................................................... 248 Temperature Derating Parameters ................................................................................................ 248 DRAM CMD/ADR, CS ................................................................................................................... 251 DQs In Receive Mode ................................................................................................................... 255 Definitions and Calculations ........................................................................................................ 256 tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................. 257 15 200b: x32 LPDDR4 SDRAM General Description General Description The 6Gb Mobile Low-Power DDR4 SDRAM (LPDDR4) is a high-speed CMOS, dynamic random-access memory. The device is internally configured with x16 I/O, 8-banks. Each of the x16’s 805,306,368-bit banks is organized as 49,152 rows by 1024 columns by 16 bits. General Notes Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be interpreted as any or all DQ collectively, unless specifically stated otherwise. “DQS” and “CK” should be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise. “CA” includes all CA pins used for a given density. In timing diagrams, “CMD” is used as an indicator only. Actual signals occur on CA[5:0]. VREF indicates V REF(CA) and V REF(DQ). Complete functionality may be described throughout the entire document. Any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. Any functionality not specifically stated herein is considered undefined, illegal, is not supported, and will result in unknown operation. 16 200b: x32 LPDDR4 SDRAM Package Block Diagrams Package Block Diagrams Figure 2: Dual-Die, Dual-Channel, Single-Rank Package Block Diagram VDD1 VDD2 VSS VDDQ VDDQ RZQ Die ZQ0 RESET_n CS0_A CKE0_A LPDDR4 Channel A CK_t_A CK_c_A CA[5:0]_A ODT_CA DMI[1:0]_A DQ[15:0]_A DQS[1:0]_t_A DQS[1:0]_c_A ODT_CA_A Die CS0_B CKE0_B CK_t_B CK_c_B CA[5:0]_B LPDDR4 Channel B ODT_CA 17 DMI[1:0]_B DQ[15:0]_B DQS[1:0]_t_B DQS[1:0]_c_B ODT_CA_B 200b: x32 LPDDR4 SDRAM Package Block Diagrams Figure 3: Quad-Die, Dual-Channel, Dual-Rank Package Block Diagram VDD1 VDD2 VSS VDDQ VDDQ RZQ Die ZQ0 RESET_n CS0_A CKE0_A DMI[1:0]_A DQ[15:0]_A DQS[1:0]_t_A DQS[1:0]_c_A LPDDR4 CK_t_A CK_c_A CA[5:0]_A ODT_CA ODT_CA_A Die CS0_B DMI[1:0]_B DQ[15:0]_B DQS[1:0]_t_B DQS[1:0]_c_B LPDDR4 CKE0_B CK_t_B CK_c_B CA[5:0]_B ODT_CA ODT_CA_B VDDQ Die RZQ ZQ1 CS1_A CKE1_A LPDDR4 ODT_CA VSS Die CS1_B CKE1_B LPDDR4 ODT_CA VSS Note: 1. ODT(ca) for Rank 0 of each channel is wired to the respective ODT ball. ODT(ca) for Rank 1 of each channel is wired to VSS in the package. 18 200b: x32 LPDDR4 SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 4: 200-Ball Dual-Channel, Single-Rank Discrete FBGA 1 2 3 4 5 A DNU DNU VSS VDD2 B DNU DQ0_A VDDQ C VSS DQ1_A D VDDQ VSS E VSS F VDD1 DQ3_A VDDQ G VSS ODT_CA_A H VDD2 J K 8 9 10 11 12 ZQ0 NC VDD2 VSS DNU DNU DQ7_A VDDQ VDDQ DQ15_A VDDQ DQ8_A DNU DMI0_A DQ6_A VSS VSS DQ14_A DMI1_A DQ9_A VSS DQS0_t_A VSS VDDQ VDDQ VSS DQS1_t_A VSS VDDQ VSS VSS DQ4_A VDD2 VDD2 VSS VDD1 VSS CA0_A NC CS0_A VSS CA1_A VSS VDD2 VSS N VDD2 P DQ2_A DQS0_c_A DQ5_A 6 7 DQ13_A DQS1_c_A DQ10_A VSS DQ12_A VDDQ DQ11_A VDD1 VSS VDD1 VSS NC VSS VDD2 VDD2 CA2_A CA3_A CA4_A VDD2 CKE0_A NC CK_t_A CK_c_A VSS CA5_A VSS VDD2 VSS NC NC VSS VDD2 VSS VDD2 VSS VDD2 VSS NC NC VSS VDD2 VSS VDD2 VSS CA1_B VSS CKE0_B NC CK_t_B CK_c_B VSS CA5_B VSS R VDD2 CA0_B NC CS0_B VDD2 VDD2 CA2_B CA3_B CA4_B VDD2 T VSS ODT_CA_B VSS VDD1 VSS VSS VDD1 VSS RESET_n VSS U VDD1 DQ3_B VDDQ DQ4_B VDD2 VDD2 DQ12_B VDDQ DQ11_B VDD1 V VSS VSS VSS W VDDQ VSS DQS0_t_B VSS VDDQ VDDQ VSS DQS1_t_B VSS VDDQ Y VSS DQ1_B DMI0_B DQ6_B VSS VSS DQ14_B DMI1_B DQ9_B VSS AA DNU DQ0_B VDDQ DQ7_B VDDQ VDDQ DQ15_B VDDQ DQ8_B DNU AB DNU DNU VSS VDD2 VSS VSS VDD2 VSS DNU DNU 1 2 3 4 5 8 9 10 11 12 L M DQ2_B DQS0_c_B DQ5_B 6 7 DQ13_B DQS1_c_B DQ10_B VSS Top View (ball down) DDR4_A (Channel A) DDR4_B (Channel B) 19 ZQ, ODT_CA, RESET Supply Ground 200b: x32 LPDDR4 SDRAM Ball Assignments and Descriptions Figure 5: 200-Ball Dual-Channel, Dual-Rank Discrete FBGA 1 2 3 4 5 A DNU DNU VSS VDD2 B DNU DQ0_A VDDQ C VSS DQ1_A D VDDQ VSS E VSS F VDD1 DQ3_A VDDQ G VSS ODT_CA_A H VDD2 J K 8 9 10 11 12 ZQ0 ZQ1 VDD2 VSS DNU DNU DQ7_A VDDQ VDDQ DQ15_A VDDQ DQ8_A DNU DMI0_A DQ6_A VSS VSS DQ14_A DMI1_A DQ9_A VSS DQS0_t_A VSS VDDQ VDDQ VSS DQS1_t_A VSS VDDQ VSS VSS DQ4_A VDD2 VDD2 VSS VDD1 VSS CA0_A CS1_A CS0_A VSS CA1_A VSS VDD2 VSS N VDD2 P DQ2_A DQS0_c_A DQ5_A 6 7 DQ13_A DQS1_c_A DQ10_A VSS DQ12_A VDDQ DQ11_A VDD1 VSS VDD1 VSS NC VSS VDD2 VDD2 CA2_A CA3_A CA4_A VDD2 CKE0_A CKE1_A CK_t_A CK_c_A VSS CA5_A VSS VDD2 VSS NC NC VSS VDD2 VSS VDD2 VSS VDD2 VSS NC NC VSS VDD2 VSS VDD2 VSS CA1_B VSS CKE0_B CKE1_B CK_t_B CK_c_B VSS CA5_B VSS R VDD2 CA0_B CS1_B CS0_B VDD2 VDD2 CA2_B CA3_B CA4_B VDD2 T VSS ODT_CA_B VSS VDD1 VSS VSS VDD1 VSS RESET_n VSS U VDD1 DQ3_B VDDQ DQ4_B VDD2 VDD2 DQ12_B VDDQ DQ11_B VDD1 V VSS VSS VSS W VDDQ VSS DQS0_t_B VSS VDDQ VDDQ VSS DQS1_t_B VSS VDDQ Y VSS DQ1_B DMI0_B DQ6_B VSS VSS DQ14_B DMI1_B DQ9_B VSS AA DNU DQ0_B VDDQ DQ7_B VDDQ VDDQ DQ15_B VDDQ DQ8_B DNU AB DNU DNU VSS VDD2 VSS VSS VDD2 VSS DNU DNU 1 2 3 4 5 8 9 10 11 12 L M DQ2_B DQS0_c_B DQ5_B 6 7 DQ13_B DQS1_c_B DQ10_B VSS Top View (ball down) DDR4_A (Channel A) DDR4_B (Channel B) 20 ZQ, ODT_CA, RESET Supply Ground 200b: x32 LPDDR4 SDRAM Ball Assignments and Descriptions Table 3: Ball/Pad Descriptions Symbol Type Description CK_t_A, CK_c_A, CK_t_B, CK_c_B Input Clock: CK_t and CK_c are differential clock inputs. All address, command and control input signals are sampled on positive edge of CK_t and the negative edge of CK_c. AC timings for CA parameters are referenced to clock. Each channel (A, B) has its own clock pair. CKE0_A, CKE1_A, CKE0_B, CKE1_B Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, input buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions. CKE is sampled at the rising edge of CK. CS0_A, CS1_A, CS0_B, CS1_B Input Chip select: Each channel (A, B) has its own CS signals. CA[5:0]_A, CA[5:0]_B Input Command/address inputs: Provide the command and address inputs according to the command truth table. Each channel (A, B) has its own CA signals. ODT_CA_A, ODT_CA_B Input CA ODT Control: The ODT_CA pin is used in conjunction with the mode register to turn on/off the on-die termination for CA pins. It is bonded to VDD2 within the package, or at the package ball, for the terminating rank, and the non-terminating ranks are bonded to VSS (or left floating with a weak pull-down on the DRAM die). The terminating rank is the DRAM that terminates the CA bus for all die on the same channel. DQ[15:0]_A, DQ[15:0]_B I/O Data input/output: Bidirectional data bus. DQS[1:0]_t_A, DQS[1:0]_c_A, DQS[1:0]_t_B, DQS[1:0]_c_B I/O Data strobe: DQS_t and DQS_c are bi-directional differential output clock signals used to strobe data during a READ or WRITE. The data strobe is generated by the DRAM for a READ and is edge-aligned with data. The data strobe is generated by the SoC memory controller for a WRITE and is trained to precede data. Each byte of data has a data strobe signal pair. Each channel (A, B) has its own DQS_t and DQS_c strobes. DMI[1:0]_A, DMI[1:0]_B I/O Data Mask/Data Bus Inversion: DMI is a dual use bi-directional signal used to indicate data to be masked, and data which is inverted on the bus. For data bus inversion (DBI), the DMI signal is driven HIGH when the data on the data bus is inverted, or driven LOW when the data is in its normal state. DBI can be disabled via a mode register setting. For data mask, the DMI signal is used in combination with the data lines to indicate data to be masked in a MASK WRITE command (see the Data Mask (DM) and Data Bus Inversion (DBI) sections for details). The data mask function can be disabled via a mode register setting. Each byte of data has a DMI signal. Each channel has its own DMI signals. ZQ0, ZQ1 Reference ZQ Calibration Reference: Used to calibrate the output drive strength and the termination resistance. There is one ZQ pin per die. The ZQ pin shall be connected to VDDQ through a 240Ω ±1% resistor. VDDQ, VDD1, VDD2 Supply Power supplies: Isolated on the die for improved noise immunity. VSS Supply Ground Reference: Power supply ground reference. RESET_n Input DNU – Do not use: Must be grounded or left floating. NC – No connect: Not internally connected. RESET: When asserted LOW, the RESET pin resets all channels of the die. 21 200b: x32 LPDDR4 SDRAM Package Dimensions Package Dimensions Figure 6: 200-Ball WFBGA – 10mm × 14.5mm (Package Code: NP) Seating plane A 200X Ø0.312 Dimensions apply to solder balls postreflow on Ø0.28 SMD ball pads. 0.08 A Ball A1 ID (covered by SR) 12 11 10 9 8 5 4 3 2 Ball A1 ID 1 A B C D E F G H J K L M N P R T U V W Y AA AB 14.5 ±0.1 13.65 CTR 0.65 TYP 0.7 ±0.1 0.8 TYP 8.8 CTR 10 ±0.1 Notes: 0.225 ±0.05 1. All dimensions are in millimeters. 2. Solder ball composition: SAC302 with NiAu pads (96.8% Sn, 3Ag, 0.2% Cu). 3. The package height does not include room temperature warpage. 22 200b: x32 LPDDR4 SDRAM Package Dimensions Figure 7: 200-Ball VFBGA – 10mm × 14.5mm (Package Code: NQ) Seating plane A 200X Ø0.312 Dimensions apply to solder balls postreflow on Ø0.28 SMD ball pads. 0.08 A Ball A1 ID (covered by SR) 12 11 10 9 8 5 4 3 2 Ball A1 ID 1 A B C D E F G H J K L M N P R T U V W Y AA AB 14.5 ±0.1 13.65 CTR 0.65 TYP 0.85 ±0.1 0.8 TYP 8.8 CTR 10 ±0.1 Notes: 0.225 ±0.05 1. All dimensions are in millimeters. 2. Solder ball composition: SAC302 with NiAu pads (96.8% Sn, 3Ag, 0.2% Cu). 3. The package height does not include room temperature warpage. 23 200b: x32 LPDDR4 SDRAM Package Dimensions Figure 8: 200-Ball WFBGA – 10mm × 14.5mm (Package Code: DS) Seating plane A 200X Ø0.363 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. 0.08 A Ball A1 ID 12 11 10 9 8 5 4 3 2 Ball A1 ID 1 A B C D E F G H J K L M N P R T U V W Y AA AB 14.5 ±0.1 13.65 CTR 0.65 TYP 0.7 ±0.1 0.8 TYP 0.227 ±0.05 8.8 CTR 10 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball composition: SAC302 with NiAu pads (96.8% Sn, 3Ag, 0.2% Cu). 3. The package height does not include room temperature warpage. 24 200b: x32 LPDDR4 SDRAM Package Dimensions Figure 9: 200-Ball WFBGA – 10mm × 14.5mm (Package Code: DT) Seating plane A 200X Ø0.363 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. 0.08 A Ball A1 ID 12 11 10 9 8 5 4 3 2 Ball A1 ID 1 A B C D E F G H J K L M N P R T U V W Y AA AB 14.5 ±0.1 13.65 CTR 0.65 TYP 0.85 ±0.1 0.8 TYP 0.227 ±0.05 8.8 CTR 10 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball composition: SAC302 with NiAu pads (96.8% Sn, 3Ag, 0.2% Cu). 3. The package height does not include room temperature warpage. 25 200b: x32 LPDDR4 SDRAM MR0, MR[6:4], MR8, MR13 Readout MR0, MR[6:4], MR8, MR13 Readout Table 4: Mode Register Contents Mode Register OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 REF MR0 0b: Both legacy and modified refresh mode supported SR Abort MR4 0b: Disable (default) 1b: Enable Manufacturer ID MR5 1111 1111b : Micron Revision ID1 MR6 0000 0001b Density MR8 OP[5:2] = 0011b: 6Gb per die (6Gb per channel) VRO MR13 0b: Normal operation (default) 1b: Output the VREF(CA) value on DQ7 and VREF(DQ) value on DQ6 Notes: 1. The contents of MR0, MR[6:4], MR8, and MR13 will reflect information specific to each in these packages. 2. Other bits not defined above and other mode registers are referred to in Mode Register Assignments and Definitions section. 26 200b: x32 LPDDR4 SDRAM IDD Parameters IDD Parameters Refer to IDD Specification Parameters and Test Conditions section for detailed conditions. Table 5: IDD Parameters – Single-Die VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V; TC = -25°C to +85°C Speed Grade Parameter IDD01 Supply 3200 Mbps 3733 Mbps Unit VDD1 3.5 3.5 mA IDD02 VDD2 45 45 IDD0Q VDDQ 0.75 0.75 IDD2P1 VDD1 1.2 1.2 IDD2P2 VDD2 3 3 IDD2PQ VDDQ 0.75 0.75 IDD2PS1 VDD1 1.2 1.2 IDD2PS2 VDD2 3 3 IDD2PSQ VDDQ 0.75 0.75 IDD2N1 VDD1 2 2 IDD2N2 VDD2 27 27 IDD2NQ VDDQ 0.75 0.75 IDD2NS1 VDD1 2 2 IDD2NS2 VDD2 23 23 IDD2NSQ VDDQ 0.75 0.75 IDD3P1 VDD1 1.2 1.2 IDD3P2 VDD2 9 9 IDD3PQ VDDQ 0.75 0.75 IDD3PS1 VDD1 1.2 1.2 IDD3PS2 VDD2 9 9 IDD3PSQ VDDQ 0.75 0.75 IDD3N1 VDD1 2.25 2.25 IDD3N2 VDD2 30 30 IDD3NQ VDDQ 0.75 0.75 IDD3NS1 VDD1 2.25 2.25 IDD3NS2 VDD2 26 26 IDD3NSQ VDDQ 0.75 0.75 IDD4R1 VDD1 2.25 2.25 IDD4R2 VDD2 275 315 IDD4RQ VDDQ 150 160 IDD4W1 VDD1 2.25 2.25 IDD4W2 VDD2 210 240 IDD4WQ VDDQ 55 65 27 Note mA mA mA mA mA mA mA mA mA mA 3 200b: x32 LPDDR4 SDRAM IDD Parameters Table 5: IDD Parameters – Single-Die (Continued) VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V; TC = -25°C to +85°C Speed Grade Parameter IDD51 Supply 3200 Mbps 3733 Mbps Unit VDD1 10 10 mA IDD52 VDD2 90 90 IDD5Q VDDQ 0.75 0.75 IDD5AB1 VDD1 2.5 2.5 IDD5AB2 VDD2 30 30 IDD5ABQ VDDQ 0.75 0.75 IDD5PB1 VDD1 2.5 2.5 IDD5PB2 VDD2 30 30 IDD5PBQ VDDQ 0.75 0.75 Notes: Note mA mA 1. Published IDD values except IDD4RQ are the maximum of the distribution of the arithmetic mean. Refer to the following note for IDD4RQ; refer to IDD6 Full-Array Self Refresh Current table for IDD6. 2. IDD4RQ value is reference only. Typical value. DBI disabled, VOH = VDDQ/3, TC = 25°C. Table 6: IDD6 Full-Array Self Refresh Current VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V Temperature Supply 25°C 85°C Note: Full-Array Self Refresh Current Unit VDD1 0.3 mA VDD2 0.5 VDDQ 0.1 VDD1 2.0 VDD2 5.0 VDDQ 0.75 1. IDD6 25°C is the typical, and IDD6 85°C is the maximum of the distribution of the arithmetic mean. Table 7: IDD Parameters – Single-Die VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V; TC = 0°C to +105°C Speed Grade Parameter Supply 3200 Mbps 3733 Mbps Unit IDD01 VDD1 3.5 3.5 mA IDD02 VDD2 45 45 IDD0Q VDDQ 0.75 0.75 IDD2P1 VDD1 1.2 1.2 IDD2P2 VDD2 3 3 IDD2PQ VDDQ 0.75 0.75 28 mA Note 200b: x32 LPDDR4 SDRAM IDD Parameters Table 7: IDD Parameters – Single-Die (Continued) VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V; TC = -25°C to +85°C Speed Grade Parameter IDD2PS1 Supply 3200 Mbps 3733 Mbps Unit VDD1 1.2 1.2 mA IDD2PS2 VDD2 3 3 IDD2PSQ VDDQ 0.75 0.75 IDD2N1 VDD1 2 2 IDD2N2 VDD2 30 30 IDD2NQ VDDQ 0.75 0.75 IDD2NS1 VDD1 2 2 IDD2NS2 VDD2 23 23 IDD2NSQ VDDQ 0.75 0.75 IDD3P1 VDD1 1.2 1.2 IDD3P2 VDD2 9 9 IDD3PQ VDDQ 0.75 0.75 IDD3PS1 VDD1 1.2 1.2 IDD3PS2 VDD2 9 9 IDD3PSQ VDDQ 0.75 0.75 IDD3N1 VDD1 2.25 2.25 IDD3N2 VDD2 36 36 IDD3NQ VDDQ 0.75 0.75 IDD3NS1 VDD1 2.25 2.25 IDD3NS2 VDD2 30 30 IDD3NSQ VDDQ 0.75 0.75 IDD4R1 VDD1 2.25 2.25 IDD4R2 VDD2 310 350 IDD4RQ VDDQ 165 170 IDD4W1 VDD1 2.25 2.25 IDD4W2 VDD2 235 265 IDD4WQ VDDQ 60 70 IDD51 VDD1 10 10 IDD52 VDD2 90 90 IDD5Q VDDQ 0.75 0.75 IDD5AB1 VDD1 2.5 2.5 IDD5AB2 VDD2 30 30 IDD5ABQ VDDQ 0.75 0.75 29 Note mA mA mA mA mA mA mA mA mA mA 3 200b: x32 LPDDR4 SDRAM IDD Parameters Table 7: IDD Parameters – Single-Die (Continued) VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V; TC = -25°C to +105°C Speed Grade Parameter IDD5PB1 Supply 3200 Mbps 3733 Mbps Unit VDD1 2.5 2.5 mA IDD5PB2 VDD2 30 30 IDD5PBQ VDDQ 0.75 0.75 Notes: Note 1. Published IDD values except IDD4RQ are the maximum of the distribution of the arithmetic mean. Refer to another note for IDD4RQ. And refer to another table for IDD6. 2. IDD4RQ value is reference only. Typical value. DBI disabled, VOH = VDDQ/3, TC = 25°C Table 8: IDD6 Full-Array Self Refresh Current VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V Temperature Supply 105°C Note: Full-Array Self Refresh Current Unit VDD1 2 mA VDD2 8 VDDQ 1 1. IDD6 105°C is the maximum of the distribution of the arithmetic mean. 30 200b: x32 LPDDR4 SDRAM Functional Description Functional Description The Mobile Low-Power DDR4 SDRAM (LPDDR4) is a high-speed CMOS, dynamic random-access memory internally configured with either 1 or 2 channels. Each channel is comprised of 16 DQs and 8 banks. LPDDR4 uses a 2-tick, single-data-rate (SDR) protocol on the CA bus to reduce the number of input signals in the system. The term "2-tick" means that the command/ address is decoded across two transactions, such that half of the command/address is captured with each of two consecutive rising edges of CK. The 6-bit CA bus contains command, address, and bank information. Some commands such as READ, WRITE, MASKED WRITE, and ACTIVATE require two consecutive 2-tick SDR commands to complete the instruction. LPDDR4 uses a double-data-rate (DDR) protocol on the DQ bus to achieve high-speed operation. The DDR interface transfers two data bits to each DQ lane in one clock cycle and is matched to a 16n-prefetch DRAM architecture. A write/read access consists of a single 16n-bit-wide data transfer to/from the DRAM core and 16 corresponding n-bitwide data transfers at the I/O pins. Read and write accesses to the device are burst-oriented. Accesses start at a selected column address and continue for a programmed number of columns in a programmed sequence. Accesses begin with the registration of an ACTIVATE command to open a row in the memory core, followed by a WRITE or READ command to access column data within the open row. The address and bank address (BA) bits registered by the ACTIVATE command are used to select the bank and row to be opened. The address and BA bits registered with the WRITE or READ command are used to select the bank and the starting column address for the burst access. Prior to normal operation, the LPDDR4 SDRAM must be initialized. Following sections provide detailed information about device initialization, register definition, command descriptions and device operations. 31 200b: x32 LPDDR4 SDRAM Monolithic Device Addressing Figure 10: Functional Block Diagram VDDQ RZQ ZQ To CLK, CS, CA ODT calibration To DQS, DQ, DMI ODT calibration ZQ Cal RESET CKE CK_t, CK_c CS_n CA[5:0] ODT_CA DQ ODT control RCVRS Command/Address Multiplex and Decode Control logic Mode registers x Refresh counter CA ODT control Rowaddress MUX Bank 7 Bank 7 Bank 6 Bank 6 Bank 5 Bank 5 Bank 4 Bank 4 Bank 3 Bank 3 Bank 2 Bank 2 Bank 1 Bank 1 Bank 0 Bank 0 rowMemory array address latch and decoder COL[3:0] 16n Read 16n MUX latch n DATA DRVRS Read data path DQS generator DQS_t, DQS_c (1...n) VSS Sense amplifier RTT,nom (1...n) 16n VSS RTT,nom I/O gating DM mask logic 0–7 SW 0–7 Bank control logic Columnaddress counter/ latch y-4 Column decoder n WRITE FIFO Mask 16n and drivers CK out CK_t, 16n CK in CK_c Data SW n/16 Input registers n RCVRS Write data path DQ[n-1:0] DQS_t, DQS_c DMI COL[3:0] 4 Monolithic Device Addressing The table below includes all monolithic device addressing options defined by JEDEC. Under the SDRAM Addressing heading near the beginning of this data sheet are addressing details for this product data sheet. 32 Table 9: Monolithic Device Addressing – 2 Channels per Die Memory density (per die) 6Gb 8Gb 12Gb 16Gb 2Gb 3Gb 4Gb 6Gb 8Gb Configuration 16Mb x 16DQ x 8 banks x 2 channels 24Mb x 16DQ x 8 banks x 2 channels 32Mb x 16DQ x 8 banks x 2 channels 48Mb x 16DQ x 8 banks x 2 channels 64Mb x 16DQ x 8 banks x 2 channels Number of channels (per die) 2 2 2 2 2 Number of banks (per channel) 8 8 8 8 8 Array prefetch (bits, per channel) 256 256 256 256 256 Number of rows (per channel) 16,384 24,576 32,768 49,152 65,536 Number of columns (fetch boundaries) 64 64 64 64 64 Page size (bytes) 2048 2048 2048 2048 2048 Channel density (bits per channel) 2,147,483,648 3,221,225,472 4,294,967,296 6,442,450,944 8,589,934,592 Total density (bits per die) 4,294,967,296 6,442,450,944 8,589,934,592 12,884,901,888 17,179,869,184 Bank address BA[2:0] BA[2:0] BA[2:0] BA[2:0] BA[2:0] x16 Row add R[13:0] R[14:0] (R13 = 0 when R14 = 1) R[14:0] R[15:0] (R14 = 0 when R15 = 1) R[15:0] Col. add C[9:0] C[9:0] C[9:0] C[9:0] C[9:0] 64 bit 64 bit 64 bit 64 bit 64 bit Memory density (per channel) 33 Burst starting address boundary 200b: x32 LPDDR4 SDRAM Monolithic Device Addressing 4Gb Table 10: Monolithic Device Addressing – 1 Channel per Die Memory density (per die) 4Gb 6Gb 8Gb Memory density (per channel) 4Gb 6Gb 8Gb Configuration 32Mb x 16 DQ x 8 banks 48Mb x 16 DQ x 8 banks 64Mb x 16 DQ x 8 banks Number of channels (per die) 1 1 1 Number of banks (per channel) 8 8 8 Array prefetch (bits, per channel) Number of rows (per channel) Number of columns (fetch boundaries) 256 256 256 32,768 49,152 65,536 64 64 64 2048 2048 2048 Channel density (bits per channel) 4,294,967,296 6,442,450,944 8,589,934,592 Total density (bits per die) 4,294,967,296 6,442,450,944 8,589,934,592 BA[2:0] BA[2:0] BA[2:0] R[14:0] R[15:0] (R14 = 0 when R15 = 1) R[15:0] Page size (bytes) Bank address x16 Row add Column add 34 Burst starting address boundary C[9:0] C[9:0] C[9:0] 64 bit 64 bit 64 bit 200b: x32 LPDDR4 SDRAM Monolithic Device Addressing 200b: x32 LPDDR4 SDRAM Monolithic Device Addressing Notes: 1. The lower two column addresses (C[1:0]) are assumed to be zero and are not transmitted on the CA bus. 2. Row and column address values on the CA bus that are not used for a particular density should be at valid logic levels. 3. For non-binary memory densities, only a quarter of the row address space is invalid. When the MSB address bit is HIGH, then the MSB - 1 address bit must be LOW. 35 200b: x32 LPDDR4 SDRAM Simplified Bus Interface State Diagram Simplified Bus Interface State Diagram The state diagram provides a simplified illustration of the bus interface, supported state transitions, and the commands that control them. For a complete description of device behavior, use the information provided in the state diagram with the truth tables and timing specifications. The truth tables describe device behavior and applicable restrictions when considering the actual state of all banks. For command descriptions, see the Commands and Timing section. Figure 11: Simplified State Diagram Automatic sequence Command sequence MPCbased training Power-on MR write MPCbased training L E M = CK E MPC H n T_ SE RE = H = RR M M REF MPC All bank refresh Idle SRX RW REF SRE Self refresh MPC MR write Per bank refresh RW CK MPCbased training MRW MRW RW MR write Reset Command bus training MR read MPC M n T_ SE RE = L SR powerdown MR R M W MR RR MR W =L CKE Command bus training MR read R MRW MR CKE =H MR read MPCbased training ACT Idle powerdown MR write MR read Activating Active powerdown MR write M = CK E RW CK L E R MR = H MPCbased training R or Per bank refresh RD MW MPC MPCbased training M RD RR or Read RA W A WRA or MWRA RDA PRE or PREA A RE PR E Write or mask write with auto precharge or E PR PR EA Precharging Notes: MR read RD Write or mask write M W RA WR W MR REF Bank active WR or MWR MR write MR read P or Read with auto precharge PRE(A) = PRECHARGE (ALL) ACT = ACTIVATE WR(A) = WRITE (with auto precharge) MWR(A) = Mask WRITE (with auto precharge) RD(A) = READ (with auto precharge) MRW = MODE REGISTER WRITE MRR = MODE REGISTER READ "CKE = L" = Enter power-down "CKE = H" = Exit power-down SRE = Enter self refresh SRX = Exit self refresh REF = REFRESH MPC = Mult-purpose command (with NOP) 1. From the self refresh state, the device can enter power-down, MRR, MRW, or any of the training modes initiated with the MPC command. See the Self Refresh section. 36 200b: x32 LPDDR4 SDRAM Power-Up and Initialization 2. All banks are precharged in the idle state. 3. In the case of using an MRW command to enter a training mode, the state machine will not automatically return to the idle state at the conclusion of training. See the applicable training section for more information. 4. In the case of an MPC command to enter a training mode, the state machine may not automatically return to the idle state at the conclusion of training. See the applicable training section for more information. 5. This diagram is intended to provide an overview of the possible state transitions and commands to control them; however, it does not contain the details necessary to operate the device. In particular, situations involving more than one bank are not captured in complete detail. 6. States that have an "automatic return" and can be accessed from more than one prior state (that is, MRW from either idle or active states) will return to the state where they were initiated (that is, MRW from idle will return to idle). 7. The RESET pin can be asserted from any state and will cause the device to enter the reset state. The diagram shows RESET applied from the power-on and idle states as an example, but this should not be construed as a restriction on RESET. 8. MRW commands from the active state cannot change operating parameters of the device that affect timing. Mode register fields which may be changed via MRW from the active state include: MR1-OP[3:0], MR1-OP[7], MR3-OP[7:6], MR10-OP[7:0], MR11OP[7:0], MR13-OP[5], MR15-OP[7:0], MR16-OP[7:0], MR17-OP[7:0], MR20-OP[7:0], and MR22-OP[4:0]. Figure 12: Simplified State Diagram a) FIFO-Based Write/Read Timing MPC Automatic sequence Command sequence MPC MPCbased training MPC b) Read DQ Calibration MPC Write -FIFO MPC Read -FIFO MPC MPC DQ Calibration = WRW MPC MRW WRW c) ZQCAL Start MPC d) ZQCAL Latch ZQ Calibration Start MPC ZQ Calibration Latch Power-Up and Initialization To ensure proper functionality for power-up and reset initialization, default values for the MR settings are provided in the table below. 37 200b: x32 LPDDR4 SDRAM Power-Up and Initialization Table 11: Mode Register Default Settings Item Mode Register Setting Default Setting FSP-OP/WR MR13 OP[7:6] 00b FSP-OP/WR[0] are enabled Description WLS MR2 OP[6] 0b WRITE latency set A is selected WL MR2 OP[5:3] 000b WL = 4 RL MR2 OP[2:0] 000b RL = 6, nRTP = 8 nWR MR1 OP[6:4] 000b nWR = 6 DBI-WR/RD MR3 OP[7:6] 00b Write and read DBI are disabled CA ODT MR11 OP[6:4] 000b CA ODT is disabled DQ ODT MR11 OP[2:0] 000b VREF(CA) setting MR12 OP[6] 1b VREF(CA) value MR12 OP[5:0] 001101b VREF(DQ) setting MR14 OP[6] 1b VREF(DQ) value MR14 OP[5:0] 001101b DQ ODT is disabled VREF(CA) range[1] is enabled Range1: 27.2% of VDD2 VREF(DQ) range[1] enabled Range1: 27.2% of VDDQ The following sequence must be used to power up the device. Unless specified otherwise, this procedure is mandatory. The power-up sequence of all channels must proceed simultaneously. Voltage Ramp 1. While applying power (after Ta), RESET_n should be held LOW (”0.2 × V DD2), and all other inputs must be between V IL,min and V IH,max. The device outputs remain at High-Z while RESET_n is held LOW. Power supply voltage ramp requirements are provided in the table below. V DD1 must ramp at the same time or earlier than V DD2. V DD2 must ramp at the same time or earlier than V DDQ. Table 12: Voltage Ramp Conditions After... Applicable Conditions Ta is reached VDD1 must be greater than VDD2 VDD2 must be greater than VDDQ - 200mV Notes: 1. Ta is the point when any power supply first reaches 300mV. 2. Voltage ramp conditions in above table apply between Ta and power-off (controlled or uncontrolled). 3. Tb is the point at which all supply and reference voltages are within their defined operating ranges. 4. Power ramp duration tINIT0 (Tb–Ta) must not exceed 20ms. 5. The voltage difference between any VSS and VSSQ must not exceed 100mV. 2. Following completion of the of the voltage ramp (Tb), RESET_n must be held LOW for tINIT1. DQ, DMI, DQS_t, and DQS_c voltage levels must be between V SSQ and V DDQ during voltage ramp to avoid latch-up. CK_t and CK_c, CS, and CA input levels must be between V SS and V DD2 during voltage ramp to avoid latch-up. Voltage ramp power supply requirements are provided in the table below. 38 200b: x32 LPDDR4 SDRAM Power-Up and Initialization 3. Beginning at Tb, RESET_n must remain LOW for at least tINIT1(Tc), after which RESET_n can be de-asserted to HIGH(Tc). At least 10ns before CKE de-assertion, CKE is required to be set LOW. All other input signals are "Don't Care." Figure 13: Voltage Ramp and Initialization Sequence Ta Tb Power Ramp Tc Reset Td Te Tf Tg Th Initialization Ti Tj Tk Training tINIT4=5tCK(MIN) CK_c CK_t tINIT0=20ms(MAX) tINIT1=200μs(MIN) Supplies RESET_n tINIT2=10ns(MIN) tINIT3=2ms(MIN) CKE tINIT5=2μs(MIN) CA[5:0] CS Exit PD DES MRW MRR tZQCAL=1μs(MIN) DES DQs ZQ Cal Start DES ZQ Cal Latch tZQLAT=MAX(30ns, 8 t CK)(MIN) DES CA BUS Training Valid DES Write Leveling Valid DES DQ Training DES Valid Valid Don’t Care Note: 1. Training is optional and may be done at the system designer's discretion. The order of training may be different than what is shown here. 4. After RESET_n is de-asserted(Tc), wait at least tINIT3 before activating CKE. CK_t, CK_c must be started and stabilized for tINIT4 before CKE goes active(Td). CS must remain LOW when the controller activates CKE. 5. After CKE is set to HIGH, wait a minimum of tINIT5 to issue any MRR or MRW commands(Te). For MRR and MRW commands, the clock frequency must be within the range defined for tCKb. Some AC parameters (for example, tDQSCK) could have relaxed timings (such as tDQSCKb) before the system is appropriately configured. 6. After completing all MRW commands to set the pull-up, pull-down, and Rx termination values, the controller can issue the ZQCAL START command to the memory(Tf). This command is used to calibrate the V OH level and the output impedance over process, voltage, and temperature. In systems where more than one device share one external ZQ resistor, the controller must not overlap the ZQ calibration sequence of each device. The ZQ calibration sequence is completed after tZQCAL (Tg). The ZQCAL LATCH command must be issued to update the DQ drivers and DQ + CA ODT to the calibrated values. 7. After tZQLAT is satisfied (Th), the command bus (internal V REF(CA), CS, and CA) should be trained for high-speed operation by issuing an MRW command (command bus training mode). This command is used to calibrate the device's internal V REF and align CS/CA with CK for high-speed operation. The device will power-up with receivers configured for low-speed operations and with V REF(CA) set to a default factory setting. Normal device operation at clock speeds higher than tCKb may not be possible until command bus training is complete. The command bus training MRW command uses the CA bus as inputs for the calibration data stream, and it outputs the results asynchro- 39 200b: x32 LPDDR4 SDRAM Power-Up and Initialization nously on the DQ bus. See command bus training in the MRW section for information on how to enter/exit the training mode. 8. After command bus training, the controller must perform write leveling. Write leveling mode is enabled when MR2 OP[7] is HIGH(Ti). See the Write Leveling section for a detailed description of the write leveling entry and exit sequence. In write leveling mode, the controller adjusts write DQS timing to the point where the device recognizes the start of write DQ data burst with desired WRITE latency. 9. After write leveling, the DQ bus (internal V REF(DQ), DQS, and DQ) should be trained for high-speed operation using the MPC TRAINING commands and by issuing MRW commands to adjust V REF(DQ). The device will power-up with receivers configured for low-speed operations and with V REF(DQ) set to a default factory setting. Normal device operation at clock speeds higher than tCKb should not be attempted until DQ bus training is complete. The MPC[READ DQ CALIBRATION] command is used together with MPC[READ-FIFO] or MPC[WRITE-FIFO] commands to train the DQ bus without disturbing the memory array contents. See the DQ Bus Training section for more information on the DQ bus training sequence. 10. At Tk, the device is ready for normal operation and is ready to accept any valid command. Any mode registers that have not previously been configured for normal operation should be written at this time. Table 13: Initialization Timing Parameters Parameter Min Max Unit tINIT0 – 20 ms Maximum voltage ramp time tINIT1 200 – μs Minimum RESET_n LOW time after completion of voltage ramp tINIT2 10 – ns Minimum CKE LOW time before RESET_n goes HIGH tINIT3 2 – ms Minimum CKE LOW time after RESET_n goes HIGH tINIT4 5 – tCK Minimum stable clock before first CKE HIGH tINIT5 2 tCKb Note – 1, 2 Notes: Note 1, 2 Comment μs Minimum idle time before first MRW/MRR command ns Clock cycle time during boot 1. Minimum tCKb guaranteed by DRAM test is 18ns. 2. The system may boot at a higher frequency than dictated by minimum tCKb. The higher boot frequency is system dependent. Reset Initialization with Stable Power The following sequence is required for RESET at no power interruption initialization. 1. Assert RESET_n below 0.2 × V DD2 anytime when reset is needed. RESET_n needs to be maintained for minimum tPW_RESET. CKE must be pulled LOW at least 10ns before de-asserting RESET_n. 2. Repeat steps 4–10 in Voltage Ramp section. 40 200b: x32 LPDDR4 SDRAM Power-Off Sequence Table 14: Reset Timing Parameter Value Parameter Min Max Unit tPW_RESET 100 – ns Comment Minimum RESET_n LOW time for reset initialization with stable power Power-Off Sequence Controlled Power-Off While powering off, CKE must be held LOW (”0.2 × V DD2); all other inputs must be between V IL,min and V IH,max. The device outputs remain at High-Z while CKE is held LOW. DQ, DMI, DQS_t, and DQS_c voltage levels must be between V SSQ and V DDQ during the power-off sequence to avoid latch-up. CK_t, CK_c, CS, and CA input levels must be between V SS and V DD2 during the power-off sequence to avoid latch-up. Tx is the point where any power supply drops below the minimum value specified in the minimum DC Operating Condition. Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off. Table 15: Power Supply Conditions The voltage difference between VSS and VSSQ must not exceed 100mV Between... Applicable Conditions VDD1 must be greater than VDD2 Tx and Tz VDD2 must be greater than VDDQ - 200mV Uncontrolled Power-Off When an uncontrolled power-off occurs, the following conditions must be met. • At Tx, when the power supply drops below the minimum values specified in the Recommended DC Operating Conditions table, all power supplies must be turned off and all power supply current capacity must be at zero, except for any static charge remaining in the system. • After Tz (the point at which all power supplies first reach 300mV), the device must power off. During this period, the relative voltage between power supplies is uncontrolled. V DD1 and V DD2 must decrease with a slope lower than 0.5 V/μs between Tx and Tz. An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device. 41 200b: x32 LPDDR4 SDRAM Mode Registers Table 16: Power-Off Timing Parameter Power-off ramp time Symbol Min Max Unit tPOFF – 2 sec Mode Registers Mode Register Assignments and Definitions Mode register definitions are provided in the Mode Register Assignments table. In the access column of the table, R indicates read-only; W indicates write-only; R/W indicates read- or write-capable or enabled. The MRR command is used to read from a register. The MRW command is used to write to a register. Table 17: Mode Register Assignments Notes 1–5 apply to entire table MR# MA[7:0] Function Access OP7 OP6 OP5 RFU RFU OP4 OP3 OP2 RZQI OP1 OP0 RFU REF Link Go to MR0 0 00h Device info R CATR 1 01h Device feature 1 W RDPST 2 02h Device feature 2 W WR Lev WLS WL 3 03h I/O config-1 W DBIWR DBI-RD PDDS 4 04h Refresh and training R /W TUF Thermal offset PPRE 5 05h Basic config-1 R Manufacturer ID Go to MR5 6 06h Basic config-2 R Revision ID1 Go to MR6 7 07h Basic config-3 R Revision ID2 Go to MR7 8 08h Basic config-4 R 9 09h Test mode W 10 0Ah I/O calibration W 11 0Bh ODT W nWR (for AP) I/O width RDPRE WRPRE BL Go to MR1 RL PPRP SR abort Go to MR2 WRPST PUCAL Refresh rate Density Type Vendor-specific test mode Go to MR4 Go to MR8 Go to MR9 RFU RFU Go to MR3 ZQ RST Go to MR10 CA ODT RFU DQ ODT Go to MR11 R/W RFU VRCA W FSP-OP FSPWR VREF(DQ) R/W RFU VRDQ 0Fh DQI-LB W 16 10h PASR_Bank W PASR bank mask Go to MR16 17 11h PASR_Seg W PASR segment mask Go to MR17 18 12h IT-LSB R DQS oscillator count – LSB Go to MR18 19 13h IT-MSB R DQS oscillator count – MSB Go to MR19 20 14h DQI-UB W Upper-byte invert register for DQ calibration Go to MR20 21 15h Vendor use W RFU Go to MR21 12 0Ch VREF(CA) 13 0Dh Register control 14 0Eh 15 VREF(CA) DMD RRO VRCG VRO Go to MR12 RPT VREF(DQ) Lower-byte invert register for DQ calibration 42 CBT Go to MR13 Go to MR14 Go to MR15 200b: x32 LPDDR4 SDRAM Mode Registers Table 17: Mode Register Assignments (Continued) Notes 1–5 apply to entire table MR# MA[7:0] Function Access 22 16h ODT feature 2 W 23 17h DQS oscillator stop W 24 18h TRR control 25 19h PPR resources 26–31 1Ah~1F h 32 20h – DQ calibration pattern A 33–39 21h≈27h Do not use OP7 OP6 RFU OP5 OP4 OP3 OP2 ODTD- ODTE- ODTECA CS CK R/W TRR mode R B7 TRR mode BAn B6 B5 B4 Unltd MAC B3 – Reserved for future use W See DQ calibration section Do not use See DQ calibration section 41–47 29h≈2Fh Do not use – Do not use 48–63 30h≈3Fh Reserved – Reserved for future use DQ calibration pattern B Notes: Go to MR23 MAC value B2 Link Go to MR22 DQS oscillator run-time setting – 28h OP0 SoC ODT W 40 OP1 B1 Go to MR24 B0 Go to MR25 Go to MR32 Go to MR40 1. RFU bits must be set to 0 during MRW commands. 2. RFU bits are read as 0 during MRR commands. 3. All mode registers that are specified as RFU or write-only shall return undefined data when read via an MRR command. 4. RFU mode registers must not be written. 5. Writes to read-only registers will not affect the functionality of the device. Table 18: MR0 Device Feature 0 (MA[7:0] = 00h) OP7 OP6 CATR OP5 OP4 RFU OP3 OP2 RZQI OP1 RFU OP0 REF Table 19: MR0 Op-Code Bit Definitions Register Information Tag Type OP Refresh mode REF Read only OP[0] Built-in self-test for RZQ information RZQI Read only OP[4:3] Definition Notes 0b: Both legacy and modified refresh mode supported 1b: Only modified refresh mode supported 00b: RZQ self-test not supported 01b: ZQ may connect to VSSQ or float 10b: ZQ may short to VDDQ 11b: ZQ pin self-test completed, no error condition detected (ZQ may not connect to VSSQ, float, or short to VDDQ) 43 1–4 200b: x32 LPDDR4 SDRAM Mode Registers Table 19: MR0 Op-Code Bit Definitions (Continued) Register Information CA terminating rank Notes: Tag Type OP CATR Read only OP[7] Definition Notes 0b: CA for this rank is not terminated 1b: CA for this rank is terminated 1. RZQI, if supported, will be set upon completion of MPC[ZQCAL START] command. (tZQCAL after MPC[ZQCAL START] command.) RZQI value will be lost after reset. 2. If ZQ is connected to VSSQ to set default calibration, OP[4:3] must be set to 01b. If ZQ is not connected to VSSQ, either OP[4:3] = 01b or OP[4:3] = 10b might indicate a ZQ pin assembly error. It is recommended that the assembly error be corrected. 3. In the case of possible assembly error, the device will default to factory trim settings for RON, and will ignore ZQ CALIBRATION commands. In either case, the device may not function as intended. 4. If the ZQ pin self-test returns OP[4:3] = 11b, the device has detected a resistor connected to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor meets the specified limits (that is, 240Ω  Table 20: MR1 Device Feature 1 (MA[7:0] = 01h) OP7 OP6 RD-PST OP5 OP4 nWR (for AP) OP3 OP2 RD-PRE WR-PRE OP1 OP0 BL Table 21: MR1 Op-Code Bit Definitions Feature Type OP BL Burst length Write only OP[1:0] Definition Notes 00b: BL = 16 sequential (default) 1, 5, 6 01b: BL= 32 sequential 10b: BL = 16 or 32 sequential (on-the-fly) 11b: Reserved WR-PRE Write preamble length Write only OP[2] RD-PRE Read preamble type Write only OP[3] nWR Write-recovery for autoprecharge command Write only OP[6:4] 0b: Reserved 1b: WR preamble = 2 × 5, 6 tCK 0b: RD preamble = Static (default) 3, 5, 6 1b: RD preamble = Toggle 000b: nWR = 6 (default) 001b: nWR = 10 010b: nWR = 16 011b: nWR = 20 100b: nWR = 24 101b: nWR = 30 110b: nWR = 34 111b: nWR = 40 44 2, 5, 6 200b: x32 LPDDR4 SDRAM Mode Registers Table 21: MR1 Op-Code Bit Definitions (Continued) Feature Type OP RD-PST Read postamble length Write only OP[7] Notes: Definition Notes 0b: RD postamble = 0.5 × tCK (default) 1b: RD postamble = 1.5 × 4, 5, 6 tCK 1. Burst length on-the-fly can be set to either BL = 16 or BL = 32 by setting the BL bit in the command operands. See the Command Truth Table. 2. The programmed value of nWR is the number of clock cycles the device uses to determine the starting point of an internal precharge after a write burst with auto precharge (AP) enabled. See Frequency Ranges for RL, WL, and nWR Settings table. 3. For READ operations, this bit must be set to select between a toggling preamble and a non-toggling preamble. (See the Preamble section.) 4. OP[7] provides an optional READ postamble with an additional rising and falling edge of DQS_t. The optional postamble cycle is provided for the benefit of certain memory controllers. 5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address. 6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, that is, the set point determined by the state of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation. 45 Table 22: Burst Sequence for Read C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16-Bit READ Operation V 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F V 0 1 0 0 4 5 6 7 8 9 A B C D E F 0 1 2 3 V 1 0 0 0 8 9 A B C D E F 0 1 2 3 4 5 6 7 V 1 1 0 0 C D E F 0 1 2 3 4 5 6 7 8 9 A B 32-Bit READ Operation 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0 0 1 0 0 4 5 6 7 8 9 A B C D E F 0 1 2 3 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 0 1 0 0 0 8 9 A B C D E F 0 1 2 3 4 5 6 7 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 D E F 0 1 2 3 4 5 6 7 8 9 A B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B 46 0 1 1 0 0 C 1 0 0 0 0 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0 1 2 3 4 5 6 7 8 9 A B C D E F 1 0 1 0 0 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 4 5 6 7 8 9 A B C D E F 0 1 2 3 1 1 0 0 0 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 1 1 0 0 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B C D E F 0 1 2 3 4 5 6 7 8 9 A B Notes: 1. C[1:0] are not present on the CA bus; they are implied to be zero. 2. The starting burst address is on 64-bit (4n) boundaries. Table 23: Burst Sequence for Write C4 C3 C2 C1 C0 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 A B C D E F 1 2 3 4 5 6 7 8 9 A B C D E F 16-Bit WRITE Operation V 0 0 0 0 0 32-Bit WRITE Operation 0 0 0 0 0 0 Notes: 1. 2. 3. 4. 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F C[1:0] are not present on the CA bus; they are implied to be zero. The starting burst address is on 256-bit (16n) boundaries for burst length 16. The starting burst address is on 512-bit (32n) boundaries for burst length 32. C[3:2] must be set to 0 for all WRITE operations. 200b: x32 LPDDR4 SDRAM Mode Registers 2 200b: x32 LPDDR4 SDRAM Mode Registers Table 24: MR2 Device Feature 2 (MA[7:0] = 02h) OP7 OP6 WR Lev WLS OP5 OP4 OP3 OP2 OP1 WL OP0 RL Table 25: MR2 Op-Code Bit Definitions Feature Type OP RL READ latency Writeonly OP[2:0] Definition Notes RL and nRTP for DBI-RD disabled (MR3 OP[6] = 0b) 1, 3, 4 000b: RL = 6, nRTP = 8 (default) 001b: RL = 10, nRTP = 8 010b: RL = 14, nRTP = 8 011b: RL = 20, nRTP = 8 100b: RL = 24, nRTP = 10 101b: RL = 28, nRTP = 12 110b: RL = 32, nRTP = 14 111b: RL = 36, nRTP = 16 RL and nRTP for DBI-RD enabled (MR3 OP[6] = 1b) 000b: RL = 6, nRTP = 8 001b: RL = 12,nRTP = 8 010b: RL = 16, nRTP = 8 011b: RL = 22, nRTP = 8 100b: RL = 28, nRTP = 10 101b: RL = 32, nRTP = 12 110b: RL = 36, nRTP = 14 111b: RL = 40, nRTP = 16 47 200b: x32 LPDDR4 SDRAM Mode Registers Table 25: MR2 Op-Code Bit Definitions (Continued) Feature Type OP WL WRITE latency Writeonly OP[5:3] Definition Notes WL set A (MR2 OP[6] = 0b) 1, 3, 4 000b: WL = 4 (default) 001b: WL = 6 010b: WL = 8 011b: WL = 10 100b: WL = 12 101b: WL = 14 110b: WL = 16 111b: WL = 18 WL set B (MR2 OP[6] = 1b) 000b: WL = 4 001b: WL = 8 010b: WL = 12 011b: WL = 18 100b: WL = 22 101b: WL = 26 110b: WL = 30 111b: WL = 34 WLS WRITE latency set Writeonly OP[6] WR Lev Write leveling Writeonly OP[7] Notes: 0b: Use WL set A (default) 1, 3, 4 1b: Use WL set B 0b: Disable write leveling (default) 2 1b: Enable write leveling 1. See Latency Code Frequency Table for allowable frequency ranges for RL/WL/nWR. 2. After an MRW command to set the write-leveling enable bit (OP[7] = 1b), the device remains in the MRW state until another MRW command clears the bit (OP[7] = 0b). No other commands are allowed until the write-leveling enable bit is cleared. 3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command this MR address, or read from with an MRR command to this address. 4. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, that is, the set point determined by the state of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation. 5. nRTP is valid for BL16 only. For BL32, the SDRAM will add 8 clocks to the nRTP value before starting a precharge. 48 200b: x32 LPDDR4 SDRAM Mode Registers Table 26: Frequency Ranges for RL, WL, nWR, and nRTP Settings READ Latency WRITE Latency No DBI w/DBI Set A Set B nWR nRTP Lower Frequency Limit (>) 6 6 4 4 6 8 10 266 10 12 6 8 10 8 266 533 14 16 8 12 16 8 533 800 20 22 10 18 20 8 800 1066 24 28 12 22 24 10 1066 1333 28 32 14 26 30 12 1333 1600 32 36 16 30 34 14 1600 1866 36 40 18 34 40 16 1866 2133 Notes: Upper Frequency Limit(≤ ≤) Units Notes MHz 1–6 1. The device should not be operated at a frequency above the upper frequency limit or below the lower frequency limit shown for each RL, WL, or nWR value. 2. DBI for READ operations is enabled in MR3 OPO[6]. When MR3 OP[6] = 0, then the "No DBI" column should be used for READ latency. When MR3 OP[6] = 1, then the "w/DBI" column should be used for READ latency. 3. WRITE latency set A and set B are determined by MR2 OP[6]. When MR2 OP[6] = 0, then WRITE latency set A should be used. When MR2 OP[6] = 1, then WRITE latency set B should be used. 4. The programmed value for nRTP is the number of clock cycles the device uses to determine the starting point of an internal PRECHARGE operation after a READ burst with AP (auto precharge) enabled . It is determined by RU(tRTP/tCK). 5. The programmed value of nWR is the number of clock cycles the device uses to determine the starting point of an internal PRECHARGE operation after a WRITE burst with AP (auto precharge) enabled. It is determined by RU(tWR/tCK). 6. nRTP shown in this table is valid for BL16 only. For BL32, the device will add 8 clocks to the nRTP value before starting a precharge. Table 27: MR3 I/O Configuration 1 (MA[7:0] = 03h) OP7 OP6 DBI-WR DBI-RD OP5 OP4 OP3 PDDS 49 OP2 OP1 OP0 PPRP WR-PST PU-CAL 200b: x32 LPDDR4 SDRAM Mode Registers Table 28: MR3 Op-Code Bit Definitions Feature OP Definition Notes PU-CAL (Pull-up calibration point) Type OP[0] 0b: VDDQ/2.5 1–4 WR-PST (WR postamble length) OP[1] 1b: VDDQ/3 (default) 0b: WR post-amble=0.5 × tCK (default) 2, 3, 5 1b: WR post-amble=1.5 × tCK PPRP (Post-package repair protection) OP[2] 0b: PPR protection disabled (default) 6 1b: PPR protection enabled PDDS (Pull-down drive strength) 000b: RFU 1, 2, 3 001b: RZQ/1 010b: RZQ/2 Write-only 011b: RZQ/3 OP[5:3] 100b: RZQ/4 101b: RZQ/5 110b:RZQ/6 (default) 111b: Reserved DBI-RD (DBI-read enable) OP[6] DBI-WR (DBI-write enable) OP[7] 0b: Disabled (default) 2, 3 1b: Enabled 0b: Disabled (default) 2, 3 1b: Enabled Notes: 1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Recalibration may be required as voltage and temperature vary. 2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1.The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be determined by the state of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. 4. For dual channel device, PU‐CAL (MR3‐OP[0]) must be set the same for both channels on a die. The SDRAM will read the value of only one register (Ch.A or Ch.B), vendor-specific, so both channels must be set the same. 5. Refer to the supplier data sheet for vender-specific function. 1.5 × tCK apply ≥ 1.6GHz clock. 6. If MR3 OP[2] is set to 1b, PPR protection mode is enabled. The PPR protection bit is a sticky bit and can only be set to 0b by a power on reset. MR4 OP[4] controls entry to PPR mode. If PPR protection is enabled then the DRAM will not allow writing of 1b to MR4 OP[4]. 50 200b: x32 LPDDR4 SDRAM Mode Registers Table 29: MR4 Device Temperature (MA[7:0] = 04h) OP7 OP6 TUF OP5 Thermal offset OP4 OP3 PPRE SR abort OP2 OP1 OP0 Refresh rate Table 30: MR4 Op-Code Bit Definitions Feature Refresh rate Type OP Read-only OP[2:0] Definition Notes 000b: SDRAM low temperature operating limit exceeded 001b: 4x refresh 1–4, 7–9 010b: 2x refresh 011b: 1x refresh (default) 100b: 0.5x refresh 101b: 0.25x refresh, no derating 110b: 0.25x refresh, with derating 111b: SDRAM high temperature operating limit exceeded SR abort (Self Refresh Abort) Write OP[3] PPRE (Post-package repair entry/exit) Write OP[4] Thermal Offset-Controller offset to TCSR (Vendor-specific function) Write 0b: Disable (default) 9 1b: Device dependent 0b: Exit PPR mode (default) 5, 9, 1b: Enter PPR mode (Reference MR25 OP[7:0] for available PPR resources) OP[6:5] 00b: No offset, 0~5°C gradient (default) 9 01b: 5°C offset, 5~10°C gradient 10b: 10°C offset, 10~15°C gradient 11b: Reserved TUF (Temperature update flag) Read-only OP7 0b: OP[2:0] No change in OP[2:0] since last MR4 read (default) 6–8 1b: Change in OP[2:0] since last MR4 read Notes: 1. The refresh rate for each MR4 OP[2:0] setting applies to tREFI, tREFIpb, and tREFW. MR4 OP[2:0] = 011b corresponds to a device temperature of 85°C. Other values require either a longer (2x, 4x) refresh interval at lower temperatures or a shorter (0.5x, 0.25x) refresh interval at higher temperatures. If MR4 OP[2] = 1b, the device temperature is greater than 85°C. 2. At higher temperatures (>85°C), AC timing derating may be required. If derating is required the device will set MR4 OP[2:0] = 110b. See derating timing requirements in the AC Timing section. 3. DRAM vendors may or may not report all of the possible settings over the operating temperature range of the device. Each vendor guarantees that their device will work at any temperature within the range using the refresh interval requested by their device. 4. The device may not operate properly when MR4 OP[2:0 ] = 000b or 111b. 5. Post‐package repair can be entered or exited by writing to MR4 OP[4]. 6. When MR4 OP[7] = 1b, the refresh rate reported in MR4 OP[2:0] has changed since the last MR4 read. A mode register read from MR4 will reset MR4 OP[7] to 0b. 7. MR4 OP[7] = 0b at power‐up. MR4 OP[2:0] bits are undefined at power‐up. 51 200b: x32 LPDDR4 SDRAM Mode Registers 8. See the Temperature Sensor section for information on the recommended frequency of reading MR4. 9. MR4 OP[6:3] can be written in this register. All other bits will be ignored by the device during an MRW command to this register. Table 31: MR5 Basic Configuration 1 (MA[7:0] = 05h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP1 OP0 OP1 OP0 Manufacturer ID Table 32: MR5 Op-Code Bit Definitions Feature Manufacturer ID Type OP Definition Read-only OP[7:0] 1111 1111b : Micron All others: Reserved Table 33: MR6 Basic Configuration 2 (MA[7:0] = 06h) OP7 OP6 OP5 OP4 OP3 OP2 Revision ID1 Note: 1. MR6 is vendor-specific. Table 34: MR6 Op-Code Bit Definitions Feature Revision ID1 Note: Type OP Definition Read-only OP[7:0] xxxx xxxxb: Revision ID1 1. MR6 is vendor-specific. Table 35: MR7 Basic Configuration 3 (MA[7:0] = 07h) OP7 OP6 OP5 OP4 OP3 OP2 Revision ID2 Table 36: MR7 Op-Code Bit Definitions Feature Revision ID2 Note: Type OP Definition Read-only OP[7:0] 1. MR7 is vendor-specific. 52 xxxx xxxxb: Revision ID2 200b: x32 LPDDR4 SDRAM Mode Registers Table 37: MR8 Basic Configuration 4 (MA[7:0] = 08h) OP7 OP6 OP5 OP4 I/O width OP3 OP2 OP1 Density OP0 Type Table 38: MR8 Op-Code Bit Definitions Feature Type Type OP Read-only OP[1:0] Definition 00b: S16 SDRAM (16n prefetch) All others: Reserved Density Read-only OP[5:2] 0000b: 4Gb per die (2Gb per channel) 0001b: 6Gb per die (3Gb per channel) 0010b: 8Gb per die (4Gb per channel) or 4Gb per die (4Gb per channel) 0011b: 12Gb per die (6Gb per channel) or 6Gb per die (6Gb per channel) 0100b: 16Gb per die (8Gb per channel) or 8Gb per die (8Gb per channel) 0101b: 24Gb per die (12Gb per channel) 0110b: 32Gb per die (16Gb per channel) All others: Reserved I/O width Read-only OP[7:6] 00b: x16/channel All others: Reserved Table 39: MR9 Test Mode (MA[7:0] = 09h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Vendor-specific test mode Table 40: MR9 Op-Code Definitions Feature Test mode Type OP Write-only OP[7:0] Definition 0000000b; Vendor-specific test mode disabled (default) Table 41: MR10 Calibration (MA[7:0] = 0Ah) OP7 OP6 OP5 OP4 OP3 RFU OP2 OP1 OP0 ZQ RESET 53 200b: x32 LPDDR4 SDRAM Mode Registers Table 42: MR10 Op-Code Bit Definitions Feature Type OP ZQ reset Write-only OP[0] Definition 0b: Normal operation (default) 1b: ZQ reset Notes: 1. See AC Timing table for calibration latency and timing. 2. If ZQ is connected to VDDQ through RZQ, either the ZQ CALIBRATION function or default calibration (via ZQ reset) is supported. If ZQ is connected to VSS, the device operates with default calibration and ZQ CALIBRATION commands are ignored. In both cases, the ZQ connection must not change after power is supplied to the device. Table 43: MR11 ODT Control (MA[7:0] = 0Bh) OP7 OP6 RFU OP5 OP4 OP3 CA ODT OP2 RFU OP1 OP0 DQ ODT Table 44: MR11 Op-Code Bit Definitions Notes 1-3 apply to entire table Feature Type DQ ODT DQ bus receiver on-dietermination Write-only OP OP[2:0] Definition 000b: Disable (default) 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU CA ODT CA bus receiver on-dietermination Write-only OP[6:4] 000b: Disable (default) 001b: RZQ/1 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU Notes: 1. All values are typical. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Re‐calibration may be required as voltage and temperature vary. 2. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 54 200b: x32 LPDDR4 SDRAM Mode Registers 3. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation. Table 45: MR12 Register Information (MA[7:0] = 0Ch) OP7 OP6 RFU VRCA OP5 OP4 OP3 OP2 OP1 OP0 VREF(CA) Table 46: MR12 Op-Code Bit Definitions Feature Type OP VREF(CA) VREF(CA) settings Read/ Write OP[5:0] VRCA VREF(CA) range Read/ Write OP[6] Notes: Data Notes 000000b–110010b: See VREF Settings Table 1–3, 5, 6 All others: Reserved 0b: VREF(CA) range[0] enabled 1, 2, 4, 5, 6 1b: VREF(CA) range[1] enabled (default) 1. This register controls the VREF(CA) levels for frequency set point[1:0]. Values from either VR(ca)[0] or VR(ca)[1] may be selected by setting MR12 OP[6] appropriately. 2. A read to MR12 places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ will be set to 0. See the MRR Operation section. 3. A write to MR12 OP[5:0] sets the internal VREF(CA) level for FSP[0] when MR13 OP[6] = 0b or sets the internal VREF(CA) level for FSP[1] when MR13 OP[6] = 1b. The time required for VREF(CA) to reach the set level depends on the step size from the current level to the new level. See the VREF(CA) training section. 4. A write to MR12 OP[6] switches the device between two internal VREF(CA) ranges. The range (range[0] or range[1]) must be selected when setting the VREF(CA) register. The value, once set, will be retained until overwritten or until the next power‐on or reset event. 5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. Table 47: MR13 Register Control (MA[7:0] = 0Dh) OP[7] OP[6] OP[5] OP[4] OP[3] OP[2] OP[1] OP[0] FSP-OP FSP-WR DMD RRO VRCG VRO RPT CBT 55 200b: x32 LPDDR4 SDRAM Mode Registers Table 48: MR13 Op-Code Bit Definition Feature CBT Command bus training Type OP Write-only OP[0] Definition 0b: Normal operation (default) Notes 1 1b: Command bus training mode enabled RPT Read preamble training OP[1] 0b: Disabled (default) VRO VREF output OP[2] 0b: Normal operation (default) VRCG VREF current generator OP[3] 0b: Normal operation (default) RRO Refresh rate option OP[4] DMD Data mask disable OP[5] FSP-WR Frequency set point write / read OP[6] FSP-OP Frequency set point operation mode OP[7] 1b: Read preamble training mode enabled 2 1b: Output the VREF(CA) and VREF(DQ) values on DQ bits 3 1b: Fast response (high current) mode 0b: Disable MR4 OP[2:0] (default) 4, 5 1b: Enable MR4 OP[2:0] 0b: DATA MASK operation enabled (default) 6 1b: DATA MASK operation disabled Notes: 0b: Frequency set point[0] (default) 7 1b: Frequency set point[1] 0b: Frequency set point[0] (default) 8 1b: Frequency set point[1] 1. A write to set OP[0]=1 causes the LPDDR4‐SDRAM to enter the Command Bus Training mode. When OP[0]=1 and CKE goes LOW, commands are ignored and the contents of CA[5:0] are mapped to the DQ bus. CKE must be brought HIGH before doing a MRW to clear this bit (OP[0]=0) and return to normal operation. See the Command Bus Training section for more information. 2. When set, the device will output the VREF(CA) and VREF(DQ) voltage on DQ pins. Only the "active" frequency set point, as defined by MR13 OP[7], will be output on the DQ pins. This function allows an external test system to measure the internal VREF levels. The DQ pins used for VREF output are vendor-specific. 3. When OP[3] = 1, the VREF circuit uses a high current mode to improve VREF settling time. 4. MR13 OP[4] RRO bit is valid only when MR0 OP[0] = 1. For LPDDR4‐SDRAM with MR0 OP[0] = 0, MR4 OP[2:0] bits are not dependent on MR13 OP[4]. 5. When OP[4] = 0, only 001b and 010b in MR4 OP[2:0] are disabled. LPDDR4‐SDRAM must report 011b instead of 001b or 010b in this case. Controller should follow the refresh mode reported by MR4 OP[2:0], regardless of RRO setting. TCSR function does not depend on RRO setting. 6. When enabled (OP[5] = 0b) data masking is enabled for the device. When disabled (OP[5] = 1b), the device will ignore any mask patterns issued during a MASKED WRITE command. See the Data Mask section for more information. 7. FSP‐WR determines which frequency set point registers are accessed with MRW and MRR commands for the following functions such as VREF(CA) setting, VREF(CA) range, VREF(DQ) setting, VREF(DQ) range. For more information, refer to Frequency Set Point section. 8. FSP‐OP determines which frequency set point register values are currently used to specify device operation for the following functions such as VREF(CA) setting, VREF(CA) range, VREF(DQ) setting, VREF(DQ) range. For more information, refer to Frequency Set Point section. 56 200b: x32 LPDDR4 SDRAM Mode Registers Table 49: Mode Register14 (MA[7:0] = 0Eh) OP[7] OP[6] RFU VRDQ OP[5] OP[4] OP[3] OP[2] OP[1] OP[0] VREF(DQ) Table 50: MR14 Op-Code Bit Definition Feature Type OP VREF(DQ) VREF(DQ) setting Read/ Write OP[5:0] VRDQ VREF(DQ) range Definition Notes 000000b–110010b: See VREF Settings Table 1–3, 5, 6 All others: Reserved OP[6] 0b: VREF(DQ) range[0] enabled 1, 2, 4–6 1b: VREF(DQ) range[1] enabled (default) Notes: 1. This register controls the VREF(DQ) levels for frequency set point[1:0]. Values from either VRDQ[vendor defined] or VRDQ[vendor defined] may be selected by setting OP[6] appropriately. 2. A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ will be set to 0. See the MRR Operation section. 3. A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6] = 0b, or sets FSP[1] when MR13 OP[6] = 1b. The time required for VREF(DQ) to reach the set level depends on the step size from the current level to the new level. See the VREF(DQ) training section. 4. A write to OP[6] switches the device between two internal VREF(DQ) ranges. The range (range[0] or range[1]) must be selected when setting the VREF(DQ) register. The value, once set, will be retained until overwritten, or until the next power‐on or reset event. 5. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP‐WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 6. There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP‐OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. 57 200b: x32 LPDDR4 SDRAM Mode Registers Table 51: VREF Setting for Range[0] and Range[1] Notes 1-3 apply to entire table Range[0] Values Range[1] Values VREF(CA) (% of VDD2 ) Function VREF Setting for MR12 and MR14 OP VREF(CA) (% of VDD2 ) VREF(DQ) (% of VDDQ ) VREF(DQ) (% of VDDQ ) OP[5:0] 000000b: 10.0% 011010b: 20.4% 000000b: 22.0% 011010b: 32.4% 000001b: 10.4% 011011b: 20.8% 000001b: 22.4% 011011b: 32.8% 000010b: 10.8% 011100b: 21.2% 000010b: 22.8% 011100b: 33.2% 000011b: 11.2% 011101b: 21.6% 000011b: 23.2% 011101b: 33.6% 000100b: 11.6% 011110b: 22.0% 000100b: 23.6% 011110b: 34.0% 000101b: 12.0% 011111b: 22.4% 000101b: 24.0% 011111b: 34.4% 000110b: 12.4% 100000b: 22.8% 000110b: 24.4% 100000b: 34.8% 000111b: 12.8% 100001b: 23.2% 000111b: 24.8% 100001b: 35.2% 001000b: 13.2% 100010b: 23.6% 001000b: 25.2% 100010b: 35.6% 001001b: 13.6% 100011b: 24.0% 001001b: 25.6% 100011b: 36.0% 001010b: 14.0% 100100b: 24.4% 001010b: 26.0% 100100b: 36.4% 001011b: 14.4% 100101b: 24.8% 001011b: 26.4% 100101b: 36.8% 001100b: 14.8% 100110b: 25.2% 001100b: 26.8% 100110b: 37.2% 001101b: 15.2% 100111b: 25.6% 001101b: 27.2% default 100111b: 37.6% 001110b: 15.6% 101000b: 26.0% 001110b: 27.6% 101000b: 38.0% 001111b: 16.0% 101001b: 26.4% 001111b: 28.0% 101001b: 38.4% 010000b: 16.4% 101010b: 26.8% 010000b: 28.4% 101010b: 38.8% 010001b: 16.8% 101011b: 27.2% 010001b: 28.8% 101011b: 39.2% 010010b: 17.2% 101100b: 27.6% 010010b: 29.2% 101100b: 39.6% 010011b: 17.6% 101101b: 28.0% 010011b: 29.6% 101101b: 40.0% 010100b: 18.0% 101110b: 28.4% 010100b: 30.0% 101110b: 40.4% 010101b: 18.4% 101111b: 28.8% 010101b: 30.4% 101111b: 40.8% 010110b: 18.8% 110000b: 29.2% 010110b: 30.8% 110000b: 41.2% 010111b: 19.2% 110001b: 29.6% 010111b: 31.2% 110001b: 41.6% 011000b: 19.6% 110010b: 30.0% 011000b: 31.6% 110010b: 42.0% 011001b: 20.0% All Others: Reserved 011001b: 32.0% All Others: Reserved Notes: 1. These values may be used for MR14 OP[5:0] and MR12 OP[5:0] to set the VREF(CA) or VREF(DQ) levels in the device. 2. The range may be selected in each of the MR14 or MR12 registers by setting OP[6] appropriately. 3. Each of the MR14 or MR12 registers represents either FSP[0] or FSP[1]. Two frequency set points each for CA and DQ are provided to allow for faster switching between terminated and un‐terminated operation or between different high‐frequency settings, which may use different terminations values. 58 200b: x32 LPDDR4 SDRAM Mode Registers Table 52: MR15 Register Information (MA[7:0] = 0Fh) OP[7] OP[6] OP[5] OP[4] OP[3] OP[2] OP[1] OP[0] Lower-byte invert register for DQ calibration Table 53: MR15 Op-code Bit Definition Feature Lower-byte invert for DQ calibration Type OP Definition Write-Only OP[7:0] Notes The following values may be written for any operand OP[7:0] and will be applied to the corresponding DQ locations DQ[7:0] within a byte lane 1–3 0b: Do not invert 1b: Invert the DQ calibration patterns in MR32 and MR40 Default value for OP[7:0] = 55h Notes: 1. This register will invert the DQ Calibration pattern found in MR32 and MR40 for any single DQ or any combination of DQ. Example: If MR15 OP[7:0] = 00010101b, then the DQ calibration patterns transmitted on DQ[7, 6, 5, 3, 1] will not be inverted, but the DQ calibration patterns transmitted on DQ[4, 2, 0] will be inverted. 2. DM[0] is not inverted and always transmits the "true" data contained in MR32 and MR40. 3. No data bus inversion (DBI) function is enacted during DQ read calibration, even if DBI is enabled in MR3-OP[6]. Table 54: MR15 Invert Register Pin Mapping PIN DQ0 DQ1 DQ2 DQ3 DMIO DQ4 DQ5 DQ6 DQ7 MR15 OP0 OP1 OP2 OP3 No invert OP4 OP5 OP6 OP7 Table 55: MR16 PASR Bank Mask (MA[7:0] = 010h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 PASR bank mask Table 56: MR16 Op-Code Bit Definitions Feature Bank[7:0] mask Type OP Write-only OP[7:0] Definition 0b: Bank refresh enabled (default) 1b: Bank refresh disabled OP[n] Bank Mask 8-Bank SDRAM 0 xxxxxxx1 Bank 0 1 xxxxxx1x Bank 1 59 OP0 200b: x32 LPDDR4 SDRAM Mode Registers OP[n] Bank Mask 8-Bank SDRAM 2 xxxxx1xx Bank 2 3 xxxx1xxx Bank 3 4 xxx1xxxx Bank 4 5 xx1xxxxx Bank 5 6 x1xxxxxx Bank 6 7 1xxxxxxx Bank 7 Notes: 1. When a mask bit is asserted (OP[n] = 1), refresh to that bank is disabled. 2. PASR bank masking is on a per-channel basis; the two channels on the die may have different bank masking. Table 57: MR17 PASR Segment Mask (MA[7:0] = 11h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 PASR segment mask Table 58: MR17 PASR Segment Mask Definitions Feature Segment[7:0] mask Type OP Write-only OP[7:0] Definition 0b: Segment refresh enabled (default) 1b: Segment refresh disabled Table 59: MR17 PASR Segment Mask Density (per channel) 2Gb 3Gb 4Gb 6Gb 8Gb 12Gb 16Gb R[13:11] R[14:12] R[14:12] R[15:13] R[15:13] TBD TBD 110b Not allowed 110b Segment OP Segment Mask 0 0 XXXXXXX1 000b 1 1 XXXXXX1X 001b 2 2 XXXXX1XX 010b 3 3 XXXX1XXX 011b 4 4 XXX1XXXX 100b 5 5 XX1XXXXX 6 6 X1XXXXXX 110b 7 7 1XXXXXXX 111b Notes: 101b Not allowed 110b 111b Not allowed 111b 111b 1. This table indicates the range of row addresses in each masked segment. "X" is “Don’t Care” for a particular segment. 2. PASR segment-masking is on a per-channel basis. The two channels on the die may have different segment masking. 3. For 3Gb, 6Gb, and 12Gb density per channel, OP[7:6] must always be LOW (= 00b). 60 200b: x32 LPDDR4 SDRAM Mode Registers Table 60: MR18 Register Information (MA[7:0]=12h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS oscillator count - LSB Table 61: MR18 LSB DQS Oscillator Count Notes 1–3 apply to entire table Function Type DQS oscillator count (WR training DQS oscillator) Read-only Notes: OP OP[7:0] Definition 0h–FFh LSB DRAM DQS oscillator count 1. MR18 reports the LSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ. 2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS oscillator count. 3. The value in this register is reset each time an MPC command is issued to start in the DQS oscillator counter. Table 62: MR19 Register Information (MA[7:0] = 13h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS oscillator count – MSB Table 63: MR19 DQS Oscillator Count Notes 1–3 apply to the entire table Function Type DQS oscillator count – MSB (WR training DQS oscillator) Read-only Notes: OP OP[7:0] Definition 0h–FFh MSB DRAM DQS oscillator count 1. MR19 reports the MSB bits of the DRAM DQS oscillator count. The DRAM DQS oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ. 2. Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS oscillator count. 3. A new MPC[START DQS OSCILLATOR]] should be issued to reset the contents of MR18/ MR19. 61 200b: x32 LPDDR4 SDRAM Mode Registers Table 64: MR20 Register Information (MA[7:0] = 14h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Upper-byte invert register for DQ calibration Table 65: MR20 Register Information Notes 1–3 apply to entire table Function Type Upper-byte invert for DQ calibration OP Write-only OP[7:0] Definition The following values may be written for any operand OP[7:0] and will be applied to the corresponding DQ locations DQ[15:8] within a byte lane 0b: Do not invert 1b: Invert the DQ calibration patterns in MR32 and MR40 Default value for OP[7:0] = 55h Notes: 1. This register will invert the DQ calibration pattern found in MR32 and MR40 for any single DQ or any combination of DQ. For example, if MR20 OP[7:0] = 00010101b, the DQ calibration patterns transmitted on DQ[15, 14, 13, 11, 9] will not be inverted, but the DQ calibration patterns transmitted on DQ[12, 10, 8] will be inverted. 2. DM[1] is not inverted and always transmits the true data contained in MR32 and MR40. 3. No data bus inversion (DBI) function is enacted during DQ read calibration, even if DBI is enabled in MR3 OP[6]. Table 66: MR20 Invert Register Pin Mapping Pin DQ8 DQ9 DQ10 DQ11 DMI1 DQ12 DQ13 DQ14 DQ15 MR20 OP0 OP1 OP2 OP3 No invert OP4 OP5 OP6 OP7 Table 67: MR21 Register Information (MA[7:0] = 15h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP2 OP1 OP0 RFU Table 68: MR22 Register Information (MA[7:0] = 16h) OP7 OP6 RFU OP5 OP4 OP3 ODTD-CA ODTE-CS ODTE-CK 62 SOC ODT 200b: x32 LPDDR4 SDRAM Mode Registers Table 69: MR22 Register Information Function Type OP Data Notes SOC ODT (controller ODT val- Write-only OP[2:0] 000b: Disable (default) ue for VOH calibration) 001b: RZQ/1 1, 2, 3 010b: RZQ/2 011b: RZQ/3 100b: RZQ/4 101b: RZQ/5 110b: RZQ/6 111b: RFU ODTE-CK (CK ODT enabled for non-terminating rank) Write-only OP[3] 2, 3, 4, 6, 8 1b: ODT-CK override enabled ODTE-CS (CS ODT enabled for Write-only non-terminating rank) OP[4] ODTD-CA (CA ODT termination disable) OP[5] Notes: 0b: ODT-CK override disabled (default) Write-only 0b: ODT-CS override disabled (default) 2, 3, 5, 6, 8 1b: ODT-CS override enabled 0b: CA ODT obeys ODT_CA bond pad (default) 2, 3, 6, 7, 8 1b: CA ODT disabled 1. All values are typical. 2. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command or read from with an MRR command to this address. 3. There are two physical registers assigned to each bit of this MR parameter: designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device and may be changed without affecting device operation. 4. When OP[3] = 1 the CK signals will be terminated to the value set by MR11 OP[6:4] regardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more devices but CK is not, enabling CK to terminate on all devices. 5. When OP[4] = 1 the CS signal will be terminated to the value set by MR11 OP[6:4] regardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more devices but CS is not, enabling CS to terminate on all devices. 6. For system configurations where the CK, CS, and CA signals are shared between packages, the package design should provide for the ODT_CA ball to be bonded on the system board outside of the memory package. This provides the necessary control of the ODT function for all die with shared command bus signals. 7. When OP[5] = 0, CA[5:0] will terminate when the ODT_CA bond pad is HIGH and MR11 OP[6:4] is valid and disable termination when ODT_CA is LOW or MR11 OP[6:4] is disabled. When OP[5] = 1, termination for CA[5:0] is disabled regardless of the state of the ODT_CA bond pad or MR11 OP[6:4]. 8. To ensure proper operation in a multi-rank configuration, when CA, CK or CS ODT is enabled via MR11 OP[6:4] and also via MR22 or ODT_CA pad setting, the rank providing ODT will continue to terminate the command bus in all DRAM states including Active, Self-refresh, Self-refresh Power-down, Active Power-down and Precharge Power-down. 63 200b: x32 LPDDR4 SDRAM Mode Registers Table 70: MR23 Register Information (MA[7:0] = 17h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS interval timer run-time setting Table 71: MR23 Register Information Notes 1–2 apply to entire table Function Type DQS interval timer runtime OP Write-only OP[7:0] Data 00000000b: Disabled (default) 00000001b: DQS timer stops automatically at the 16th clock after timer start 00000010b: DQS timer stops automatically at the 32nd clock after timer start 00000011b: DQS timer stops automatically at the 48th clock after timer start 00000100b: DQS timer stops automatically at the 64th clock after timer start --------- Through --------00111111b: DQS timer stops automatically at the (63 × 16)th clock after timer start 01XXXXXXb: DQS timer stops automatically at the 2048th clock after timer start 10XXXXXXb: DQS timer stops automatically at the 4096th clock after timer start 11XXXXXXb: DQS timer stops automatically at the 8192nd clock after timer start Notes: 1. MPC command with OP[6:0] = 1001101b (stop DQS Interval Oscillator) stops the DQS interval timer in the case of MR23 OP[7:0] = 00000000b. 2. MPC command with OP[6:0] = 1001101b (stop DQS Interval Oscillator) is illegal with valid nonzero values in MR23 OP[7:0]. Table 72: MR24 Register Information (MA[7:0] = 18h) OP7 TRR mode OP6 OP5 OP4 OP3 TRR mode BAn Unlimited MAC 64 OP2 OP1 MAC value OP0 200b: x32 LPDDR4 SDRAM Mode Registers Table 73: MR24 Register Information Function Type MAC value Read OP Data Notes OP[2:0] 000b: Unknown (OP[3] = 0) or Unlimited (OP[3]=1) 1,2 001b: 700K 010b: 600K 011b: 500K 100b: 400K 101b: 300K 110b: 200K 111b: Reserved Unlimited MAC Read OP[3] 0b: OP[2:0] defines the MAC value 1b: Unlimited MAC value TRR mode BAn Write 2, 3 OP[6:4] 000b: Bank 0 001b: Bank 1 010b: Bank 2 011b: Bank 3 100b: Bank 4 101b: Bank 5 110b: Bank 6 111b: Bank 7 TRR mode Write OP[7] 0b: Disabled (default) 1b: Enabled Notes: 1. Unknown means that the device is not tested for tMAC and pass/fail values are unknown. Unlimited means that there is no restriction on the number of activates between refresh windows. 2. There is no restriction to the number of activates. 3. MR24 OP[2:0] set to 000b. Table 74: MR25 Register Information (MA[7:0] = 19h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 Table 75: MR25 Register Information Function PPR resources Type OP Data Read-only OP[7:0] 0b: PPR resource is not available 1b: PPR resource is available Note: 1. When OP[n] = 0, there is no PPR resource available for that bank. When OP[n] = 1, there is a PPR resource available for that bank, and PPR can be initiated by the controller. 65 200b: x32 LPDDR4 SDRAM Mode Registers Table 76: MR26:31 Register Information (MA[7:0] = 1Ah–1Fh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP2 OP1 OP0 Reserved for future use Table 77: MR32 Register Information (MA[7:0] = 20h) OP7 OP6 OP5 OP4 OP3 DQ calibration pattern A (default = 5Ah) Table 78: MR32 Register Information Function Type OP Data Notes Return DQ calibration pattern Write-only OP[7:0] Xb: An MPC command issued with OP[6:0] = MR32 + MR40 1000011b causes the device to return the DQ calibration pattern contained in this register and (followed by) the contents of MR40. A default pattern 5Ah is loaded at power-up or reset, or the pattern may be overwritten with a MRW to this register. The contents of MR15 and MR20 will invert the MR32/MR40 data pattern for a given DQ (see MR15/MR20 for more information). Notes: 1, 2, 3 1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when DQ read calibration is initiated via an MPC command. The pattern is transmitted serially on each data lane and organized little endian such that the low-order bit in a byte is transmitted first. If the data pattern is 27H, the first bit transmitted is a 1 followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111. 2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins. 3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3 OP[6]. 4. No data bus inversion (DBI) function is enacted during DQ read calibration, even if DBI is enabled in MR3 OP[6]. Table 79: MR33:39 Register Information (MA[7:0] = 21h–27h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP3 OP2 OP1 OP0 Do not use Table 80: MR40 Register Information (MA[7:0] = 28h) OP7 OP6 OP5 OP4 DQ calibration pattern B (default = 3Ch) 66 200b: x32 LPDDR4 SDRAM Commands and Timing Table 81: MR40 Register Information Function Type OP Data Notes Return DQ calibration pattern Write-only OP[7:0] Xb: A default pattern 3Ch is loaded at power-up MR32 + MR40 or reset, or the pattern may be overwritten with a MRW to this register. See MR32 for more information. Notes: 1, 2, 3 1. The pattern contained in MR40 is concatenated to the end of MR32 and transmitted on DQ[15:0] and DMI[1:0] when DQ read calibration is initiated via an MPC command. The pattern is transmitted serially on each data lane and organized little endian such that the low-order bit in a byte is transmitted first. If the data pattern in MR40 is 27H, the first bit transmitted will be a 1, followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111. 2. MR15 and MR20 may be used to invert the MR32/MR40 data patterns on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins. 3. The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3 OP[6]. 4. No data bus inversion (DBI) function is enacted during DQ read calibration, even if DBI is enabled in MR3 OP[6]. Table 82: MR41:47 Register Information (MA[7:0] = 29h–2Fh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP2 OP1 OP0 Do not use Table 83: MR48:63 Register Information (MA[7:0] = 30h–3Fh) OP7 OP6 OP5 OP4 OP3 Reserved for future use Commands and Timing Commands transmitted on the CA bus are encoded into two parts and are latched on two consecutive rising edges of the clock. This is called 2-tick CA capture because each command requires two clock edges to latch and decode the entire command. Truth Tables Truth tables provide complementary information to the state diagram. They also clarify device behavior and applicable restrictions when considering the actual state of the banks. Unspecified operations and timings are illegal. To ensure proper operation after an illegal event, the device must be either reset by asserting the RESET_n command or powered down and then restarted using the specified initialization sequence before normal operation can continue. CKE signal has to be held HIGH when the commands listed in the command truth table input. 67 200b: x32 LPDDR4 SDRAM Truth Tables Table 84: Command Truth Table Commands are transmitted to the device across a six-lane interface and use CK, CKE, and CS to control the capture of transmitted data SDR CA Pins Command CS CA0 CA1 CA2 CA3 CA4 CA5 MRW-1 H L H H L L OP7 1 L MA0 MA1 MA2 MA3 MA4 MA5 2 H L H H L H OP6 1 L OP0 OP1 OP2 OP3 OP4 OP5 2 H L H H H L V 1 L MA0 MA1 MA2 MA3 MA4 MA5 2 REFRESH (all/per bank) H L L L H L AB 1 L BA0 BA1 BA2 V V V 2 ENTER SELF REFRESH H L L L H H V 1 ACTIVATE-1 H H L R12 R13 R14 R15 1 L BA0 BA1 BA2 R16 R10 R11 2 H H H R6 R7 R8 R9 1 L R0 R1 R2 R3 R4 R5 2 H L L H L L BL 1 L BA0 BA1 BA2 V C9 AP 2 EXIT SELF REFRESH H L L H L H V 1 MASK WRITE-1 H L L H H L BL 1 L BA0 BA1 BA2 V C9 AP 2 H L L H H H V 1 MRW-2 MRR-1 ACTIVATE-2 WRITE-1 RFU L V L RFU H H L L RFU H H L READ-1 CAS-2 (WRITE-2, MASKED WRITE-2, READ-2, MRR-2, MPC (except NOP) H L 1, 2, 12 1, 2, 3, 4 1, 2 1, 2, 3, 11 1, 11 1, 2, 3, 6, 7, 9 1, 2 1, 2, 3, 5, 6, 7, 9 1, 2 L V 2 1, 2 2 H H V V 2 1, 2 2 H L H L L L BL 1 L BA0 BA1 BA2 V C9 AP 2 H L H L L H C8 1 L C2 C3 C4 C5 C6 C7 2 68 1, 11 2 V L 1, 11 2 V L Notes 2 V L CK Edge 1, 2, 3, 6, 7, 9 1, 8, 9 200b: x32 LPDDR4 SDRAM Truth Tables Table 84: Command Truth Table (Continued) Commands are transmitted to the device across a six-lane interface and use CK, CKE, and CS to control the capture of transmitted data SDR CA Pins Command CS CA0 CA1 CA2 CA3 CA4 CA5 PRECHARGE (all/per bank) H L L L L H AB 1 L BA0 BA1 BA2 V V V 2 MPC (TRAIN, NOP) H L L L L L OP6 1 L OP0 OP1 OP2 OP3 OP4 OP5 2 DESELECT L Notes: X CK Edge 1 Notes 1, 2, 3, 4 1, 2, 13 1, 2 1. All commands except for DESELECT are two clock cycles and are defined by the current state of CS and CA[5:0] at the rising edge of the clock. DESELECT command is one clock cycle and is not latched by the device. 2. V = H or L (a defined logic level); X = "Don't Care," in which case CS, CK_t, CK_c, and CA[5:0] can be floated. 3. Bank addresses BA[2:0] determine which bank is to be operated upon. 4. AB HIGH during PRECHARGE or REFRESH commands indicate the command must be applied to all banks, and the bank addresses are "Don't Care." 5. MASK WRITE-1 command only supports BL16. For MASK WRITE-1 commands, CA5 must be driven LOW on the first rising clock cycle (R1). 6. AP HIGH during a WRITE-1, MASK WRITE-1, or READ-1 command indicates that an auto precharge will occur to the bank the command is operating on. AP LOW indicates that no auto precharge will occur and the bank will remain open upon completion of the command. 7. When enabled in the mode register, BL HIGH during a WRITE-1, MASK-WRITE-1, or READ-1 command indicates the burst length should be set on-the-fly to BL = 32; BL LOW during one of these commands indicates the burst length should be set on-the-fly to BL = 16. If on-the-fly burst length is not enabled in the mode register, this bit should be driven to a valid level and is ignored by the device. 8. For CAS-2 commands (WRITE-2, MASK WRITE-2, READ-2, MRR-2, or MPC (only WRITEFIFO, READ-FIFO, and READ DQ CALIBRATION)), C[1:0] are not transmitted on the CA [5:0] bus and are assumed to be zero. Note that for CAS-2 WRITE-2 or CAS-2 MASK WRITE-2 command, C[3:2] must be driven LOW. 9. WRITE-1, MASK-WRITE-1, READ-1, MODE REGISTER READ-1, or MPC (only WRITE-FIFO, READ-FIFO, and READ DQ CALIBRATION) command must be immediately followed by CAS-2 command consecutively without any other command in between. WRITE-1, MASK WRITE-1, READ-1, MRR-1, or MPC (only WRITE-FIFO, READ-FIFO, and READ DQ CALIBRATION) command must be issued first before issuing CAS-2 command. MPC (only START and STOP DQS OSCILLATOR, ZQCAL START and LATCH) commands do not require CAS-2 command; they require two additional DES or NOP commands consecutively before issuing any other commands. 10. The ACTIVATE-1 command must be followed by the ACTIVATE-2 command consecutively without any other command between them. The ACTIVATE-1 command must be issued prior to the ACTIVATE-2 command. When the ACTIVATE-1 command is issued, the ACTIVATE-2 command must be issued before issuing another ACTIVATE-1 command. 11. The MRW-1 command must be followed by the MRW-2 command consecutively without any other command between them. The MRW-1 command must be issued prior to the MRW-2 command. 69 200b: x32 LPDDR4 SDRAM ACTIVATE Command 12. The MRR-1 command must be followed by the CAS-2 command consecutively without any other commands between them. The MRR-1 command must be issued prior to the CAS-2 command. 13. The MPC command for READ or WRITE TRAINING operations must be followed by the CAS-2 command consecutively without any other commands between them. The MPC command must be issued prior to the CAS-2 command. ACTIVATE Command The ACTIVATE command must be executed before a READ or WRITE command can be issued. The ACTIVATE command is issued in two parts: The bank and upper-row addresses are entered with activate-1 and the lower-row addresses are entered with ACTIVATE-2. ACTIVATE-1 and ACTIVATE-2 are executed by strobing CS HIGH while setting CA[5:0] at valid levels (see Command table) at the rising edge of CK. The bank addresses (BA[2:0]) are used to select the desired bank. The row addresses (R[15:0]) are used to determine which row to activate in the selected bank. The ACTIVATE-2 command must be applied before any READ or WRITE operation can be executed. The device can accept a READ or WRITE command at time tRCD after the ACTIVATE-2 command is sent. After a bank has been activated, it must be precharged to close the active row before another ACTIVATE-2 command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive ACTIVATE-2 commands to the same bank is determined by the row cycle time of the device (tRC). The minimum time interval between ACTIVATE-2 commands to different banks is tRRD. Certain restrictions must be observed for bank ACTIVATE and REFpb operations. • Four-activate window (tFAW): No more than 4 banks may be activated (or refreshed, in the case of REFpb) per channel in a rolling tFAW window. Convert to clocks by dividing tFAW[ns] by tCK[ns] and rounding up to the next integer value. As an example of the rolling window, if RU[(tFAW/tCK)] is 64 clocks, and an ACTIVATE command is issued on clock N, no more than three additional ACTIVATE commands may be issued between clock N + 1 and N + 63. REFpb also counts as bank activation for the purposes of tFAW. • 8-bank per channel, precharge all banks (AB) allowance: tRP for a PRECHARGE ALL BANKS command for an 8-bank device must equal tRPab, which is greater than tRPpb. 70 200b: x32 LPDDR4 SDRAM Read and Write Access Modes Figure 14: ACTIVATE Command T0 T1 T2 T3 Ta0 RA RA BA0 RA RA RA Ta1 Ta2 Ta3 RA RA Tb0 Tb1 Tb2 Tb3 Valid BA0 CA CA Tc0 Tc1 Td0 Td1 Td2 Td3 RA RA Td4 Td5 CK_c CK_t CKE CS CA RA BA1 RA BA0 Valid RA BA0 tRP tRRD tRCD Command ACTIVATE-1 ACTIVATE-2 DES ACTIVATE-1 ACTIVATE-2 CAS2 READ1 DES DES PRECHARGE per bank DES DES ACTIVATE-2 ACTIVATE-1 DES tRAS tRC Don’t Care 1. A PRECHARGE command uses tRPab timing for all-bank precharge and tRPpb timing for single-bank precharge. In this figure, tRP is used to denote either all-bank precharge or a single-bank precharge. tCCD = MIN, 1.5nCK postamble, 533 MHz < clock frequency ≤ 800 MHz, ODT worst timing case. Note: Figure 15: tFAW Timing T0 T1 T2 T3 Ta0 RA RA BA0 RA RA RA Ta1 Ta2 Ta3 RA RA Tb0 Tb1 Tb2 Tb3 RA BA2 RA RA Tc0 Tc1 Tc2 Tc3 RA RA Tc4 Td0 Td1 Td2 Td3 Td4 RA RA BA4 RA RA CK_c CK_t CKE CS CA Command ACTIVATE-1 ACTIVATE-2 DES RA BA1 ACTIVATE-1 ACTIVATE-2 RA DES tRRD ACTIVATE-1 ACTIVATE-2 RA DES RA BA3 ACTIVATE-1 ACTIVATE-2 DES DES ACTIVATE-1 ACTIVATE-2 tRRD tRRD t FAW Don’t Care Note: 1. REFpb may be substituted for one of the ACTIVATE commands for the purposes of tFAW. Read and Write Access Modes After a bank has been activated, a READ or WRITE command can be executed. This is accomplished by asserting CKE asynchronously, with CS and CA[5:0] set to the proper state (see Command Truth Table) on the rising edge of CK. The device provides a fast column access operation. A single READ or WRITE command will initiate a burst READ or WRITE operation, where data is transferred to/from the device on successive clock cycles. Burst interrupts are not allowed; however, the optimal burst length may be set on-the-fly (see Command Truth Table). 71 200b: x32 LPDDR4 SDRAM Preamble and Postamble Preamble and Postamble The DQS strobe for the device requires a preamble prior to the first latching edge (the rising edge of DQS_t with data valid), and it requires a postamble after the last latching edge. The preamble and postamble options are set via MODE REGISTER WRITE commands. The read preamble is two tCK in length and is either static or has one clock toggle before the first latching edge. The read preamble option is enabled via MRW to MR1 OP[3] (0 = Static; 1 = Toggle). The read postamble has a programmable option to extend the postamble by 1nCK (tRPSTE). The extended postamble option is enabled via MRW to MR1 OP[7] (0 = 0.5nCK; 1 = 1.5nCK). Figure 16: DQS Read Preamble and Postamble – Toggling Preamble and 0.5nCK Postamble T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command RD-1 CAS-2 RL tDQSCK tRPRE DQS_c DQS_t tDQSQ DQ DMI tRPST DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15 Notes: 1. BL = 16, Preamble = Toggling, Postamble = 0.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tRPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE. 72 200b: x32 LPDDR4 SDRAM Preamble and Postamble Figure 17: DQS Read Preamble and Postamble – Static Preamble and 1.5nCK Postamble T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command CAS-2 RD-1 tDQSCK RL tRPRE DQS_c DQS_t tRPSTE tDQSQ DQ DMI DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15 Notes: 1. BL = 16, Preamble = Static, Postamble = 1.5nCK (extended). 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tRPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tRPRE. Figure 18: DQS Write Preamble and Postamble – 0.5nCK Postamble T0 T1 T2 T3 Valid Valid Valid Valid T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CKE CS CA Command WRITE-1 CAS-2 WL tDQSS t WPRE t WPST DQS_c DQS_t BL/2 tDQS2DQ DQ DMI DIN n0 DIN n1 DIN n2 DIN n3 DIN n8 DIN n9 DIN n10 DIN n11 DIN n12 DIN n13 DIN n14 DIN n15 Don’t Care Notes: 1. BL = 16, Postamble = 0.5nCK. 2. DQS and DQ terminated VSSQ. 73 200b: x32 LPDDR4 SDRAM Preamble and Postamble 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tWPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE. Figure 19: DQS Write Preamble and Postamble – 1.5nCK Postamble T0 T1 T2 T3 Valid Valid Valid Valid T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CKE CS CA Command WRITE-1 CAS-2 WL tDQSS t t WPST WPRE DQS_c DQS_t BL/2 tDQS2DQ DQ DMI DIN n0 DIN n1 DIN n2 DIN n3 DIN n8 DIN n9 DIN n10 DIN n11 DIN n12 DIN n13 DIN n14 DIN n15 Don’t Care Notes: 1. BL = 16, Postamble = 1.5nCK. 2. DQS and DQ terminated VSSQ. 3. DQS_t/DQS_c is "Don’t Care" prior to the start of tWPRE. No transition of DQS is implied, as DQS_t/DQS_c can be HIGH, LOW, or High-Z prior to tWPRE. 74 200b: x32 LPDDR4 SDRAM Burst READ Operation Burst READ Operation A burst READ command is initiated with CKE, CS, and CA[5:0] asserted to the proper state on the rising edge of CK, as defined by the Command Truth Table. The command address bus inputs determine the starting column address for the burst. The two loworder address bits are not transmitted on the CA bus and are implied to be 0; therefore, the starting burst address is always a multiple of four (that is, 0x0, 0x4, 0x8, 0xC). The READ latency (RL) is defined from the last rising edge of the clock that completes a READ command (for example, the second rising edge of the CAS-2 command) to the rising edge of the clock from which the tDQSCK delay is measured. The first valid data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of clock that completes a READ command. The data strobe output is driven tRPRE before the first valid rising strobe edge. The first data bit of the burst is synchronized with the first valid (post-preamble) rising edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge-aligned with the data strobe. At the end of a burst, the DQS signals are driven for another half cycle postamble, or for a 1.5-cycle postamble if the programmable postamble bit is set in the mode register. The RL is programmed in the mode registers. Pin timings for the data strobe are measured relative to the cross-point of DQS_t and DQS_c. Figure 20: Burst Read Timing T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T5 T6 T7 T15 T16 T17 T18 T19 BL BA0, CA, AP CAm CAm T20 T21 T22 T23 DES DES DES T33 T34 T35 T36 T41 T42 T43 T44 DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES DES t DES DES READ-1 CAS-2 DES CCD = 16 RL = 14 RL = 14 t DQSCK t DQSCK BL/2 = 8 BL/2 = 16 t t RPST RPRE DQS_c DQS_t tDQSQ tDQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n7 n26 n27 n28 n29 n30 n31 m0 m1 m10 m11 m12 m13 m14 m15 n1 n2 n6 n0 n3 n4 n5 DQ DMI Don’t Care Notes: 1. BL = 32 for column n, BL = 16 for column m, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 75 200b: x32 LPDDR4 SDRAM Burst READ Operation Figure 21: Burst Read Followed by Burst Write or Burst Mask Write T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 T5 Ta0 Ta1 Ta2 BL BA0, CA, AP Ta3 Ta4 CA CA Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 DES DES DES DES DES DES Tb6 Tb7 Tc0 Tc1 DES DES DES DES Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 DES DES CK_c CK_t CS CA READ-1 Command CAS-2 DES WR-1/MWR-1 DES DES CAS-2 RL + RU( tDQSCK(MAX)/ tCK) + BL/2 + RD( tRPST) - WL + tWPRE WL t DQSCK RL t DES DES DES DES t DQSS BL/2 = 8 t RPRE WPRE DQS_c DQS_t tDQSQ DQ DMI tDQS2DQ tRPST DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n9 n10 n11 n12 n13 n14 n15 DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n9 n10 n11 n12 n13 n14 n15 n0 Don’t Care 1. BL=16, Read preamble = Toggle, Read postamble = 0.5nCK, Write preamble = 2nCK, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DOUT n = data-out from column n and DIN n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Notes: Figure 22: Seamless Burst Read T0 T1 T2 T3 Ta0 Ta1 BL BA0, CA, AP CAn CAn BL BA0, CA, AP Ta2 Ta3 CAm CAm Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 DES DES DES Tc2 Tc3 Td0 Td1 Td2 Td3 Te0 Te1 DES DES DES DES DES Te2 Te3 CK_c CK_t CS CA Command READ-1 CAS-2 DES CAS-2 READ-1 BL DES BA1, CA, AP CAn READ-1 CAn CAS-2 DES DES DES DES t DQSCK RL t DQSCK RL RL DES t DQSCK t RPRE DQS_c DQS_t tDQSQ DQ DMI tDQSQ tDQSQ tRPST DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n15 n10 n11 n12 n13 n14 n0 n1 n10 n11 n12 n13 n14 n15 m0 m1 m10 m11 m12 m13 m14 m15 n0 n1 Bank 0 Bank 1 Don’t Care Notes: 1. BL = 16, tCCD = 8, Preamble = Toggle, Postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 76 200b: x32 LPDDR4 SDRAM Burst READ Operation Read Timing Figure 23: Read Timing T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command RD-1 CAS-2 t HZ(DQS) t RL t DQSCK LZ(DQS) t RPRE DQS_c DQS_t t DQSQ t RPST t HZ(DQ) t LZ(DQ) DQ DMI DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n10 n11 n12 n13 n14 n15 Notes: 1. 2. 3. 4. BL = 16, Preamble = Toggling, Postamble = 0.5nCK. DQS, DQ, and DMI terminated VSSQ. Output driver does not turn on before an endpoint of tLZ(DQS) and tLZ(DQ). Output driver does not turn off before an endpoint of tHZ(DQS) and tHZ(DQ). tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ). This section shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single ended. 77 200b: x32 LPDDR4 SDRAM Burst READ Operation tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) Figure 24: tLZ(DQS) Method for Calculating Transitions and Endpoint CK_t – CK_c crossing at the second CAS-2 of READ command CK_t CK_c tLZ(DQS) DQS_c VOH 0.5 x VOH VSW2 VSW1 End point: Extrapolated point 0V Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohm, VOH = VDDQ/3. 2. Termination condition for DQS_t and DQS_C = 50 ohm to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. Figure 25: tHZ(DQS) Method for Calculating Transitions and Endpoint CK_t – CK_c crossing at the second CAS-2 of READ command CK_t CK_c tHZ(DQS) End point: Extrapolated point VOH VSW2 0.5 x VOH VSW1 DQS_c 0V Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohm, VOH = VDDQ/3. 2. Termination condition for DQS_t and DQS_C = 50 ohm to VSSQ. 78 200b: x32 LPDDR4 SDRAM Burst READ Operation 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. Table 85: Reference Voltage for tLZ(DQS), tHZ(DQS) Timing Measurements Measured Parameter Symbol Vsw1 Vsw2 Unit DQS_c Low-Z time from CK_t, CK_c tLZ(DQS) 0.4 × VOH 0.6 × VOH V DQS_c High-Z time from CK_t, CK_c tHZ(DQS) 0.4 × VOH 0.6 × VOH Measured Parameter tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) Figure 26: tLZ(DQ) Method for Calculating Transitions and Endpoint CK_t – CK_c crossing at the second CAS-2 of READ command CK_t CK_c t LZ(DQ) DQs VOH 0.5 x VOH VSW2 VSW1 End point: Extrapolated point 0V Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohm, VOH = VDDQ/3. 2. Termination condition for DQ and DMI = 50 ohm to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. 79 200b: x32 LPDDR4 SDRAM Burst READ Operation Figure 27: tHZ(DQ) Method for Calculating Transitions and Endpoint CK_t – CK_c crossing at the second CAS-2 of READ command CK_t CK_c tHZ(DQ) End point: Extrapolated point VOH VSW2 0.5 x VOH VSW1 DQs 0V Notes: 1. Conditions for calibration: Pull down driver RON = 40 ohm, VOH = VDDQ/3. 2. Termination condition for DQ and DMI = 50 ohm to VSSQ. 3. The VOH level depends on MR22 OP[2:0] and MR3 OP[0] settings as well as device tolerances. Use the actual VOH value for tHZ and tLZ measurements. Table 86: Reference Voltage for tLZ(DQ), tHZ(DQ) Timing Measurements Measured Parameter Symbol Vsw1 Vsw2 Unit DQ Low-Z time from CK_t, CK_c tLZ(DQ) 0.4 × VOH 0.6 × VOH V DQ High-Z time from CK_t, CK_c tHZ(DQ) 0.4 × VOH 0.6 × VOH Measured Parameter 80 200b: x32 LPDDR4 SDRAM Burst WRITE Operation Burst WRITE Operation A burst WRITE command is initiated with CKE, CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Command Truth Table. Column addresses C[3:2] should be driven LOW for burst WRITE commands, and column addresses C[1:0] are not transmitted on the CA bus and are assumed to be zero so that the starting column burst address is always aligned with a 32-byte boundary. The WRITE latency (WL) is defined from the last rising edge of the clock that completes a WRITE command (for example, the second rising edge of the CAS-2 command) to the rising edge of the clock from which tDQSS is measured. The first valid latching edge of DQS must be driven WL × t CK + tDQSS after the rising edge of clock that completes a WRITE command. The device uses an unmatched DQS DQ path for lower power, so the DQS strobe must arrive at the SDRAM ball prior to the DQ signal by tDQS2DQ. The DQS strobe output must be driven tWPRE before the first valid rising strobe edge. The tWPRE preamble is required to be 2 × tCK at any speed ranges. The DQS strobe must be trained to arrive at the DQ pad latch center-aligned with the DQ data. The DQ data must be held for TdiVW, and the DQS must be periodically trained to stay roughly centered in the TdiVW. Burst data is captured by the SDRAM on successive edges of DQS until the 16- or 32-bit data burst is complete. The DQS strobe must remain active (toggling) for tWPST (write postamble) after the completion of the burst WRITE. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank can be issued. Signal input timings are measured relative to the cross point of DQS_t and DQS_c. 81 200b: x32 LPDDR4 SDRAM Burst WRITE Operation Figure 28: Burst WRITE Operation T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Valid BA0 Tc3 Tc4 Td0 Td1 Td2 Td3 Tb4 Td5 RA BA0, RA RA RA CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES DES DES DES WL DES DES DES DES DES DES DES tWPRE PRECHARGE tWR BL/2 + 1 Clock tDQSS DES DES DES DES DES ACT-1 ACT-2 tRP (MIN) tDSH DQS_c tDSS tWPST DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n5 n12 n13 n14 n15 DQ tDQSS (Nominal) tWPRE DQS_c DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n11 n12 n13 n14 n15 tDQSS (MAX) DQ tWPRE DQS_c DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n11 n12 n13 n14 n15 DQ Don’t Care Notes: 1. 2. 3. 4. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. DIN n = data-in to column n. tWR starts at the rising edge of CK after the last latching edge of DQS. DES commands are shown for ease of illustration; other commands may be valid at these times. 82 200b: x32 LPDDR4 SDRAM Burst WRITE Operation Figure 29: Burst Write Followed by Burst Read T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 BL BA0, CA, AP CA CA Tc7 Tc8 Tc9 Tc10 DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES DES DES DES WL DES DES DES DES DES DES DES tWPRE DES DES READ-1 tWTR BL/2 + 1 Clock tDQSS DES CAS-2 RL (MIN) tDSH tDSS tWPST DQS_c DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n5 n12 n13 n14 n15 DQ Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. The minimum number of clock cycles from the burst WRITE command to the burst READ command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)]. t 4. WTR starts at the rising edge of CK after the last latching edge of DQS. 5. DES commands are shown for ease of illustration; other commands may be valid at these times. 83 200b: x32 LPDDR4 SDRAM Burst WRITE Operation Write Timing Figure 30: Write Timing T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 DES DES DES DES DES DES DES DES Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 DES DES DES DES DES DES CK_c CK_t CS CA Command CAS-2 WRITE-1 DES WL tDQSS tDQSS tWPRE (MIN) (MIN) tDSH tDSS tWPST DQS_c DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n5 n12 n13 n14 n15 DQ tDQSS tDQSS (Nominal) (Nominal) tDSH tWPRE tDSS DQS_c DQS_t tDQS2DQ DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n11 n12 n13 n14 n15 DQ tDQSS tDQSS (MAX) (MAX) tWPRE tDSH tDSS DQS_c DQS_t tDQS2DQ tDQSH tDQSL DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN n0 n1 n2 n3 n4 n11 n12 n13 n14 n15 DQ Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n = data-in to column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 84 200b: x32 LPDDR4 SDRAM Burst WRITE Operation tWPRE Calculation for ATE (Automatic Test Equipment) Figure 31: Method for Calculating tWPRE Transitions and Endpoints CK_t Vref(CA) CK_c Resulting differential signal relevant for tWPRE specification Vsw2 Vsw1 DQS_t - DQS_c 0V  Begin point: Extrapolated point tWPRE Note: 1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohm to VSSQ. Table 87: Method for Calculating tWPRE Transitions and Endpoints Measured Parameter Measured Parameter Symbol Vsw1 Vsw2 Unit tWPRE VIHL_AC × 0.3 VIHL_AC × 0.7 V DQS_t, DQS_c differential write preamble tWPST Calculation for ATE (Automatic Test Equipment) Figure 32: Method for Calculating tWPST Transitions and Endpoints CK_t Vref(CA) CK_c Resulting differential signal relevant for tWPST specification 0V Vsw2 Vsw1 DQS_t - DQS_c tWPST Notes: End point: Extrapolated point 1. Termination condition for DQS_t, DQS_c, DQ, and DMI = 50 ohm to VSSQ. 2. Write postamble: 0.5tCK 3. The method for calculating differential pulse widths for 1.5tCK postamble is same as 0.5tCK postamble. 85 200b: x32 LPDDR4 SDRAM MASK WRITE Operation Table 88: Reference Voltage for tWPST Timing Measurements Measured Parameter Measured Parameter Symbol Vsw1 Vsw2 Unit tWPST –(VIHL_AC × 0.7) –(VIHL_AC × 0.3) V DQS_t, DQS_c differential write postamble MASK WRITE Operation The device requires that WRITE operations that include a byte mask anywhere in the burst sequence must use the MASK WRITE command. This allows the device to implement efficient data protection schemes based on larger data blocks. The MASK WRITE-1 command is used to begin the operation, followed by a CAS-2 command. A MASKED WRITE command to the same bank cannot be issued until tCCDMW later, to allow the device to finish the internal READ-MODIFY-WRITE operation. One datamask-invert (DMI) pin is provided per byte lane, and the data-mask-invert timings match data bit (DQ) timing. See Data Mask Invert for more information on the use of the DMI signal. Figure 33: MASK WRITE Command – Same Bank T0 T1 T2 T3 BL BA0, CA, AP CA CA T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 BL BA0, CA, AP Tc5 Tc6 CA CA Tc7 Tc8 Tc9 Tc10 DES DES DES DES CK_c CK_t CS CA Command MASK WRITE-1 CAS-2 DES DES DES DES DES DES DES DES DES DES DES DES tCCDMW WL DES DES DES MASK WRITE-1 CAS-2 WL tDQSS(MIN) t tWPRE WPST DQS_c DQS_t tDQS2DQ DIN n0 DQ DMI DIN DIN n1 n2 DIN DIN n3 n4 DIN DIN DIN DIN n5 n12 n13 n14 DIN n15 Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. 2. DIN n = data-in to column n. 3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16-bit wide data for MASKED WRITE operation. 4. DES commands are shown for ease of illustration; other commands may be valid at these time. 86 200b: x32 LPDDR4 SDRAM MASK WRITE Operation Figure 34: MASK WRITE Command – Different Bank T0 T1 T2 T3 T8 T9 BL BA0, CA, AP CA CA BL BA0, CA, AP T10 T11 CA CA T16 T17 T18 T19 T24 T25 T26 T27 T32 T33 T34 T35 BL BA0, CA, AP CA CA BL BA0, CA, AP CA CA BL BA0, CA, AP CA CA T36 T37 T38 DES DES DES CK_c CK_t CS CA Command MASK WRITE-1 CAS-2 MASK WRITE-1 DES CAS-2 DES MASK WRITE-1 tCCD DES CAS-2 MASK WRITE-1 tCCD DES CAS-2 tCCD MASK WRITE-1 CAS-2 tCCD tCCDMW WL tDQSS tWPRE DQS_c DQS_t tDQS2DQ DQ DMI DIN n0 DIN n1 DIN n2 DIN DIN n3 n10 DIN DIN DIN DIN DIN n11 n12 n13 n14 n15 DIN n0 DIN DIN n1 n2 DIN DIN n3 n10 DIN DIN n11 n12 DIN DIN DIN n13 n14 n15 DIN n0 DIN n1 DIN DIN n2 n10 DIN DIN n11 n12 DIN DIN DIN n13 n14 n15 DIN n0 DIN n1 DIN n2 DIN DIN n3 n4 DIN n5 DIN n6 DIN DIN n8 n7 Don’t Care Notes: 1. BL = 16, DQ/DQS/DMI: VSSQ termination. 2. DIN n = data-in to column n. 3. Mask-write supports only BL16 operations. For BL32 configuration, the system needs to insert only 16-bit wide data for MASKED WRITE operation. 4. DES commands are shown for ease of illustration; other commands may be valid at these time. 87 200b: x32 LPDDR4 SDRAM MASK WRITE Operation Mask Write Timing Constraints for BL16 Table 89: Same Bank (ODT Disabled) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE Illegal RU(tRCD/tCK) RU(tRCD/tCK) RU(tRCD/tCK) RU(tRAS/tCK) READ (with BL = 16) Illegal 81 RL + RL + RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/ tCK) + BL/2 - WL + tCK) + BL/2 - WL + tWPRE + RD( tRPST) tWPRE + RD( tRPST) BL/2 + MAX{(8,RU(tRTP/ tCK)} - 8 READ (with BL = 32) Illegal 162 RL + RL + RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/ tCK) + BL/2 - WL + tCK) + BL/2 - WL + tWPRE + RD( tRPST) tWPRE + RD( tRPST) BL/2 + MAX{(8,RU(tRTP/ tCK)} - 8 WRITE (with BL = 16) Illegal WL + 1+ BL/2 + RU(tWTR/tCK) 81 WRITE (with BL = 32) Illegal WL + 1 + BL/2 + RU(tWTR/tCK) 162 MASK WRITE Illegal WL + 1 + BL/2 + RU(tWTR/tCK) tCCD tCCDMW3 WL + 1 + BL/2 + RU(tWR/tCK) PRECHARGE RU(tRP/tCK), RU(tRPab/tCK) Illegal Illegal Illegal 4 ACTIVE Notes: 1. 2. 3. 4. tCCDMW3 tCCDMW + 84 WL + 1 + BL/2 + RU(tWR/tCK) WL + 1 + BL/2 + RU(tWR/tCK) In the case of BL = 16, tCCD is 8 × tCK. In the case of BL = 32, tCCD is 16 × tCK. tCCDMW = 32 × tCK (4 × tCCD at BL = 16). WRITE with BL = 32 operation is 8 × tCK longer than BL = 16. Table 90: Different Bank (ODT Disabled) Next CMD Current CMD ACTIVE READ (with BL = 16) ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE RU(tRRD/tCK) 4 4 4 22 4 81 RL + RL + 22 RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/ tCK) + BL/2 - WL + tCK) + BL/2 - WL + + RD( tRPST) tWPRE + RD( tRPST) tWPRE READ (with BL = 32) 4 162 RL + RL + RU(tDQSCK(MAX)/ RU(tDQSCK(MAX)/ tCK) 22 + BL/2 - WL + tCK) + BL/2 - WL + + RD( tRPST) tWPRE + RD( tRPST) tWPRE WRITE (with BL = 16) 4 WL + 1+ BL/2 + RU(tWTR/tCK) 81 81 22 WRITE (with BL = 32) 4 WL + 1 + BL/2 + RU(tWTR/tCK) 162 162 22 MASK WRITE 4 WL + 1 + BL/2 + RU(tWTR/tCK) 81 81 22 88 200b: x32 LPDDR4 SDRAM MASK WRITE Operation Table 90: Different Bank (ODT Disabled) (Continued) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE 4 4 4 4 4 PRECHARGE Notes: 1. In the case of BL = 16, tCCD is 8 × tCK 2. In the case of BL = 32, tCCD is 16 × tCK Table 91: Same Bank (ODT Enabled) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE ACTIVE Illegal RU(tRCD/tCK) RU(tRCD/tCK) RU(tRCD/tCK) RU(tRAS/tCK) READ (with BL = 16) Illegal 81 RL + RU( RL + RU( BL/2 + MAX{(8,RU(tRTP/ tCK)} - 8 tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK) + BL/2 + RD( tRPST) + BL/2 + RD( tRPST) - ODTLon - RD( - ODTLon - RD( tODTon(MIN)/ tCK) tODTon(MIN)/ tCK) READ (with BL = 32) 162 Illegal RL + RU( RL + RU( tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK) + BL/2 + RD( tRPST) + BL/2 + RD( tRPST) - ODTLon - RD( - ODTLon - RD( tODTon(MIN)/ tCK) tODTon(MIN)/ tCK) WRITE (with BL = 16) Illegal WL + 1+ BL/2 + RU(tWTR/tCK) 81 WRITE (with BL = 32) Illegal WL + 1 + BL/2 + RU(tWTR/tCK) 162 MASK WRITE Illegal WL + 1 + BL/2 + RU(tWTR/tCK) tCCD tCCDMW3 WL + 1 + BL/2 + RU(tWR/tCK) PRECHARGE RU(tRP/tCK), RU(tRPab/tCK) Illegal Illegal Illegal 4 Notes: 1. 2. 3. 4. tCCDMW3 BL/2 + MAX{(8,RU(tRTP/ tCK)} - 8 tCCDMW + 84 WL + 1 + BL/2 + RU(tWR/tCK) WL + 1 + BL/2 + RU(tWR/tCK) In the case of BL = 16, tCCD is 8 × tCK. In the case of BL = 32, tCCD is 16 × tCK. tCCDMW = 32 × tCK (4 × tCCD at BL = 16). WRITE with BL = 32 operation is 8 × tCK longer than BL = 16. Table 92: Different Bank (ODT Enabled) Next CMD Current CMD ACTIVE READ (with BL = 16) ACTIVE READ (BL = 16 or 32) WRITE (BL = 16 or 32) MASK WRITE PRECHARGE RU(tRRD/tCK) 4 4 4 22 4 81 RL + RU( RL + RU( 22 tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK) + BL/2 + RD( tRPST) + BL/2 + RD( tRPST) - ODTLon - RD( - ODTLon - RD( tODTon(MIN)/ tCK) tODTon(MIN)/ tCK) 89 200b: x32 LPDDR4 SDRAM Data Mask and Data Bus Inversion (DBI [DC]) Function Table 92: Different Bank (ODT Enabled) (Continued) Next CMD Current CMD ACTIVE READ (BL = 16 or 32) READ (with BL = 32) 4 162 WRITE (with BL = 16) 4 WL + 1+ BL/2 + RU(tWTR/tCK) 81 81 22 WRITE (with BL = 32) 4 WL + 1 + BL/2 + RU(tWTR/tCK) 162 162 22 MASK WRITE 4 WL + 1 + BL/2 + RU(tWTR/tCK) 81 81 22 PRECHARGE 4 4 4 4 4 Notes: WRITE (BL = 16 or 32) MASK WRITE RL + RU( RL + RU( tDQSCK(MAX)/ tCK) tDQSCK(MAX)/ tCK) + BL/2 + RD( tRPST) + BL/2 + RD( tRPST) - ODTLon - RD( - ODTLon - RD( tODTon(MIN)/ tCK) tODTon(MIN)/ tCK) PRECHARGE 22 1. In the case of BL = 16, tCCD is 8 × tCK. 2. In the case of BL = 32, tCCD is 16 × tCK. Data Mask and Data Bus Inversion (DBI [DC]) Function Data mask (DM) is supported for WRITE operations and the data bus inversion DBI (DC) is supported for READ, WRITE, MASK WRITE, MRR, and MRW operations. DM and DBI (DC) functions are supported with byte granularity. DBI (DC) for READ operations (READ, MRR) can be enabled or disabled via MR3 OP[6]. DBI (DC) for WRITE operations (WRITE, MASK WRITE, MRW) can be enabled or disabled via MR3 OP[7]. DM for MASK WRITE operations can be enabled or disabled via MR13 OP[5]. The device has one data mask inversion (DMI) pin per byte and a total of two DMI pins per channel. The DMI signal is a bidirectional DDR signal, is sampled with the DQ signals, and is electrically identical to a DQ signal. There are eight possible states for the device with the DM and DBI (DC) functions. Table 93: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations DMI Signal DM Function Write DBI (DC) Read DBI (DC) During WRITE During MASKED WRITE During READ During During During MPC[WRIT MPC[READ- MPC[READ E-FIFO] FIFO] DQ CAL] Disabled Disabled Disabled Don't Care1 Illegal1, 3 High-Z2 Don't Care1 High-Z2 High-Z2 Illegal3 High-Z2 Train9 Train10 Train11 Disabled Enabled Disabled Disabled Disabled Enabled Don't Care1 Illegal3 DBI (DC)5 Train9 Train10 Train11 Disabled Enabled Enabled DBI (DC)4 Illegal3 DBI (DC)5 Train9 Train10 Train11 Enabled Disabled Disabled Don't Care6 DM7 High-Z2 Train9 Train10 Train11 High-Z2 Train9 Train10 Train11 DBI (DC)5 Train9 Train10 Train11 Enabled Enabled Disabled Enabled Disabled Enabled DBI (DC)4 DBI (DC)4 Don't Care6 DBI (DC)8 DM7 90 200b: x32 LPDDR4 SDRAM Data Mask and Data Bus Inversion (DBI [DC]) Function Table 93: Function Behavior of DMI Signal During WRITE, MASKED WRITE, and READ Operations (Continued) DMI Signal DM Function Write DBI (DC) Read DBI (DC) During WRITE During MASKED WRITE Enabled Enabled Enabled DBI (DC)4 DBI (DC)8 Notes: During READ DBI (DC)5 During During During MPC[WRIT MPC[READ- MPC[READ E-FIFO] FIFO] DQ CAL] Train9 Train10 Train11 1. The DMI input signal is "Don’t Care." DMI input receivers are turned off. 2. DMI output drivers are turned off. 3. The MASK WRITE command is not allowed and is considered an illegal command when the DM function is disabled. 4. The DMI signal is treated as DBI and indicates whether the device needs to invert the write data received on DQ within a byte. The device inverts write data received on the DQ inputs if DMI is sampled HIGH and leaves the write data non-inverted if DMI is sampled LOW. 5. The device inverts read data on its DQ outputs associated within a byte and drives the DMI signal HIGH when more than four data bits = 1 within a given byte lane; otherwise, the device does not invert the read data and drives DMI signal LOW. 6. The device does not perform a MASK operation when it receives a WRITE (or MRW) command. During the WRITE burst, the DMI signal must be driven LOW. 7. The device requires an explicit MASKED WRITE command for all MASKED WRITE operations. The DMI signal is treated as a data mask (DM) and indicates which bytes within a burst will be masked. When the DMI signal is sampled HIGH, the device masks that beat of the burst for the given byte lane. All DQ input signals within a byte are "Don't Care" (either HIGH or LOW) when DMI is HIGH. When the DMI signal is sampled LOW, the device does not perform a MASK operation and data received on the DQ inputs is written to the array. 8. The device requires an explicit MASKED WRITE command for all MASKED WRITE operations. The device masks the write data received on the DQ inputs if five or more data bits = 1 on DQ[2:7] or DQ[10:15] (for lower byte or upper byte respectively) and the DMI signal is LOW. Otherwise, the device does not perform the MASK operation and treats it as a legal DBI pattern. The DMI signal is treated as a DBI signal, and data received on the DQ input is written to the array. 9. The DMI signal is treated as a training pattern. The device does not perform any MASK operation and does not invert write data received on the DQ inputs. 10. The DMI signal is treated as a training pattern. The device returns the data pattern written to the WRITE-FIFO. 11. The DMI signal is treated as a training pattern. For more information, see the Read DQ Calibration Training section. 91 200b: x32 LPDDR4 SDRAM Data Mask and Data Bus Inversion (DBI [DC]) Function Figure 35: MASKED WRITE Command with Write DBI Enabled; DM Enabled T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 DES DES DES DES DES DES DES DES DES CK_c CK_t CKE CS CA Valid Valid Valid Valid Command MASK WRITE-1 CAS-2 t WL DQSS DQS_c DQS_t t t DQS2DQ WPRE DQ[7:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid N1 I 2 I M3 N I N M N N DMI[0] Don’t Care Notes: 1. N: Input data is written to DRAM cell. 2. I: Input data is inverted, then written to DRAM cell. 3. M: Input data is masked. The total count of 1 data bits on DQ[7:2] is equal to or greater than five. 4. Data mask (DM) is enable: MR13 OP [5] = 0, Data bus inversion (DBI) write is enable: MR3 OP[7] = 1. 92 200b: x32 LPDDR4 SDRAM Data Mask and Data Bus Inversion (DBI [DC]) Function Figure 36: WRITE Command with Write DBI Enabled; DM Disabled T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 DES DES DES DES DES DES DES DES DES CK_c CK_t CKE CS CA Valid Valid Valid Valid Command WRITE-1 CAS-2 t WL DQSS DQS_c DQS_t t DQS2DQ t WPRE DQ[7:0] Valid Valid Valid N1 N Valid Valid Valid Valid Valid Valid Valid I2 I N N I N N N DMI[0] Don’t Care Notes: 1. N: Input data is written to DRAM cell. 2. I: Input data is inverted, then written to DRAM cell. 3. Data mask (DM) is disable: MR13 OP [5] = 1, Data bus inversion (DBI) write is enable: MR3 OP[7] = 1. 93 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior Preamble and Postamble Behavior Preamble, Postamble Behavior in READ-to-READ Operations The following illustrations show the behavior of the device's read DQS_t and DQS_c pins during cases where the preamble, postamble, and/or data clocking overlap. DQS will be driven with the following priority 1. Data clocking edges will always be driven 2. Postamble 3. Preamble Essentially the data clocking, preamble, and postamble will be ordered such that all edges will be driven. Additional examples of seamless and borderline non-overlapping cases have been included for clarity. READ-to-READ Operations – Seamless Figure 37: READ Operations: tCCD = MIN, Preamble = Toggle, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 CAm CAm T12 T13 T14 T15 T16 T17 T18 T19 T20 T26 T27 T28 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 BL DES DES t BA0, CA, AP READ-1 CAS-2 CCD = 8 RL = 6 t RL = 6 t DQSCK DQSCK t t RPST RPRE DQS_c DQS_t High-Z High-Z t DQ DMI High-Z t DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 94 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior READ-to-READ Operations – Consecutive Figure 38: Seamless READ: tCCD = MIN + 1, Preamble = Toggle, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 BL BA0, CA, AP CAm CAm T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES READ-1 CAS-2 CCD = 9 t RL = 6 t RL = 6 DQSCK DQSCK t t RPST RPRE t RPST DQS_c High-Z DQS_t High-Z t DQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DMI t DQSQ High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Notes: Figure 39: Consecutive READ: tCCD = MIN + 1, Preamble = Toggle, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 CAm CAm T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 BL DES DES t DES BA0, CA, AP READ-1 CAS-2 CCD = 9 RL = 6 t RL = 6 t DQSCK DQSCK t t RPRE t RPST RPRE t RPST DQS_c DQS_t High-Z High-Z t DQ DMI High-Z t DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 95 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 40: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 BL BA0, CA, AP CAm CAm T13 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES READ-1 CAS-2 CCD = 9 t RL = 6 t RL = 6 DQSCK DQSCK t t RPRE t RPST RPST DQS_c High-Z DQS_t High-Z t DQ DMI t DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 BL/2 = 8 High-Z BL/2 = 8 Don’t Care 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Notes: Figure 41: Consecutive READ: tCCD = MIN + 1, Preamble = Static, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 CAm CAm T13 T14 T15 T16 T17 T18 DES DES DES DES DES DES T19 T20 T21 T26 T27 T28 T29 T30 DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 BL DES DES t DES BA0, CA, AP READ-1 CAS-2 CCD = 9 RL = 6 RL = 6 t t DQSCK DQSCK t t RPRE t RPRE RPST DQS_c DQS_t High-Z High-Z t DQ DMI High-Z t DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 0.5nCK. 96 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 42: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 BL BA0, CA, AP CAm CAm T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES READ-1 CAS-2 CCD = 10 RL = 6 t RL = 6 t DQSCK DQSCK t t RPRE RPST t t RPRE RPST DQS_c DQS_t High-Z High-Z t DQ DMI High-Z t DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 97 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior Figure 43: Consecutive READ: tCCD = MIN + 2, Preamble = Toggle, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 BL BA0, CA, AP CAm CAm T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES READ-1 CAS-2 CCD = 10 t RL = 6 t RL = 6 DQSCK DQSCK t RPRE t t RPST RPRE t DQS_c RPST High-Z DQS_t High-Z t DQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DMI t High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 BL/2 = 8 Don’t Care 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Notes: Figure 44: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 BL BA0, CA, AP CAm CAm T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES READ-1 CAS-2 CCD = 10 RL = 6 t RL = 6 t DQSCK DQSCK t t RPRE RPST t t RPRE RPST DQS_c DQS_t High-Z High-Z t DQ DMI High-Z t DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 98 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 45: Consecutive READ: tCCD = MIN + 2, Preamble = Static, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 BL BA0, CA, AP CAm CAm T14 T15 T16 T17 T18 T19 T20 T21 T22 T28 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES READ-1 CAS-2 CCD = 10 RL = 6 t RL = 6 t DQSCK DQSCK t RPRE t RPST t RPRE t RPST DQS_c DQS_t High-Z High-Z t DQ DMI High-Z t DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 99 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior Figure 46: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 T14 BL BA0, CA, AP CAm CAm T15 T16 T17 T18 T19 T20 T21 T22 T23 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES DES READ-1 CAS-2 CCD = 11 t RL = 6 t RL = 6 DES DQSCK DQSCK t t RPRE t RPST t RPRE RPST DQS_c High-Z DQS_t High-Z t DQ DMI t DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DQSQ DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 High-Z BL/2 = 8 Don’t Care 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Notes: Figure 47: Consecutive READ: tCCD = MIN + 3, Preamble = Toggle, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 T14 BL BA0, CA, AP CAm CAm T15 T16 T17 T18 T19 T20 T21 T22 T23 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES DES READ-1 CAS-2 CCD = 11 RL = 6 t RL = 6 t DQSCK DQSCK t t RPRE t RPST RPRE t DQS_c DQS_t High-Z DMI High-Z RPST High-Z t DQ DES High-Z t DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6; Preamble = Toggle; Postamble = 0.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 100 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior Figure 48: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 T14 BL BA0, CA, AP CAm CAm T15 T16 T17 T18 T19 T20 T21 T22 T23 T29 T30 T31 DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES DES READ-1 CAS-2 CCD = 11 t RL = 6 t RL = 6 DES DQSCK DQSCK t t RPRE t RPST t RPRE RPST DQS_c High-Z DQS_t High-Z t DQ DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 High-Z DMI t DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 High-Z BL/2 = 8 Don’t Care 1. BL = 16 for column n and column m; RL = 6; Preamble = Static; Postamble = 1.5nCK. 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Notes: Figure 49: Consecutive READ: tCCD = MIN + 3, Preamble = Static, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T7 T8 T9 T10 T11 T12 T13 T14 BL BA0, CA, AP CAm CAm T15 T16 T17 T18 T19 T20 DES DES DES DES DES DES T21 T22 T23 T29 T30 T31 DES DES DES DES DES DES CK_c CK_t CS CA Command READ-1 CAS-2 DES DES t DES DES DES READ-1 CAS-2 CCD = 11 RL = 6 t RL = 6 t DES DQSCK DQSCK t t RPRE t RPST RPRE t RPST DQS_c DQS_t High-Z High-Z t DQ DMI High-Z High-Z t DQSQ DQSQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 BL/2 = 8 High-Z DOUT DOUT DOUT DOUT DOUT DOUT m0 m1 m12 m13 m14 m15 High-Z BL/2 = 8 Don’t Care Notes: 1. BL = 16 for column n and column m; RL = 6, Preamble = Static; Postamble = 0.5nCK 2. DOUT n/m = data-out from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 101 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior WRITE-to-WRITE Operations – Seamless Figure 50: Seamless WRITE: tCCD = MIN, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T5 T6 T7 T8 T9 T10 T11 BL BA0, CA CAm CAm T12 T13 T14 T15 T16 T17 T18 T23 T24 T25 T26 T27 T28 DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES t DES DES WRITE-1 CAS-2 CCD = 8 WL = 4 WL = 4 t t t DQSS DQSS WPRE t WPST DQS_c DQS_t t DQ DIN n0 DMI t DQS2DQ DIN DIN DIN n1 n2 n3 DIN n4 DIN DIN n5 n6 DIN n7 DIN n8 BL/2 = 8 DIN n9 DIN DIN DIN DIN DIN DIN n10 n11 n12 n13 n14 n15 DIN m0 DQS2DQ DIN m1 DIN m2 DIN m3 DIN m12 DIN DIN DIN m13 m14 m15 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n/m = data-in from column n and column m. 3. The minimum number of clock cycles from the burst WRITE command to the burst WRITE command for any bank is BL/2. 4. DES commands are shown for ease of illustration; other commands may be valid at these times. 102 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior Figure 51: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble, 533 MHz < Clock Frequency ≤ 800 MHz, ODT Worst Timing Case T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T7 T8 T9 T10 T11 BL BA0, CA CAm CAm T12 T13 T14 T15 T16 T17 T23 T24 T25 DES DES DES DES DES DES DES DES DES T31 T32 T33 T34 T35 T36 DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES t WRITE-1 CAS-2 CCD = 8 WL = 12 WL = 12 t t t DES DQSS DQSS t WPRE WPST DQS_c DQS_t t DQ DIN n0 DMI ODTLon = 6 DRAM RTT t ODTon (MAX) t DQS2DQ DIN DIN DIN DIN DIN n1 n2 n13 n14 n15 BL/2 = 8 DIN m0 DQS2DQ DIN m1 DIN m2 DIN DIN DIN m13 m14 m15 BL/2 = 8 ODT on ODT High-Z ODTLoff = 22 ODT High-Z t ODToff (MIN) Don’t Care Notes: Clock frequency = 800 MHz, tCK(AVG) = 1.25ns. BL = 16, Write postamble = 1.5nCK. DIN n/m = data-in from column n and column m. The minimum number of clock cycles from the burst WRITE command to the burst WRITE command for any bank is BL/2. 5. DES commands are shown for ease of illustration; other commands may be valid at these times. 1. 2. 3. 4. 103 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior Figure 52: Seamless WRITE: tCCD = MIN, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T7 T8 T9 T10 T11 BL BA0, CA CAm CAm T12 T15 T16 T17 T18 T19 T25 T26 T27 DES DES DES DES DES DES DES DES DES T33 T34 T35 T36 T37 T38 DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES t CCD = 8 WRITE-1 CAS-2 WL = 14 WL = 14 t t t DES DQSS DQSS t WPRE WPST DQS_c DQS_t t DQ t DQS2DQ DIN n0 DMI DIN DIN DIN DIN DIN n1 n2 n13 n14 n15 BL/2 = 8 DIN m0 DQS2DQ DIN m1 DIN m2 DIN DIN DIN m13 m14 m15 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m. 3. The minimum number of clock cycles from the burst WRITE command to the burst WRITE command for any bank is BL/2. 4. DES commands are shown for ease of illustration; other commands may be valid at these times. 104 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior WRITE-to-WRITE Operations – Consecutive Figure 53: Consecutive WRITE: tCCD = MIN + 1, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T8 T9 T10 T11 T12 BL BA0, CA CAm CAm T13 T14 T15 T16 T17 T23 T24 T25 T26 T32 DES DES DES DES DES DES DES DES DES T33 T34 T35 T36 T37 DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES WRITE-1 DES t CAS-2 CCD = 9 WL = 12 WL = 12 t t t DES DQSS DQSS WPRE t WPST DQS_c DQS_t t DQ DMI t DQS2DQ DQS2DQ DIN m0 DIN DIN DIN DIN DIN n1 n2 n13 n14 n15 DIN n0 DIN m2 DIN m1 DIN DIN DIN m13 m14 m15 BL/2 = 8 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 54: Consecutive WRITE: tCCD = MIN + 1, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T8 T9 T10 T11 T12 BL BA0, CA CAm CAm T13 T14 T15 T16 T17 T23 T24 T25 T26 T32 DES DES DES DES DES DES DES DES DES T33 T34 T35 T36 T37 DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES WRITE-1 DES t CAS-2 CCD = 9 WL = 12 WL = 12 t t t DES DQSS DQSS t WPRE WPST DQS_c DQS_t t DQ DIN n0 DMI DQS2DQ DIN DIN DIN DIN DIN n1 n2 n13 n14 n15 BL/2 = 8 t DQS2DQ DIN m0 DIN m1 DIN m2 DIN DIN DIN m13 m14 m15 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m. 105 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 55: Consecutive WRITE: tCCD = MIN + 2, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T9 T10 T11 T12 T13 BL BA0, CA CAm CAm T14 T15 T16 T17 T23 T24 T25 T26 T27 T33 T34 T35 T36 T37 T38 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES WRITE-1 DES t CAS-2 CCD = 10 WL = 12 WL = 12 t t t DQSS DQSS t WPRE WPRE t WPST DQS_c DQS_t t DQ DMI t DQS2DQ DQS2DQ DIN m0 DIN DIN DIN DIN DIN n1 n2 n13 n14 n15 DIN n0 DIN m2 DIN m1 DIN DIN DIN m13 m14 m15 BL/2 = 8 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 56: Consecutive WRITE: tCCD = MIN + 2, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T9 T10 T11 T12 T13 BL BA0, CA CAm CAm T14 T15 T16 T17 T23 T24 T25 T26 T27 T33 T34 T35 T36 T37 T38 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES WRITE-1 DES t CAS-2 CCD = 10 WL = 12 WL = 12 t t t DQSS DQSS t WPRE t WPRE WPST DQS_c DQS_t t DQ DIN n0 DMI DQS2DQ DIN DIN DIN DIN DIN n1 n2 n13 n14 n15 BL/2 = 8 t DQS2DQ DIN m0 DIN m1 DIN m2 DIN DIN DIN m13 m14 m15 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 1.5nCK. 106 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 57: Consecutive WRITE: tCCD = MIN + 3, 0.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T9 T10 T11 T12 T13 T14 BL BA0, CA CAm CAm T15 T16 T17 T23 T24 T25 T26 T27 T28 T34 T35 T36 T37 T38 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES DES t WRITE-1 CAS-2 CCD = 11 WL = 12 WL = 12 t t t DQSS DQSS WPRE t WPST t WPRE t WPST DQS_c DQS_t t DQ DIN n0 DMI DQS2DQ DIN DIN DIN DIN DIN n1 n2 n13 n14 n15 BL/2 = 8 t DQS2DQ DIN m0 DIN m1 DIN m2 Din DIN DIN m13 m14 m15 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 107 200b: x32 LPDDR4 SDRAM Preamble and Postamble Behavior Figure 58: Consecutive WRITE: tCCD = MIN + 3, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T9 T10 T11 T12 T13 T14 BL BA0, CA CAm CAm T15 T16 T17 T23 T24 T25 T26 T27 T28 T34 T35 T36 T37 T38 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES WRITE-1 DES DES t CAS-2 CCD = 11 WL = 12 WL = 12 t t t DQSS DQSS t WPRE t WPST t WPRE WPST DQS_c DQS_t t DQ DMI t DQS2DQ DQS2DQ DIN m0 DIN DIN DIN DIN DIN n1 n2 n13 n14 n15 DIN n0 DIN m2 DIN m1 DIN DIN DIN m13 m14 m15 BL/2 = 8 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Figure 59: Consecutive WRITE: tCCD = MIN + 4, 1.5nCK Postamble T0 T1 T2 T3 BL BA0, CA CAn CAn T4 T9 T10 T11 T12 T13 T14 BL BA0, CA CAm CAm T15 T16 T17 T23 T24 T25 T26 T27 T28 T29 T35 T36 T37 T38 DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES WRITE-1 DES t CAS-2 CCD = 12 WL = 12 WL = 12 t t t DQSS DQSS t WPRE WPST t t WPRE WPST DQS_c DQS_t t DQ DIN n0 DMI DQS2DQ DIN DIN DIN DIN DIN n1 n2 n13 n14 n15 BL/2 = 8 t DIN m0 DQS2DQ DIN m1 DIN m2 DIN DIN DIN m13 m14 m15 BL/2 = 8 Don’t Care Notes: 1. BL = 16, Write postamble = 1.5nCK. 2. DIN n/m = data-in from column n and column m. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 108 200b: x32 LPDDR4 SDRAM PRECHARGE Operation PRECHARGE Operation The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command is initiated with CKE, CS, and CA[5:0] in the proper state (see Command Truth Table). The PRECHARGE command can be used to precharge each bank independently or all banks simultaneously. The all banks (AB) flag and the bank address bit are used to determine which bank(s) to precharge. The precharged bank(s) will be available for subsequent row access tRPab after an all-bank PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command is issued. To ensure that the device can meet the instantaneous current demands, the row precharge time for an all-bank PRECHARGE ( tRPab) is longer than the per-bank precharge time (tRPpb). Table 94: Precharge Bank Selection AB (CA[5], R1) BA2 (CA[2], R2) BA1 (CA[1], R2) BA0 (CA[0], R2) Precharged Bank 0 0 0 0 Bank 0 only 0 0 0 1 Bank 1 only 0 0 1 0 Bank 2 only 0 0 1 1 Bank 3 only 0 1 0 0 Bank 4 only 0 1 0 1 Bank 5 only 0 1 1 0 Bank 6 only 0 1 1 1 Bank 7 only 1 Don't Care Don't Care Don't Care All banks Burst READ Operation Followed by Precharge The PRECHARGE command can be issued as early as BL/2 clock cycles after a READ command, but the PRECHARGE command cannot be issued until after tRAS is satisfied. A new bank ACTIVATE command can be issued to the same bank after the row precharge time (tRP) has elapsed. The minimum read-to-precharge time must also satisfy a minimum analog time from the second rising clock edge of the CAS-2 command. tRTP begins BL/2 - 8 clock cycles after the READ command. 109 200b: x32 LPDDR4 SDRAM PRECHARGE Operation Figure 60: Burst READ Followed by Precharge – BL16, Toggling Preamble, 0.5nCK Postamble T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Valid Valid Valid Valid Valid Valid Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t CA[5:0] Valid Valid Valid Valid Valid Valid tRTP READ-1 Command CAS-2 Valid Valid Valid Valid Valid tRP Valid PRECHARGE Valid Valid Valid Valid ACT-2 ACT-1 DQS_t DQS_c DQ[15:0] DMI[1:0] Valid Don’t Care Transitioning Data Figure 61: Burst READ Followed by Precharge – BL32, 2tCK, 0.5nCK Postamble T0 T1 T2 T3 T4 T5 T10 T11 T12 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t CA[5:0] Valid Valid Valid Valid Valid tRTP Command READ-1 CAS-2 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid tRP PRECHARGE Valid Valid Valid ACT-1 ACT-2 DQS_t DQS_c DQ[15:0] DMI[1:0] Valid Transitioning Data Don’t Care Burst WRITE Followed by Precharge A write recovery time (tWR) must be provided before a PRECHARGE command may be issued. This delay is referenced from the next rising edge of CK after the last valid DQS clock of the burst. Devices write data to the memory array in prefetch multiples (prefetch = 16). An internal WRITE operation can only begin after a prefetch group has been clocked; therefore, tWR starts at the prefetch boundaries. The minimum write-to-precharge time for commands to the same bank is WL + BL/2 + 1 + RU( tWR /tCK) clock cycles. 110 200b: x32 LPDDR4 SDRAM Auto Precharge Figure 62: Burst WRITE Followed by PRECHARGE – BL16, 2nCK Preamble, 0.5nCK Postamble T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Ta Ta+1 Ta+2 Tn Tn+1 Tn+2 Tn+3 Ty Ty+1 Ty+2 Ty+3 Ty+4 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid PRECHARGE Valid CK_c CK_t CA WL Command WRITE-1 CAS-2 Valid Valid Valid tDQSS Valid Valid Valid tWR (MAX) ACT-1 ACT-2 tRP DQS_c DQS_t tDQS2DQ DQ DMI Valid Transitioning Data Don’t Care Auto Precharge Before a new row can be opened in an active bank, the active bank must be precharged using either the PRECHARGE command or the auto precharge (AP) function. When a READ or a WRITE command is issued to the device, the AP bit (CA5) can be set to enable the active bank to automatically begin precharge at the earliest possible moment during the burst READ or WRITE cycle. If AP is LOW when the READ or WRITE command is issued, the normal READ or WRITE burst operation is executed, and the bank remains active at the completion of the burst. If AP is HIGH when the READ or WRITE command is issued, the auto PRECHARGE function is engaged. This feature enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon READ or WRITE latency), thus improving system performance for random data access. Burst READ With Auto Precharge If AP is HIGH when a READ command is issued, the READ with AUTO PRECHARGE function is engaged. The devices start an AUTO PRECHARGE operation on the rising edge of the clock at BL/2 after the second beat of the READ w/AP command, or BL/4 - 4 + RU (tRTP/tCK) clock cycles after the second beat of the READ w/AP command, whichever is greater. Following an AUTO PRECHARGE operation, an ACTIVATE command can be issued to the same bank if the following two conditions are both satisfied: 1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge began, and 2. The RAS cycle time (tRC) from the previous bank activation has been satisfied. 111 200b: x32 LPDDR4 SDRAM Auto Precharge Figure 63: Burst READ With Auto Precharge – BL16, Non-Toggling Preamble, 0.5nCK Postamble T0 T1 T2 T3 T4 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Valid Valid Valid Valid Valid Valid Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t CA[5:0] Valid Valid Valid Valid Valid Valid tRTP READ-1 w/AP Command CAS-2 Valid Valid Valid Valid Valid tRPpb Valid Valid Valid Valid Valid Valid ACT-2 ACT-1 DQS_t DQS_c DQ[15:0] DMI[1:0] Valid Don’t Care Transitioning Data Figure 64: Burst READ With Auto Precharge – BL32, Toggling Preamble, 1.5nCK Postamble T0 T1 T2 T3 T4 T5 T10 T11 T12 T13 T14 Tx Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Ty Ty+1 Ty+2 Ty+3 Ty+4 CK_c CK_t CA[5:0] Valid Valid Valid tRTP Command READ-1 CAS-2 Valid Valid Valid Valid Valid Valid Valid Valid Valid tRP Valid Valid Valid Valid Valid ACT-1 ACT-2 DQS_t DQS_c DQ[15:0] DMI[1:0] Valid Transitioning Data Don’t Care Burst WRITE With Auto Precharge If AP is HIGH when a WRITE command is issued, the WRITE with AUTO PRECHARGE function is engaged. The device starts an auto precharge on the rising edge tWR cycles after the completion of the burst WRITE. Following a WRITE with AUTO PRECHARGE, an ACTIVATE command can be issued to the same bank if the following conditions are met: 1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge began, and 112 200b: x32 LPDDR4 SDRAM Auto Precharge 2. The RAS cycle time (tRC) from the previous bank activation has been satisfied. Figure 65: Burst WRITE With Auto Precharge – BL16, 2nCK Preamble, 0.5nCK Postamble T0 T1 T2 T3 T4 Valid Valid Valid Valid Valid Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Ta Ta+1 Ta+2 Tn Tn+1 Tn+2 Tn+3 Ty Ty+1 Ty+2 Ty+3 Ty+4 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid CK_c CK_t CA WL Command WRITE-1 CAS-2 Valid Valid Valid tDQSS Valid Valid Valid Valid Valid tWR (MAX) ACT-1 ACT-2 tRP DQS_c DQS_t tDQS2DQ DQ[15:0] DMI[1:0] Valid Transitioning Data Don’t Care Table 95: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable Minimum Delay Between "From Command" and "To Command" Unit Notes PRECHARGE (to same bank as READ) tRTP tCK 1, 6 PRECHARGE ALL tRTP tCK 1, 6 PRECHARGE (to same bank as READ) 8tCK + tRTP tCK 1, 6 PRECHARGE ALL 8tCK + tRTP tCK 1, 6 PRECHARGE (to same bank as READ w/AP) nRTP tCK 1, 10 PRECHARGE ALL nRTP tCK 1, 10 nRTP + tRPpb tCK 1, 8, 10 WRITE or WRITE w/AP (same bank) Illegal – MASK-WR or MASK-WR w/AP (same bank) Illegal – WRITE or WRITE w/AP (different bank) RL + RU (tDQSCK MAX/tCK) + BL/2 + RD (tRPST) - WL + tWPRE tCK 3, 4, 5 MASK-WR or MASK-WR w/AP (different bank) RL + RU (tDQSCK MAX/tCK) + BL/2 + RD (tRPST) - WL + tWPRE tCK 3, 4, 5 READ or READ w/AP (same bank) Illegal – READ or READ w/AP (different bank) BL/2 tCK From Command To Command READ BL = 16 READ BL = 32 READ w/AP BL = 16 ACTIVATE (to same bank as READ w/AP) 113 3 200b: x32 LPDDR4 SDRAM Auto Precharge Table 95: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable (Continued) Minimum Delay Between "From Command" and "To Command" Unit Notes PRECHARGE (to same bank as READ w/AP) 8tCK + nRTP tCK 1, 10 PRECHARGE ALL 8tCK + nRTP tCK 1, 10 tCK 1, 8, 10 From Command To Command READ w/AP BL = 32 8tCK ACTIVATE (to same bank as READ w/AP) WRITE BL = 16 and 32 MASK-WR BL = 16 WRITE w/AP BL = 16 and 32 + nRTP + tRPpb WRITE or WRITE w/AP (same bank) Illegal – MASK-WR or MASK-WR w/AP (same bank) Illegal – WRITE or WRITE w/AP (different bank) RL + RU (tDQSCK MAX/tCK) + BL/2 + RD (tRPST) - WL + tWPRE tCK 3, 4, 5 MASK-WR or MASK-WR w/AP (different bank) RL + RU (tDQSCK MAX/tCK) + BL/2 + RD (tRPST) - WL + tWPRE tCK 3, 4, 5 READ or READ w/AP (same bank) Illegal – READ or READ w/AP (different bank) BL/2 tCK 3 PRECHARGE (to same bank as WRITE) WL + BL/2 + tWR + 1 tCK 1, 7 PRECHARGE ALL WL + BL/2 + tWR + 1 tCK 1, 7 tCK 1, 7 tWR +1 PRECHARGE (to same bank as MASK-WR) WL + BL/2 + PRECHARGE ALL WL + BL/2 + tWR + 1 tCK 1, 7 PRECHARGE (to same bank as WRITE w/AP) WL + BL/2 + nWR + 1 tCK 1, 11 PRECHARGE ALL WL + BL/2 + nWR + 1 tCK 1, 11 tCK 1, 8, 11 ACTIVATE (to same bank as WRITE w/AP) WL + BL/2 + nWR + 1 + tRPpb WRITE or WRITE w/AP (same bank) Illegal – READ or READ w/AP (same bank) Illegal – WRITE or WRITE w/AP (different bank) BL/2 tCK 3 MASK-WR or MASK-WR w/AP (different bank) BL/2 tCK 3 WL + BL/2 + tWTR + 1 tCK 3, 9 READ or READ w/AP (different bank) 114 200b: x32 LPDDR4 SDRAM Auto Precharge Table 95: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Disable (Continued) Minimum Delay Between "From Command" and "To Command" Unit Notes PRECHARGE (to same bank as MASK-WR w/AP) WL + BL/2 + nWR +1 tCK 1, 11 PRECHARGE ALL WL + BL/2 + nWR + 1 tCK 1, 11 tCK 1, 8, 11 From Command To Command MASK-WR w/AP BL = 16 WL + BL/2 + nWR + 1 + ACTIVATE (to same bank as MASK-WR w/AP) PRECHARGE PRECHARGE ALL tRPpb WRITE or WRITE w/AP (same bank) Illegal – 3 MASK-WR or MASK-WR w/AP (same bank) Illegal – 3 WRITE or WRITE w/AP (different bank) BL/2 tCK 3 MASK-WR or MASK-WR w/AP (different bank) BL/2 tCK 3 READ or READ w/AP (same bank) Illegal – 3 READ or READ w/AP (different bank) WL + BL/2 + tWTR + 1 tCK 3, 9 PRECHARGE (to same bank as PRECHARGE) 4 tCK 1 PRECHARGE ALL 4 tCK 1 PRECHARGE 4 tCK 1 PRECHARGE ALL 4 tCK 1 Notes: 1. For a given bank, the precharge period should be counted from the latest PRECHARGE command, whether per-bank or all-bank, issued to that bank. The precharge period is satisfied tRP after that latest PRECHARGE command. 2. Any command issued during the minimum delay time as specified in the table above is illegal. 3. After READ w/AP, seamless READ operations to different banks are supported. After WRITE w/AP or MASK-WR w/AP, seamless WRITE operations to different banks are supported. READ, WRITE, and MASK-WR operations may not be truncated or interrupted. 4. tRPST values depend on MR1 OP[7] respectively. 5. tWPRE values depend on MR1 OP[2] respectively. 6. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup (tRTP [ns]/tCK [ns]). 7. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup (tWR [ns]/tCK [ns]). 115 200b: x32 LPDDR4 SDRAM Auto Precharge 8. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tRPpb (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup (tRPpb [ns]/tCK [ns]). 9. Minimum delay between "from command" and "to command" in clock cycle is calculated by dividing tWTR (in ns) by tCK (in ns) and rounding up to the next integer: Minimum delay [cycles] = roundup (tWTR [ns]/tCK [ns]). 10. For READ w/AP the value is nRTP, which is defined in mode register 2. 11. For WRITE w/AP the value is nWR, which is defined in mode register 1. Table 96: Timing Between Commands (PRECHARGE and AUTO PRECHARGE): DQ ODT is Enable From Command To Command READ w/AP BL = 16 WRITE or WRITE w/AP (different bank) MASK-WR or MASK-WR w/AP (different bank) READ w/AP BL = 32 WRITE or WRITE w/AP (different bank) MASK-WR or MASK-WR w/AP (different bank) Notes: Minimum Delay Between "From Command" and "To Command" Unit Notes RL + RU (tDQSCK MAX/tCK) + BL/2 + RD (tRPST) - ODTLon - RD (tODTon MIN/tCK) + 1 tCK 2, 3 RL + RU (tDQSCK MAX/tCK) + BL/2 - ODTLon - RD (tODTon MIN/tCK) + 1 tCK 2, 3 RL + RU (tDQSCK MAX/tCK) + BL/2 - ODTLon - RD (tODTon MIN/tCK) + 1 tCK 2, 3 RL + RU (tDQSCK MAX/tCK) + BL/2 - ODTLon - RD (tODTon MIN/tCK) + 1 tCK 2, 3 + RD (tRPST) + RD (tRPST) + RD (tRPST) 1. The rest of the timing about PRECHARGE and AUTO PRECHARGE is same as DQ ODT is disable case. 2. After READ w/AP, seamless read operations to different banks are supported. READ, WRITE, and MASK-WR operations may not be truncated or interrupted. 3. tRPST values depend on MR1 OP[7] respectively. RAS Lock Function READ with AUTO PRECHARGE or WRITE/MASK WRITE with AUTO PRECHARGE commands may be issued after tRCD has been satisfied. The LPDDR4 SDRAM RAS lockout feature will schedule the internal precharge to assure that tRAS is satisfied. tRC needs to be satisfied prior to issuing subsequent ACTIVATE commands to the same bank. The figure below shows example of RAS lock function. 116 200b: x32 LPDDR4 SDRAM Auto Precharge Figure 66: Command Input Timing with RAS Lock T0 T1 T2 T3 RA RA BA0 RA RA T4 T19 T20 T21 T22 T23 T24 T25 T31 T32 T38 T39 T47 T48 Ta0 Ta1 Ta2 Ta3 Ta4 RA RA BA0 RA Ta5 CK_c CK_t CKE CS CA Command ACTIVATE-1 ACTIVATE-2 Valid DES DES BA0 CA RDA-1 tRCD CA CAS-2 DES = 20nCK DES DES 8nCK DES DES DES DES DES DES DES ACTIVATE-1 RA ACTIVATE-2 nRTP = 8nCK tRAS tRC Don’t Care Notes: 1. tCK (AVG) = 0.938ns, Data rate = 2133 Mbps, tRCD (MIN) = MAX (18ns, 4nCK), tRAS (MIN) = MAX (42ns, 3nCK), nRTP = 8nCK, BL = 32. 2. tRCD = 20nCK comes from roundup (18ns/0.938ns). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. Delay Time From WRITE-to-READ with Auto Precharge In the case of WRITE command followed by READ with AUTO PRECHARGE, controller must satisfy tWR for the WRITE command before initiating the device internal auto-precharge. It means that (tWTR + nRTP) should be equal or longer than (tWR) when BL setting is 16, as well as (tWTR + nRTP + 8nCK) should be equal or longer than (tWR) when BL setting is 32. Refer to the following figure for details. Figure 67: Delay Time From WRITE-to-READ with Auto Precharge T0 T1 T2 T3 BL BA0 CA CA CA T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Td0 Td1 Td2 DES DES DES DES Td3 Td4 CK_c CK_t CKE CS CA Command WRITE-1 CAS-2 Valid DES DES WL DES DES DES DES DES DES DES DES BA0 CA RDA-1 CAS-2 tWTR BL/2 + 1 clock CA DES DES nRTP tWR Don’t Care Notes: 1. Burst length at read = 16. 117 200b: x32 LPDDR4 SDRAM REFRESH Command 2. DES commands are shown for ease of illustration; other commands may be valid at these times. REFRESH Command The REFRESH command is initiated with CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3 HIGH and CA4 LOW at the first rising edge of clock. Per bank REFRESH is initiated with CA5 LOW at the first rising edge of the clock. The all-bank REFRESH is initiated with CA5 HIGH at the first rising edge of clock. A per bank REFRESH command (REFpb) is performed to the bank address as transferred on CA0, CA1, and CA2 on the second rising edge of the clock. Bank address BA0 is transferred on CA0, bank address BA1 is transferred on CA1, and bank address BA2 is transferred on CA2. A per bank REFRESH command (REFpb) to the eight banks can be issued in any order. For example, REFpb commands may be issued in the following order: 1-3-0-2-4-7-5-6. After the eight banks have been refreshed using the per bank REFRESH command, the controller can send another set of per bank REFRESH commands in the same order or a different order. One possible order can be a sequential round robin: 0-1-2-3-4-5-6-7. It is illegal to send a per bank REFRESH command to the same bank unless all eight banks have been refreshed using the per bank REFRESH command. The count of eight REFpb commands starts with the first REFpb command after a synchronization event. The bank count is synchronized between the controller and the device by resetting the bank count to zero. Synchronization can occur upon reset procedure or at every exit from self refresh. The REFab command also synchronizes the counter between the controller and the device to zero. The device can be placed in self refresh, or a REFab command can be issued at any time without cycling through all eight banks using per bank REFRESH command. After the bank count is synchronized to zero, the controller can issue per bank REFRESH commands in any order, as described above. A REFab command issued when the bank counter is not zero will reset the bank counter to zero and the device will perform refreshes to all banks as indicated by the row counter. If another REFRESH command (REFab or REFpb) is issued after the REFab command then it uses an incremented value of the row counter. The table below shows examples of both bank and refresh counter increment behavior. Table 97: Bank and Refresh Counter Increment Behavior # Command BA0 0 BA1 BA2 Refresh Bank # Reset, SRX, or REFab Bank Counter # Ref. Conter # (Row Address #) To 0 – n 1 REFpb 0 0 0 0 0 to 1 2 REFpb 0 0 1 1 1 to 2 3 REFpb 0 1 0 2 2 to 3 4 REFpb 0 1 1 3 3 to 4 5 REFpb 1 0 0 4 4 to 5 6 REFpb 1 0 1 5 5 to 6 7 REFpb 1 1 0 6 6 to 7 8 REFpb 1 1 1 7 7 to 0 118 200b: x32 LPDDR4 SDRAM REFRESH Command Table 97: Bank and Refresh Counter Increment Behavior (Continued) # Command BA0 BA1 BA2 Refresh Bank # Bank Counter # Ref. Conter # (Row Address #) 9 REFpb 1 1 0 6 0 to 1 n+1 10 REFpb 1 1 1 7 1 to 2 11 REFpb 0 0 1 1 2 to 3 12 REFpb 0 1 1 3 3 to 4 13 REFpb 1 0 1 5 4 to 5 14 REFpb 0 1 0 2 5 to 6 15 REFpb 0 0 0 0 6 to 7 16 REFpb 1 0 0 4 7 to 0 17 REFpb 0 0 0 0 0 to 1 18 REFpb 0 0 1 1 1 to 2 19 REFpb 0 1 0 2 2 to 3 20 REFab V V V 0 to 7 To 0 n+2 21 REFpb 1 1 0 6 0 to 1 n+3 22 REFpb 1 1 1 7 1 to 2 n+2 Snip A bank must be idle before it can be refreshed. The controller must track the bank being refreshed by the per bank REFRESH command. The REFpb command must not be issued to the device until the following conditions have been met: • • • • tRFCab has been satisfied after the prior REFab command has been satisfied after the prior REFpb command tRP has been satisfied after the prior PRECHARGE command to that bank tRRD has been satisfied after the prior ACTIVATE command (for example, after activating a row in a different bank than the one affected by the REFpb command) tRFCpb The target bank is inaccessible during per bank REFRESH cycle time (tRFCpb). However, other banks within the device are accessible and can be addressed during the cycle. During the REFpb operation, any of the banks other than the one being refreshed can be maintained in an active state or accessed by a READ or a WRITE command. When the per bank REFRESH cycle has completed, the affected bank will be in the idle state. After issuing REFpb, the following conditions must be met: • • • • tRFCpb must be satisfied before issuing a REFab command must be satisfied before issuing an ACTIVATE command to the same bank tRRD must be satisfied before issuing an ACTIVATE command to a different bank tRFCpb must be satisfied before issuing another REFpb command tRFCpb An all-bank REFRESH command (REFab) issues a REFRESH command to every bank in a channel. All banks must be idle when REFab is issued (for example, by issuing a PRECHARGE ALL command prior to issuing an all-bank REFRESH command). The REFab 119 200b: x32 LPDDR4 SDRAM REFRESH Command command must not be issued to the device until the following conditions have been met: • tRFCab has been satisfied following the prior REFab command • tRFCpb has been satisfied following the prior REFpb command • tRP has been satisfied following the prior PRECHARGE command When an all-bank REFRESH cycle has completed, all banks will be idle. After issuing REFab: • RFCab latency must be satisfied before issuing an ACTIVATE command, • RFCab latency must be satisfied before issuing a REFab or REFpb command Table 98: REFRESH Command Timing Constraints Symbol Minimum Delay From... To tRFCab REFab REFab Notes ACTIVATE command to any bank REFpb tRFCpb REFpb REFab ACTIVATE command to same bank as REFpb REFpb tRRD REFpb ACTIVATE command to a different bank than REFpb ACTIVATE REFpb 1 ACTIVATE command to a different bank than the prior ACTIVATE command 1. A bank must be in the idle state before it is refreshed; therefore, REFab is prohibited following an ACTIVATE command. REFpb is supported only if it affects a bank that is in the idle state. Note: Figure 68: All-Bank REFRESH Operation T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0 Tc1 Tc2 Tc3 CK_c CK_t CKE CS CA Valid t Command PRECHARGE ALL bank Valid Valid Valid Valid Valid DES DES t RPab DES DES All bank REFRESH DES DES Valid Valid t RFCab DES DES All bank REFRESH DES DES RFCab DES DES Any command DES Don’t Care 120 200b: x32 LPDDR4 SDRAM REFRESH Command Figure 69: Per Bank REFRESH Operation T0 T1 T2 T3 Ta0 Ta1 Ta2 Valid BA0 Ta3 Ta4 Tb0 Tb1 Tb2 Valid BA1 Tb3 Tb4 Tc0 Tc1 Tc2 Tc3 Tc4 Valid BA1 Valid Valid Tc5 Tc6 DES DES CK_c CK_t CKE CS CA Valid Valid t Command PRECHARGE ALL bank DES t RPab DES DES Per bank REFRESH DES t RFCpb DES DES Per bank REFRESH DES RFCpb DES DES ACTIVATE-1 ACTIVATE-2 Don’t Care Notes: 1. In the beginning of this example, the REFpb bank is pointing to bank 0. 2. Operations to banks other than the bank being refreshed are supported during the tRFCpb period. In general, a REFRESH command needs to be issued to the device regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be postponed during operation of the device, but at no point in time are more than a total of eight REFRESH commands allowed to be postponed. And a maximum number of pulled-in or postponed REF command is dependent on refresh rate. It is described in the table below. In the case where eight REFRESH commands are postponed in a row, the resulting maximum interval between the surrounding REFRESH commands is limited to 9 × tREFI. A maximum of eight additional REFRESH commands can be issued in advance (pulled in), with each one reducing the number of regular REFRESH commands required later by one. Note that pulling in more than eight REFRESH commands in advance does not reduce the number of regular REFRESH commands required later; therefore, the resulting maximum interval between two surrounding REFRESH commands is limited to 9 × tREFI. At any given time, a maximum of 16 REFRESH commands can be issued within 2 × tREFI. Self refresh mode may be entered with a maximum of eight REFRESH commands being postponed. After exiting self refresh mode with one or more REFRESH commands postponed, additional REFRESH commands may be postponed to the extent that the total number of postponed REFRESH commands (before and after self refresh) will never exceed eight. During self refresh mode, the number of postponed or pulled-in REFRESH commands does not change. And for per bank refresh, a maximum of 8 x 8 per bank REFRESH commands can be postponed or pulled in for scheduling efficiency. At any given time, a maximum of 2 x 8 x 8 per bank REFRESH commands can be issued within 2 x tREFI. 121 200b: x32 LPDDR4 SDRAM REFRESH Command Table 99: Legacy REFRESH Command Timing Constraints MR4 OP[2:0] 000b Refresh Rate Max. No. of pulled-in or postponed REFab Max. Interval between Two REFab Max. No. of REFab1 Per Bank Refresh Low Temp. Limit N/A N/A N/A N/A 001b 4× tREFI 010b 2 × tREFI 011b 1 × tREFI 100b tREFI 0.5 × 101b 0.25 × tREFI 110b 0.25 × tREFI 111b High Temp. Limit Note: 8 9×4× tREFI 16 1/8 of REFab 8 9 × 2 × tREFI 16 1/8 of REFab 8 9 × tREFI 16 1/8 of REFab 8 9 × 0.5 × tREFI 16 1/8 of REFab 8 9 × 0.25 × tREFI 16 1/8 of REFab 8 9 × 0.25 × tREFI 16 1/8 of REFab N/A N/A N/A N/A 1. Maximum number of REFab within MAX(2 × tREFI × refresh rate multiplier, 16 × tRFC). Table 100: Modified REFRESH Command Timing Constraints MR4 OP[2:0] Refresh Rate Max. No. of pulled-in or postponed REFab 000B LOW Temp. Limit 001B 4 × tREFI 010B 2 × tREFI 011B tREFI 1× Max. Interval between Two REFab Max. No. of REFab1 N/A N/A N/A N/A 2 3 × 4 × tREFI 4 1/8 of REFab 4 5 × 2 × tREFI 8 1/8 of REFab 16 1/8 of REFab 8 tREFI 9× tREFI tREFI Per Bank Refresh 100B 0.5 × 8 9 × 0.5 × 16 1/8 of REFab 101B 0.25 × tREFI 8 9 × 0.25 × tREFI 16 1/8 of REFab 110B 0.25 × tREFI 8 9 × 0.25 × tREFI 16 1/8 of REFab 111B HIGH Temp. Limit N/A N/A N/A N/A Notes: 1. For any thermal transition phase where refresh mode is transitioned to either 2 × tREFI or 4 × tREFI, LPDDR4 devices will support the previous postponed refresh requirement provided the number of postponed refreshes is monotonically reduced to meet the new requirement. However, the pulled-in REFRESH commands in previous thermal phase are not applied in new thermal phase. Entering new thermal phase the controller must count the number of pulled-in REFRESH commands as zero, regardless of remaining pulled-in REFRESH commands in previous thermal phase. 2. LPDDR4 devices are refreshed properly if memory controller issues REFRESH commands with same or shorter refresh period than reported by MR4 OP[2:0]. If shorter refresh period is applied, the corresponding requirements from Table apply. For example, when MR4 OP[2:0] = 001b, controller can be in any refresh rate from 4 × tREFI to 0.25 × tREFI. When MR4 OP[2:0] = 010b, the only prohibited refresh rate is 4 × tREFI. 122 200b: x32 LPDDR4 SDRAM Refresh Requirement Figure 70: Postponing REFRESH Commands (Example) tREFI 9 tREFI t tRFC 8 REFRESH commands postponed Figure 71: Pulling In REFRESH Commands (Example) tREFI 9 tREFI t tRFC 8 REFRESH commands pulled in Refresh Requirement Between the SRX command and SRE command, at least one extra REFRESH command is required. After the SELF REFRESH EXIT command, in addition to the normal REFRESH command at tREFI interval, the device requires a minimum of one extra REFRESH command prior to the SELF REFRESH ENTRY command. Table 101: Refresh Requirement Parameters Density (per channel) Parameter Symbol 12Gb 16Gb Unit – 8 TBD TBD – (tREFW): tREFW 32 TBD TBD ms Refresh window (tREFW): 1/2 rate refresh tREFW 16 TBD TBD ms Number of banks per channel Refresh window TCASE ≤ 85°C 2Gb 3Gb 123 4Gb 6Gb 8Gb 200b: x32 LPDDR4 SDRAM SELF REFRESH Operation Table 101: Refresh Requirement Parameters (Continued) Density (per channel) Parameter Refresh window 1/4 rate refresh Symbol (tREFW): Required number of REFRESH commands in tREFW window Average refresh interval REFab REFpb 12Gb 16Gb Unit 8 TBD TBD ms R 8192 TBD TBD – tREFI 3.904 TBD TBD μs tREFIpb 488 TBD TBD ns tREFW 2Gb 3Gb 4Gb 6Gb 8Gb REFRESH cycle time (all banks) tRFCab 130 180 280 TBD TBD ns REFRESH cycle time (per bank) tRFCpb 60 90 140 TBD TBD ns Notes: 1. Refresh for each channel is independent of the other channel on the die, or other channels in a package. Power delivery in the user’s system should be verified to make sure the DC operating conditions are maintained when multiple channels are refreshed simultaneously. 2. Self refresh abort feature is available for higher density devices starting with 6Gb density per channel device and tXSR_abort(min) is defined as tRFCpb + 17.5ns. SELF REFRESH Operation Self Refresh Entry and Exit The SELF REFRESH command can be used to retain data in the device without external REFRESH commands. The device has a built-in timer to accommodate SELF REFRESH operation. Self refresh is entered by the SELF REFRESH ENTRY command defined by having CS HIGH, CA0 LOW, CA1 LOW, CA2 LOW, CA3 HIGH, CA4 HIGH, and CA5 valid (valid meaning that it is at a logic level HIGH or LOW) for the first rising edge, and CS LOW, CA0 valid, CA1 valid, CA2 valid, CA3 valid, CA4 valid, and CA5 valid at the second rising edge of clock. The SELF REFRESH command is only allowed when READ DATA burst is completed and the device is in the idle state. During self refresh mode, external clock input is needed and all input pins of the device are activated. The device can accept the following commands: MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2, except PASR bank/segment setting. The device can operate in self refresh mode within the standard and elevated temperature ranges. It also manages self refresh power consumption when the operating temperature changes: lower at low temperatures and higher at high temperatures. For proper SELF REFRESH operation, power supply pins (VDD1, V DD2, and V DDQ) must be at valid levels. V DDQ can be turned off during self refresh with power-down after tCKELCK is satisfied. (Refer to the Self Refresh Entry/Exit Timing with Power-Down Entry/Exit figure.) Prior to exiting self refresh with power-down, V DDQ must be within specified limits. The minimum time that the device must remain in self refresh mode is tSR (MIN). After self refresh exit is registered, only MRR-1, CAS-2, DES, MPC, MRW-1, and MRW-2 except PASR bank/segment setting are allowed until tXSR is satisfied. The use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when self refresh exit is registered. Upon exit from self refresh, it is 124 200b: x32 LPDDR4 SDRAM SELF REFRESH Operation required that at least one REFRESH command (8 per-bank or 1 all-bank) is issued before entry into a subsequent self refresh. This REFRESH command is not included in the count of regular REFRESH commands required by the tREFI interval, and does not modify the postponed or pulled-in refresh counts; the REFRESH command does count toward the maximum refreshes permitted within 2 × tREFI. Figure 72: Self Refresh Entry/Exit Timing T0 T1 T2 T3 T4 T5 T6 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 DES Any command Any command DES DES CK_c CK_t CKE CS CA Valid Valid Valid Valid Valid Valid Valid Valid t SR Command DES SELF REFRESH DES ENTRY Enter self refresh DES DES t XSR DES DES DES SELF REFRESH DES EXIT DES DES Exit self refresh Don’t Care Notes: 1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2 commands (except PASR bank/ segment setting) are allowed during self refresh. 2. DES commands are shown for ease of illustration; other commands may be valid at these times. Power-Down Entry and Exit During Self Refresh Entering/exiting power-down mode is allowed during self refresh mode. The related timing parameters between self refresh entry/exit and power-down entry/exit are shown below. 125 200b: x32 LPDDR4 SDRAM SELF REFRESH Operation Figure 73: Self Refresh Entry/Exit Timing with Power-Down Entry/Exit T0 T1 T2 T3 Ta0 Tb0 Tb1 Tc0 Td1 Te0 Tf0 Tf1 Tg0 Tg1 Th0 Tk0 Tk1 Tk2 Tk3 CK_c Note 2 CK_t t CKE t t CKELCK CKCKEH CKE t CSCKE tCKELCS t CSCKEH t CKEHCS CS t ESCKE t CMDCKE CA Valid Valid Valid t XP Valid Valid Valid t SR Note 3 Command SELFWrite-2 REFRESH Any command MR ENTRY Enter self refresh DES DES DES SELF REFRESH DES EXIT Exit self refresh Don’t Care Notes: 1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2 commands (except PASR bank/ segment setting) are allowed during self refresh. 2. Input clock frequency can be changed, or the input clock can be stopped, or floated after tCKELCK satisfied and during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior to power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use. 3. Two clock command for example. Command Input Timing After Power-Down Exit Command input timings after power-down exit during self refresh mode are shown below. 126 200b: x32 LPDDR4 SDRAM SELF REFRESH Operation Figure 74: Command Input Timings after Power-Down Exit During Self Refresh T0 T1 T2 T3 Ta0 Tb0 Tb1 Tc0 Td1 Te0 Tf0 Tf1 Tg0 Tg1 Th0 Tk0 Tk1 Tk2 Tk3 CK_c Note 2 CK_t t CKE t t CKELCK CKCKEH CKE t CSCKE tCKELCS t CSCKEH t CKEHCS CS t ESCKE t CMDCKE CA Valid Valid Valid t XP Valid Valid Valid t SR Note 3 Note 3 Command SELFWrite-2 REFRESH Any command MR ENTRY Enter self refresh DES DES DES Any command DES Exit self refresh Don’t Care Notes: 1. MRR-1, CAS-2, DES, SRX, MPC, MRW-1, and MRW-2 commands (except PASR bank/ segment setting) are allowed during self refresh. 2. Input clock frequency can be changed or the input clock can be stopped or floated after tCKELCK satisfied and during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior to power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use. 3. Two clock command for example. Self Refresh Abort If MR4 OP[3] is enabled, the device aborts any ongoing refresh during self refresh exit and does not increment the internal refresh counter. The controller can issue a valid command after a delay of tXSR_abort instead of tXSR. The value of tXSR_abort (MIN) is defined as tRFCpb + 17.5ns. Upon exit from self refresh mode, the device requires a minimum of one extra refresh (eight per bank or one for the entire bank) before entering a subsequent self refresh mode. This requirement remains the same irrespective of the setting of the MR bit for self refresh abort. Self refresh abort feature is valid for 6Gb density per channel and larger densities only. MRR, MRW, MPC Commands During tXSR, tRFC MODE REGISTER READ (MRR) command, MODE REGISTER WRITE (MRW) command and MULTI PURPOSE command (MPC) can be issued during tXSR period. 127 200b: x32 LPDDR4 SDRAM SELF REFRESH Operation Figure 75: MRR, MRW, and MPC Commands Issuing Timing During tXSR T0 T1 T2 T3 T4 T5 T6 T7 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 CK_c CK_t CKE CS “H” for case 2 CS CA Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid t MRD Command DES (Case 1) SRX MPC (2 clock command) DES DES DES DES MRW-1 MRW-2 DES DES DES Note 3 DES Any command t MRD Command DES (Case 2) SRX MPC (4 clock command) CAS-2 DES DES MRW-1 MRW-2 DES DES DES Note 3 DES Any command XSR Note 2 t Don’t Care Notes: 1. MPC and MRW commands are shown. Any combination of MRR, MRW, and MPC is allowed during tXSR period. 2. "Any command" includes MRR, MRW, and all MPC commands. MRR, MRW, and MPC can be issued during tRFC period. 128 200b: x32 LPDDR4 SDRAM SELF REFRESH Operation Figure 76: MRR, MRW, and MPC Commands Issuing Timing During tRFC T0 T1 T2 T3 T4 T5 T6 T7 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 CK_c CK_t CKE CS “H” for case 2 CS CA Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid t MRD Command DES REF all bank (Case 1) MPC (2 clock command) DES DES DES DES MRW-1 MRW-2 DES DES DES Note 3 DES Any command t MRD Command DES REF all bank (Case 2) MPC (4 clock command) CAS-2 DES DES MRW-1 MRW-2 DES DES DES Note 3 DES Any command RFCab Note 2 t Don’t Care Notes: 1. MPC and MRW commands are shown. Any combination of MRR, MRW, and MPC is allowed during tRFCab or tRFCpb period. 2. REFRESH cycle time depends on REFRESH command. In the case of per bank REFRESH command issued, REFRESH cycle time will be tRFCpb. 3. "Any command" includes MRR, MRW, and all MPC commands. 129 200b: x32 LPDDR4 SDRAM Power-Down Mode Power-Down Mode Power-Down Entry and Exit Power-down is asynchronously entered when CKE is driven LOW. CKE must not go LOW while the following operations are in progress: • • • • • • • • Mode register read Mode register write Read Write VREF(CA) range and value setting via MRW VREF(DQ) range and value setting via MRW Command bus training mode entering/exiting via MRW VRCG HIGH current mode entering/exiting via MRW CKE can go LOW while any other operations such as row activation, precharge, auto precharge, or refresh are in progress. The power-down I DD specification will not be applied until such operations are complete. Power-down entry and exit are shown below. Entering power-down deactivates the input and output buffers, excluding CKE and RESET_n. To ensure that there is enough time to account for internal delay on the CKE signal path, CS input is required stable LOW level and CA input level is "Don’t Care" after CKE is driven LOW, this timing period is defined as tCKELCS. Clock input is required after CKE is driven LOW, this timing period is defined as tCKELCK. CKE LOW will result in deactivation of all input receivers except RESET_n after tCKELCK has expired. In powerdown mode, CKE must be held LOW; all other input signals except RESET_n are "Don't Care." CKE LOW must be maintained until tCKE(MIN) is satisfied. VDDQ can be turned off during power-down after tCKELCK is satisfied. Prior to exiting power-down, V DDQ must be within its minimum/maximum operating range. No REFRESH operations are performed in power-down mode except self refresh power-down. The maximum duration in non-self-refresh power-down mode is only limited by the refresh requirements outlined in the REFRESH command section. The power-down state is asynchronously exited when CKE is driven HIGH. CKE HIGH must be maintained until tCKE(MIN) is satisfied. A valid, executable command can be applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit latency is defined in the AC timing parameter table. Clock frequency change or clock stop is inhibited during tCMDCKE, tCKELCK, tCKCKEH, tXP, tMRWCKEL, and tZQCKE periods. If power-down occurs when all banks are idle, this mode is referred to as idle powerdown. if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. And If power-down occurs when self refresh is in progress, this mode is referred to as self refresh power-down in which the internal refresh is continuing in the same way as self refresh mode. When CA, CK, and/or CS ODT is enabled via MR11 OP[6:4] and also via MR22 or CAODT pad setting, the rank providing ODT will continue to terminate the command bus in all DRAM states including power-down when V DDQ is stable and within its minimum/maximum operating range. 130 200b: x32 LPDDR4 SDRAM Power-Down Mode The LPDDR4 DRAM cannot be placed in power-down state during start DQS interval oscillator operation. Figure 77: Basic Power-Down Entry and Exit Timing T0 T1 Ta0 Tb0 Tb1 Tc0 CK_c Tc1 Td0 Te0 Te1 Tf0 Tf1 Tg0 Th0 Th1 Th2 Th3 Tk0 Tk1 Tk2 Note 1 CK_t tCKE t CMDCKE t CKELCK t CKE t CKCKEH t XP CKE t CSCKE t CKELCS t CSCKEH t CKEHCS CS CA Valid Valid Command Valid Valid Valid DES DES DES Valid DES DES Don’t Care Note: 1. Input clock frequency can be changed or the input clock can be stopped or floated during power-down, provided that upon exiting power-down, the clock is stable and within specified limits for a minimum of tCKCKEH of stable clock prior to power-down exit and the clock frequency is between the minimum and maximum specified frequency for the speed grade in use. 131 200b: x32 LPDDR4 SDRAM Power-Down Mode Figure 78: Read and Read with Auto Precharge to Power-Down Entry T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 DES DES DES Tc2 Tc3 Tc4 Td0 Td1 CK_c CK_t CKE See Note 2 CS CA Valid Valid Valid Valid Command READ-1 CAS-2 DES DES DES DES DES DES t RL DES DQSCK DQS_c DQS_t t t DQ DMI RPRE RPST DO DO DO DO DO DO n0 n1 n2 n13 n14 n15 Don’t Care Notes: 1. CKE must be held HIGH until the end of the burst operation. 2. Minimum delay time from READ command or READ with AUTO PRECHARGE command to falling edge of CKE signal is as follows: When read postamble = 0.5nCK (MR1 OP[7] = [0]), (RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 1tCK When read postamble = 1.5nCK (MR1 OP[7] = [1]), (RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 2tCK 132 200b: x32 LPDDR4 SDRAM Power-Down Mode Figure 79: Write and Mask Write to Power-Down Entry T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tc0 DES DES DES DES Tc1 Tc2 Td0 Td1 Td2 CK_c CK_t CKE See Note 2 CS CA Command Valid Valid Valid Valid WRITE-1 MASK WRITE-1 CAS-2 DES DES DES WL t DES DES t DQSS WPRE t DES t DQS2DQ DI n0 DI n1 WPST BL/2 t WR DI DI DI DI n2 n13 n14 n15 Don’t Care Notes: 1. CKE must be held HIGH until the end of the burst operation. 2. Minimum delay time from WRITE command or MASK WRITE command to falling edge of CKE signal is as follows: (WL × tCK) + tDQSS(MAX) + tDQS2DQ(MAX) + ((BL/2) × tCK) + tWR 3. This timing is applied regardless of DQ ODT disable/enable setting: MR11 OP[2:0]. 4. This timing diagram only applies to the WRITE and MASK WRITE commands without auto precharge. 133 200b: x32 LPDDR4 SDRAM Power-Down Mode Figure 80: Write With Auto Precharge and Mask Write With Auto Precharge to Power-Down Entry T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 DES DES DES DES DES DES DES Tc4 Td0 CK_c CK_t CKE See Note 2 CS CA Valid Valid Valid Valid Command WRITE-1 MASK WRITE-1 CAS-2 DES DES DES DES WL t DES t DQSS WPRE t DES t DQS2DQ DI n0 DI n1 WPST BL/2 DI DI DI DI n2 n13 n14 n15 Don’t Care Notes: 1. CKE must be held HIGH until the end of the burst operation. 2. Delay time from WRITE with AUTO PRECHARGE command or MASK WRITE with AUTO PRECHARGE command to falling edge of CKE signal is more than (WL × tCK) + tDQSS(MAX) + tDQS2DQ(MAX) + ((BL/2) × tCK) + (nWR × tCK) + (2 × tCK) 3. This timing is applied regardless of DQ ODT disable/enable setting: MR11 OP[2:0]. 134 200b: x32 LPDDR4 SDRAM Power-Down Mode Figure 81: Refresh Entry to Power-Down Entry T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tb10 CK_c CK_t CKE t CMDCKE CS CA Valid Valid Command REFRESH DES DES Don’t Care Note: 1. CKE must be held HIGH until tCMDCKE is satisfied. Figure 82: ACTIVATE Command to Power-Down Entry T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 CK_c CK_t CKE t CMDCKE CS CA Valid Valid Valid Valid Command ACTIVATE-1 ACTIVATE-2 DES DES Don’t Care Note: 1. CKE must be held HIGH until tCMDCKE is satisfied. 135 200b: x32 LPDDR4 SDRAM Power-Down Mode Figure 83: PRECHARGE Command to Power-Down Entry T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tb10 Tb11 CK_c CK_t CKE t CMDCKE CS CA Valid Valid Command PRECHARGE DES DES Don’t Care Note: 1. CKE must be held HIGH until tCMDCKE is satisfied. 136 200b: x32 LPDDR4 SDRAM Power-Down Mode Figure 84: Mode Register Read to Power-Down Entry T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb1 Tb0 Tb2 Tb3 Tc0 Tc1 DES DES DES Tc2 Tc3 Tc4 Td0 Td1 CK_c CK_t CKE See Note 2 CS CA Valid Valid Valid Valid Command MR READ-1 CAS-2 DES DES DES DES DES DES t RL DES DQSCK DQS_c DQS_t t t DQ DMI RPRE RPST DO DO DO DO DO DO n0 n1 n2 n13 n14 n15 Don’t Care Notes: 1. CKE must be held HIGH until the end of the burst operation. 2. Minimum delay time from MODE REGISTER READ command to falling edge of CKE signal is as follows: When read postamble = 0.5nCK ( MR1 OP[7] = [0]), (RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 1tCK When read postamble = 1.5nCK (MR1 OP[7] = [1]), (RL × tCK) + tDQSCK(MAX) + ((BL/2) × tCK) + 2tCK 137 200b: x32 LPDDR4 SDRAM Power-Down Mode Figure 85: Mode Register Write to Power-Down Entry T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 CK_c CK_t CKE t MRWCKEL CS CA Valid Valid Valid Valid Command MR WRITE-1 MR WRITE-2 DES DES DES Don’t Care Notes: 1. CKE must be held HIGH until tMRWCKEL is satisfied. 2. This timing is the general definition for power-down entry after MODE REGISTER WRITE command. When a MODE REGISTER WRITE command changes a parameter or starts an operation that requires special timing longer than tMRWCKEL, that timing must be satisfied before CKE is driven LOW. Changing the VREF(DQ) value is one example, in this case the appropriate tVREF-SHORT/MIDDLE/LONG must be satisfied. 138 200b: x32 LPDDR4 SDRAM Power-Down Mode Figure 86: MULTI PURPOSE Command for ZQCAL Start to Power-Down Entry T0 T1 T2 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tb10 Tb11 CK_c CK_t CKE t ZQCKE CS CA Valid Valid MPC Command [ZQCAL START] DES DES ZQ calibration progresses ZQ Cal Status t ZQCAL Don’t Care Note: 1. ZQ calibration continues if CKE goes LOW after tZQCKE is satisfied. 139 200b: x32 LPDDR4 SDRAM Input Clock Stop and Frequency Change Input Clock Stop and Frequency Change Clock Frequency Change – CKE LOW During CKE LOW, the device supports input clock frequency changes under the following conditions: • • • • tCK(abs) (MIN) is met for each clock cycle Refresh requirements apply during clock frequency change During clock frequency change, only REFab or REFpb commands may be executing Any ACTIVATE or PRECHARGE commands have completed prior to changing the frequency • Related timing conditions, tRCD and tRP, have been met prior to changing the frequency • The initial clock frequency must be maintained for a minimum of tCKELCK after CKE goes LOW • The clock satisfies tCH(abs) and tCL(abs) for a minimum of tCKCKEH prior to CKE going HIGH After the input clock frequency changes and CKE is held HIGH, additional MRW commands may be required to set the WR, RL, and so forth. These settings may require adjustment to meet minimum timing requirements at the target clock frequency. Clock Stop – CKE LOW During CKE LOW, the device supports clock stop under the following conditions: • • • • CK_t and CK_c are don't care during clock stop Refresh requirements apply during clock stop During clock stop, only REFab or REFpb commands may be executing Any ACTIVATE or PRECHARGE commands have completed prior to stopping the clock • Related timing conditions, tRCD and tRP, have been met prior to stopping the clock • The initial clock frequency must be maintained for a minimum of tCKELCK after CKE goes LOW • The clock satisfies tCH(abs) and tCL(abs) for a minimum of tCKCKEH prior to CKE going HIGH Clock Frequency Change – CKE HIGH During CKE HIGH, the device supports input clock frequency change under the following conditions: • • • • tCK(abs) (MIN) is met for each clock cycle Refresh requirements apply during clock frequency change During clock frequency change, only REFab or REFpb commands may be executing Any ACTIVATE, READ, WRITE, PRECHARGE, MODE REGISTER WRITE, or MODE REGISTER READ commands (and any associated data bursts) have completed prior to changing the frequency • Related timing conditions (tRCD, tWR, tRP, tMRW, and tMRR) have been met prior to changing the frequency 140 200b: x32 LPDDR4 SDRAM Input Clock Stop and Frequency Change • During clock frequency change, CS is held LOW • The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 × tCK + tXP After the input clock frequency is changed, additional MRW commands may be required to set the WR, RL, and so forth. These settings may need to be adjusted to meet minimum timing requirements at the target clock frequency. Clock Stop – CKE HIGH During CKE HIGH, the device supports clock stop under the following conditions: • • • • • • • • • CK_t is held LOW and CK_c is held HIGH during clock stop During clock stop, CS is held LOW Refresh requirements apply during clock stop During clock stop, only REFab or REFpb commands may be executing Any ACTIVATE, READ, WRITE, MPC (WRITE-FIFO, READ-FIFO, READ DQ CALIBRATION), PRECHARGE, MODE REGISTER WRITE, or MODE REGISTER READ commands have completed, including any associated data bursts and extra 4 clock cycles must be provided prior to stopping the clock Related timing conditions (tRCD, tWR, tRP, tMRW, tMRR, tZQLAT, and so forth) have been met prior to stopping the clock READ with AUTO PRECHARGE and WRITE with AUTO PRECHARGE commands need extra 4 clock cycles in addition to the related timing constraints, nWR and nRTP, to complete the operations REFab, REFpb, SRE, SRX, and MPC[ZQCAL START] commands are required to have extra 4 clock cycles prior to stopping the clock The device is ready for normal operation after the clock is restarted and satisfies tCH(abs) and tCL(abs) for a minimum of 2 × tCK + tXP 141 200b: x32 LPDDR4 SDRAM MODE REGISTER READ Operation MODE REGISTER READ Operation The MODE REGISTER READ (MRR) command is used to read configuration and status data from the device registers. The MRR command is initiated with CS and CA[5:0] in the proper state as defined by the Command Truth Table. The mode register address operands (MA[5:0]) enable the user to select one of 64 registers. The mode register contents are available on the first four UI data bits of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ following the MRR command. Subsequent data bits contain valid but undefined content. DQS is toggled for the duration of the MODE REGISTER READ burst. The MRR has a command burst length of 16. MRR operation must not be interrupted. Table 102: MRR UI 0 1 2 3 4 5 6 7 8 9 10 DQ0 OP0 V DQ1 OP1 V DQ2 OP2 V DQ3 OP3 V DQ4 OP4 V DQ5 OP5 V DQ6 OP6 V DQ7 OP7 12 13 14 15 V DQ8– DQ15 V DMI0– DMI1 V Notes: 11 1. MRR data are extended to the first 4 UIs, allowing the LPDRAM controller to sample data easily. 2. DBI may apply or may not apply during normal MRR. It’s vendor-specific. If read DBI is enable with MRS and vendor cannot support the DBI during MRR, DMI pin status should be LOW. 3. The read preamble and postamble of MRR are the same as for a normal read. 142 200b: x32 LPDDR4 SDRAM MODE REGISTER READ Operation Figure 87: MODE REGISTER READ Operation T0 T1 T2 T3 MA CAn CAn T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0 Tc1 DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Valid Command MR READ-1 CAS-2 Valid Valid DES DES Valid Valid Any command Any command t MRR t RL DQSCK t BL/2 = 8 RPRE DQS_c DQS_t t t DQSQ OP Code out DQ7:0 RPST Va- Va- Va- Valid lid lid lid Va- Va- Va- Va- Va- Va- Va- Valid lid lid lid lid lid lid lid DQ15:8 DMI1:0 Don’t Care Notes: 1. Only BL = 16 is supported. 2. Only DESELECT is allowed during tMRR period. 3. There are some exceptions about issuing commands after tMRR. Refer to MRR/MRW Timing Constraints Table for detail. 4. DBI is disable mode. 5. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times. 6. DQ/DQS: VSSQ termination MRR After a READ and WRITE Command After a prior READ command, the MRR command must not be issued earlier than BL/2 clock cycles, in a similar way WL + BL/2 + 1 + RU ( tWTR/tCK) clock cycles after a PRIOR WRITE, WRITE with AP, MASK WRITE, MASK WRITE with AP, and MPC[WRITE-FIFO] command in order to avoid the collision of READ and WRITE burst data on device internal data bus. 143 200b: x32 LPDDR4 SDRAM MODE REGISTER READ Operation Figure 88: READ-to-MRR Timing T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 T15 T16 T17 T18 T19 Valid MA CAn CAn T20 T21 T33 T34 T35 T36 T37 T43 DES DES DES DES DES DES DES DES T44 CK_c CK_t CS CA Command READ-1 CAS-2 DES DES MRR-1 CAS-2 RL/2 = 14 BL/2 RL = 14 t DQSCK t t DQSCK BL/2 = 8 BL/2 = 16 RPRE t RPST DQS_c DQS_t t DQSQ t DQSQ Va- Valid lid DQ7:0 DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n2 n3 n26 n27 n28 n29 n30 n31 DQ15:8 DMI1:0 DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT Va- Va- Va- Va- Va- Van0 n1 n2 n3 n26 n27 n28 n29 n30 n31 lid lid lid lid lid lid OP Code out Don’t Care Notes: 1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2. 2. Read BL = 32, MRR BL = 16, RL = 14, Preamble = Toggle, Postamble = 0.5nCK, DBI = Disable, DQ/DQS: VSSQ termination. 3. DOUT n = data-out to column n. 4. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times. 144 200b: x32 LPDDR4 SDRAM MODE REGISTER READ Operation Figure 89: WRITE-to-MRR Timing T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Valid MA CAn CAn Tc5 CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES DES DES WL DES DES DES DES DES t WPRE MRR-1 t BL/2 + 1 clock t DQS_c DES WTR CAS-2 DES t MMR WPST DQS_t t DQ DMI DQS2DQ DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n12 n13 n14 n15 Don’t Care Notes: 1. 2. 3. 4. Write BL=16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination. Only DES is allowed during tMRR period. DOUT n = data-out to column n. The minimum number of clock cycles from the BURST WRITE command to MRR command is WL + BL/2 + 1 + RU(tWTR/tCK). t 5. WTR starts at the rising edge of CK after the last latching edge of DQS. 6. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times. MRR After Power-Down Exit Following the power-down state, an additional time, tMRRI, is required prior to issuing the MODE REGISTER READ (MRR) command. This additional time (equivalent to tRCD) is required in order to maximize power-down current savings by allowing more power-up time for the MRR data path after exit from power-down mode. 145 200b: x32 LPDDR4 SDRAM MODE REGISTER WRITE Figure 90: MRR Following Power-Down T0 Ta0 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td1 Td0 Td2 Td3 Td4 Td5 Td6 Td7 Td8 Td9 CK_c CK_t t CKCKEH CKE t t XP t MRRI MMR CS CA Valid Valid Command DES DES Valid Valid Valid Any command Any command DES DES DES MA MRR-1 DES CAn CAn CAS-2 DES DES DES Don't Care 1. Only DES is allowed during tMRR period. 2. DES commands except tMRR period are shown for ease of illustration; other commands may be valid at these times. Notes: MODE REGISTER WRITE The MODE REGISTER WRITE (MRW) writes configuration data to the mode registers. The MRW command is initiated with CKE, CS, and CA[5:0] to valid levels at the rising edge of the clock. The mode register address and the data written to it is contained in CA[5:0] according to the Command Truth Table. The MRW command period is defined by tMRW. Mode register WRITEs to read-only registers have no impact on the functionality of the device. Figure 91: MODE REGISTER WRITE Timing T0 T1 T2 T3 OPn MA OPn OPn T4 Ta0 Ta1 Ta2 Ta3 Ta4 OPn MA OPn OPn Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Valid Valid Valid Valid Tb5 Tb6 DES DES Tb７ CK_c CK_t CS CA tMRW Command MRW-1 MRW-2 DES DES MRW-1 tMRD MRW-2 DES DES Any command Any command DES Don’t Care 146 200b: x32 LPDDR4 SDRAM MODE REGISTER WRITE Mode Register Write States MRW can be issued from either a bank-idle or a bank-active state. Certain restrictions may apply for MRW from an active state. Table 103: Truth Table for MRR and MRW Current State All banks idle Bank(s) active Command Intermediate State Next State MRR Reading mode register, all banks idle All banks idle MRW Writing mode register, all banks idle All banks idle MRR Reading mode register Bank(s) active MRW Writing mode register Bank(s) active Table 104: MRR/MRW Timing Constraints: DQ ODT is Disable Minimum Delay Between "From Command" and "To Command" Unit MRR tMRR – RD/RDA tMRR From Command To Command MRR WR/WRA/MWR/MWRA MRW RD/RDA RL + + BL/2 -WL + RD(tRPST) RD with AUTO PRECHARGE WR/ MWR/ WR-FIFO WR/MWR with AUTO PRECHARGE nCK nCK BL/2 nCK nCK tMRD – tXP POWER-DOWN EXIT RD/ RD-FIFO/ READ DQ CAL + WL + 1 + BL/2 + RU(tWTR/tCK) MRW MRW tWPRE RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 3 MRR WR/WRA/MWR/ MWRA – RU(tDQSCK(MAX)/tCK) + tMRRI – RD/RDA tMRD – WR/WRA/MWR/MWRA tMRD – MRW tMRW MRW RU(tDQSCK(MAX)/tCK) – RD(tRPST) RL + BL/2 + + MAX(RU(7.5ns/tCK), 8nCK) + nCK RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + MAX(RU(7.5ns/tCK), 8nCK) + nRTP - 8 nCK WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) nCK WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) + nWR nCK 147 Notes 200b: x32 LPDDR4 SDRAM VREF Current Generator (VRCG) Table 105: MRR/MRW Timing Constraints: DQ ODT is Enable Minimum Delay Between "From Command" and "To Command" Unit MRR tMRR – RD/RDA tMRR – From Command To Command MRR WR/WRA/MWR/MWRA RD/RDA RU(tDQSCK(MAX)/tCK) + BL/2 - ODTLon RL + RD(tODTon(MIN)/tCK) + RD(tRPST) + 1 RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 3 nCK MRR BL/2 nCK WL + 1 + BL/2 + RU(tWTR/tCK) nCK tMRD – MRW tXP POWER-DOWN EXIT MRW RD/ RD-FIFO/ READ DQ CAL nCK MRW WR/WRA/MWR/ MWRA + tMRRI – RD/RDA tMRD – WR/WRA/MWR/MWRA tMRD – MRW tMRW RU(tDQSCK(max)/tCK) MRW – RD(tRPST) RL + BL/2 + + MAX(RU(7.5ns/tCK), 8nCK) RD with AUTO PRECHARGE WR/ MWR/ WR-FIFO WR/MWR with AUTO PRECHARGE Notes + nCK RL + BL/2 + RU(tDQSCK(MAX)/tCK) + RD(tRPST) + MAX(RU(7.5ns/tCK), 8nCK) + nRTP - 8 nCK WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) nCK WL + 1 + BL/2 + MAX(RU(7.5ns/tCK), 8nCK) + nWR nCK VREF Current Generator (VRCG) LPDDR4 SDRAM V REF current generators (VRCG) incorporate a high current mode to reduce the settling time of the internal V REF(DQ) and V REF(CA) levels during training and when changing frequency set points during operation. The high current mode is enabled by setting MR13[OP3] = 1. Only DESELECT commands may be issued until tVRCG_ENABLE is satisfied. tVRCG_ENABLE timing is shown below. 148 200b: x32 LPDDR4 SDRAM VREF Current Generator (VRCG) Figure 92: VRCG Enable Timing T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 DES DES Valid Valid Valid Valid DES DES Valid Valid Valid Valid DES DES DES DES DES DES DES DES CK_c CK_t CKE CS CA DES MRW1 MRW1 MRW2 MRW2 Command DES VRCG enable: MR13 [OP3] = 1 t Valid Valid VRCG_ENABLE VRCG high current mode is disabled by setting MR13[OP3] = 0. Only DESELECT commands may be issued until tVRCG_DISABLE is satisfied. tVRCG_DISABLE timing is shown below. Figure 93: VRCG Disable Timing T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 CA DES Valid Valid Valid Valid DES DES MRW1 MRW1 MRW2 MRW2 Command DES DES DES VRCG disable: MR13 [OP3] = 0 Ta5 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 DES DES Valid Valid Valid Valid DES DES DES DES DES DES CK_c CK_t CKE CS Valid t Valid VRCG_DISABLE Note that LPDDR4 SDRAM devices support V FER(CA) and V REF(DQ) range and value changes without enabling VRCG high current mode. Table 106: VRCG Enable/Disable Timing Parameter Symbol Min Max VREF high current mode enable time tVRCG_ENABLE – 200 ns VREF high current mode disable time tVRCG_DISABLE – 100 ns 149 Unit 200b: x32 LPDDR4 SDRAM VREF Training VREF Training VREF(CA) Training The device's internal V REF(CA) specification parameters are operating voltage range, step size, V REF step time, V REF full-range step time, and V REF valid level. The voltage operating range specifies the minimum required V REF setting range for LPDDR4 devices. The minimum range is defined by V REF,max and V REF,min. Figure 94: VREF Operating Range (VREF,max, VREF,min) VDD2 VIN(DC)max VREF,max VREF range VREF,min VIN(DC)min VSWING large System variance VSWING small Total range The V REF step size is defined as the step size between adjacent steps. However, for a given design, the device has one value for V REF step size that falls within the given range. The V REF set tolerance is the variation in the V REF voltage from the ideal setting. This accounts for accumulated error over multiple steps. There are two ranges for V REF set tolerance uncertainty. The range of V REF set tolerance uncertainty is a function of the number of steps n. The V REF set tolerance is measured with respect to the ideal line that is based on the two endpoints, where the endpoints are at the minimum and maximum V REF values for a specified range. 150 200b: x32 LPDDR4 SDRAM VREF Training Figure 95: VREF Set-Point Tolerance and Step Size VREF level Actual VREF output VREF set-point tolerance Straight line endpoint fit VREF step size VREF step setting The V REF increment/decrement step times are defined by tVREF_TIME-SHORT, t REF_TIME-MIDDLE, and VREF_TIME-LONG. The parameters are defined from TS to TE as shown below, where TE is referenced to when the V REF voltage is at the final DC level within the V REF valid tolerance (VREF,val_tol). tV The V REF valid level is defined by V REF,val_tol to qualify the step time TE (see the following figures). This parameter is used to ensure an adequate RC time constant behavior of the voltage level change after any V REF increment/decrement adjustment. This parameter is only applicable for LPDDR4 component level validation/characterization. tV REF_TIME-SHORT is for a single step size increment/decrement change in the V REF voltage. tV REF_TIME-MIDDLE is at least two stepsizes increment/decrement change within the same V REF(CA) range in V REF voltage. tV REF_TIME-LONG is the time including up to V REF,min to V REF,max or V REF,max to V REF,min change across the V REF(CA) range in V REF voltage. TS is referenced to MRW command clock. TE is referenced to V REF_val_tol. 151 200b: x32 LPDDR4 SDRAM VREF Training Figure 96: tVref for Short, Middle, and Long Timing Diagram T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 CK_c CK_t CKE CS CA DES MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES Command DES VRFF(CA) value/range set DES DES DES DES DES DES DES DES DES DES DES DES DES DES VREF_time – short/middle/long New VREF setting Updating VRFF(CA) setting Old VREF setting TS VREF setting adjustment TE The MRW command to the mode register bits are as follows; MR12 OP[5:0] : V REF(CA) Setting MR12 OP[6] : V REF(CA) Range The minimum time required between two V REF MRW commands is tVREF_TIME-SHORT for a single step and tVREF_TIME-MIDDLE for a full voltage range step. Figure 97: VREF(CA) Single-Step Increment VREF voltage VREF(DC) VREF_val_tol step size t1 Time 152 200b: x32 LPDDR4 SDRAM VREF Training Figure 98: VREF(CA) Single-Step Decrement VREF voltage t1 stepsize VREF_val_tol VREF(DC) Time Figure 99: VREF(CA) Full Step from VREF,min to VREF,max VREF voltage VREF(DC) VREF,max VREF_val_tol Full range step t1 VREF,min Time Figure 100: VREF(CA) Full Step from VREF,max to VREF,min VREF VREF,max voltage Full range step t1 VREF_val_tol VREF,min VREF(DC) Time The following table contains the CA internal V REF specification that will be characterized at the component level for compliance. 153 200b: x32 LPDDR4 SDRAM VREF Training Table 107: Internal VREF(CA) Specifications Min Typ Max Unit Notes VREF(CA),max_r0 Symbol VREF(CA) range-0 MAX operating point – – 30% VDD2 1, 11 VREF(CA),min_r0 VREF(CA) range-0 MIN operating point 10% – – VDD2 1, 11 VREF(CA),max_r1 VREF(CA) range-1 MAX operating point – – 42% VDD2 1, 11 VREF(CA),min_r1 VREF(CA) range-1 MIN operating point 22% – – VDD2 1, 11 VREF(CA) step size 0.30% 0.40% 0.50% VDD2 2 VREF(CA) set tolerance –1.00% 0.00% 1.00% VDD2 3, 4, 6 –0.10% 0.00% 0.10% VDD2 3, 5, 7 VREF(CA),step VREF(CA),set_tol tV REF_TIME-SHORT Parameter – – 100 ns 8 tV REF_TIME-MIDDLE – – 200 ns 12 tV REF_TIME-LONG – – 250 ns 9 tV REF_time_weak – – 1 ms 13, 14 –0.10% 0.00% 0.10% VDD2 10 VREF(CA)_val_tol VREF(CA) step time VREF(CA) valid tolerance Notes: 1. VREF(CA) DC voltage referenced to VDD2(DC). 2. VREF(CA) step size increment/decrement range. VREF(CA) at DC level. 3. VREF(CA),new = VREF(CA),old + n × VREF(CA),step; n = number of steps; if increment, use "+"; if decrement, use "–". 4. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 1.0% × VDD2. The maximum value of VREF(CA) setting tolerance = VREF(CA),new + 1.0% × VDD2. For n > 4. 5. The minimum value of VREF(CA) setting tolerance = VREF(CA),new - 0.10% × VDD2. The maximum value of VREF(CA) setting tolerance = VREF(CA),new + 0.10% × VDD2. For n < 4. 6. Measured by recording the minimum and maximum values of the VREF(CA) output over the range, drawing a straight line between those points and comparing all other VREF(CA) output settings to that line. 7. Measured by recording the minimum and maximum values of the VREF(CA) output across four consecutive steps (n = 4), drawing a straight line between those points and comparing all other VREF(CA) output settings to that line. 8. Time from MRW command to increment or decrement one step size for VREF(CA) . 9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to VREF,min change across the VREF(CA) range in VREF voltage. 10. Only applicable for DRAM component level test/characterization purposes. Not applicable for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level. 11. DRAM range-0 or range-1 set by MR12 OP[6]. 12. Time from MRW command to increment or decrement more than one step size up to a full range of VREF voltage within the same VREF(CA) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0b. 14. tVREF_time_weak covers all VREF(CA) range and value change conditions are applied to tV REF_TIME-SHORT/MIDDLE/LONG. 154 200b: x32 LPDDR4 SDRAM VREF Training VREF(DQ) Training The device's internal V REF(DQ) specification parameters are operating voltage range, step size, V REF step tolerance, V REF step time and V REF valid level. The voltage operating range specifies the minimum required V REF setting range for LPDDR4 devices. The minimum range is defined by V REF,max and V REF,min. Figure 101: VREF Operating Range (VREF,max, VREF,min) VDDQ VIN(DC)max VREF,max VREF range VREF,min VIN(DC)min VSWING large System variance VSWING small Total range The V REF step size is defined as the step size between adjacent steps. However, for a given design, the device has one value for V REF step size that falls within the given range. The V REF set tolerance is the variation in the V REF voltage from the ideal setting. This accounts for accumulated error over multiple steps. There are two ranges for V REF set tolerance uncertainty. The range of V REF set tolerance uncertainty is a function of the number of steps n. The V REF set tolerance is measured with respect to the ideal line that is based on the two endpoints, where the endpoints are at the minimum and maximum V REF values for a specified range. 155 200b: x32 LPDDR4 SDRAM VREF Training Figure 102: VREF Set Tolerance and Step Size VREF level Actual VREF output VREF set-point tolerance Straight line endpoint fit VREF step size VREF step setting The V REF increment/decrement step times are defined by tVREF_TIME-SHORT, t t t REF_TIME-MIDDLE and VREF_TIME-LONG. The VREF_TIME-SHORT, VREF_TIMEt MIDDLE and VREF_TIME-LONG times are defined from TS to TE in the following figure where TE is referenced to when the V REF voltage is at the final DC level within the V REF valid tolerance (VREF,VAL_TOL). tV The V REF valid level is defined by V REF,VAL_TOL to qualify the step time TE (see the figure below). This parameter is used to ensure an adequate RC time constant behavior of the voltage level change after any V REF increment/decrement adjustment. This parameter is only applicable for DRAM component level validation/characterization. tV REF_TIME-SHORT is for a single step size increment/decrement change in the V REF voltage. tV REF_TIME-MIDDLE is at least two step sizes of increment/decrement change in the VREF(DQ) range in the V REFvoltage. tV REF_TIME-LONG is the time including and up to the full range of V REF (MIN to MAX or MAX to MIN) across the V REF(DQ) range in V REF voltage. 156 200b: x32 LPDDR4 SDRAM VREF Training Figure 103: VREF(DQ) Transition Time for Short, Middle, or Long Changes T0 T1 T2 T3 T4 T5 Ta Ta+1 Ta+2 Ta+3 Ta+4 Ta+5 Ta+6 Ta+7 Ta+8 Ta+9 T+10 T+11 T+12 CK_c CK_t CKE CS CA[5:0] DES MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES Command DES VREF(DQ) value/range set DES DES DES DES DES DES DES DES DES DES DES DES DES DES VREF_time – short/middle/long VREF Old VREF setting Updating VREF(DQ) setting New VREF setting TS VREF setting adjustment Notes: TE 1. TS is referenced to MRW command clock. 2. TE is referenced to VREF,VAL_TOL. The MRW command to the mode register bits are defined as: MR14 OP[5:0]: V REF(DQ) setting MR14 OP[6]: V REF(DQ) range The minimum time required between two V REF MRW commands is tVREF_TIME-SHORT for a single step and tVREF_TIME-MIDDLE for a full voltage range step. Figure 104: VREF(DQ) Single-Step Size Increment VREF voltage VREF(DC) VREF_val_tol step size t1 Time 157 200b: x32 LPDDR4 SDRAM VREF Training Figure 105: VREF(DQ) Single-Step Size Decrement VREF voltage t1 stepsize VREF_val_tol VREF(DC) Time Figure 106: VREF(DQ) Full Step from VREF,min to VREF,max VREF voltage VREF(DC) VREF,max VREF_val_tol Full range step t1 VREF,min Time Figure 107: VREF(DQ) Full Step from VREF,max to VREF,min VREF VREF,max voltage Full range step t1 VREF_val_tol VREF,min VREF(DC) Time The following table contains the DQ internal V REF specification that will be characterized at the component level for compliance. 158 200b: x32 LPDDR4 SDRAM VREF Training Table 108: Internal VREF(DQ) Specifications Min Typ Max Unit Notes VREF(DQ),max_r0 Symbol VREF MAX operating point Range-0 – – 30% VDDQ 1, 11 VREF(DQ),min_r0 VREF MIN operating point Range-0 10% – – VDDQ 1, 11 VREF(DQ),max_r1 VREF MAX operating point Range-1 – – 42% VDDQ 1, 11 VREF(DQ),min_r1 VREF MIN operating point Range-1 22% – – VDDQ 1, 11 VREF(DQ) step size 0.30% 0.40% 0.50% VDDQ 2 VREF(DQ) set tolerance –1.00% 0.00% 1.00% VDDQ 3, 4, 6 –0.10% 0.00% 0.10% VDDQ 3, 5, 7 – – 100 ns 8 – – 200 ns 12 REF_TIME-LONG – – 250 ns 9 tV – – 1 ms 13, 14 –0.10% 0.00% 0.10% VDDQ 10 VREF(DQ),step VREF(DQ),set_tol tV tV REF_TIME-SHORT Parameter VREF(DQ) step time REF_TIME-MIDDLE tV REF_time_weak VREF(DQ),val_tol VREF(DQ) valid tolerance Notes: 1. VREF(DQ) DC voltage referenced to VDDQ(DC). 2. VREF(DQ) step size increment/decrement range. VREF(DQ) at DC level. 3. VREF(DQ),new = VREF(DQ),old + n × VREF(DQ),step; n = number of steps; if increment, use "+"; if decrement, use "–". 4. The minimum value of VREF(DQ) setting tolerance = VREF(DQ),new - 1.0% × VDDQ. The maximum value of VREF(DQ) setting tolerance = VREF(DQ),new + 1.0% × VDDQ. For n > 4. 5. The minimum value of VREF(DQ)setting tolerance = VREF(DQ),new - 0.10% × VDDQ. The maximum value of VREF(DQ) setting tolerance = VREF(DQ),new + 0.10% × VDDQ. For n < 4. 6. Measured by recording the minimum and maximum values of the VREF(DQ) output over the range, drawing a straight line between those points and comparing all other VREF(DQ) output settings to that line. 7. Measured by recording the minimum and maximum values of the VREF(DQ) output across four consecutive steps (n = 4), drawing a straight line between those points and comparing all other VREF(DQ) output settings to that line. 8. Time from MRW command to increment or decrement one step size for VREF(DQ) . 9. Time from MRW command to increment or decrement VREF,min to VREF,max or VREF,max to VREF,min change across the VREF(DQ) Range in VREF(DQ) Voltage. 10. Only applicable for DRAM component level test/characterization purposes. Not applicable for normal mode of operation. VREF valid is to qualify the step times which will be characterized at the component level. 11. DRAM range-0 or range-1 set by MR14 OP[6]. 12. Time from MRW command to increment or decrement more than one step size up to a full range of VREF voltage within the same VREF(DQ) range. 13. Applies when VRCG high current mode is not enabled, specified by MR13 [OP3] = 0. 14. tVREF_time_weak covers all VREF(DQ) Range and Value change conditions are applied to tV REF_TIME-SHOR/MIDDLE/LONG. 159 200b: x32 LPDDR4 SDRAM Command Bus Training Command Bus Training Command Bus Training Mode The command bus must be trained before enabling termination for high-frequency operation. The device provides an internal V REF(CA) that defaults to a level suitable for unterminated, low-frequency operation, but the V REF(CA) must be trained to achieve suitable receiver voltage margin for terminated, high-frequency operation. The training mode described here centers the internal V REF(CA) in the CA data eye and at the same time allows for timing adjustments of the CS and CA signals to meet setup/ hold requirements. Because it can be difficult to capture commands prior to training the CA inputs, the training mode described here uses a minimum of external commands to enter, train, and exit the CA bus training mode. The die has a bond-pad (ODT_CA) to control the command bus termination for multirank operation. Other mode register bits are provided to fine tune termination control in a variety of system configuration. See On-Die Termination for more information. The device uses frequency set points to enable multiple operating settings for the die. The device defaults to FSP-OP[0] at power-up, which has the default settings to operate in un-terminated, low-frequency environments. Prior to training, the termination should be enabled for one die in each channel by setting MR13 OP[6] = 1b (FSP-WR[1]) and setting all other mode register bits for FSP-OP[1] to the desired settings for highfrequency operation. Upon training entry, the device will automatically switch to FSPOP[1] and use the high-frequency settings during training (See the Command Bus Training Entry Timing figure for more information on FSP-OP register sets). Upon training exit, the device will automatically switch back to FSP-OP[0], returning to a "knowngood" state for unterminated, low-frequency operation. To enter command bus training mode, issue a MRW-1 command followed by a MRW-2 command to set MR13 OP[0] = 1b (command bus training mode enabled). After time tMRD, CKE may be set LOW, causing the device to switch to FSP-OP[1], and completing the entry into command bus training mode. A status DQS_t, DQS_c, DQ, and DMI are as noted below; the DQ ODT state will be followed by FREQUENCY SET POINT function except in the case of output pins. • • • • • DQS_t[0], DQS_c[0] become input pins for capturing DQ[6:0] levels by toggling. DQ[5:0] become input pins for setting V REF(CA) level. DQ[6] becomes an input pin for setting V REF(CA) range. DQ[7] and DMI[0] become input pins, and their input level is valid or floating. DQ[13:8] become output pins to feedback, capturing value via the command bus using the CS signal. • DQS_t[1], DQS_c[1], DMI[1], and DQ[15:14] become output pins or are disabled, meaning the device may be driven to a valid level or may be left floating. At time tCAENT later, the device may change its V REF(CA) range and value using input signals DQS_t[0], DQS_c[0], and DQ[6:0] from existing value that is set via MR12 OP[6:0]. The mapping between MR12 OP code and DQs is shown below. At least one VREF(CA) setting is required before proceeding to the next training step. 160 200b: x32 LPDDR4 SDRAM Command Bus Training Table 109: Mapping MR12 Op Code and DQ Numbers Mapping MR12 OP code OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQ number DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 The new V REF(CA) value must "settle" for time tVREFCA_Long before attempting to latch CA information. Note: If DQ ODT is enabled in MR11-OP[2:0], then the SDRAM will terminate the DQ lanes during command bus training when entering V REF(CA) range and values on DQ[6:0]. To verify that the receiver has the correct V REF(CA) setting, and to further train the CA eye relative to clock (CK), values latched at the receiver on the CA bus are asynchronously output to the DQ bus. To exit command bus training mode, drive CKE HIGH, and after time tVREFCA_Long, issue the MRW-1 command followed by the MRW-2 command to set MR13 OP[0] = 0b. After time tMRW, the device is ready for normal operation. After training exit, the device will automatically switch back to the FSP-OP registers that were in use prior to training. Command bus training (CBT) may be executed from the idle or self refresh state. When executing CBT within the self refresh state, the device must not be in a power-down state (for example, CKE must be HIGH prior to training entry). CBT entry and exit is the same, regardless of the state from which CBT is initiated. Training Sequence for Single-Rank Systems The sequence example shown here assumes an initial low-frequency, non-terminating operating point training a high-frequency, terminating operating point. The bold text shows high-frequency instructions. Any operating point may be trained from any known good operating point. 1. Set MR13 OP[6] = 1b to enable writing to frequency set point 1 (FSP-WR[1]) (or FSP-OP[0]). 2. Write FSP-WR[1] (or FSP-WR[0]) registers for all channels to set up high-frequency operating parameters. 3. Issue MRW-1 and MRW-2 commands to enter command bus training mode. 4. Drive CKE LOW, and change CK frequency to the high-frequency operating point. 5. Perform command bus training (VREF(CA), CS, and CA). 6. Exit training by driving CKE HIGH, change CK frequency to the low-frequency operating point, and issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the device will automatically switch back to the FSP-OP registers that were in use prior to training (trained values are not retained). 7. Write the trained values to FSP-WR[1] (or FSP-WR[0]) by issuing MRW-1 and MRW-2 commands to the SDRAM and setting all applicable mode register parameters. 8. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1] (or FSP-OP[0]), to turn on termination, and change CK frequency to the high-frequency operating point. At this point the command bus is trained and you may proceed to other training or normal operation. 161 200b: x32 LPDDR4 SDRAM Command Bus Training Training Sequence for Multiple-Rank Systems The sequence example shown here is assuming an initial low-frequency operating point, training a high-frequency operating point. The bold text shows high-frequency instructions. Any operating point may be trained from any known good operating point. 1. Set MR13 OP[6] = 1b to enable writing to frequency set point 1 (FSP-WR[1]) (or FSP-WR[0]). 2. Write FSP-WR[1] (or FSP-WR[0]) registers for all channels and ranks to set up high-frequency operating parameters. 3. Read MR0 OP[7] on all channels and ranks to determine which die are terminating, signified by MR0 OP[7] = 1b. 4. Issue MRW-1 and MRW-2 commands to enter command bus training mode on the terminating rank. 5. Drive CKE LOW on the terminating rank (or all ranks), and change CK frequency to the high-frequency operating point. 6. Perform command bus training on the terminating rank (VREF(CA), CS, and CA). 7. Exit training by driving CKE HIGH, change CK frequency to the low-frequency operating point, and issue MRW-1 and MRW-2 commands to write the trained values to FSP-WR[1] (or FSP-WR[0]). When CKE is driven HIGH, the SDRAM will automatically switch back to the FSP-OP registers that were in use prior to training (trained values are not retained by the device). 8. Issue MRW-1 and MRW-2 commands to enter training mode on the non-terminating rank (but keep CKE HIGH). 9. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1] (or FSP-OP[0]), to turn on termination, and change CK frequency to the high-frequency operating point. 10. Drive CKE LOW on the non-terminating (or all) ranks. The non-terminating rank(s) will now be using FSP-OP[1] (or FSP-OP[0]). 11. Perform command bus training on the non-terminating rank (VREF(CA), CS, and CA). 12. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSPOP[0] (or FSP-OP[1]) to turn off termination. 13. Exit training by driving CKE HIGH on the non-terminating rank, change CK frequency to the low-frequency operating point, and issue MRW-1 and MRW-2 commands. When CKE is driven HIGH, the device will automatically switch back to the FSP-OP registers that were in use prior to training (that is, trained values are not retained by the device). 14. Write the trained values to FSP-WR[1] (or FSP-WR[0]) by issuing MRW-1 and MRW-2 commands and setting all applicable mode register parameters. 15. Issue MRW-1 and MRW-2 commands to switch the terminating rank to FSP-OP[1] (or FSP-OP[0]), to turn on termination, and change CK frequency to the high-frequency operating point. At this point the command bus is trained for both ranks and the user may proceed to other training or normal operation. 162 200b: x32 LPDDR4 SDRAM Command Bus Training Relation Between CA Input Pin and DQ Output Pin Table 110: Mapping of CA Input Pin and DQ Output Pin Mapping CA number CA5 CA4 CA3 CA2 CA1 CA0 DQ number DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 Figure 108: Command Bus Training Mode Entry – CA Training Pattern I/O with VREF(CA) Value Update T0 T1 T2 T3 T4 T5 Ta Tb Tb+1 Tc See Note 1 Td Te Te+1 Te+2 Tf Tg Th Th+1 Th+2 CK_c CK_t tCKPRECS See Note 7 tCKPSTCS See Note 2 CKE tMRD tCKELCK See Note 3 tCACD CS CA DES MRW1 MRW1 MRW2 MRW2 DES DES DES DES Valid DES Valid CA training pattern B Command DES Enter command bus training mode DES DES DES DES CA training pattern A DES tDQSCKE tVREFCA_Long tCAENT (see Note 5) tADR See Note 4 DQS0_t DQS0_c tDS,train tDH,train Valid DQ[6:0] DQ7 DMI0 DQ[13:8] Pattern A DQ[15:14] DMI1 DQS1_t DQS1_c VREF(CA) (reference) Setting value of MR X (Y) Updating setting from FSP switching tCKELODTon ODT_CA (reference) Mode register X (Y) Updating setting Temporary setting value (see Note 6) Switching MR Mode register X (Y) Don’t Care Notes: 1. After tCKELCK, the clock can be stopped or the frequency changed any time. 2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS. 3. Continue to drive CK, and hold CA and CS LOW, until tCKELCK after CKE is LOW (which disables command decoding). 4. The device may or may not capture the first rising edge of DQS_t/DQS_c due to an unstable first rising edge. Therefore, at least two consecutive pulses of DQS signal input is required every for DQS input signal while capturing DQ[6:0] signals. The captured value of the DQ[6:0] signal level by each DQS edge may be overwritten at any time and the device will temporarily update the VREF(CA) setting of MR12 after time tVREFCA_Long. 5. tVREFCA_Long may be reduced to tVREFCA_Short if the following conditions are met: 1) The new VREF setting is a single step above or below the old VREF setting; 2) The DQS pulses a single time, or the new VREF setting value on DQ[6:0] is static and meets tDS,train/ tDH,train for every DQS pulse applied. 163 200b: x32 LPDDR4 SDRAM Command Bus Training 6. When CKE is driven LOW, the device will switch its FSP-OP registers to use the alternate (non-active) set. For example, if the device is currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be written to the alternate mode registers before entering command bus training to ensure that ODT settings, RL/WL/nWR setting, and so forth, are set to the correct values. If the alternate FSP-OP has ODT_CA disabled, then termination will not be enabled in command bus training mode. If the ODT_CA pad is bonded to VSS or floating, ODT_CA termination will never enable for that die. 7. When CKE is driven LOW in command bus training mode, the device will change operation to the alternate FSP, that is, the inverse of the FSP programmed in the FSP-OP mode register. Figure 109: Consecutive VREF(CA) Value Update T0 Ta Tb Tb+1 Tc See Note 1 Td Te Te+1 Te+2 Te+3 Te+4 Te+5 Te+6 Te+7 Te+8 Te+9 Te+10 Tf Tf+1 Tf+2 Tf+3 CK_c CK_t tCKELCK (see Note 2) See Note 7 CKE tCKELCK (see Note 3) CS CA DES DES Command DES DES DES DES DES DES DES DES tDQSCKE Valid CA training pattern A tVREFCA_Long tCAENT (see Note 5) tCS_VREF See Note 4 tVREFCA_Long (see Note 5) See Note 4 DQS0_t DQS0_c tDS,train tDH,train tDS,train Valid Valid DQ[6:0] tDH,train DQ7 DMI0 tADR DQ[13:8] Pattern A DQ[15:14] DMI1 DQS1_t DQS1_c VREF(CA) (reference) Setting value of MR X (Y) Updating setting from FSP switching tCKELODTon ODT_CA (reference) Mode register X (Y) Updating setting Temporary setting value Updating setting (see Note 6) Switching MR Mode register X (Y) Don’t Care Notes: 1. After tCKELCK, the clock can be stopped or the frequency changed any time. 2. The input clock condition should be satisfied tCKPRECS and tCKPSTCS. 3. Continue to drive CK, and hold CA and CS LOW, until tCKELCK after CKE is LOW (which disables command decoding). 4. The device may or may not capture the first rising edge of DQS_t/DQS_c due to an unstable first rising edge. Therefore, at least two consecutive pulses of DQS signal input is required every for DQS input signal while capturing DQ[6:0] signals. The captured value of the DQ[6:0] signal level by each DQS edge may be overwritten at any time and the device will temporarily update the VREF(CA) setting of MR12 after time tVREFCA_Long. 5. tVREFCA_Long may be reduced to tVREFCA_Short if the following conditions are met: 1) The new VREF setting is a single step above or below the old VREF setting; 2) The DQS 164 200b: x32 LPDDR4 SDRAM Command Bus Training pulses a single time, or the new VREF setting value on DQ[6:0] is static and meets tDS,train/ tDH,train for every DQS pulse applied. 6. When CKE is driven LOW, the device will switch its FSP-OP registers to use the alternate (non-active) set. For example, if the device is currently using FSP-OP[0], then it will switch to FSP-OP[1] when CKE is driven LOW. All operating parameters should be written to the alternate mode registers before entering command bus training to ensure that ODT settings, RL/WL/nWR setting, and so forth, are set to the correct values. If the alternate FSP-OP has ODT_CA disabled, then termination will not be enabled in command bus training mode. If the ODT_CA pad is bonded to VSS or floating, ODT_CA termination will never enable for that die. 7. When CKE is driven LOW in command bus training mode, the device will change operation to the alternate FSP, that is, the inverse of the FSP programmed in the FSP-OP mode register. Figure 110: Command Bus Training Mode Exit with Valid Command T0 T1 T2 Ta Ta+1 Ta+2 Tb Tc Td Td+1 Te Te+1 Tf Tf+1 Tf+2 Tf+3 Tf+4 Tg Tg+1 Tg+2 Tg+3 Tg+4 Tg+5 Valid Valid Valid DES CK_c CK_t tCPSTCS See Note 5 CKE tCACD tCCKCKEH tFC (see Note 1) tMRW CS See Note 2 CA Valid Command Valid Valid Valid tADR tADR DES DES DES DES DES DES DES DES DES DES DES DES MRW1 MRW1 MRW2 MRW2 Exiting command bus training mode DES DES Valid Valid DES tCKEHDQS DQS0_t DQS0_c DQ[6:0] DQ7 DMI0 tMRZ DQ[13:8] Pattern A Pattern B DQ[15:14] DMI1 DQS1_t DQS1_c VREF(CA) (reference) Pattern C See Note 4 Temporary setting value Switching MR tCKELODToff ODT_CA (reference) Mode register X (Y) Setting value of MR X (Y) (see Note 3) Switching MR Mode register X (Y) Don’t Care Notes: 1. The clock can be stopped or the frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven HIGH. When CKE is driven HIGH, the clock frequency must be returned to the original frequency (that is, the frequency corresponding to the FSP at command bus training mode entry. 2. CS and CA[5:0] must be deselected (LOW) tCKCKEH before CKE is driven HIGH. 3. When CKE is driven HIGH, ODT_CA will revert to the state/value defined by FSP-OP prior to command bus training mode entry, that is, the original frequency set point (FSP-OP, MR13-OP[7]). For example, if the device was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH. 165 200b: x32 LPDDR4 SDRAM Command Bus Training 4. Training values are not retained by the device and must be written to the FSP-OP register set before returning to operation at the trained frequency. For example, VREF(CA) will return to the value programmed in the original set point. 5. When CKE is driven HIGH, the device will revert to the FSP in operation at command bus training mode entry. Figure 111: Command Bus Training Mode Exit with Power-Down Entry T0 T1 T2 Ta Ta+1 Ta+2 Tb Tc Td Td+1 Te Te+1 Tf Tf+1 Tf+2 Tf+3 Tf+4 Tg Tg+1 Tg+2 Tg+3 Th Tk CK_c CK_t tCPSTCS tCKELCK See Note 5 CKE tCACD tCCKCKEH tFC (see Note 1) tMRD tCKELCMD CS See Note 2 CA Valid Valid CA Pattern B CA Pattern C Command tADR tADR DES DES DES DES DES DES DES DES DES DES DES DES MRW1 MRW1 MRW2 MRW2 Exiting command bus training mode DES Valid Valid DES DES DES Power-down entry DES DES tCKEHDQS DQS0_t DQS0_c DQ[6:0] DQ7 DMI0 tMRZ DQ[13:8] Pattern A Pattern B DQ[15:14] DMI1 DQS1_t DQS1_c VREF(CA) (reference) Pattern C See Note 4 Temporary setting value Switching MR tCKEHODToff ODT_CA (reference) Mode register X (Y) Setting value of MR X (Y) (see Note 3) Switching MR Mode register X (Y) Don’t Care Notes: 1. The clock can be stopped or the frequency changed any time before tCKCKEH. CK must meet tCKCKEH before CKE is driven HIGH. When CKE is driven HIGH, the clock frequency must be returned to the original frequency (that is, the frequency corresponding to the FSP at command bus training mode entry. 2. CS and CA[5:0] must be deselected (LOW) tCKCKEH before CKE is driven HIGH. 3. When CKE is driven HIGH, ODT_CA will revert to the state/value defined by FSP-OP prior to command bus training mode entry, that is, the original frequency set point (FSP-OP, MR13-OP[7]). For example, if the device was using FSP-OP[1] for training, then it will switch to FSP-OP[0] when CKE is driven HIGH. 4. Training values are not retained by the device and must be written to the FSP-OP register set before returning to operation at the trained frequency. For example, VREF(CA) will return to the value programmed in the original set point. 5. When CKE is driven HIGH, the device will revert to the FSP in operation at command bus training mode entry. 166 200b: x32 LPDDR4 SDRAM Write Leveling Write Leveling Mode Register Write-WR Leveling Mode To improve signal-integrity performance, the device provides a write leveling feature to compensate for CK-to-DQS timing skew, affecting timing parameters such as tDQSS, tDSS, and tDSH. The memory controller uses the write leveling feature to receive feedback from the device, enabling it to adjust the clock-to-data strobe signal relationship for each DQS_t/DQS_c signal pair. The device samples the clock state with the rising edge of DQS signals and asynchronously feeds back to the memory controller. The memory controller references this feedback to adjust the clock-to-data strobe signal relationship for each DQS_t/DQS_c signal pair. All data bits (DQ[7:0] for DQS[0] and DQ[15:8] for DQS[1]) carry the training feedback to the controller. Both DQS signals in each channel must be leveled independently. Write leveling entry/exit is independent between channels for dual channel devices. The device enters write leveling mode when mode register MR2-OP[7] is set HIGH. When entering write leveling mode, the state of the DQ pins is undefined. During write leveling mode, only DESELECT commands, or a MRW command to exit the WRITE LEVELING operation, are allowed. Depending on the absolute values of tQSL and tQSH in the application, the value of tDQSS may have to be better than the limits provided in the AC Timing Parameters section in order to satisfy the tDSS and tDSH specifications. Upon completion of the WRITE LEVELING operation, the device exits write leveling mode when MR2-OP[7] is reset LOW. Write leveling should be performed before write training (DQS2DQ training). Write Leveling Procedure 1. Enter write leveling mode by setting MR2-OP[7]=1. 2. Once in write leveling mode, DQS_t must be driven LOW and DQS_c HIGH after a delay of tWLDQSEN. 3. Wait for a time tWLDQSEN before providing the first DQS signal input. The delay time tWLMRD(MAX) is controller-dependent. 4. The device may or may not capture the first rising edge of DQS_t due to an unstable first rising edge; therefore, at least two consecutive pulses of DQS signal input is required for every DQS input signal during write training mode. The captured clock level for each DQS edge is overwritten, and the device provides asynchronous feedback on all DQ bits after time tWLO. 5. The feedback provided by the device is referenced by the controller to increment or decrement the DQS_t and/or DQS_c delay settings. 6. Repeat steps 4 and 5 until the proper DQS_t/DQS_c delay is established. 7. Exit write leveling mode by setting MR2-OP[7] = 0. 167 200b: x32 LPDDR4 SDRAM Write Leveling Figure 112: Write Leveling Timing – tDQSL (MAX) T0 T1 T2 T3 T4 Ta Ta1 Tb Tb1 Tc Tc1 MRW MA MRW MA MRW OP MRW OP DES DES DES DES DES DES DES Td Td1 Td2 Td3 Te DES DES DES DES DES Te1 Tf Tf1 Tf2 Tf3 Tf4 Tg Tg1 Tg2 Tg3 Tg4 MRW MA MRW MA MRW OP MRW OP DES DES Valid Valid Valid Valid MRW-2 WR LEVELING exit DES CK_c CK_t CA[5:0] Command MRW-1 WR LEVELING MRW-2 WR LEVELING DES DES DES DES DES DES DES MRW-1 WR LEVELING exit DES DES Valid Valid tDQSH tWLDQSEN tDQSL tWLWPRE DQS_c DQS_t tWLMRD tWLO tWLO tWLO tMRD tWLO DQ[15:0] DMI[1:0] Don’t Care 1. Clock can be stopped except during DQS toggle period (CK_t = LOW, CK_c = HIGH). However, a stable clock prior to sampling is required to ensure timing accuracy. Note: Figure 113: Write Leveling Timing – tDQSL (MIN) T0 T1 T2 T3 T4 Ta Ta1 Tb Tb1 Tc Tc1 MRW MA MRW MA MRW OP MRW OP DES DES DES DES DES DES DES Td Td1 Td2 Td3 Te DES DES DES DES DES Te1 Tf Tf1 Tf2 Tf3 Tf4 Tg Tg1 Tg2 Tg3 MRW MA MRW MA MRW OP MRW OP DES DES Valid Valid Valid Valid MRW-2 WR LEVELING exit DES CK_c CK_t CA[5:0] Command MRW-1 WR LEVELING MRW-2 WR LEVELING DES tWLDQSEN DES tWLWPRE DES DES DES DES DES tDQSH DES DES MRW1 WR LEVELING exit Valid Valid tDQSL DQS_c DQS_t tWLMRD tWLO tWLO tMRD tWLO DQ[15:0] DMI[1:0] Don’t Care Note: 1. Clock can be stopped except during DQS toggle period (CK_t = LOW, CK_c = HIGH). However, a stable clock prior to sampling is required to ensure timing accuracy. Input Clock Frequency Stop and Change The input clock frequency can be stopped or changed from one stable clock rate to another stable clock rate during write leveling mode. The frequency stop or change timing is shown below. 168 200b: x32 LPDDR4 SDRAM Write Leveling Figure 114: Clock Stop and Timing During Write Leveling T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2 Tc0 Td0 Te0 Te1 Te2 Te3 Te4 Tf0 Tf1 Tf2 Tf3 DES DES DES DES DES CK_c CK_t t CKPSTDQS t CKPRDQS CS CKE CA Command MRW MA MRW MA MRW-1 WR LEVELING MRW OP MRW OP MRW-2 WR LEVELING DES DES DES DESELECT DESELECT t WLDQSEN DES DES DES DES DES DESELECT DES DES DES DESELECT DESELECT t DQSH t WLWPRE DES DESELECT DESELECT DESELECT t DQSL DQS_t DQS_c t WLMRD t WLO t WLO t WLO t WLO DQ DMI Don’t Care Notes: 1. CK_t is held LOW and CK_c is held HIGH during clock stop. 2. CS will be held LOW during clock clock stop. Table 111: Write Leveling Timing Parameters Parameter DQS_t/DQS_c delay after write leveling mode is programmed Symbol Min/Max Value Units tWLDQSEN MIN 20 tCK MAX – MIN 20 Write preamble for write leveling tWLWPRE First DQS_t/DQS_c edge after write leveling mode is programmed tWLMRD Write leveling output delay tWLO MODE REGISTER SET command delay tMRD Valid clock requirement before DQS toggle tCKPRDQS Valid clock requirement after DQS toggle tCKPSTDQS MAX – MIN 40 MAX – MIN 0 MAX 20 MIN MAX (14ns, 10nCK) MAX – MIN MAX (7.5ns, 4nCK) MAX – MIN MAX (7.5ns, 4nCK) MAX – tCK tCK ns ns – – Table 112: Write Leveling Setup and Hold Timing Data Rate Parameter Write leveling hold time Symbol Min/Max 1600 2400 3200 3733 4267 Unit tWLH MIN 150 100 75 62.5 50 ps 169 200b: x32 LPDDR4 SDRAM Write Leveling Table 112: Write Leveling Setup and Hold Timing (Continued) Data Rate Parameter Symbol Min/Max 1600 2400 3200 3733 4267 Unit Write leveling setup time tWLS MIN 150 100 75 62.5 50 ps Write leveling input valid window tWLIVW MIN 240 160 120 105 90 ps Notes: 1. In addition to the traditional setup and hold time specifications, there is value in a invalid window-based specification for write leveling training. As the training is based on each device, worst case process skews for setup and hold do not make sense to close timing between CK and DQS. 2. tWLIVW is defined in a similar manner to TdIVW_total, except that here it is a DQS invalid window with respect to CK. This would need to account for all voltage and temperature (VT) drift terms between CK and DQS within the device that affect the write leveling invalid window. The figure below shows the DQS input mask for timing with respect to CK. The “total” mask (tWLIVW) defines the time the input signal must not encroach in order for the DQS input to be successfully captured by CK. The mask is a receiver property and it is not the valid data-eye. Figure 115: DQS_t/DQS_c to CK_t/CK_c Timings at the Pins Referenced from the Internal Latch Internal composite DQS eye center aligned to CK CK_c CK_t DQ_diff = DQS_t–DQS_c tWLIVW 170 200b: x32 LPDDR4 SDRAM MULTIPURPOSE Operation MULTIPURPOSE Operation The device uses the MULTIPURPOSE command to issue a NO OPERATION (NOP) command and to access various training modes. The MPC command is initiated with CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by the Command Truth Table. The MPC command has seven operands (OP[6:0]) that are decoded to execute specific commands in the SDRAM. OP[6] is a special bit that is decoded on the first rising CK edge of the MPC command. When OP[6] = 0, the device executes a NOP command, and when OP[6] = 1, the device further decodes one of several training commands. When OP[6] = 1 and the training command includes a READ or WRITE operation, the MPC command must be followed immediately by a CAS-2 command. For training commands that read or write, READ latency (RL) and WRITE latency (WL) are counted from the second rising CK edge of the CAS-2 command with the same timing relationship as a typical READ or WRITE command. The operands of the CAS-2 command following a MPC READ/WRITE command must be driven LOW. The following MPC commands must be followed by a CAS-2 command: • WRITE-FIFO • READ-FIFO • READ DQ CALIBRATION All other MPC commands do not require a CAS-2 command, including the following: • • • • • NOP START DQS OSCILLATOR STOP DQS OSCILLATOR ZQCAL START ZQCAL LATCH Table 113: MPC Command Definition SDR Command Pins SDR CA Pins CKE SDR Command MPC (Train, NOP) CK_t (n-1) CK_t(n) CS CA0 CA1 CA2 CA3 CA4 CA5 H H H L L L L L OP6 1 L OP0 OP1 OP2 OP3 OP4 OP5 2 Notes: CK_t Edge Notes 1, 2 1. See the Command Truth Table for more information. 2. MPC commands for READ or WRITE TRAINING operations must be immediately followed by the CAS-2 command, consecutively, without any other commands in between. The MPC command must be issued before issuing the CAS-2 command. 171 200b: x32 LPDDR4 SDRAM MULTIPURPOSE Operation Table 114: MPC Commands Function Operand Training Modes OP[6:0] Data 0XXXXXXb: NOP 1000001b: READ-FIFO: READ-FIFO supports only BL16 operation 1000011b: READ DQ CALIBRATION (MR32/MR40) 1000101b: RFU 1000111b: WRITE-FIFO: WRITE-FIFO supports only BL16 operation 1001001b: RFU 1001011b: START DQS OSCILLATOR 1001101b: STOP DQS OSCILLATOR 1001111b: ZQCAL START 1010001b: ZQCAL LATCH All Others: Reserved 1. See command truth table for more information. 2. MPC commands for READ or WRITE TRAINING operations must be immediately followed by CAS-2 command consecutively without any other commands in-between. MPC command must be issued first before issuing the CAS-2 command. 3. WRITE-FIFO and READ-FIFO commands will only operate as BL16, ignoring the burst length selected by MR1 OP[1:0]. Notes: Figure 116: WRITE-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK T0 T1 T2 T3 BL BA0, CA CAn CAn T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Valid Valid Valid Valid Tc5 Td0 Td1 Td2 Td3 Td4 Valid Valid Valid Valid Td5 Te0 Te1 Te2 Tf0 Tf1 Tg0 Tg1 Tg2 DES DES DES DES DES DES DES DES Tg3 CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES DES DES DES DES DES MPC [WRITE-FIFO] CAS-2 DES DES MPC [WRITE-FIFO] tCCD t WRWTR WL =8 CAS-2 DES DES WL WL tDQSS t WPRE tDQSS tDQSS t WPST WPRE t WPST DQS_c DQS_t tDQS2DQ tDQS2DQ DQ[15:0] DMI[1:0] n0 n13 n14 n15 tDQS2DQ n0 n13 n14 n15 n0 n13 n14 n15 Don’t Care Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during refresh or during self refresh, with CKE HIGH. 2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC[WRITE-FIFO] is tWRWTR. 3. Seamless MPC[WRITE-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[WRITE-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a WRITE-1 command. 5. A maximum of five MPC[WRITE-FIFO] commands may be executed consecutively without corrupting FIFO data. The sixth MPC[WRITE-FIFO] command will overwrite the FIFO data 172 200b: x32 LPDDR4 SDRAM MULTIPURPOSE Operation from the first command. If fewer than five MPC[WRITE-FIFO] commands are executed, then the remaining FIFO locations will contain undefined data. 6. For the CAS-2 command following an MPC command, the CAS-2 operands must be driven LOW. 7. To avoid corrupting the FIFO contents, MPC[READ-FIFO] must immediately follow MPC[WRITE-FIFO]/CAS-2 without any other commands in-between. See Write Training section for more information on FIFO pointer behavior. Figure 117: READ-FIFO – tWPRE = 2nCK, tWPST = 0.5nCK, tRPRE = Toggling, tRPST = 1.5nCK T0 T1 T2 T3 T4 Ta Ta+1 Ta+2 Ta+3 Tb Tb+1 Tb+2 Tb+3 Tb+4 Tb+5 Tc+2 Tc+3 Tc+4 Tc+5 Tc+6 Tc+7 Td Td+1 Td+2 Td+3 Valid Valid Valid Valid Valid Valid Valid Td+4 Td+5 Valid Valid Te Te+1 Tf Tf+1 Tf+2 Tf+3 Tf+4 Valid Valid Valid Valid Valid Valid Valid CK_c CK_t tCCD CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid WL Command MPC [WRITE-FIFO] CAS-2 Valid RL Valid Valid Valid MPC [READ-FIFO] tDQSS CAS-2 Valid MPC [READ-FIFO] tWTR CAS-2 Valid Valid Valid Valid Valid Valid Valid tDQSCK DQS_t DQS_c tDQS2DQ DQ[15:0] DMI[1:0] tRPRE D0 D1 D12 D13 D14 D15 tRPST D0 D1 D2 D13 D14 D15 D0 D11 D12 D13 D14 D15 Don’t Care Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during refresh or during self refresh with CKE HIGH. 2. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time. 3. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a READ-1 command. 4. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE-FIFO] commands were executed, then the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior. 5. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 6. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training for more information on DMI behavior. 173 200b: x32 LPDDR4 SDRAM MULTIPURPOSE Operation Figure 118: READ-FIFO – tRPRE = Toggling, tRPST = 1.5nCK T0 T1 T2 T3 T4 Ta Ta+1 Ta+2 Ta+3 Ta+4 Ta+5 Tb Valid Valid Valid Valid Tb+1 Tb+2 Tb+3 Tb+4 Valid Valid Valid Tc Tc+1 Tc+2 Td Td+1 Td+2 Td+3 Te Te+1 Te+2 Te+3 Te+4 Te+5 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid CK_c CK_t tRTRRD CA[5:0] Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid RL RL Command MPC [READ-FIFO] CAS-2 Valid READ-1 CAS-2 Valid Valid Valid Valid Valid Valid Valid Valid tDQSCK Valid Valid tDQSCK DQS_t DQS_c tRPST tRPRE DQ[15:0] DMI[1:0] tRPST tRPRE D0 D1 D12 D13 D14 D15 D0 D1 D12 D13 D14 D15 Don’t Care Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active, during refresh or during self refresh with CKE HIGH. 2. MPC[READ-FIFO] to READ-1 operation is shown as an example of command-to-command timing for MPC. Timing from MPC[READ-FIFO] command to read is tRTRRD. 3. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK) as a READ-1 command. 5. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE-FIFO] commands are executed, then the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior. 6. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 7. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training for more information on DMI behavior. Table 115: Timing Constraints for Training Commands Previous Command Next Command Minimum Delay Unit Notes WR/MWR MPC[WRITE-FIFO] tWRWTR nCK 1 MPC[READ-FIFO] Not allowed – 2 RU(tDQSS(MAX)/tCK) MPC[READ DQ CALIBRATION] RD/MRR WL + BL/2 + RU(tWTR/tCK) + nCK MPC[WRITE-FIFO] tRTW nCK 4 MPC[READ-FIFO] Not allowed – 2 MPC[READ DQ CALIBRATION] tRTRRD nCK 3 174 200b: x32 LPDDR4 SDRAM MULTIPURPOSE Operation Table 115: Timing Constraints for Training Commands (Continued) Previous Command Next Command Minimum Delay Unit Notes MPC[WRITE-FIFO] WR/MWR Not allowed – 2 MPC[WRITE-FIFO] tCCD nCK RD/MRR Not allowed – RU(tDQSS(MAX)/tCK) MPC[READ-FIFO] Notes: + nCK MPC[READ DQ CALIBRATION] Not allowed – 2 WR/MWR tRTW nCK 4 MPC[WRITE-FIFO] tRTW nCK 4 RD/MRR tRTRRD nCK 3 MPC[READ-FIFO] tCCD nCK MPC[READ DQ CALIBRATION] tRTRRD nCK 3 WR/MWR tRTW nCK 4 MPC[WRITE-FIFO] tRTW nCK 4 RD/MRR tRTRRD nCK 3 MPC[READ-FIFO] Not allowed – 2 MPC[READ DQ CALIBRATION] tCCD nCK MPC[READ-FIFO] MPC[READ DQ CALIBRATION] WL + BL/2 + RU(tWTR/tCK) 2 1. tWRWTR = WL + BL/2 + RU(tDQSS(MAX)/tCK) + MAX(RU(7.5ns/tCK), 8nCK). 2. No commands are allowed between MPC[WRITE-FIFO] and MPC[READ-FIFO] except the MRW commands related to training parameters. 3. tRTRRD = RL + RU(tDQSCK(MAX)/tCK) + BL/2 + tRPST + 0.5 + MAX(RU(7.5ns/tCK), 8nCK). 4. In case of DQ ODT disable MR11 OP[2:0] = 000b, tRTW = RL + RU(tDQSCK(MAX)/tCK) + BL/2 - WL + tWPRE + RD(tRPST). In case of DQ ODT enable MR11 OP[2:0] ≠ 000b, tRTW = RL + RU(tDQSCK(MAX)/tCK) + BL/2 + tRPST - ODTLon - RD(tODTon(Min)/tCK) + 1. 175 200b: x32 LPDDR4 SDRAM Read DQ Calibration Training Read DQ Calibration Training The READ DQ CALIBRATION TRAINING function outputs a 16-bit, user-defined pattern on the DQ pins. Read DQ calibration is initiated by issuing a MPC[READ DQ CALIBRATION] command followed by a CAS-2 command, which causes the device to drive the contents of MR32, followed by the contents of MR40 on each of DQ[15:0] and DMI[1:0]. The pattern can be inverted on selected DQ pins according to user-defined invert masks written to MR15 and MR20. Read DQ Calibration Training Procedure 1. Issue MRW commands to write MR32 (first eight bits), MR40 (second eight bits), MR15 (eight-bit invert mask for byte 0), and MR20 (eight-bit invert mask for byte 1). In the alternative, this step could be replaced with the default pattern: • MR32 default = 5Ah • MR40 default = 3Ch • MR15 default = 55h • MR20 default = 55h 2. Issue an MPC command, followed immediately by a CAS-2 command. • Each time an MPC command, followed by a CAS-2, is received by the device, a 16-bit data burst will drive the eight bits programmed in MR32 followed by the eight bits programmed in MR40 on all I/O pins after the currently set RL. • The data pattern will be inverted for I/O pins with a 1 programmed in the corresponding invert mask mode register bit (see table below). • The pattern is driven on the DMI pins, but no DATA BUS INVERSION function is enabled, even if read DBI is enabled in the mode register. • The MPC command can be issued every tCCD seamlessly, and tRTRRD delay is required between ARRAY READ command and the MPC command as well the delay required between the MPC command and an ARRAY READ. • The operands received with the CAS-2 command must be driven LOW. 3. DQ Read DQ calibration training can be performed with any or no banks active during refresh or during self refresh with CKE HIGH. Table 116: Invert Mask Assignments DQ pin 0 1 2 3 DMI0 4 5 6 7 MR15 bit 0 1 2 3 N/A 4 5 6 7 DQ pin 8 9 10 11 DMI1 12 13 14 15 MR20 bit 0 1 2 3 N/A 4 5 6 7 176 200b: x32 LPDDR4 SDRAM Read DQ Calibration Training Figure 119: Read DQ Calibration Training Timing: Read-to-Read DQ Calibration T0 T1 T2 T3 BL BA0, CA CAn CAn T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Valid Valid Tc7 Td1 Td2 Td3 Td4 Td5 Td6 Te0 DES DES DES DES DES DES DES Te1 Te2 Te3 CK_c CK_t CS CA Command Valid CAS-2 READ-1 DES DES DES DES DES DES DES DES DES DES DES Valid MPC [RD DQ CAL] DES CAS-2 DES tRTRRD t RL RL DES DES DQSCK t RPST t RPRE t RPST High-Z High-Z tDQSQ DQ DMI DES DQSCK t RPRE DQS_c DQS_t t High-Z tDQSQ High-Z n0 n13 n14 n15 n0 n13 n14 n15 Don’t Care 1. Read-1 to MPC operation is shown as an example of command-to-command timing. Timing from Read-1 to MPC command is tRTRRD. 2. MPC uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a Read-1 command. 3. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK. 4. DES commands are shown for ease of illustration; other commands may be valid at these times. Notes: Figure 120: Read DQ Calibration Training Timing: Read DQ Calibration to Read DQ Calibration/Read T0 T1 T2 T3 T8 T9 T10 T11 Valid Valid Valid Valid Valid Valid Valid Valid T12 T13 T14 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 BA0, CA CAn CAn Tc5 Td0 DES DES Td1 Td2 Td3 Td4 DES DES DES Te0 Te1 CK_c CK_t CS CA Command MPC [RD DQ CAL] CAS-2 DES MPC [RD DQ CAL] CAS-2 BL DES DES DES DES DES DES t CCD DES DES READ-1 CAS-2 RL DES DES DES tDQSCK tDQSCK RL t RPST t RPRE High-Z High-Z t RPRE t RPST High-Z tDQSQ DQ DMI DES tDQSCK RL DQS_c DQS_t DES tRTRRD t DQSQ n0 n9 n10 n11 n12 n13 n14 n15 n0 n13 n14 n15 tDQSQ High-Z n0 n13 n14 n15 Don’t Care Notes: 1. MPC[READ DQ CALIBRATION] to MPC[READ DQ CALIBRATION] operation is shown as an example of command-to-command timing. 2. MPC[READ DQ CALIBRATION] to READ-1 operation is shown as an example of command-to-command timing. 3. MPC[READ DQ CALIBRATION] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ) as a READ-1 command. 4. Seamless MPC[READ DQ CALIBRATION] commands may be executed by repeating the command every tCCD time. 5. Timing from MPC[READ DQ CALIBRATION] command to READ-1 is tRTRRD. 177 200b: x32 LPDDR4 SDRAM Read DQ Calibration Training 6. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK. 7. DES commands are shown for ease of illustration; other commands may be valid at these times. Read DQ Calibration Training Example An example of read DQ calibration training output is shown in table below. This shows the 16-bit data pattern that will be driven on each DQ in byte 0 when one READ DQ CALIBRATION TRAINING command is executed. This output assumes the following mode register values are used: • • • • MR32 = 1CH MR40 = 59H MR15 = 55H MR20 = 55H Table 117: Read DQ Calibration Bit Ordering and Inversion Example Bit Sequence → Pin Invert 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DQ0 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ1 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ2 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ3 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DMI0 Never 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ4 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ5 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ6 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ7 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ8 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ9 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ10 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ11 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DMI1 Never 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ12 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ13 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 DQ14 Yes 1 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 DQ15 No 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 0 Notes: 1. The patterns contained in MR32 and MR40 are transmitted on DQ[15:0] and DMI[1:0] when read DQ calibration is initiated via a MPC[READ DQ CALIBRATION] command. The pattern transmitted serially on each data lane, organized little endian such that the loworder bit in a byte is transmitted first. If the data pattern is 27H, then the first bit transmitted with be a 1, followed by 1, 1, 0, 0, 1, 0, and 0. The bit stream will be 00100111 →. 2. MR15 and MR20 may be used to invert the MR32/MR40 data pattern on the DQ pins. See MR15 and MR20 for more information. Data is never inverted on the DMI[1:0] pins. 3. DMI [1:0] outputs status follows MR Setting vs. DMI Status table. 178 200b: x32 LPDDR4 SDRAM Write Training 4. No DATA BUS INVERSION (DBI) function is enacted during read DQ calibration, even if DBI is enabled in MR3-OP[6]. Table 118: MR Setting vs. DMI Status DM Function MR13 OP[5] WRITE DBIdc Function MR3 OP[7] READ DBIdc Function MR3 OP[6] DMI Status 1: Disable 0: Disable 0: Disable High-Z 1: Disable 1: Enable 0: Disable The data pattern is transmitted 1: Disable 0: Disable 1: Enable The data pattern is transmitted 1: Disable 1: Enable 1: Enable The data pattern is transmitted 0: Enable 0: Disable 0: Disable The data pattern is transmitted 0: Enable 1: Enable 0: Disable The data pattern is transmitted 0: Enable 0: Disable 1: Enable The data pattern is transmitted 0: Enable 1: Enable 1: Enable The data pattern is transmitted MPC[READ DQ CALIBRATION] After Power-Down Exit Following the power-down state, an additional time, tMRRI, is required prior to issuing the MPC[READ DQ CALIBRATION] command. This additional time (equivalent to tRCD) is required in order to be able to maximize power-down current savings by allowing more power-up time for the read DQ data in MR32 and MR40 data path after exit from standby, power-down mode. Figure 121: MPC[READ DQ CALIBRATION] Following Power-Down State T0 Ta0 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8 Td9 DES DES DES CK_c CK_t t CKCKEH CKE t MRRI t XP CS CA Command Valid Valid Valid Valid DES DES DES DES DES DES DES DES DES DES MPC [READ DQ CAL] CAS-2 Don’t Care Write Training The device uses an unmatched DQS-DQ path to enable high-speed performance and save power. As a result, the DQS strobe must be trained to arrive at the DQ latch centeraligned with the data eye. The DQ receiver is located at the DQ pad and has a shorter internal delay than the DQS signal. The DQ receiver will latch the data present on the 179 200b: x32 LPDDR4 SDRAM Write Training DQ bus when DQS reaches the latch, and training is accomplished by delaying the DQ signals relative to DQS such that the data eye arrives at the receiver latch centered on the DQS transition. Two modes of training are available: • Command-based FIFO WR/RD with user patterns • An internal DQS clock-tree oscillator, which determines the need for, and the magnitude of, required training The command-based FIFO WR/RD uses the MPC command with operands to enable this special mode of operation. When issuing the MPC command, if CA[5] is set LOW (OP[6] = 0), then the device will perform a NOP command. When CA[5] is set HIGH, the CA[4:0] pins enable training functions or are reserved for future use (RFU). MPC commands that initiate a read or write to the device must be followed immediately by a CAS-2 command. See the MPC Operation section for more information. To perform write training, the controller can issue an MPC[WRITE-FIFO] command with OP[6:0] set, followed immediately by a CAS-2 command (CAS-2 operands should be driven LOW) to initiate a WRITE-FIFO. Timings for MPC[WRITE-FIFO] are identical to WRITE commands, with WL timed from the second rising clock edge of the CAS-2 command. Up to five consecutive MPC[WRITE-FIFO] commands with user-defined patterns may be issued to the device, which will store up to 80 values (BL16 × 5) per pin that can be read back via the MPC[READ-FIFO] command. (The WRITE/READ-FIFO POINTER operation is described in a different section. After writing data with the MPC[WRITE-FIFO] command, the data can be read back with the MPC[READ-FIFO] command and results can be compared with "expected" data to determine whether further training (DQ delay) is needed. MPC[READ-FIFO] is initiated by issuing an MPC command, as described in the MPC Operation section, followed immediately by a CAS-2 command (CAS-2 operands must be driven LOW). Timings for the MPC[READ-FIFO] command are identical to READ commands, with RL timed from the second rising clock edge of the CAS-2 command. READ-FIFO is nondestructive to the data captured in the FIFO; data may be read continuously until it is disturbed by another command, such as a READ, WRITE, or another MPC[WRITE-FIFO]. If fewer than five WRITE-FIFO commands are executed, unwritten registers will have undefined (but valid) data when read back. For example: If five WRITE-FIFO commands are executed sequentially, then a series of READ-FIFO commands will read valid data from FIFO[0], FIFO[1]….FIFO[4] and then wrap back to FIFO[0] on the next READ-FIFO. However, if fewer than five WRITE-FIFO commands are executed sequentially (example = 3), then a series of READ-FIFO commands will return valid data for FIFO[0], FIFO[1], and FIFO[2], but the next two READFIFO commands will return undefined data for FIFO[3] and FIFO[4] before wrapping back to the valid data in FIFO[0]. The READ-FIFO pointer and WRITE-FIFO pointer are reset under the following conditions: • • • • Power-up initialization RESET_n asserted Power-down entry Self refresh power-down entry 180 200b: x32 LPDDR4 SDRAM Write Training The MPC[WRITE-FIFO] command advances the WRITE-FIFO pointer, and the MPC[READ-FIFO] advances the READ-FIFO pointer. Also any normal (non-FIFO) READ operation (RD, RDA) advances both WRITE-FIFO pointer and READ-FIFO pointer. Issuing (non-FIFO) READ operation command is inhibited during write training period. To keep the pointers aligned, the SoC memory controller must adhere to the following restriction at the end of Write training period: b = a + (n × c) Where: 'a' is the number of MPC[WRITE-FIFO] commands 'b' is the number of MPC[READ-FIFO] commands 'c' is the FIFO depth (= 5 for LPDDR4) 'n' is a positive integer, •0 Figure 122: WRITE-to-MPC[WRITE-FIFO] Operation Timing T0 T1 T2 T3 BL BA0, CA CAn CAn T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Valid Valid Valid Valid Tc5 Td0 Td1 Td2 Td3 Td4 Valid Valid Valid Valid Td5 Te0 Te1 Te2 Tf0 Tf1 Tg0 Tg1 Tg2 DES DES DES DES DES DES DES Tg3 CK_c CK_t CS CA Command WRITE-1 CAS-2 DES DES DES DES DES DES DES MPC [WRITE-FIFO] CAS-2 DES DES MPC [WRITE-FIFO] tCCD t WRWTR WL =8 CAS-2 DES DES DES WL WL tDQSS t WPRE tDQSS tDQSS t WPST WPRE t WPST DQS_c DQS_t tDQS2DQ tDQS2DQ DQ[15:0] DMI[1:0] n0 n13 n14 n15 tDQS2DQ n0 n13 n14 n15 n0 n13 n14 n15 Don’t Care Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during REFRESH or during SELF REFRESH with CKE HIGH. 2. Write-1 to MPC is shown as an example of command-to-command timing for MPC. Timing from Write-1 to MPC[WRITE-FIFO] is tWRWTR. 3. Seamless MPC[WR-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[WRITE-FIFO] uses the same command-to-data timing relationship (WL, tDQSS, tDQS2DQ) as a WRITE-1 command. 5. A maximum of five MPC[WRITE-FIFO] commands may be executed consecutively without corrupting FIFO data. The sixth MPC[WRITE-FIFO] command will overwrite the FIFO data from the first command. If fewer than five MPC[WRITE-FIFO] commands are executed, then the remaining FIFO locations will contain undefined data. 6. For the CAS-2 command following an MPC command, the CAS-2 operands must be driven LOW. 7. To avoid corrupting the FIFO contents, MPC[READ-FIFO] must immediately follow MPC[WRITE-FIFO]/CAS-2 without any other commands disturbing FIFO pointers in between. FIFO pointers are disturbed by CKE LOW, WRITE, MASKED WRITE, READ, READ DQ CALIBRATION, and MRR. 8. BL = 16, Write postamble = 0.5nCK. 9. DES commands are shown for ease of illustration; other commands may be valid at these times. 181 200b: x32 LPDDR4 SDRAM Write Training Figure 123: MPC[WRITE-FIFO]-to-MPC[READ-FIFO] Timing T0 T1 T2 T3 BL BA0, CA CAn CAn T4 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Valid Valid Valid Valid Tc5 Td0 Td1 Td2 Td3 Td4 Valid Valid Td5 Te0 Te1 Te2 Te3 Tf0 Tf1 Tg0 Tg1 DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command MPC [WRITE-FIFO] CAS-2 DES DES DES WL DES DES DES DES DES MPC [READ-FIFO] CAS-2 DES DES Valid MPC [READ-FIFO] tCCD tWTR BL/2 + 1 clock Valid =8 RL tDQSS t WPRE CAS-2 tDQSCK t RPRE t WPST t RPST DQS_c DQS_t tDQS2DQ DQ DMI tDQSQ n0 n13 n14 n15 n0 n13 n14 n15 n0 n13 n14 n15 Don’t Care Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during refresh or during self refresh with CKE HIGH. 2. MPC[WRITE-FIFO] to MPC[READ-FIFO] is shown as an example of command-to-command timing for MPC. Timing from MPC[WRITE-FIFO] to MPC[READ-FIFO] is specified in the command-to-command timing table. 3. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ ) as a READ-1 command. 5. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE-FIFO] commands were executed, then the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior. 6. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 7. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training section for more information on DMI behavior. 8. BL = 16, Write postamble = 0.5nCK, Read preamble: Toggle, Read postamble: 0.5nCK. 9. DES commands are shown for ease of illustration; other commands may be valid at these times. 182 200b: x32 LPDDR4 SDRAM Write Training Figure 124: MPC[READ-FIFO] to Read Timing T0 T1 T2 T3 Valid Valid CAn CAn T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Tb0 Tb1 Tb2 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 BL BA0, CA CAn CAn Tc7 Td1 Td2 Td3 Td4 Td5 Td6 Te0 DES DES DES DES DES DES DES Te1 Te2 Te3 CK_c CK_t CS CA Command MPC RAD FIFO CAS-2 DES DES DES DES DES DES DES DES DES DES DES tRTRRD RL t DES READ-1 CAS-2 DES RL t DES DES DES DQSCK DQSCK t RPRE t RPRE t RPST t RPST DQS_c DQS_t tDQSQ DQ DMI tDQSQ n0 n13 n14 n15 n0 n13 n14 n15 Don’t Care Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during refresh or during self refresh with CKE HIGH. 2. MPC[READ-FIFO] to READ-1 operation is shown as an example of command-to-command timing for MPC. Timing from MPC[READ-FIFO] command to READ is tRTRRD. 3. Seamless MPC[READ-FIFO] commands may be executed by repeating the command every tCCD time. 4. MPC[READ-FIFO] uses the same command-to-data timing relationship (RL, tDQSCK, tDQSQ ) as a READ-1 command. 5. Data may be continuously read from the FIFO without any data corruption. After five MPC[READ-FIFO] commands, the FIFO pointer will wrap back to the first FIFO and continue advancing. If fewer than five MPC[WRITE-FIFO] commands were executed, then the MPC[READ-FIFO] commands to those FIFO locations will return undefined data. See Write Training for more information on the FIFO pointer behavior. 6. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 7. DMI[1:0] signals will be driven if WR-DBI, RD-DBI, or DM is enabled in the mode registers. See Write Training for more information on DMI behavior. 8. BL = 16, Read preamble: Toggle, Read postamble: 0.5nCK 9. DES commands are shown for ease of illustration; other commands may be valid at these times. 183 200b: x32 LPDDR4 SDRAM Write Training Figure 125: MPC[WRITE-FIFO] with DQ ODT Timing T0 T1 T2 T3 Valid Valid Valid Valid T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t CS CA Command MPC [WRITE-FIFO] CAS-2 WL tDQSS t WPRE t WPST DQS_c DQS_t tDQS2DQ DQ DMI n0 ODTLon t ODTon(MAX) t DRAM RTT ODT High-Z n1 n2 n13 n14 n15 ODTon(MIN) Transition Transition ODT On ODTLoff t t ODT High-Z ODToff(MIN) ODToff(MAX) Don’t Care Notes: 1. MPC[WRITE-FIFO] can be executed with a single bank or multiple banks active during refresh or during self refresh with CKE HIGH. 2. MPC[WRITE-FIFO] uses the same command-to-data/ODT timing relationship (RL, tDQSCK, tDQS2DQ, ODTLon, ODTLoff, tODTon, tODToff) as a WRITE-1 command. 3. For the CAS-2 command immediately following an MPC command, the CAS-2 operands must be driven LOW. 4. BL = 16, Write postamble = 0.5nCK. 5. DES commands are shown for ease of illustration; other commands may be valid at these times. 184 200b: x32 LPDDR4 SDRAM Write Training Figure 126: Power-Down Exit to MPC[WRITE-FIFO] Timing T0 Ta0 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8 Td9 CK_c CK_t t CKCKEH CKE t t XP MPCWR (= t RCD + 3nCK) WL CS CA Valid Valid Valid Valid Valid Valid Valid Valid Note 1 DES Command DES Any command Any command DES DES DES DES MPC [WRITE-FIFO] CAS-2 DES DES DES Don’t Care Notes: 1. Any commands except MPC[WRITE-FIFO] and other exception commands defined other section in this document (for example. MPC[READ DQ CALIBRATION]). 2. DES commands are shown for ease of illustration; other commands may be valid at these times. Table 119: MPC[WRITE-FIFO] AC Timing Parameter Symbol tXP has expired until Additional time after MPC[WRITE-FIFO] command may be issued tMPCWR MIN/MAX MIN Value tRCD + 3nCK Unit – Internal Interval Timer As voltage and temperature change on the device, the DQS clock-tree delay will shift, requiring retraining. The device includes an internal DQS clock-tree oscillator to measure the amount of delay over a given time interval (determined by the controller), allowing the controller to compare the trained delay value to the delay value seen at a later time. The DQS oscillator will provide the controller with important information regarding the need to retrain and the magnitude of potential error. The DQS interval oscillator is started by issuing an MPC command with OP[5:0] = 101011b, which will start an internal ring oscillator that counts the number of time a signal propagates through a copy of the DQS clock tree. The DQS oscillator may be stopped by issuing an MPC[STOP DQS OSCILLATOR] command with OP[6:0] set, as described in MPC Operation, or the controller may instruct the SDRAM to count for a specific number of clocks and then stop automatically (See MR23 for more information). If MR23 is set to automatically stop the DQS oscillator, then the MPC[STOP DQS OSCILLATOR] command should not be used (illegal). When the DQS oscillator is stopped by either method, the result of the oscillator counter is automatically stored in MR18 and MR19. The controller may adjust the accuracy of the result by running the DQS interval oscillator for shorter (less accurate) or longer (more accurate) duration. The accuracy of the 185 200b: x32 LPDDR4 SDRAM Write Training result for a given temperature and voltage is determined by the following equation, where run time = total time between START and STOP commands and DQS delay = the value of the DQS clock tree delay (tDQS2DQ MIN/MAX): DQS oscillator granularity error = 2 x (DQS delay) run time Additional matching error must be included, which is the difference between DQS training circuit and the actual DQS clock tree across voltage and temperature. The matching error is vendor specific. Therefore, the total accuracy of the DQS oscillator counter is given by: DQS oscillator accuracy = 1 - granularity error - matching error For example, if the total time between START and STOP commands is 100ns, and the maximum DQS clock tree delay is 800ps (tDQS2DQ MAX), then the DQS oscillator granularity error is: DQS oscillator granularity error = 2 x (0.8ns) = 1.6% 100ns This equates to a granularity timing error of 12.8ps. Assuming a circuit matching error of 5.5ps across voltage and temperature, the accuracy is: DQS oscillator accuracy = 1 - 12.8 + 5.5 = 97.7% 800 For example, running the DQS oscillator for a longer period improves the accuracy. If the total time between START and STOP commands is 500ns, and the maximum DQS clock tree delay is 800ps (tDQS2DQ MAX), then the DQS oscillator granularity error is: DQS oscillator granularity error = 2 x (0.8ns) = 0.32% 500ns This equates to a granularity timing error or 2.56ps. Assuming a circuit matching error of 5.5ps across voltage and temperature, the accuracy is: DQS oscillator accuracy = 1 - 2.56 + 5.5 = 99.0% 800 The result of the DQS interval oscillator is defined as the number of DQS clock tree delays that can be counted within the run time, determined by the controller. The result is stored in MR18-OP[7:0] and MR19-OP[7:0]. MR18 contains the least significant bits (LSB) of the result, and MR19 contains the most significant bits (MSB) of the result. MR18 and MR19 are overwritten by the SDRAM when a MPC[STOP DQS OSCILLATOR] command is received. The SDRAM counter will count to its maximum value (= 2^16) and stop. If the maximum value is read from the mode registers, the memory controller must assume that the counter overflowed the register and therefore discard the result. The longest run time for the oscillator that will not overflow the counter registers can be calculated as follows: Longest runtime interval = 216 x tDQS2DQ(MIN) = 216 × 0.2ns = 13.1μs 186 200b: x32 LPDDR4 SDRAM Write Training DQS Interval Oscillator Matching Error The interval oscillator matching error is defined as the difference between the DQS training ckt (interval oscillator) and the actual DQS clock tree across voltage and temperature. Parameters: tDQS2DQ: Actual DQS clock tree delay tDQS OSC: Training ckt (interval oscillator) delay OSCOffset: Average delay difference over voltage and temperature (shown below) OSCMatch: DQS oscillator matching error Figure 127: Interval Oscillator Offset – OSCoffset Offset 2 tDQS2DQ tDQS OSC Time (ps) OSC offset = AVG(offset1, offset2) Offset 1 (at end point) = tDQS2DQ(V,T) – tDQSOSC(V,T) Offset 2 (at end point) = tDQS2DQ(V,T) – tDQSOSC(V,T) Offset 1 Temperature(T)/Voltage(V) OSCMatch : OSCMatch = [ tDQS2DQ(V,T) - tDQSOSC (V,T) - OSCoffset ] tDQS tDQS OSC: OSC(V,T) = [ Runtime 2 × Count ] Table 120: DQS Oscillator Matching Error Specification Parameter Symbol MIN MAX Unit Notes DQS oscillator matching error OSCMatch –20 20 ps 1, 2, 3, 4, 5, 6, 7, 8 DQS oscillator offset OSCoffset –100 100 ps 2, 4. 7 Notes: 1. The OSCMatch is the matching error per between the actual DQS and DQS interval oscillator over voltage and temperature. 187 200b: x32 LPDDR4 SDRAM Write Training 2. This parameter will be characterized or guaranteed by design. 3. The OSCMatch is defined as the following: OSCMatch = [ tDQS2DQ(V, T) - tDQSOSC(V, T) - OSCoffset ] Where tDQS2DQ(V,T) and tDQSOSC(V,T) are determined over the same voltage and temperature conditions. 4. The runtime of the oscillator must be at least 200ns for determining tDQSOSC(V,T). tDQS OSC(V,T) = [ Runtime 2 × Count ] 5. The input stimulus for tDQS2DQ will be consistent over voltage and temperature conditions. 6. The OSCoffset is the average difference of the endpoints across voltage and temperature. 7. These parameters are defined per channel. 8. tDQS2DQ(V,T) delay will be the average of DQS-to-DQ delay over the runtime period. OSC Count Readout Time OSC Stop to its counting value readout timing is shown in following figures. Figure 128: In Case of DQS Interval Oscillator is Stopped by MPC Command T0 T1 T2 Valid Valid T3 T4 T5 Ta0 Ta1 Ta2 Valid Valid Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Valid Valid Valid Valid Tb6 CK_c CK_t CKE CS CA Command DES MPC :START MROSCILLATOR Write-2 DQS DES DES DES DES MPC :STOP DQS OSCILLATOR DES DES DES DES MRR-1 MR18/MR19 CAS-2 t OSCO Don’t Care Note: 1. DQS interval timer run time setting :MR23 OP[7:0] = 00000000b. 188 200b: x32 LPDDR4 SDRAM Write Training Figure 129: In Case of DQS Interval Oscillator is Stopped by DQS Interval Timer T0 T1 T2 Valid Valid T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Valid Valid Valid Valid Tb6 CK_c CK_t CKE CS CA Command DES MPC :START MROSCILLATOR Write-2 DQS DES DES DES DES DES DES DES DES DES DES MRR-1 MR18/MR19 CAS-2 t OSCO See Note 2 Don’t Care Notes: 1. DQS interval timer run time setting: MR23 OP[7:0] ≠ 00000000b. 2. Setting counts of MR23. Table 121: DQS Interval Oscillator AC Timing Parameter Delay time from OSC stop to mode register readout Note: Symbol MIN/MAX Value Unit tOSCO MIN MAX (40ns, 8nCK) ns 1. START DQS OSCILLATOR command is prohibited until tOSCO(MIN) is satisfied. 189 200b: x32 LPDDR4 SDRAM Thermal Offset Thermal Offset Because of tight thermal coupling, hot spots on an SOC can induce thermal gradients across the device. Because these hot spots may not be located near the thermal sensor, the temperature compensated self refresh (TCSR) circuit may not generate enough refresh cycles to guarantee memory retention. To address this shortcoming, the controller can provide a thermal offset that the memory can use to adjust its TCSR circuit to ensure reliable operation. This thermal offset is provided through MR4 OP[6:5] to either or both channels (dual channel devices). This temperature offset may modify refresh behaviour for the channel to which the offset is provided. It will take a maximum of 200μs to have the change reflected in MR4 OP[2:0] for the channel to which the offset is provided. If the induced thermal gradient from the device temperature sensor location to the hot spot location of the controller is greater than 15°C, self refresh mode will not reliably maintain memory contents. To accurately determine the temperature gradient between the memory thermal sensor and the induced hot spot, the memory thermal sensor location must be provided to the controller. Support of the thermal offset function is optional. Please refer to the vendor data sheet to determine if this function is supported. Temperature Sensor The device has a temperature sensor that can be read from MR4. This sensor can be used to determine the appropriate refresh rate, to determine whether AC timing de-rating is required at an elevated temperature range, and to monitor the operating temperature. Either the temperature sensor or the device T OPER can be used to determine if operating temperature requirements are being met. The device monitors device temperature and updates MR4 according to tTSI. Upon exiting self refresh or power-down, the device temperature status bits shall be no older than tTSI. When using the temperature sensor, the actual device case temperature may be higher than the T OPER specification that applies to standard or elevated temperature ranges. For example, T CASE may be above 85°C when MR4[2:0] = b011. The device enables a 2°C temperature margin between the point when the device updates the MR4 value and the point when the controller reconfigures the system accordingly. When performing tight thermal coupling of the device to external hot spots, the maximum device temperature may be higher than indicated by MR4. To ensure proper operation when using the temperature sensor, consider the following: • TempGradient is the maximum temperature gradient experienced by the device at the temperature of interest over a range of 2°C. • ReadInterval is the time period between MR4 reads from the system. • TempSensorInterval (tTSI) is the maximum delay between the internal updates of MR4. • SysRespDelay is the maximum time between a read of MR4 and a response from the system. 190 200b: x32 LPDDR4 SDRAM ZQ Calibration In order to determine the required frequency of polling MR4, the system uses the TempGradient and the maximum response time of the system in the following equation: TempGradient × (ReadInterval + tTSI + SysRespDelay) ” 2°C Table 122: Temperature Sensor Parameter Symbol Max/Min Value Unit TempGradient MAX System Dependent °C/s ReadInterval MAX System Dependent ms tTSI MAX 32 ms System response delay SysRespDelay MAX System Dependent ms Device temperature margin TempMargin MAX 2 °C System temperature gradient MR4 read interval Temperature sensor interval For example, if TempGradient is 10°C/s and the SysRespDelay is 1ms: (10°C/s) x (ReadInterval + 32ms + 1ms) ” 2°C In this case, ReadInterval shall be no greater than 167ms. Figure 130: Temperature Sensor Timing Temperature < [tTSI + ReadInterval + SysRespDelay] Device temperature margin ient Grad 2° p Tem MR4 trip level tTSI MR4 = 0x03 MR4 = 0x06 Temperature sensor update Host MR4 read MR4 = 0x06 MR4 = 0x06 ReadInterval MRR MR4 = 0x06 MR4 = 0x06 MR4 = 0x06 Time SysRespDelay MRR MR4 = 0x06 ZQ Calibration The MPC command is used to initiate ZQ calibration, which calibrates the output driver impedance and CA/DQ ODT impedance across process, temperature, and voltage. ZQ calibration occurs in the background of device operation and is designed to eliminate any need for coordination between channels (that is, it allows for channel independence). ZQ calibration is required each time that the PU-Cal value (MR3-OP[0]) is changed. Additional ZQ CALIBRATION commands may be required as the voltage and temperature change in the system environment. CA ODT values (MR11-OP[6:4]) and 191 200b: x32 LPDDR4 SDRAM ZQ Calibration DQ ODT values (MR11-OP[2:0]) may be changed without performing ZQ calibration, as long as the PU-Cal value doesn’t change. There are two ZQ calibration modes initiated with the MPC command: ZQCAL START and ZQCAL LATCH. ZQCAL START initiates the calibration procedure, and ZQCAL LATCH captures the result and loads it into the drivers. A ZQCAL START command may be issued anytime the device is not in a power-down state. A ZQCAL LATCH command may be issued anytime outside of power-down after tZQCAL has expired and all DQ bus operations have completed. The CA bus must maintain a deselect state during tZQLAT to allow CA ODT calibration settings to be updated. The DQ calibration value will not be updated until ZQCAL LATCH is performed and tZQLAT has been met. The following mode register fields that modify I/O parameters cannot be changed following a ZQCAL START command and before tZQCAL has expired: • • • • PU-Cal (pull-up calibration V OH point) PDDS (pull-down drive strength and Rx termination) DQ ODT (DQ ODT value) CA ODT (CA ODT value) ZQCAL Reset The ZQCAL RESET command resets the output impedance calibration to a default accuracy of ±30% across process, voltage, and temperature. This command is used to ensure output impedance accuracy to ±30% when ZQCAL START and ZQCAL LATCH commands are not used. The ZQCAL RESET command is executed by writing MR10-OP[0] = 1B. Table 123: ZQ Calibration Parameters Parameter Symbol Min/Max Value Unit ZQCAL START to ZQCAL LATCH command interval tZQCAL MIN 1 μs ZQCAL LATCH to next valid command interval tZQLAT MIN MAX (30ns, 8nCK) ns ZQCAL RESET to next valid command interval tZQRESET MIN MAX (50ns, 3nCK) ns 192 200b: x32 LPDDR4 SDRAM ZQ Calibration Figure 131: ZQCAL Timing T0 T1 T2 T3 T4 T5 T6 T7 T8 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc0 Tc1 Tc2 Tc3 Tc4 Valid Valid Tc5 Tc6 DES DES CK_c CK_t tZQLAT tZQCAL CA ZQCAL ZQCAL START START WR WR CAS ZQCAL ZQCAL LATCH LATCH CAS WL Command MPC TRAIN/CAL DES DES WRITE CAS2 DES DES DES DES DES DES DES DES DES DES DES DES DES DES MPC TRAIN/CAL DES DES DES DES PRECHARGE tDQSS DQS_t DQS_c tWPRE tWPST tDQS2DQ DQ[15:0] Transitioning Data Notes: Don’t Care 1. WRITE and PRECHARGE operations are shown for illustrative purposes. Any single or multiple valid commands may be executed within the tZQCAL time and prior to latching the results. 2. Before the ZQCAL LATCH command can be executed, any prior commands that utilize the DQ bus must have completed. WRITE commands with DQ termination must be given enough time to turn off the DQ ODT before issuing the ZQCAL LATCH command. See the ODT section for ODT timing. Multichannel Considerations The device includes a single ZQ pin and associated ZQ calibration circuitry. Calibration values from this circuit will be used by both channels according to the following protocol: • The ZQCAL START command can be issued to either or both channels. • The ZQCAL START command can be issued when either or both channels are executing other commands, and other commands can be issued during tZQCAL. • The ZQCAL START command can be issued to both channels simultaneously. • The ZQCAL START command will begin the calibration unless a previously requested ZQ calibration is in progress. • If the ZQCAL START command is received while a ZQ calibration is in progress, the command will be ignored and the in-progress calibration will not be interrupted. • The ZQCAL LATCH command is required for each channel. • The ZQCAL LATCH command can be issued to both channels simultaneously. • The ZQCAL LATCH command will latch results of the most recent ZQCAL START command provided tZQCAL has been met. • ZQCAL LATCH commands that do not meet tZQCAL will latch the results of the most recently completed ZQ calibration. • The ZQRESET MRW commands will only reset the calibration values for the channel issuing the command. In compliance with complete channel independence, either channel may issue ZQCAL START and ZQCAL LATCH commands as needed without regard to the state of the other channel. 193 200b: x32 LPDDR4 SDRAM ZQ Calibration ZQ External Resistor, Tolerance, and Capacitive Loading To use the ZQ CALIBRATION function, a 240 ohm, ±1% tolerance external resistor must be connected between the ZQ pin and V DDQ. If the system configuration shares the CA bus to form a x32 (or wider) channel, the ZQ pin of each die’s x16 channel must use a separate ZQCAL resistor. If the system configuration has more than one rank, and if the ZQ pins of both ranks are attached to a single resistor, then the SDRAM controller must ensure that the ZQCAL's don’t overlap. The total capacitive loading on the ZQ pin must be limited to 25pF. For example, if a system configuration shares a CA bus between n channels to form an n x16 wide bus, and no means are available to control the ZQCAL separately for each channel (that is, separate CS, CKE, or CK), then each x16 channel must have a separate ZQCAL resistor. For a x32, two-rank system, each x16 channel must have its own ZQCAL resistor, but the ZQCAL resistor can be shared between ranks on each x16 channel. In this configuration, the CS signal can be used to ensure that the ZQCAL commands for Rank[0] and Rank[1] don’t overlap. 194 200b: x32 LPDDR4 SDRAM Frequency Set Points Frequency Set Points Frequency set points enable the CA bus to be switched between two differing operating frequencies with changes in voltage swings and termination values, without ever being in an untrained state, which could result in a loss of communication to the device. This is accomplished by duplicating all CA bus mode register parameters, as well as other mode register parameters commonly changed with operating frequency. These duplicated registers form two sets that use the same mode register addresses, with read/write access controlled by MR bit FSP-WR (frequency set point write/read) and the operating point controlled by MR bit FSP-OP (FREQUENCY SET POINT operation). Changing the FSP-WR bit enables MR parameters to be changed for an alternate frequency set-point without affecting the current operation. Once all necessary parameters have been written to the alternate set point, changing the FSP-OP bit will switch operation to use all of the new parameters simultaneously (within tFC), eliminating the possibility of a loss of communication that could be caused by a partial configuration change. Parameters which have two physical registers controlled by FSP-WR and FSP-OP include: Table 124: Mode Register Function with Two Physical Registers MR Number Operand MR1 OP[1:0] WR-PRE (Write preamble length) RD-PRE (Read preamble type) MR12 RD-PST (Read postamble length) RL (READ latency) OP[5:3] WL (WRITE latency) OP[6] WLS (WRITE latency set) OP[0] PU-CAL (Pull-up calibration point) OP[1] WR-PST (Write postamble length) PDDS (Pull-down drive strength) OP[6] DBI-RD (DBI-read enable) OP[7] DBI-WR (DBI-write enable) OP[2:0] DQ ODT (DQ bus receiver on-die termination) OP[6:4] CA ODT (CA bus receiver on-die termination) OP[5:0] VREF(CA) (VREF(CA) setting) OP[6] MR14 nWR (Write-recovery for AUTO PRECHARGE command) OP[2:0] OP[5:3] MR11 BL (Burst length) OP[3] OP[7] MR3 Notes OP[2] OP[6:4] MR2 Function OP[5:0] OP[6] VRCA (VREF(CA) range) VREF(DQ) (VREF(DQ) setting) VRDQ (VREF(DQ) range) 195 1 200b: x32 LPDDR4 SDRAM Frequency Set Points Table 124: Mode Register Function with Two Physical Registers (Continued) MR Number Operand MR22 OP[2:0] Function Notes SOC ODT (Controller ODT value for VOH calibration) OP[3] ODTE-CK (CK ODT enabled for non-terminating rank) OP[4] ODTE-CS (CS ODT enable for non-terminating rank) OP[5] ODTD-CA (CA ODT termination disable) 1. PU-CAL setting is required as the same value for both Ch. A and Ch. B before issuing ZQCAL START command. See Mode Register Definition section for more details. Note: Table below shows how the two mode registers for each of the parameters above can be modified by setting the appropriate FSP-WR value, and how device operation can be switched between operating points by setting the appropriate FSP-OP value. The FSPWR and FSP-OP functions operate completely independently. Table 125: Relation Between MR Setting and DRAM Operation Function MR# and Operand Data FSP-WR MR13 OP[6] 0 (default) Data write to mode register N for FSP-OP[0] by MRW command. 1 Data write to mode register N for FSP-OP[1] by MRW command. FSP-OP MR13 OP[7] Notes: Operation Notes 0 (default) DRAM operates with mode register N for FSP-OP[0] setting. 1 DRAM operates with mode register N for FSP-OP[1] setting. 1 2 1. FSP-WR stands for frequency set point write/read. 2. FSP-OP stands for frequency set point operating point. Frequency Set Point Update Timing The frequency set point update timing is shown below. When changing the frequency set point via MR13 OP[7], the V RCG setting: MR13 OP[3] have to be changed into V REF fast response (high current) mode at the same time. After frequency change time (tFC) is satisfied. V RCG can be changed into normal operation mode via MR13 OP[3]. 196 200b: x32 LPDDR4 SDRAM Frequency Set Points Figure 132: Frequency Set Point Switching Timing . T0 T1 T2 T3 T4 T5 Ta0 Ta1 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 CK_c CK_t Note 1 Frequency change tCKFSPE tVRCG_DISABLE tCKFSPX CKE CS CA DES Command DES MRW-1 MRW-1 MRW-2 MRW-2 FSP changes from 0 to 1 VRCG changes from normal to HIGH current DES DES DES DES DES MRW-1 MRW-1 MRW-2 MRW-2 DES DES DES DES DES DES VRCG changes from HIGH current to normal DES tFC_short/middle/long Applicable mode register Switching mode register Mode register for FSP-OP0 Mode register for FSP-OP1 Don’t Care Note: 1. For frequency change during frequency set point switching, refer to input Clock Stop and Frequency Change section. Table 126: Frequency Set Point AC Timing Parameter Symbol Min/ Max Frequency set point switching time tFC_short MIN tFC_middle MIN tFC_long Valid clock requirement after entering FSP change tCKFSPE Valid clock requirement before first valid command after FSP change tCKFSPX Note: Data Rate 1600 3200 3733 4267 Unit Notes 200 ns 1 200 ns MIN 250 ns MIN MAX(7.5ns, 4nCK) – MIN MAX(7.5ns, 4nCK) – 1. Frequency set point switching time depends on value of VREF(CA) setting: MR12 OP[5:0] and VREF(CA) range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in table below. Additionally change of frequency set point may affect VREF(DQ) setting. Settling time of VREF(DQ) level is the same as VREF(CA) level. Table 127: tFC Value Mapping Step Size Range Application From FSP-OP0 To FSP-OP1 From FSP-OP0 To FSP-OP1 tFC_short Base A single step size increment/decrement Base No change 197 200b: x32 LPDDR4 SDRAM Frequency Set Points Table 127: tFC Value Mapping (Continued) Step Size Range Application From FSP-OP0 To FSP-OP1 From FSP-OP0 To FSP-OP1 tFC_middle Base Two or more step size increment/decrement Base No change tFC_long – – Base Change Note: 1. As well as change from FSP-OP1 to FSP-OP0. Table 128: tFC Value Mapping: Example Case From/To FSP-OP: MR13 OP[7] VREF(CA) Setting: MR12: OP[5:0] VREF(CA) Range: MR12 OP[6] Application Notes 1 From 0 001100 0 tFC_short 1 To 1 001101 0 2 From 0 001100 0 tFC_middle 2 To 1 001110 0 3 From 0 Don't Care 0 tFC_long 3 To 1 Don't Care 1 Notes: 1. A single step size increment/decrement for VREF(CA) setting value. 2. Two or more step size increment/decrement for VREF(CA) setting value. 3. VREF(CA) range is changed. In this case, changing VREF(CA) setting doesn’t affect tFC value. The LPDDR4 SDRAM defaults to FSP-OP[0] at power-up. Both set points default to settings needed to operate in un-terminated, low-frequency environments. To enable the device to operate at higher frequencies, Command bus training mode should be utilized to train the alternate frequency set point. See Command Bus Training section for more details on this training mode. 198 200b: x32 LPDDR4 SDRAM Frequency Set Points Figure 133: Training for Two Frequency Set Points Power-up/ Initialization Prepare for CA bus training of FSP1 for high frequency FSP-OP = 0 FSP-WR = 0 Freq. = Boot FSP-OP = 0 FSP-WR = 1 Freq. = Boot CA bus training, FSP-OP1 CKE High to Low FSP-WR = 1 Freq. = High CKE LOW to HIGH Exit CA bus training Switch to highspeed mode FSP-OP = 0 FSP-WR = 1 Freq. = Boot FSP-OP = 1 FSP-WR = 1 Freq. = High Prepare for CA bus training of FSP0 for medium frequency FSP-OP = 1 FSP-WR = 0 Freq. = High CKE HIGH to LOW CA bus training, FSP-OP0 Exit CA bus training FSP-WR = 0 Freq. = Medium FSP-OP = 1 FSP-WR = 0 Freq. = High CKE LOW to HIGH Operate at high speed Once both of the frequency set points have been trained, switching between points can be performed with a single MRW followed by waiting for time tFC. Figure 134: Example of Switching Between Two Trained Frequency Set Points State n-1: FSP-OP = 1 MRW command State n: FSP-OP = 0 Operate at high speed State n-1: FSP-OP = 0 MRW command State n: FSP-OP = 1 tFC Operate at medium speed Operate at high speed tFC Switching to a third (or more) set point can be accomplished if the memory controller has stored the previously-trained values (in particular the V REF(CA) calibration value) and rewrites these to the alternate set point before switching FSP-OP. 199 200b: x32 LPDDR4 SDRAM Pull-Up and Pull-Down Characteristics and Calibration Figure 135: Example of Switching to a Third Trained Frequency Set Point State n-1: FSP-WR = 1 MRW command State n: FSP-WR = 0 Operate at high speed State n-1: FSP-OP = 1 MRW command State n: FSP-OP = 0 MRW command {VREF(CA) CA ODT, DQ ODT, RL, WL, VREF(DQ), ODTD-CA...} tFC Operate at third speed tFC Pull-Up and Pull-Down Characteristics and Calibration Table 129: Pull-Down Driver Characteristics – ZQ Calibration RONPD,nom Register Min Nom Max Unit 40 Ohm RON40PD 0.90 1.0 1.10 RZQ/6 48 Ohm RON48PD 0.90 1.0 1.10 RZQ/5 60 Ohm RON60PD 0.90 1.0 1.10 RZQ/4 80 Ohm RON80PD 0.90 1.0 1.10 RZQ/3 120 Ohm RON120PD 0.90 1.0 1.10 RZQ/2 240 Ohm RON240PD 0.90 1.0 1.10 RZQ/1 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%. Note: Table 130: Pull-Up Characteristics – ZQ Calibration VOHPU,nom VOH,nom Min Nom Max Unit VDDQ/2.5 440 0.90 1.0 1.10 VOH,nom VDDQ/3 367 0.90 1.0 1.10 VOH,nom Notes: 1. All value are after ZQ calibration. Without ZQ calibration, RONPD values are ±30%. 2. VOH,nom (mV) values are based on a nominal VDDQ = 1.1V. Table 131: Valid Calibration Points ODT Value VOHPU 240 120 80 60 48 40 VDDQ/2.5 Valid Valid Valid DNU DNU DNU 200 200b: x32 LPDDR4 SDRAM On-Die Termination for the Command/Address Bus Table 131: Valid Calibration Points (Continued) ODT Value VOHPU 240 120 80 60 48 40 VDDQ/3 Valid Valid Valid Valid Valid Valid Notes: 1. Once the output is calibrated for a given VOH(nom) calibration point, the ODT value may be changed without recalibration. 2. If the VOH(nom) calibration point is changed, then recalibration is required. 3. DNU = Do not use. On-Die Termination for the Command/Address Bus The on-die termination (ODT) feature allows the device to turn on/off termination resistance for CK_t, CK_c, CS, and CA[5:0] signals without the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to turn on and off termination resistance for any target DRAM devices via the mode register setting. A simple functional representation of the DRAM ODT feature is shown below. Figure 136: ODT for CA RTT = VOUT |IOUT| VDD2 To other circuitry like RCV, ... ODT CA IOUT RTT VOUT VSS ODT Mode Register and ODT State Table ODT termination values are set and enabled via MR11. The CA bus (CK_t, CK_c, CS, CA[5:0]) ODT resistance values are set by MR11 OP[6:4]. The default state for the CA is ODT disabled. ODT is applied on the CA bus to the CK_t, CK_c, CS, and CA signals. The CA ODT of the device is designed to enable one rank to terminate the entire command bus in a multirank system, so only one termination load will be present even if multiple devices are 201 200b: x32 LPDDR4 SDRAM On-Die Termination for the Command/Address Bus sharing the command signals. For this reason, CA ODT remains on, even when the device is in the power-down or self refresh power-down state. The die has a bond pad (ODT_CA) for multirank operations. When the ODT_CA pad is LOW, the die will not terminate the CA bus regardless of the state of the mode register CA ODT bits (MR11 OP[6:4]). If, however, the ODT_CA bond pad is HIGH and the mode register CA ODT bits are enabled, the die will terminate the CA bus with the ODT values found in MR11 OP[6:4]. In a multirank system, the terminating rank should be trained first, followed by the non-terminating rank(s). Table 132: Command Bus ODT State CA ODT MR11[6:4] ODT_CA Bond Pad ODTD-CA MR22 OP[5] ODTE-CK MR22 OP[3] ODTE-CS MR22 OP[4] ODT State for CA ODT State for CK ODT State for CS Disabled1 Valid2 Valid3 Valid3 Valid3 Off Off Off 0 Valid3 0 0 Off Off Off Valid 3 Valid 3 0 Valid3 0 1 Off Off On Valid 3 0 Valid3 1 0 Off On Off Valid 3 0 Valid3 1 1 Off On On 0 Valid3 Valid3 On On On 1 Valid3 Valid3 Off On On Valid 3 Valid 3 1 1 Notes: 1. 2. 3. 4. Default value. Valid = H or L (a defined logic level) Valid = 0 or 1. The state of ODT_CA is not changed when the device enters power-down mode. This maintains termination for alternate ranks in multirank systems. ODT Mode Register and ODT Characteristics Table 133: ODT DC Electrical Characteristics – up to 3200 Mbps RZQ Ω ±1% over entire operating range after calibration MR11 OP[6:4] RTT VOUT 001b 010b 011b 100b Ω Ω Ω Ω Min Nom Max Unit Notes VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/1 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 RZQ/2 1, 2 RZQ/3 1, 2 RZQ/4 1, 2 VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 V OM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 202 200b: x32 LPDDR4 SDRAM On-Die Termination for the Command/Address Bus Table 133: ODT DC Electrical Characteristics – up to 3200 Mbps (Continued) RZQ Ω ±1% over entire operating range after calibration MR11 OP[6:4] RTT VOUT 101b 110b Ω Ω Mismatch, CA -CA within clock group Notes: Min Nom Max Unit Notes VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/5 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/6 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.2 0.33 × VDD2 – – 2 % 1, 2, 3 1. The tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the section on voltage and temperature sensitivity. 2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDD2. Other calibration points may be required to achieve the linearity specification shown above, for example, calibration at 0.5 × VDD2 and 0.1 × VDD2. 3. CA to CA mismatch within clock group variation for a given component including CK_t, CK_c ,and CS (characterized). CA-to-CA mismatch = RODT (MAX) - RODT (MIN) RODT (AVG) Table 134: ODT DC Electrical Characteristics – Beyond 3200 Mbps RZQ Ω ±1% over entire operating range after calibration MR11 OP[6:4] RTT VOUT 001b 010b 011b 100b 101b Ω Ω Ω Ω Ω Min Nom Max Unit Notes RZQ/1 1, 2 RZQ/2 1, 2 RZQ/3 1, 2 RZQ/4 1, 2 RZQ/5 1, 2 VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 V OM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 203 200b: x32 LPDDR4 SDRAM On-Die Termination for the Command/Address Bus Table 134: ODT DC Electrical Characteristics – Beyond 3200 Mbps (Continued) RZQ Ω ±1% over entire operating range after calibration MR11 OP[6:4] RTT VOUT Min Nom Max Unit Notes VOL(DC) = 0.1 × VDD2 0.8 1.0 1.1 RZQ/6 1, 2 VOM(DC) = 0.33 × VDD2 0.9 1.0 1.1 VOH(DC) = 0.5 × VDD2 0.9 1.0 1.3 0.33 × VDD2 – – 2 % 1, 2, 3 Ω 110b Mismatch, CA -CA within clock group Notes: 1. The tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the section on voltage and temperature sensitivity. 2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDD2. Other calibration points may be required to achieve the linearity specification shown above, e.g. calibration at 0.5 × VDD2 and 0.1 × VDD2. 3. CA to CA mismatch within clock group variation for a given component including CK_t, CK_c ,and CS (characterized). CA-to-CA mismatch = RODT (MAX) - RODT (MIN) RODT (AVG) ODT for CA Update Time Figure 137: ODT for CA Setting Update Timing in 4-Clock Cycle Command T0 T1 T2 T3 T4 T5 Ta Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 DES MRW1 MRW1 MRW2 MRW2 DES DES DES DES DES Valid 1 Valid 1 Valid 1 Valid 1 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid CK_c CK_t CKE CS_n Command CA[5:0] CA ODT Old setting value Updating setting New setting value tODTUP Don’t Care 204 200b: x32 LPDDR4 SDRAM DQ On-Die Termination DQ On-Die Termination On-die termination (ODT) is a feature that allows the device to turn on/off termination resistance for each DQ, DQS, and DMI signal without the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to turn on and off termination resistance for any target DRAM devices during WRITE or MASK WRITE operation. The ODT feature is off and cannot be supported in power-down and self refresh modes. The switch is enabled by the internal ODT control logic, which uses the WRITE-1 or MASK WRITE-1 command and other mode register control information. The value of RTT is determined by the MR bits. RTT = VOUT |IOUT| Figure 138: Functional Representation of DQ ODT VDDQ To other circuitry like RCV, ... ODT DQ IOUT VOUT RTT VSSQ Table 135: ODT DC Electrical Characteristics – up to 3200 Mbps RZQ Ω ±1% over entire operating range after calibration MR11 OP[2:0] RTT VOUT 001b 010b 011b Ω Ω Ω Min Nom Max Unit Notes VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/1 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/2 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 RZQ/3 1, 2 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 205 200b: x32 LPDDR4 SDRAM DQ On-Die Termination Table 135: ODT DC Electrical Characteristics – up to 3200 Mbps (Continued) RZQ Ω ±1% over entire operating range after calibration MR11 OP[2:0] RTT VOUT 100b 101b 110b Ω Ω Ω Mismatch error, DQ-to-DQ within a channel Notes: Min Nom Max Unit Notes VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/4 1, 2 V OM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 RZQ/5 1, 2 RZQ/6 1, 2 % 1, 2, 3 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.2 0.33 × VDDQ – – 2 1. The ODT tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the following section on voltage and temperature sensitivity. 2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDDQ. Other calibration points may be required to achieve the linearity specification shown above, (for example, calibration at 0.5 × VDDQ and –0.1 × VDDQ. 3. DQ-to-DQ mismatch within byte variation for a given component, including DQS (characterized). DQ-to-DQ mismatch= RODT (MAX) - RODT (MIN) RODT (AVG) Table 136: ODT DC Electrical Characteristics – Beyond 3200 Mbps RZQ Ω ±1% over entire operating range after calibration MR11 OP[2:0] RTT VOUT 001b 010b 011b 100b Ω Ω Ω Ω Min Nom Max Unit Notes VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/1 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 RZQ/2 1, 2 RZQ/3 1, 2 RZQ/4 1, 2 VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 V OM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 206 200b: x32 LPDDR4 SDRAM DQ On-Die Termination Table 136: ODT DC Electrical Characteristics – Beyond 3200 Mbps (Continued) RZQ Ω ±1% over entire operating range after calibration MR11 OP[2:0] RTT VOUT Ω 101b Ω 110b Mismatch error, DQ-to-DQ within a channel Notes: Min Nom Max Unit Notes VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 RZQ/5 1, 2 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 RZQ/6 1, 2 % 1, 2, 3 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 VOL(DC) = 0.1 × VDDQ 0.8 1.0 1.1 VOM(DC) = 0.33 × VDDQ 0.9 1.0 1.1 VOH(DC) = 0.5 × VDDQ 0.9 1.0 1.3 0.33 × VDDQ – – 2 1. The ODT tolerance limits are specified after calibration with stable temperature and voltage. To understand the behavior of the tolerance limits when voltage or temperature changes after calibration, see the following section on voltage and temperature sensitivity. 2. Pull-down ODT resistors are recommended to be calibrated at 0.33 × VDDQ. Other calibration points may be required to achieve the linearity specification shown above, for example, calibration at 0.5 × VDDQ and –0.1 × VDDQ. 3. DQ-to-DQ mismatch within byte variation for a given component, including DQS (characterized). DQ-to-DQ mismatch= RODT (MAX) - RODT (MIN) RODT (AVG) Output Driver and Termination Register Temperature and Voltage Sensitivity When temperature and/or voltage change after calibration, the tolerance limits are widen according to the tables below. Table 137: Output Driver and Termination Register Sensitivity Definition Resistor Definition Point Min Max Unit Notes RONPD 0.33 × VDDQ 90 - (dRONdT ΔT|) - (dRONdV ΔV|) 110 + (dRONdT ΔT|) + (dRONdV ΔV|) % 1, 2 VOHPU 0.33 × VDDQ 90 - (dVOHdT ΔT|) - (dVOHdV ΔV|) 110 + (dVOHdT ΔT|) + (dVOHdV ΔV|) 1, 2, 5 RTT(I/O) 0.33 × VDDQ 90 - (dRONdT ΔT|) - (dRONdV ΔV|) 110 + (dRONdT ΔT|) + (dRONdV ΔV|) 1, 2, 3 RTT(IN) 0.33 × VDD2 90 - (dRONdT ΔT|) - (dRONdVΔV|) 110 + (dRONdT ΔT|) + (dRONdV ΔV|) 1, 2, 4 Notes: 1. ΔT = T - T(@calibration), ΔV = V - V(@calibration) 2. dRONdT, dRONdV, dVOHdT, dVOHdV, dRTTdV, and dRTTdT are not subject to production test but are verified by design and characterization. 3. This parameter applies to input/output pin such as DQS, DQ, and DMI. 4. This parameter applies to input pin such as CK, CA, and CS. 5. Refer to Pull-up/Pull-down Driver Characteristics for VOHPU. 207 200b: x32 LPDDR4 SDRAM DQ On-Die Termination Table 138: Output Driver and Termination Register Temperature and Voltage Sensitivity Symbol Min Max Unit dRONdT Parameter RON temperature sensitivity 0 0.75 %/˚C dRONdV RON voltage sensitivity 0 0.20 %/mV dVOHdT VOH temperature sensitivity 0 0.75 %/˚C dVOHdV VOH voltage sensitivity 0 0.35 %/mV dRTTdT RTT temperature sensitivity 0 0.75 %/˚C dRTTdV RTT voltage sensitivity 0 0.20 %/mV ODT Mode Register The ODT mode is enabled if MR11 OP[2:0] are non-zero. In this case, the value of RTT is determined by the settings of those bits. The ODT mode is disabled if MR11 OP[2:0] = 0. Asynchronous ODT When ODT mode is enabled in MR11 OP[2:0], DRAM ODT is always High-Z. The DRAM ODT feature is automatically turned ON asynchronously after a WRITE-1, MASK WRITE-1, or MPC[WRITE-FIFO] command. After the burst write is complete, the DRAM ODT turns OFF asynchronously. The DQ bus ODT control is automatic and will turn the ODT resistance on/off if DQ ODT is enabled in the mode register. The following timing parameters apply when the DQ bus ODT is enabled: • ODTLon, tODTon (MIN), tODTon (MAX) • ODTLoff, tODToff (MIN), tODToff (MAX) ODTLON is a synchronous parameter and is the latency from a CAS-2 command to the tODTon reference. ODTL ON latency is a fixed latency value for each speed bin. Each speed bin has a different ODTLON latency. Minimum RTT turn-on time ( tODTon (MIN)) is the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn on time ( tODTon (MAX)) is the point in time when the ODT resistance is fully on. tODTon (MIN) and tODTon (MAX) are measured once ODTLon latency is satisfied from CAS-2 command. ODTLOFF is a synchronous parameter and it is the latency from CAS-2 command to tODToff reference. ODTL OFF latency is a fixed latency value for each speed bin. Each speed bin has a different ODTLOFF latency. Minimum RTT turn-off time ( tODToff (MIN)) is the point in time when the device termination circuit starts to turn off the ODT resistance. Maximum ODT turn off time ( tODToff (MAX)) is the point in time when the on-die termination has reached High-Z. tODToff (MIN) and tODToff (MAX) are measured once ODTLoff latency is satisfied from CAS-2 command. 208 200b: x32 LPDDR4 SDRAM DQ On-Die Termination Table 139: ODTLON and ODTLOFF Latency Values ODTLON Latency1 WL Set A (nCK) WL Set B (nCK) WL Set A (nCK) WL Set B (nCK) Lower Frequency Limit (>) (MHz) N/A N/A N/A N/A 10 266 N/A N/A N/A N/A 266 533 N/A 6 N/A 22 533 800 4 12 20 28 800 1066 4 14 22 32 1066 1333 6 18 24 36 1333 1600 6 20 26 40 1600 1866 8 24 28 44 1866 2133 tWPRE = 2 tCK ODTLOFF Latency2 Upper Frequency Limit (≤ ≤) (MHz) 1. ODTLON is referenced from CAS-2 command. 2. ODTLOFF as shown in table assumes BL = 16. For BL32, 8 tCK should be added. Notes: Figure 139: Asynchronous ODTon/ODToff Timing T0 T1 T2 T3 BL BA0, CA, AP CAn CAn T4 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 Ta13 Ta14 Ta15 Ta16 DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES Ta17 Ta18 Ta19 Ta20 Ta21 DES DES CK_c CK_t CS CA Command WRITE-1 CAS-2 t WL DES DES DES DES DQSS(MIN) t t WPRE WPST DQS_c DQS_t t DQ DMI DIN n0 t DQS2DQ DIN DIN n1 n2 DIN n3 DIN n4 DIN n5 DIN n6 DIN n7 DIN n8 DIN n9 DIN DIN DIN DIN DIN DIN n10 n11 n12 n13 n14 n15 DQSS(MAX) t t WPRE WPST DQS_c DQS_t t DQ DMI DIN n0 t ODTLon t DRAM RTT DQS2DQ DIN DIN n1 n2 DIN n3 DIN n4 DIN n5 DIN n6 DIN n8 DIN n9 DIN DIN DIN DIN DIN DIN n10 n11 n12 n13 n14 n15 t ODTon(MAX) t ODTon(MIN) ODT High-Z DIN n7 ODTL2Q Transition ODToff(MAX) ODToff(MIN) Transition ODT High-Z ODTLoff Don’t Care Notes: 1. BL = 16, Write postamble = 0.5nCK, DQ/DQS: VSSQ termination 2. Din n = data-in to column n. 209 200b: x32 LPDDR4 SDRAM DQ On-Die Termination 3. DES commands are shown for ease of illustration; other commands may be valid at these times. DQ ODT During Power-Down and Self Refresh Modes DQ bus ODT will be disabled in power-down mode. In self refresh mode, the ODT will be turned off when CKE is LOW but will be enabled if CKE is HIGH and DQ ODT is enabled in the mode register. ODT During Write Leveling Mode If ODT is enabled in MR11 OP[2:0] in write leveling mode, the device always provides the termination on DQS signals. DQ termination is always off in write leveling mode. Table 140: Termination State in Write Leveling Mode DQS Termination DQ[15:0]/DMI[1:0] Termination Disabled Off Off Enabled On Off ODT State in MR11 OP[2:0] 210 200b: x32 LPDDR4 SDRAM Target Row Refresh Mode Target Row Refresh Mode The device limits the number of times that a given row can be accessed within a refresh period (tREFW × 2) prior to requiring adjacent rows to be refreshed. The maximum activate count (MAC) is the maximum number of activates that a single row can sustain within a refresh period before the adjacent rows need to be refreshed. The row receiving the excessive actives is the target row (TRn), the adjacent rows to be refreshed are the victim rows. When the MAC limit is reached on TRn, either the device receives all (R × 2) REFRESH commands before another row activate is issued, or the device should be placed into targeted row refresh (TRR) mode. The TRR mode will refresh the rows adjacent to the TRn that encountered tMAC limit. If the device supports unlimited MAC value: MR24 OP[2:0] = 000 and MR24 OP[3] = 1, TARGET ROW REFRESH operation is not required. Even though the device allows to set MR24 OP[7] = 1: TRR mode enable, in this case the device behavior is vendor specific. For example, a certain device may ignore MRW command for entering/exiting TRR mode or a certain device may support commands related TRR mode. See vendor device datasheets for details about TRR mode definition at supporting unlimited MAC value case. There could be a maximum of two target rows to a victim row in a bank. The cumulative value of the activates from the two target rows on a victim row in a bank should not exceed MAC value. MR24 fields are required to support the new TRR settings. Setting MR24 OP[7] = 1 enables TRR mode and setting MR24 OP[7] = 0 disables TRR mode. MR24 OP[6:4] defines which bank (BAn) the target row is located in (refer to MR24 table for details). The TRR mode must be disabled during initialization as well as any other device calibration modes. The TRR mode is entered from a DRAM idle state, once TRR mode has been entered, no other mode register commands are allowed until TRR mode is completed; however, setting MR24 OP[7] = 0 to interrupt and reissue the TRR mode is allowed. When enabled, TRR mode is self-clearing. the mode will be disabled automatically after the completion of defined TRR flow (after the third BAn precharge has completed plus tMRD). Optionally, the TRR mode can also be exited via another MRS command at the completion of TRR by setting MR24 OP[7] = 0. If the TRR is exited via another MRS command, the value written to MR24 OP[6:4] are "Don’t Care." TRR Mode Operation 1. The timing diagram depicts TRR mode. The following steps must be performed when TRR mode is enabled. This mode requires all three ACT (ACT1, ACT2, and ACT3) and three corresponding PRE commands (PRE1, PRE2, and PRE3) to complete TRR mode. PRECHARGE All (PREA) commands issued while the device is in TRR mode will also perform precharge to BAn and counts towards PREn command. 2. Prior to issuing the MRW command to enter TRR mode, the device should be in the idle state. MRW command must be issued with MR24 OP[7] = 1 and MR24 OP[6:4] defining the bank in which the targeted row is located. All other MR24 bits should remain unchanged. 3. No activity is to occur with the device until tMRD has been satisfied. When tMRD has been satisfied, the only commands allowed BAn, until TRR mode has completed, are ACT and PRE. 211 200b: x32 LPDDR4 SDRAM Target Row Refresh Mode 4. The first ACT to the BAn with the TRn address can now be applied; no other command is allowed at this point. All other banks must remain inactive from when the first BAn ACT command is issued until [(1.5 x tRAS) + tRP] is satisfied. 5. After the first ACT to the BAn with the TRn address is issued, PRE to BAn is to be issued (1.5 × tRAS) later; and then followed tRP later by the second ACT to the BAn with the TRn address. 6. After the second ACT to the BAn with the TRn address is issued, PRE to BAn is to be issued tRAS later and then followed tRP later by the third ACT to the BAn with the TRn address. 7. After the third ACT to the BAn with the TRn address is issued, PRE to BAn would be issued tRAS later. TRR mode is completed once tRP plus tMRD is satisfied. 8. TRR mode must be completed as specified to guarantee that adjacent rows are refreshed. Anytime the TRR mode is interrupted and not completed, the interrupted TRR mode must be cleared and then subsequently performed again. To clear an interrupted TRR mode, MR24 change is required with setting MR24 OP[7] = 0, MR24 OP[6:4] are "Don’t care," followed by three PRE to BAn, with tRP time in between each PRE command. The complete TRR sequence (steps 2–7) must be then reissued and completed to guarantee that the adjacent rows are refreshed. 9. A REFRESH command to the device, or entering self refresh mode, is not allowed while the device is in TRR mode. Figure 140: Target Row Refresh Mode T0 T1 T2 T3 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Td0 Td1 Td2 Td3 Te0 Te1 Tf0 Tf1 Tf2 Tf3 Tg0 Tg1 Tg2 Tg3 Th0 Th1 Th2 Th3 Tk0 Tk1 Tk2 Tm0 Tm1 Tm2 Tm3 Tm4 Tm5 CK_c CK_t CKE CS ACT1 Command MRW-1 MRW-2 DES PRE1 ACT-2 ACT-1 1st ACT TRR entry N/A N/A N/A N/A N/A BAn N/A N/A Address OP MA OP OP TRn TRn TRn TRn tMRD BAn BAn in idle ACT-1 PRE2 ACT-2 DES CMD-1 CMD-2 2nd ACT BAn N/A BAn N/A N/A V Non BAn N/A N/A TRn TRn TRn TRn V V tRP DES PRE ACT3 DES CMD-1 CMD-2 DES V N/A BAn V Non BAn V V V N/A N/A V V V CMD-1 CMD-2 N/A BAn N/A N/A V Non BAn V TRn TRn TRn TRn V V 9 BAn TRR operation allowed DES PRE V V N/A BAn V V N/A N/A tRAS Activity allowed No activity allowed in other banks (Banks closed) DES DES CMD-2 CMD-1 DES 3rd PRE V t RP No activity allowed (Banks closed) DES 3rd ACT V tRAS PRE3 ACT-2 ACT-1 2nd PRE N/A 1.5 × tRAS Non BAn in idle ACT2 DES PRE 1st PRE Bank Address Non BAn DES tRP V Any BAn V V V V V V + tMRD No activity allowed (may have bank(s) open) Activity allowed Activity allowed Don’t Care Notes: 1. TRn is the targeted row. 2. Bank BAn represents the bank in which the targeted row is located. 3. TRR mode self-clears after tMRD + tRP measured from the third BAn precharge PRE3 at clock edge Th4. 4. TRR mode or any other activity can be re-engaged after tRP + tMRD from the third BAn precharge PRE3. PRE_ALL also counts if it is issued instead of PREn. TRR mode is cleared by the device after PRE3 to the BAn bank. 5. ACTIVATE commands to BAn during TRR mode do not provide refresh support (the refresh counter is unaffected). 6. The device must restore the degraded row(s) caused by excessive activation of the targeted row (TRn) necessary to meet refresh requirements. 7. A new TRR mode must wait tMRD + tRP time after the third precharge. 8. BAn may not be used with any other command. 9. ACT and PRE are the only allowed commands to BAn during TRR mode. 10. REFRESH commands are not allowed during TRR mode. 212 200b: x32 LPDDR4 SDRAM Post-Package Repair 11. All timings are to be met by DRAM during TRR mode, such as tFAW. Issuing ACT1, ACT2, and ACT3 counts towards tFAW budget. Post-Package Repair The device has fail row address repair as an optional post-package repair (PPR) feature and it is readable through MR25 OP[7:0]. PPR provides simple and easy repair method in the system and fail row address can be repaired by the electrical programming of Electrical-fuse scheme. The device can correct one row per bank with PPR. Electrical-fuse cannot be switched back to un-fused states once it is programmed. The controller should prevent unintended PPR mode entry and repair. Failed Row Address Repair 1. 2. 3. 4. 5. 6. 7. 8. Before entering PPR mode, all banks must be precharged. Enable PPR using MR4 OP[4] = 1 and wait tMRD. Issue ACT command with fail row address. Wait tPGM to allow the device repair target row address internally then issue PRECHARGE Wait tPGM_EXIT after PRECHARGE, which allows the device to recognize repaired row address RAn. Exit PPR mode with setting MR4 OP[4] = 0. The device is ready for any valid command after tPGMPST. In more than one fail address repair case, repeat step 2 to 7. Once PPR mode is exited, to confirm whether the target row has correctly repaired, the host can verify the repair by writing data into the target row and reading it back after PPR exit with MR4 OP[4] = 0 and tPGMPST. The following timing diagram shows PPR operation. 213 200b: x32 LPDDR4 SDRAM Post-Package Repair Figure 141: Post-Package Repair Timing T0 T1 T2 T3 T4 T5 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Td0 Td1 Td2 Td3 Td4 Td5 CK_c CK_t CKE CS Command DES MR WRITE-1 MR WRITE-2 DES BA Address PPR staus ACT-1 ACT-2 DES PRE DES DES Any command MR WRITE-1 MR WRITE-2 DES Any command N/A N/A N/A N/A Valid BA Valid Valid Valid Valid N/A N/A N/A N/A Valid Valid Valid Valid MA OP RAn RAn RAn RAn Valid Valid OP MA OP Valid Valid Valid Valid OP OP Normal mode (All banks must be idle) Move to PPR mode PPR repair t MRD OP Move to PPR mode PPR recognition t PGM t PGM_Exit Normal mode t PGMPST Don’t Care Notes: 1. 2. 3. 4. During tPGM, any other commands (including refresh) are not allowed on each die. With one PPR command, only one row can be repaired at one time per die. When PPR procedure completes, reset procedure is required before normal operation. During PPR, memory contents are not refreshed and may be lost. Table 141: Post-Package Repair Timing Parameters Parameter PPR programming time PPR exit time New address setting time Symbol Min Max Units tPGM 1000 – ms tPGM_EXIT 15 – ns tPGMPST 50 – μs 214 200b: x32 LPDDR4 SDRAM Read Preamble Training Read Preamble Training Read preamble training is supported through the MPC function. This mode can be used to train or read level the DQS receivers. After read preamble training is enabled by MR13 OP[1] = 1, the device will drive DQS_t LOW and DQS_c HIGH within tSDO and remain at these levels until an MPC[READ DQ CALIBRATION] command is issued. During read preamble training, the DQS preamble provided during normal operation will not be driven by the device. After the MPC[READ DQ CALIBRATION] command is issued, the device will drive DQS_t/DQS_c and DQ like a normal READ burst after RL and tDQSCK. Prior to the MPC[READ DQ CALIBRATION] command, the device may or may not drive DQ[15:0] in this mode. While in read preamble training mode, only READ DQ CALIBRATION commands may be issued. • Issue an MPC[READ DQ CALIBRATION] command followed immediately by a CAS-2 command. • Each time an MPC[READ DQ CALIBRATION] command followed by a CAS-2 is received by the device, a 16-bit data burst will, after the currently set RL, drive the eight bits programmed in MR32 followed by the eight bits programmed in MR40 on all I/O pins. • The data pattern will be inverted for I/O pins with a 1 programmed in the corresponding invert mask mode register bit. • Note that the pattern is driven on the DMI pins, but no DATA BUS INVERSION function is enabled, even if read DBI is enabled in the DRAM mode register. • This command can be issued every tCCD seamlessly. • The operands received with the CAS-2 command must be driven LOW. Read preamble training is exited within tSDO after setting MR13 OP[1] = 0. The device supports the READ preamble training as optional feature. Refer to vendorspecific data sheets. Figure 142: Read Preamble Training T0 T1 T2 T3 Ta2 Ta3 Ta4 Ta6 T4 Ta0 Ta1 Ta5 DES DES MPC MPC DES [RD DQ CAL] [RD DQ CAL] CAS-2 CAS-2 DES Tb0 Tb1 Tc0 Tc1 DES DES Tc2 Tc3 Tc4 Td0 Td1 Td2 Td3 Td4 Td5 Te0 Te1 CK_c CK_t CS Command MRW-1 MRW-1 MRW-2 MRW-2 tSDO DES DES DES DES DES DES MRW-1 MRW-1 MRW-2 MRW-2 tDQSCK RL DES DES DES tSDO Read preamble training mode = Enable: MR13[OP1] = 1 Read preamble training mode = Enable: MR13[OP1] = 0 DQS_c DQS_t t DQSQ DQ DMI DOUT DOUT DOUT DOUT DOUT DOUT n0 n1 n12 n13 n14 n15 DQ (High-Z or Driven ) DQ (High-Z or Driven ) Don’t Care Note: 1. Read DQ calibration supports only BL16 operation. 215 200b: x32 LPDDR4 SDRAM Electrical Specifications Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed in the table below may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these conditions, or any other conditions outside those indicated in the operational sections of this document, is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 142: Absolute Maximum DC Ratings Parameter Symbol Min Max Unit Notes VDD1 –0.4 2.1 V 1 VDD2 supply voltage relative to VSS VDD2 –0.4 1.5 V 1 VDDQ supply voltage relative to VSS VDDQ –0.4 1.5 V 1 Voltage on any ball relative to VSS VIN, VOUT –0.4 1.5 V TSTG –55 125 ˚C VDD1 supply voltage relative to VSS Storage temperature Notes: 2 1. For information about relationships between power supplies, see the Voltage Ramp and Device Initialization section. 2. Storage temperature is the case surface temperature on the center/top side of the device. For measurement conditions, refer to the JESD51-2 standard. AC and DC Operating Conditions Operation or timing that is not specified is illegal. To ensure proper operation, the device must be initialized properly. Table 143: Recommended DC Operating Conditions Symbol Min Typ Max DRAM Unit Notes VDD1 1.7 1.8 1.95 Core 1 power V 1, 2 VDD2 1.06 1.1 1.17 Core 2 power/Input buffer power V 1, 2, 3 VDDQ 1.06 1.1 1.17 I/O buffer power V 2, 3 Notes: 1. VDD1 uses significantly less power than VDD2. 2. The voltage range is for DC voltage only. DC voltage is the voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz at the DRAM package ball. 3. The voltage noise tolerance from DC to 20 MHz exceeding a peak-to-peak tolerance of 45mV at the DRAM ball is not included in the TdIVW. 216 200b: x32 LPDDR4 SDRAM AC and DC Operating Conditions Table 144: Input Leakage Current Parameter/Condition Symbol Min Max Unit Notes IL –4 4 μA 1, 2 Input leakage current Notes: 1. For CK_t, CK_c, CKE, CS, CA, ODT_CA, and RESET_n. Any input 0V ≤ VIN ≤ VDD2. (All other pins not under test = 0V. 2. CA ODT is disabled for CK_t, CK_c, CS, and CA. Table 145: Input/Output Leakage Current Parameter/Condition Symbol Min Max Unit Notes IOZ –5 5 μA 1, 2 Input/Output leakage current Notes: 1. For DQ, DQS_t, DQS_c, and DMI. Any I/O 0V ≤ VOUT ≤ VDDQ. 2. I/Os status are disabled: High Impedance and ODT off. Table 146: Operating Temperature Range Parameter/Condition Standard Symbol Min Max Unit TOPER Note 4 85 ˚C 85 Note 4 ˚C Elevated Notes: 1. Operating temperature is the case surface temperature at the center of the top side of the device. For measurement conditions, refer to the JESD51-2 standard. 2. When using the device in the elevated temperature range, some derating may be required. See Mode Registers for vendor-specific derating. 3. Either the device case temperature rating or the temperature sensor can be used to set an appropriate refresh rate, determine the need for AC timing derating, and/or monitor the operating temperature (see Temperature Sensor). When using the temperature sensor, the actual device case temperature may be higher than the TOPER rating that applies for the standard or elevated temperature range. For example, TCASE could be above +85˚C when the temperature sensor indicates a temperature of less than +85˚C. 4. Refer to Operating temperature range on top page. 217 200b: x32 LPDDR4 SDRAM AC and DC Input Measurement Levels AC and DC Input Measurement Levels Input Levels for CKE Table 147: Input Levels Parameter Symbol Min Max Unit Notes Input HIGH level (AC) VIH(AC) 0.75 × VDD2 VDD2 + 0.2 V 1 Input LOW level (AC) VIL(AC) –0.2 0.25 × VDD2 V 1 Input HIGH level (DC) VIH(DC) 0.65 × VDD2 VDD2 + 0.2 V Input LOW level (DC) VIL(DC) –0.2 0.35 × VDD2 V Note: 1. See the AC Overshoot and Undershoot section. Figure 143: Input Timing Definition for CKE VIH(AC) VIH(DC) VIL(AC) VIL(DC) Input level Don’t Care Input Levels for RESET_n and ODT_CA Table 148: Input Levels Parameter Symbol Min Max Unit Notes Input HIGH level VIH 0.80 × VDD2 VDD2 + 0.2 V 1 Input LOW level VIL –0.2 0.20 × VDD2 V 1 Note: 1. See the AC Overshoot and Undershoot section. Figure 144: Input Timing Definition for RESET_n and ODT_CA VIH VIH VIL VIL Input level Don’t Care Differential Input Voltage for CK The minimum input voltage needs to satisfy both V indiff_CK and V indiff_CK/2 specification at input receiver and their measurement period is 1tCK. V indiff_CK is the peak-to-peak 218 200b: x32 LPDDR4 SDRAM AC and DC Input Measurement Levels voltage centered on 0 volts differential and V indiff_CK/2 is maximum and minimum peak voltage from 0 volts. 0.0  Vindiff_CK Vindiff_CK/2 Peak voltage Vindiff_CK/2 Differential Input Voltage : CK_t - CK_c Figure 145: CK Differential Input Voltage Peak voltage Time Table 149: CK Differential Input Voltage 1600/1867 2133/2400/3200 3733/4267 Parameter Symbol Min Max Min Max Min Max Unit Note CK differential input voltage Vindiff_CK 420 – 380 – 360 – mV 1 Note: 1. The peak voltage of differential CK signals is calculated in a following equation. • • • • Vindiff_CK = (Maximum peak voltage) - (Minimum peak voltage) Maximum peak voltage = MAX(f(t)) Minimum peak voltage = MIN(f(t)) f(t) = VCK_t - VCK_c Peak Voltage Calculation Method The peak voltage of differential clock signals are calculated in a following equation. • VIH.DIFF.peak voltage = MAX(f(t)) • VIL.DIFF.peak voltage = MIN(f(t)) • f(t) = V CK_t - V CK_c 219 200b: x32 LPDDR4 SDRAM AC and DC Input Measurement Levels Figure 146: Definition of Differential Clock Peak Voltage Single Ended Input Voltage CK_t Min(f(t)) Max(f(t)) VREF(CA) CK_c Time 1. VREF(CA) is device internal setting value by VREF training. Note: Single-Ended Input Voltage for Clock The minimum input voltage need to satisfy V inse_CK, V inse_CK_HIGH, and V inse_CK_LOW specification at input receiver. Figure 147: Clock Single-Ended Input Voltage Vinse_CK_LOW Vinse_CK Vinse_CK_HIGH Vinse_CK_HIGH Vinse_CK_LOW VREF(CA) Vinse_CK Single Ended Input Voltage CK_t CK_c Time Note: 1. VREF(CA) is device internal setting value by VREF training. 220 200b: x32 LPDDR4 SDRAM AC and DC Input Measurement Levels Table 150: Clock Single-Ended Input Voltage 1600/1867 2133/2400/3200 3733/4267 Parameter Symbol Min Max Min Max Min Max Unit Clock single-ended input voltage Vinse_CK 210 – 190 – 180 – mV Clock single-ended input voltage HIGH from VREF(CA) Vinse_CK_HIGH 105 – 95 – 90 – mV Clock single-ended input voltage LOW from VREF(CA) Vinse_CK_LOW 105 – 95 – 90 – mV Differential Input Slew Rate Definition for Clock Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown below in figure and the tables. Figure 148: Differential Input Slew Rate Definition for CK_t, CK_c Differential Input Voltage : f(t) = CK_t - CK_c Peak Voltage VIHdiff_CK 0.0 VILdiff_CK Peak Voltage Delta TFdiff Delta TRdiff Time Notes: 1. Differential signal rising edge from VILdiff_CK to VIHdiff_CK must be monotonic slope. 2. Differential signal falling edge from VIHdiff_CK to VILdiff_CK must be monotonic slope. Table 151: Differential Input Slew Rate Definition for CK_t, CK_c Description From To Differential input slew rate for rising edge (CK_t - CK_c) VILdiff_CK VIHdiff_CK |VILdiff_CK - VIHdiff_CKΔTRdiff Differential input slew rate for falling edge (CK_t - CK_c) VIHdiff_CK VILdiff_CK |VILdiff_CK - VIHdiff_CKΔTFdiff 221 Defined by 200b: x32 LPDDR4 SDRAM AC and DC Input Measurement Levels Table 152: Differential Input Level for CK_t, CK_c 1600/1867 2133/2400/3200 3733/4267 Parameter Symbol Min Max Min Max Min Max Unit Differential Input HIGH VIHdiff_CK 175 – 155 – 145 – mV Differential Input LOW VILdiff_CK – –175 – –155 – –145 mV Table 153: Differential Input Slew Rate for CK_t, CK_c 1600/1867 Parameter Differential input slew rate for clock 2133/2400/3200 3733/4267 Symbol Min Max Min Max Min Max Unit SRIdiff_CK 2 14 2 14 2 14 V/ns Differential Input Cross-Point Voltage The cross-point voltage of differential input signals (CK_t, CK_c) must meet the requirements in table below. The differential input cross-point voltage V IX is measured from the actual cross-point of true and complement signals to the mid level that is V REF(CA). Figure 149: Vix Definition (Clock) VDD Single-Ended Input Voltage CK_t Max(f(t)) ViX_CK_RF ViX_CK_FR VREF(CA) ViX_CK_RF Min(f(t)) ViX_CK_FR CK_c VSS Time Note: 1. The base levels of Vix_CK_FR and Vix_CK_RF are VREF(CA) that is device internal setting value by VREF training. 222 200b: x32 LPDDR4 SDRAM AC and DC Input Measurement Levels Table 154: Cross-Point Voltage for Differential Input Signals (Clock) Notes 1 and 2 apply to entire table 1600/1867 Parameter Clock single-ended cross-point voltage ratio 2133/2400/3200 3733/4267 Symbol Min Max Min Max Min Max Unit Vix_CK_ratio – 25 – 25 – 25 % 1. Vix_CK_ratio is defined by this equation: Vix_CK_ratio = Vix_CK_FR/|MIN(f(t))| 2. Vix_CK_ratio is defined by this equation: Vix_CK_ratio = Vix_CK_RF/MAX(f(t)) Notes: Differential Input Voltage for DQS The minimum input voltage needs to satisfy both V indiff_DQS and V indiff_DQS/2 specification at input receiver and their measurement period is 1UI (tCK/2). V indiff_DQS is the peak to peak voltage centered on 0 volts differential and V indiff_DQS/2 is maximum and minimum peak voltage from 0 volts. 0.0  Vindiff_DQS Vindiff_DQS /2 Peak voltage Vindiff_DQS /2 Differential Input Voltage : DQS_t - DQS_c Figure 150: DQS Differential Input Voltage Peak voltage Time Table 155: DQS Differential Input Voltage 1600/1867 2133/2400/3200 3733/4267 Parameter Symbol Min Max Min Max Min Max Unit Note DQS differential input voltage Vindiff_DQS 360 – 360 – 340 – mV 1 Note: 1. The peak voltage of differential DQS signals is calculated in a following equation. • • • • Vindiff_DQS = (Maximum peak voltage) - (Minimum peak voltage) Maximum peak voltage = MAX(f(t)) Minimum peak voltage = MIN(f(t)) f(t) = VDQS_t - VDQS_c Peak Voltage Calculation Method The peak voltage of differential DQS signals are calculated in a following equation. 223 200b: x32 LPDDR4 SDRAM AC and DC Input Measurement Levels • VIH.DIFF.peak voltage = MAX(f(t)) • VIL.DIFF.peak voltage = MIN(f(t)) • f(t) = V DQS_t - V DQS_c Figure 151: Definition of Differential DQS Peak Voltage Single Ended Input Voltage DQS_t Min(f(t)) Max(f(t)) VREF(DQ) DQS_c Time 1. VREF(DQ) is device internal setting value by VREF training. Note: Single-Ended Input Voltage for DQS The minimum input voltage need to satisfy V inse_DQS, V inse_DQS_HIGH, and V inse_DQS_LOW specification at input receiver. Figure 152: DQS Single-Ended Input Voltage Vinse_DQS_LOW Vinse_DQS Vinse_DQS_HIGH Vinse_DQS_HIGH Vinse_DQS_LOW VREF(DQ) Vinse_DQS Single Ended Input Voltage DQS_t DQS_c Time Note: 1. VREF(DQ) is device internal setting value by VREF training. 224 200b: x32 LPDDR4 SDRAM AC and DC Input Measurement Levels Table 156: DQS Single-Ended Input Voltage 1600/1867 2133/2400/3200 3733/4267 Parameter Symbol Min Max Min Max Min Max Unit DQS single-ended input voltage Vinse_DQS 180 – 180 – 170 – mV DQS single-ended input voltage HIGH from VREF(DQ) Vinse_DQS_HIGH 90 – 90 – 85 – mV DQS single-ended input voltage LOW from VREF(DQ) Vinse_DQS_LOW 90 – 90 – 85 – mV Differential Input Slew Rate Definition for DQS Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown below in figure and the tables. Figure 153: Differential Input Slew Rate Definition for DQS_t, DQS_c Differential Input Voltage : f(t) = CK_t - CK_c Peak Voltage VIHdiff_CK 0.0 VILdiff_CK Peak Voltage Delta TFdiff Delta TRdiff Time Notes: 1. Differential signal rising edge from VILdiff_DQS to VIHdiff_DQS must be monotonic slope. 2. Differential signal falling edge from VIHdiff_DQS to VILdiff_DQS must be monotonic slope. Table 157: Differential Input Slew Rate Definition for DQS_t, DQS_c Description From To Differential input slew rate for rising edge (DQS_t - DQS_c) VILdiff_DQS VIHdiff_DQS |VILdiff_DQS - VIHdiff_DQSΔTRdiff Differential input slew rate for falling edge (DQS_t - DQS_c) VIHdiff_DQS VILdiff_DQS |VILdiff_DQS - VIHdiff_DQSΔTFdiff 225 Defined by 200b: x32 LPDDR4 SDRAM AC and DC Input Measurement Levels Table 158: Differential Input Level for DQS_t, DQS_c 1600/1867 Parameter 2133/2400/3200 3733/4267 Symbol Min Max Min Max Min Max Unit Differential Input HIGH VIHdiff_DQS 140 – 140 – 120 – mV Differential Input LOW VILdiff_DQS – –140 – –140 – –120 mV Table 159: Differential Input Slew Rate for DQS_t, DQS_c 1600/1867 Parameter 2133/2400/3200 3733/4267 Symbol Min Max Min Max Min Max Unit SRIdiff 2 14 2 14 2 14 V/ns Differential input slew rate Differential Input Cross-Point Voltage The cross-point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in table below. The differential input cross-point voltage V IX is measured from the actual cross-point of true and complement signals to the mid level that is VREF(DQ). Figure 154: Vix Definition (DQS) VDDQ Single-Ended Input Voltage DQS_t Max(f(t)) ViX_DQS_RF ViX_DQS_FR VREF(DQ) ViX_DQS_RF Min(f(t)) ViX_DQS_FR DQS_c VSSQ Time Note: 1. The base levels of Vix_DQS_FR and Vix_DQS_RF are VREF(DQ) that is device internal setting value by VREF training. 226 200b: x32 LPDDR4 SDRAM Output Slew Rate and Overshoot/Undershoot specifications Table 160: Cross-Point Voltage for Differential Input Signals (DQS) Notes 1 and 2 apply to entire table 1600/1867 Parameter Clock single-ended cross-point voltage ratio Notes: 2133/2400/3200 3733/4267 Symbol Min Max Min Max Min Max Unit Vix_DQS_ratio – 20 – 20 – 20 % 1. Vix_DQS_ratio is defined by this equation: Vix_DQS_ratio = Vix_DQS_FR/|MIN(f(t))| 2. Vix_DQS_ratio is defined by this equation: Vix_DQS_ratio = Vix_DQS_RF/MAX(f(t)) Input Levels for ODT Table 161: Input Levels Parameter Symbol Min ODT input HIGH level (AC) VIHODT(AC) ODT input LOW level (AC) VILODT(AC) ODT input HIGH level (DC) ODT input LOW level (DC) Note: Max Unit Notes 0.75 × VDD2 VDD2 + 0.2 V 1 –0.2 0.25 × VDD2 V 1 VIHODT(DC) 0.65 × VDD2 VDD2 + 0.2 V VILODT(DC) –0.2 0.35 × VDD2 V 1. See the Overshoot and Undershoot section. Output Slew Rate and Overshoot/Undershoot specifications Single-Ended Output Slew Rate Table 162: Single-Ended Output Slew Rate Note 1-5 applies to entire table Value Symbol Min Max Units Single-ended output slew rate (VOH = VDDQ/3) Parameter SRQse 3.5 9.0 V/ns Output slew rate matching ratio (rise to fall) – 0.8 1.2 – Notes: 1. SR = Slew rate; Q = Query output; se = Single-ended signal 2. Measured with output reference load. 3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 4. The output slew rate for falling and rising edges is defined and measured between VOL(AC) = 0.2 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC). 5. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching. 227 200b: x32 LPDDR4 SDRAM Output Slew Rate and Overshoot/Undershoot specifications Figure 155: Single-Ended Output Slew Rate Definition Single-Ended Output Voltage (DQ) ¨TRSE VOH(AC) VCENT VOL(AC) ¨TFSE Time Differential Output Slew Rate Table 163: Differential Output Slew Rate Note 1-4 applies to entire table Value Parameter Symbol Min Max Units Differential output slew rate (VOH = VDDQ/3) SRQdiff 7 18 V/ns Notes: 1. SR = Slew rate; Q = Query output; se = Differential signal 2. Measured with output reference load. 3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) = 0.2 × VOH(DC) and VOH(AC) = 0.8 × VOH(DC). 4. Slew rates are measured under average SSO conditions with 50% of the DQ signals per data byte switching. Figure 156: Differential Output Slew Rate Definition Differential Output Voltage (DQ) ¨TRdiff 0 ¨TFdiff Time 228 200b: x32 LPDDR4 SDRAM Driver Output Timing Reference Load Overshoot and Undershoot Specifications Table 164: AC Overshoot/Undershoot Specifications Parameter 1600 1866 3200 3733 4267 Unit Maximum peak amplitude provided for overshoot area MAX 0.3 0.3 0.3 0.3 0.3 V Maximum peak amplitude provided for undershoot area MAX 0.3 0.3 0.3 0.3 0.3 V Maximum area above VDD/ VDDQ MAX 0.1 0.1 0.1 0.1 0.1 V-ns Maximum area below VSS/ VSSQ MAX 0.1 0.1 0.1 0.1 0.1 V-ns Notes: 1. VDD stands for VDD2 for CA[5:0], CK_t, CS_n, CKE, and ODT. VDD stands for VDDQ for DQ, DMI, DQS_t, and DQS_c. 2. VSS stands for VSS for CA[5:0], CK_t, CK_c, CS_n, CKE, and ODT. VSS stands for VSSQ for DQ, DMI, DQS_t, and DQS_c. 3. Maximum peak amplitude values are referenced from actual VDD and VSS values. 4. Maximum area values are referenced from maximum VDD and VSS values. Table 165: Overshoot/Undershoot Specification for CKE and RESET Parameter Specification Maximum peak amplitude provided for overshoot area 0.35V Maximum peak amplitude provided for undershoot area 0.35V Maximum area above VDD 0.8 V-ns Maximum area below VSS 0.8 V-ns Figure 157: Overshoot and Undershoot Definition Maximum amplitude Volts (V) Overshoot area VDD Time (ns) VSS Undershoot area Maximum amplitude Driver Output Timing Reference Load Timing reference loads are not intended as a precise representation of any particular system environment or depiction of an actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. 229 200b: x32 LPDDR4 SDRAM LVSTL I/O System Figure 158: Driver Output Timing Reference Load DRAM 50 Ohms 1. All output timing parameter values are reported with respect to this reference load; this reference load is also used to report slew rate. Note: LVSTL I/O System LVSTL I/O cells are comprised of a driver pull-up and pull-down and a terminator. Figure 159: LVSTL I/O Cell VDDQ Pull-Up DQ ODT Enabled when receiving Pull-Down VSSQ VSSQ To ensure that the target impedance is achieved, calibrate the LVSTL I/O cell as following example: 1. Calibrate the pull-down device against a 240 ohm resistor to V DDQ via the ZQ pin. • Set strength control to minimum setting • Increase drive strength until comparator detects data bit is less than V DDQ/3 • NMOS pull-down device is calibrated to 120 ohms 2. Calibrate the pull-up device against the calibrated pull-down device. • Set V OH target and NMOS controller ODT replica via MRS (VOH can be automatically controlled by ODT MRS) 230 200b: x32 LPDDR4 SDRAM Input/Output Capacitance • Set strength control to minimum setting • Increase drive strength until comparator detects data bit is greater than V OH target • NMOS pull-up device is calibrated to V OH target Figure 160: Pull-Up Calibration VDDQ Strength contol [N-1:0] N Comparator VOH target Controller ODT replica could be 60 Ohm, 120 Ohm, ... via MRS setting Calibrated NMOS PD control + ODT information VSSQ Input/Output Capacitance Table 166: Input/Output Capacitance Notes 1 and 2 apply to entire table Parameter Symbol Min Max Unit Input capacitance, CK_t and CK_c CCK 0.5 0.9 Input capacitance delta, CK_t and CK_c CDCK 0 0.09 3 Input capacitance, all other input-only pins CI 0.5 0.9 4 Input capacitance delta, all other input-only pins CDI –0.1 0.1 pF Notes 5 CIO 0.7 1.3 CDDQS 0 0.1 7 Input/output capacitance delta, DQ, DMI CDIO –0.1 0.1 8 Input/output capacitance, ZQ pin CZQ 0 5.0 Input/output capacitance, DQ, DMI, DQS_t, DQS_c Input/output capacitance delta, DQS_t, DQS_c Notes: 6 1. This parameter applies to LPDDR4 die only (does not include package capacitance). 2. This parameter is not subject to production testing; it is verified by design and characterization. The capacitance is measured according to JEP147 (procedure for measuring input capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, and VSS applied; all other pins are left floating. 3. Absolute value of CCK_t – CCK_c. 4. CI applies to CS, CKE, and CA[5:0]. 5. CDI = CI – 0.5 × (CCK_t + CCK_c); it does not apply to CKE. 6. DMI loading matches DQ and DQS. 7. Absolute value of CDQS_t and CDQS_c. 231 200b: x32 LPDDR4 SDRAM IDD Specification Parameters and Test Conditions 8. CDIO = CIO – 0.5 × (CDQS_t + CDQS_c) in byte-lane. IDD Specification Parameters and Test Conditions Table 167: IDD Measurement Conditions Switching for CA CK_t edge R1 R2 R3 R4 R5 R6 R7 R8 CKE HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH CS LOW LOW LOW LOW LOW LOW LOW LOW CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH Notes: 1. LOW = VIN ≤ VIL(DC) MAX HIGH = VIN ≥ VIH(DC) MIN STABLE = Inputs are stable at a HIGH or LOW level 2. CS must always be driven LOW. 3. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus. 4. The pattern is used continuously during IDD measurement for IDD values that require switching on the CA bus. Table 168: CA Pattern for IDD4R Clock Cycle Number CKE CS Command CA0 CA1 CA2 CA3 CA4 CA5 N HIGH HIGH Read-1 L H L L L L N+1 HIGH LOW L H L L L L N+2 HIGH HIGH L H L L H L N+3 HIGH LOW L L L L L L N+4 HIGH LOW DES L L L L L L N+5 HIGH LOW DES L L L L L L N+6 HIGH LOW DES L L L L L L N+7 HIGH LOW DES L L L L L L N+8 HIGH HIGH Read-1 L H L L L L L H L L H L L H L L H H H H H H H H CAS-2 N+9 HIGH LOW N+10 HIGH HIGH N+11 HIGH LOW N+12 HIGH LOW DES L L L L L L N+13 HIGH LOW DES L L L L L L N+14 HIGH LOW DES L L L L L L CAS-2 232 200b: x32 LPDDR4 SDRAM IDD Specification Parameters and Test Conditions Table 168: CA Pattern for IDD4R (Continued) Clock Cycle Number CKE CS Command CA0 CA1 CA2 CA3 CA4 CA5 N+15 HIGH LOW DES L L L L L L Notes: 1. BA[2:0] = 010; CA[9:4] = 000000 OR 111111; Burst order CA[3:2] = 00 or 11 (same as LPDDR3 IDDR3 specification). 2. CA pins are kept LOW with DES CMD to reduce ODT current (different from LPDDR3 IDDR3 specification). Table 169: CA Pattern for IDD4W Clock Cycle Number CKE CS Command CA0 CA1 CA2 CA3 CA4 CA5 N HIGH HIGH Write-1 L L H L L L N+1 HIGH LOW L H L L L L N+2 HIGH HIGH N+3 HIGH LOW N+4 HIGH LOW N+5 HIGH N+6 N+7 CAS-2 L H L L H L L L L L L L DES L L L L L L LOW DES L L L L L L HIGH LOW DES L L L L L L HIGH LOW DES L L L L L L N+8 HIGH HIGH Write-1 L L H L L L N+9 HIGH LOW L H L L H L N+10 HIGH HIGH N+11 HIGH LOW N+12 HIGH LOW N+13 HIGH N+14 N+15 L H L L H H L L H H H H DES L L L L L L LOW DES L L L L L L HIGH LOW DES L L L L L L HIGH LOW DES L L L L L L Notes: CAS-2 1. BA[2:0] = 010; CA[9:4] = 000000 or 111111 (same as LPDDR3 specification). 2. No burst ordering (different from LPDDR3 specification). 3. CA pins are kept LOW with DES CMD to reduce ODT current (different from LPDDR3 specification). Table 170: Data Pattern for IDD4W (DBI Off) DBI Off Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 1 1 1 1 1 1 1 1 0 8 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 233 200b: x32 LPDDR4 SDRAM IDD Specification Parameters and Test Conditions Table 170: Data Pattern for IDD4W (DBI Off) (Continued) DBI Off Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 1 1 0 0 0 0 0 4 BL16 1 1 1 1 1 1 0 0 0 6 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 1 1 1 1 1 1 1 1 0 8 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 0 0 0 6 BL27 1 1 1 1 0 0 0 0 0 4 BL28 1 1 1 1 1 1 1 1 0 8 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 # of 1s 16 16 16 16 16 16 16 16 Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for IDD4W pattern programming. Table 171: Data Pattern for IDD4R (DBI Off) DBI Off Case BL0 DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s 1 1 1 1 1 1 1 1 0 8 234 200b: x32 LPDDR4 SDRAM IDD Specification Parameters and Test Conditions Table 171: Data Pattern for IDD4R (DBI Off) (Continued) DBI Off Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 1 1 0 0 0 0 0 4 BL16 1 1 1 1 1 1 1 1 0 8 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 0 0 0 0 BL19 0 0 0 0 1 1 1 1 0 4 BL20 1 1 1 1 1 1 0 0 0 6 BL21 0 0 0 0 1 1 1 1 0 4 BL22 0 0 0 0 0 0 1 1 0 2 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 0 0 0 0 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 1 1 0 8 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 1 1 0 2 BL29 1 1 1 1 0 0 0 0 0 4 BL30 1 1 1 1 1 1 0 0 0 6 BL31 0 0 0 0 1 1 1 1 0 4 # of 1s 16 16 16 16 16 16 16 16 Note: 1. Simplified pattern; same data pattern was applied to DQ[4], DQ[5], DQ[6], and DQ[7] to reduce complexity for IDD4W pattern programming. 235 200b: x32 LPDDR4 SDRAM IDD Specification Parameters and Test Conditions Table 172: Data Pattern for IDD4W (DBI On) DBI On Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 1 1 0 0 0 0 0 4 BL16 0 0 0 0 0 0 1 1 1 3 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 0 0 0 0 0 0 0 0 1 1 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 1 1 1 3 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 0 0 1 1 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 # of 1s 8 8 8 8 8 8 16 16 8 236 200b: x32 LPDDR4 SDRAM IDD Specification Parameters and Test Conditions Table 173: Data Pattern for IDD4R (DBI On) DBI On Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI # of 1s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 1 1 0 0 0 0 0 4 BL16 0 0 0 0 0 0 0 0 1 1 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 0 0 0 0 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 1 1 1 3 BL21 0 0 0 0 1 1 1 1 0 4 BL22 0 0 0 0 0 0 1 1 0 2 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 0 0 0 0 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 0 0 1 1 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 1 1 0 2 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 1 1 1 3 BL31 0 0 0 0 1 1 1 1 0 4 # of 1s 8 8 8 8 8 8 16 16 8 237 200b: x32 LPDDR4 SDRAM IDD Specification Parameters and Test Conditions IDD Specifications IDD values are for the entire operating voltage range, and all of them are for the entire standard temperature range. Table 174: IDD Specification Parameters and Operating Conditions VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V Parameter/Condition tCK tCK = Operating one bank active-precharge current: (MIN); tRC = tRC (MIN); CKE is HIGH; CS is LOW between valid commands; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled Idle power-down standby current: tCK = tCK (MIN); CKE is LOW; CS is LOW; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled Idle power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS is LOW; All banks are idle; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled tCK tCK = (MIN); CKE is Idle non-power-down standby current: HIGH; CS is LOW; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled Idle non-power-down standby current with clock stopped: CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS is LOW; All banks are idle; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled Active power-down standby current: tCK = tCK (MIN); CKE is LOW; CS is LOW; One bank is active; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled Active power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS is LOW; One bank is active; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled Active non-power-down standby current: tCK = tCK (MIN); CKE is HIGH; CS is LOW; One bank is active; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled Active non-power-down standby current with clock stopped: CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS is LOW; One bank is active; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled Operating burst READ current: tCK = tCK (MIN); CS is LOW between valid commands; One bank is active; BL = 16 or 32; RL = RL (MIN); CA bus inputs are switching; 50% data change each burst transfer; ODT is disabled 238 Symbol Power Supply IDD01 VDD1 IDD02 VDD2 IDD0Q VDDQ IDD2P1 VDD1 IDD2P2 VDD2 IDD2PQ VDDQ IDD2PS1 VDD1 IDD2PS2 VDD2 IDD2PSQ VDDQ IDD2N1 VDD1 IDD2N2 VDD2 IDD2NQ VDDQ IDD2NS1 VDD1 IDD2NS2 VDD2 IDD2NSQ VDDQ IDD3P1 VDD1 IDD3P2 VDD2 IDD3PQ VDDQ IDD3PS1 VDD1 IDD3PS2 VDD2 IDD3PSQ VDDQ IDD3N1 VDD1 IDD3N2 VDD2 IDD3NQ VDDQ IDD3NS1 VDD1 IDD3NS2 VDD2 IDD3NSQ VDDQ IDD4R1 VDD1 IDD4R2 VDD2 IDD4RQ VDDQ Notes 2 2 2 2 2 2 3 3 3 4 200b: x32 LPDDR4 SDRAM IDD Specification Parameters and Test Conditions Table 174: IDD Specification Parameters and Operating Conditions (Continued) VDD2, VDDQ = 1.06–1.17V; VDD1 = 1.70–1.95V Parameter/Condition tCK tCK = (MIN); CS is LOW beOperating burst WRITE current: tween valid commands; One bank is active; BL = 16 or 32; WL = WL (MIN); CA bus inputs are switching; 50% data change each burst transfer; ODT is disabled All-bank REFRESH burst current: tCK = tCK (MIN); CKE is HIGH between valid commands; tRC = tRFCab (MIN); Burst refresh; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled All-bank REFRESH average current: tCK = tCK (MIN); CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled tCK tCK = (MIN); CKE is Per-bank REFRESH average current: HIGH between valid commands; tRC = tREFI/8; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled Power-down self refresh current: CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are stable; Maximum 1x self refresh rate; ODT is disabled Notes: 1. 2. 3. 4. 5. Symbol Power Supply IDD4W1 VDD1 IDD4W2 VDD2 IDD4WQ VDDQ IDD51 VDD1 IDD52 VDD2 IDD5Q VDDQ IDD5AB1 VDD1 IDD5AB2 VDD2 IDD5ABQ VDDQ IDD5PB1 VDD1 Notes 3 3 3 IDD5PB2 VDD2 IDD5PBQ VDDQ 3 IDD61 VDD1 5, 6 IDD62 VDD2 5, 6 IDD6Q VDDQ 3, 5, 6 ODT disabled: MR11[2:0] = 000b. IDD current specifications are tested after the device is properly initialized. Measured currents are the summation of VDDQ and VDD2. Guaranteed by design with output load = 5pF and RON = 40 ohm. The 1x self refresh rate is the rate at which the device is refreshed internally during self refresh before going into the elevated temperature range. 6. This is the general definition that applies to full-array self refresh. 7. For all IDD measurements, VIHCKE = 0.8 × VDD2; VILCKE = 0.2 × VDD2. 239 200b: x32 LPDDR4 SDRAM AC Timing AC Timing Table 175: Clock Timing Parameter Symbol Average clock period tCK(avg) Average HIGH pulse width tCH(avg) Average LOW pulse width tCL(avg) Absolute clock period tCK(abs) Absolute clock HIGH pulse width tCH(abs) Absolute clock LOW pulse width tCL(abs) Clock period jitter Maximum clock jitter between two consecutive clock cycles (includes clock period jitter) Data Rate Min/ Max 1600 Min 1250 625 535 468 ps Max 100 100 100 100 ns 3200 3733 Min 0.46 Max 0.54 Min 0.46 Max 0.54 tCK(avg)min Min 4267 Unit tCK(avg) tCK(avg) + tJIT(per)min Min 0.43 Max 0.57 Min 0.43 Max 0.57 ps tCK(avg) tCK(avg) tJIT(per)al- Min –70 –40 –34 –30 lowed Max 70 40 34 30 tJIT(cc)allowed Max 140 80 68 60 ps ps Table 176: Read Output Timing Parameter Symbol DQS output access time from CK_t/CK_c tDQSCK DQS output access time from CK_t/CK_c - voltage variation DQS output access time from CK_t/CK_c - temperature variation CK to DQS rank to rank variation DQS_t, DQS_c to DQ skew total, per group, per access (DBI Disabled) DQ output hold time total from DQS_t, DQS_c (DBI Disabled) Min/ Max Data Rate 533 1066 1600 2133 2667 3200 3733 4267 Unit Notes ps 1 Min 1500 Max 3500 Max 7 ps/mV 2 Max 4 ps°/C 3 Max 1.0 ns 4, 5 tDQSQ Max 0.18 UI 6 tQH Min MIN(tQSH, tQSL) ps 6 tDQSCK_ VOLT tDQSCK_ TEMP tDQSCK_r ank2rank 240 200b: x32 LPDDR4 SDRAM AC Timing Table 176: Read Output Timing (Continued) Parameter Symbol Data output valid window time total, per pin (DBI-Disabled) DQS_t, DQS_c to DQ skew total, per group, per access (DBI-Enabled) DQ output hold time total from DQS_t, DQS_c (DBI-Enabled) Data output valid window time total, per pin (DBI-Enabled) tQW_to- tal tDQSQ_D BI tQH_DBI tQW_to- tal_DBI Min/ Max Data Rate 533 Min 1066 1600 2133 2667 3200 3733 4267 0.75 0.73 0.68 Unit Notes UI 6, 11 Max 0.18 UI 6 Min MIN(tQSH_DBI, tQSL_DBI) ps 6 UI 6, 11 Min 0.75 0.73 0.68 DQS_t, DQS_c differential output LOW time (DBIDisabled) tQSL Min tCL(abs) - 0.05 tCK(avg) 9, 11 DQS_t, DQS_c differential output HIGH time (DBIDisabled) tQSH Min tCH(abs) - 0.05 tCK(avg) 10, 11 DQS_t, DQS_c differential output LOW time (DBIEnabled) tQSL-DBI Min tCL(abs) - 0.045 tCK(avg) 9, 11 DQS_t, DQS_c differential output HIGH time (DBIEnabled) tQSH-DBI Min tCH(abs) - 0.045 tCK(avg) 10, 11 Read preamble tRPRE Min 1.8 tCK(avg) Read postamble tRPST Min 0.4 (or 1.4 if extra postamble is programmed in MR) tCK(avg) tLZ(DQS) Min (RL x tCK) + tDQSCK(Min) - (tRPRE(Max) x tCK) - 200ps ps tLZ(DQ) Min (RL x tCK) + tDQSCK(Min) - 200ps ps DQS Low-Z from clock DQ Low-Z from clock DQS High-Z from clock DQ High-Z from clock tHZ(DQS) Min tHZ(DQ) Min Notes: (RL x tCK) + tDQSCK(Max)+(BL/2 tCK) x - 100ps tCK) + (tRPST(Max) x (RL x tCK) + tDQSCK(Max) + tDQSQ(Max) + (BL/2 x tCK) 100ps ps ps 1. This parameter includes DRAM process, voltage, and temperature variation. It also includes the AC noise impact for frequencies >20 MHz and a MAX voltage of 45mV peakto-peak from DC-20 MHz at a fixed temperature on the package. The voltage supply noise must comply with the component MIN/MAX DC operating conditions. 2. tDQSCK_volt MAX delay variation as a function of DC voltage variation for VDDQ and VDD2. The voltage supply noise must comply with the component MIN/MAX DC operating conditions. The voltage variation is defined as the MAX[abs(tDQSCKmin@V1 tDQSCKmax@V2), abs(tDQSCKmax@V1 - tDQSCKmin@V2)]/abs(V1 - V2). For tester measurement VDDQ = VDD2 is assumed. t 3. DQSCK_temp MAX delay variation as a function of temperature. 4. The same voltage and temperature are applied to tDQSCK_rank2rank. 241 200b: x32 LPDDR4 SDRAM AC Timing 5. tDQSCK_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same design dies. 6. DQ-to-DQS differential jitter where the total includes the sum of deterministic and random timing terms for a specified BER. 7. The deterministic component of the total timing. 8. This parameter will be characterized and guaranteed by design. 9. tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as measured from one falling edge to the next consecutive rising edge. 10. tQSH describes the instantaneous differential output high pulse width on DQS_t DQS_c, as measured from one falling edge to the next consecutive rising edge. 11. This parameter is a function of input clock jitter. These values assume MIN tCH(abs) and tCL(abs). When the input clock jitter MIN tCH(abs) and tCL(abs) is 0.44 or greater than tCK(avg), the MIN value of tQSL will be tCL(abs) - 0.04 and tQSH will be tCH(abs) - 0.04. Table 177: Write Voltage and Timing Note UI = tCK(AVG)(MIN)/2 Min/ Max Data Rate Parameter Symbol Rx timing window total at VdIVW voltage levels TdIVW_t otal Max DQ and DMI input pulse width (at VCENT_DQ) TdIPW Min 0.45 Min 200 Max 800 Max tDQS2DQ DQ-to-DQS offset tDQDQ DQ-to-DQ offset DQ-to-DQS offset temperature variation tDQS2DQ DQ-to-DQS offset voltage variation tDQS2DQ _temp _volt 533 1066 1600 2133 2667 3200 3733 4267 Unit Notes UI 1, 2, 3 UI 7 ps 6 30 ps 7 Max 0.6 ps/°C 8 Max 33 ps/50mV 9 Min 0.75 Max 1.25 0.22 0.25 WRITE command to first DQS transition tDQSS DQS input HIGH-level width tDQSH – 0.4 tCK(avg) DQS input LOW-level width tDQSL Min 0.4 tCK(avg) DQS falling edge to CK setup time tDSS Min 0.2 tCK(avg) DQS falling edge from CK hold time tDSH Min 0.2 tCK(avg) Write postamble tWPST Min 0.4 (or 1.4 if extra postamble is programmed in MR) tCK(avg) Write preamble tWPRE Min 1.8 tCK(avg) Notes: tCK(avg) 1. Data Rx mask voltage and timing parameters are applied per pin and include the DRAM DQ-to-DQS voltage AC noise impact for frequencies >20 MHz with a maximum voltage of 45mV peak-to-peak at a fixed temperature on the package. The voltage supply noise must comply to the component MIN/MAX DC operating conditions. 242 200b: x32 LPDDR4 SDRAM AC Timing 2. Rx differential DQ-to-DQS jitter total timing window at the VdIVW voltage levels. 3. Defined over the DQ internal VREF range. The Rx mask at the pin must be within the internal VREF DQ range irrespective of the input signal common mode. 4. Rx mask defined for one pin toggling with other DQ signals in a steady state. 5. DQ-only minimum input pulse width defined at the VCENT_DQ(pin_mid). 6. DQ-to-DQS offset is within byte from DRAM pin to DRAM internal latch. Includes all DRAM process, voltage, and temperature variations. 7. DQ-to-DQ offset defined within byte from DRAM pin to DRAM internal latch for a given component. 8. tDQS2DQ (MAX) delay variation as a function of temperature. 9. tDQS2DQ (MAX) delay variation as a function of the DC voltage variation for VDDQ and VDD2. It includes the VDDQ and VDD2 AC noise impact for frequencies >20 MHz and MAX voltage of 45mV peak-to-peak from DC-20 MHz at a fixed temperature on the package. For tester measurement, VDDQ = VDD2 is assumed. Table 178: CKE Input Timing Symbol Min/ Max tCKE Min Delay from valid command to CKE input LOW tCMDCKE Valid clock requirement after CKE input LOW tCKELCK Valid CS requirement before CKE input LOW tCSCKE Valid CS requirement after CKE input LOW tCKELCS Valid Clock requirement before CKE Input HIGH Parameter Data Rate Unit Notes MAX(7.5ns, 4nCK) ns 1 Min MAX(1.75ns, 3nCK) ns 1 Min MAX(5ns, 5nCK) ns 1 Min 1.75 ns Min MAX(5ns, 5nCK) ns 1 tCKCKEH Min MAX(1.75ns, 3nCK) ns 1 Exit power-down to next valid command delay tXP Min MAX(7.5ns, 5nCK) ns 1 Valid CS requirement before CKE input HIGH tCSCKEH Min 1.75 ns Valid CS requirement after CKE input HIGH tCKEHCS Min MAX(7.5ns, 5nCK) ns 1 Valid clock and CS requirement after CKE input LOW after MRW command tMRWCKEL Min MAX(14ns, 10nCK) ns 1 Valid clock and CS requirement after CKE input LOW after ZQ calibration start command tZQCKE Min MAX(1.75ns, 3nCK) ns 1 CKE minimum pulse width (HIGH and LOW pulse width) Note: 1600 3200 3733 4267 1. Delay time has to satisfy both analog time(ns) and clock count(nCK). For example, tCMDCKE will not expire until CK has toggled through at least 3 full cycles (3tCK) and 3.75ns has transpired. The case which 3nCK is applied to is shown below. 243 200b: x32 LPDDR4 SDRAM AC Timing Figure 161: tCMDCKE Timing T-1 T0 T1 T2 T3 T4 CK_c CK_t tCMDCKE CKE CS CA Valid Valid Command Valid DES Don’t Care Table 179: Command Address Input Timing Symbol Min/ Max Command/address valid window (referenced from CA VIL/VIH to CK VIX) tcIVW Min Address and control input pulse width (referenced to VREF) tcIPW Min Parameter Notes: Data Rate 533 1066 1600 2133 2667 3200 3733 4267 0.3 0.55 0.55 0.55 0.6 0.6 0.6 Unit Notes 0.35 0.4 tCK(avg) 1, 2, 3 0.7 0.8 tCK(avg) 4 1. CA Rx mask timing parameters at the pin including voltage and temperature drift. 2. Rx differential CA to CK jitter total timing window at the VcIVW voltage levels. 3. Defined over the CA internal VREF range. The Rx mask at the pin must be within the internal VREF(CA) range irrespective of the input signal common mode. 4. CA only minimum input pulse width defined at the VCENT_CA(pin mid). Table 180: Boot Timing Parameters (10–55 MHz) Parameter Clock cycle time DQS output data acess time from CK DQS edge to output data edge Symbol tCKb tDQSCKb tDQSQb Min/ Max Value Min 18 Max 100 Min 1.0 Max 10.0 Max 1.2 244 Unit ns ns ns 200b: x32 LPDDR4 SDRAM AC Timing Table 181: Mode Register Timing Parameters Data Rate Symbol Min/ Max MODE REGISTER WRITE (MRW) command period tMRW Min MAX(10ns, 10nCK) ns MODE REGISTER READ (MRR) command period tMRR Min 8 tCK(avg) Additional time after tXP has expired until the MRR command may be issued tMRRI Min tRCD(min) + 3nCK ns Delay from MRW command to DQS driven out tSDO Max MAX(12nCK, 20ns) ns Parameter 1600 3200 3733 4267 Unit Table 182: Core Timing Parameters Refresh rate is determined by the value in MR4 OP[2:0] Data Rate Symbol Min/ Max READ latency (DBI disabled) RL-A Min 6 10 14 20 24 28 32 36 tCK(avg) READ latency (DBI enabled) RL-B Min 6 12 16 22 28 32 36 40 tCK(avg) WRITE latency (Set A) WL-A Min 4 6 8 10 12 14 16 18 tCK(avg) WRITE latency (Set B) WL-B Min 4 8 12 18 22 26 30 34 tCK(avg) Parameter 533 1066 1600 2133 2667 3200 3733 4267 Unit Min tRAS + tRPab (with all-bank precharge) tRAS + tRPpb (with per-bank precharge) ns tSR Min MAX(15ns, 3nCK) ns Self refresh exit to next valid command delay tXSR Min MAX(tRFCab + 7.5ns, 2nCK) ns CAS-to-CAS delay tCCD Min 8 tCK(avg) CAS-to-CAS delay masked write tCCDMW MIN 32 tCK(avg) Internal READ-to-PRECHARGE command delay tRTP Min MAX(7.5ns, 8nCK) ns RAS-to-CAS delay tRCD Min MAX(18ns, 4nCK) ns Row precharge time (single bank) tRPpb Min MAX(18ns, 3nCK) ns Row precharge time (all banks) tRPab Min MAX(21ns, 3nCK) ns ACTIVATE-to-ACTIVATE command period (same bank) tRC Minimum self refresh time (entry to exit) 245 Notes 1 200b: x32 LPDDR4 SDRAM AC Timing Table 182: Core Timing Parameters (Continued) Refresh rate is determined by the value in MR4 OP[2:0] Parameter Symbol Min/ Max Data Rate 533 1066 1600 2133 2667 3200 3733 4267 Min MAX(42ns, 3nCK) Max tREFI Unit Notes ns 1 Row active time tRAS Write recovery time tWR Min MAX(18ns, 4nCK) ns Write-to-read delay tWTR Min MAX(10ns, 8nCK) ns Active bank A to active bank B tRRD Min MAX(10ns, 4nCK) ns Precharge-to-precharge delay tPPD Min 4 tCK(avg) Four-bank activate window tFAW Min 40 ns tESCKE Min MAX(1.75ns, 3nCK) – Delay from SRE command to CKE input LOW Notes: MIN(9 × × Refresh Rate1, 70.2) μs 2 3 1. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime. 2. Precharge to precharge timing restriction does not apply to AUTO PRECHARGE commands. 3. Delay time has to satisfy both analog time(ns) and clock count (nCK). It means that tESCKE will not expire until CK has toggled through at least three full cycles (3 tCK) and 1.75ns has transpired. The case which 3nCK is applied to is shown below. Figure 162: tESCKE Timing T-1 T0 T1 T2 T3 T4 CK_c CK_t t ESCKE CKE CS CA Valid Valid REFRESH Command SELF Entry DES Don’t Care 246 200b: x32 LPDDR4 SDRAM AC Timing Table 183: CA Bus ODT Timing Symbol Min/ Max Data Rate Parameter CA ODT value update time tODTUP Min RU(20ns/tCK,avg) 533-4267 Table 184: CA Bus Training Parameters Data Rate Parameter Symbol Min/ Max Valid clock requirement after CKE Input LOW tCKELCK Min MAX(5ns, 5nCK) tCK Data setup for VREF training mode tDStrain Min 2 ns Data hold for VREF training mode tDHtrain Min 2 ns tADR Max 20 ns CA BUS TRAINING command-tocommand delay tCACD Min RU(tADR/tCK) tCK Valid strobe requirement before CKE LOW tDQSCKE Min 10 ns First CA BUS TRAINING command following CKE LOW tCAENT Min 250 ns Max 250 ns Asynchronous data read tVREF- VREF step time – multiple steps ca_LONG 1600 3200 3733 4267 Unit VREF step time – one step tVREFca_SHORT Max 80 ns Valid clock requirement before CS HIGH tCKPRECS Min 2tCK + tXP – Valid clock requirement after CS HIGH tCKPSTCS Min MAX(7.5ns, 5nCK) – Minimum delay from CS to DQS toggle in command bus training tCS_VREF Min 2 tCK tCKEHDQS Min 10 ns tMRZ Min 1.5 ns tCKELODTon Min 20 ns Min 20 ns Minimum delay from CKE HIGH to strobe High-Z CA bus training CKE HIGH to DQ tri-state ODT turn-on latency from CKE ODT turn-off latency from CKE Note: tCKEHODT- off Notes 1 1. If tCACD is violated, the data for samples that violate tCACD will not be available, except for the last sample (where tCACD after this sample is met). Valid data for the last sample will be available after tADR. 247 200b: x32 LPDDR4 SDRAM AC Timing Table 185: Asynchronous ODT Turn On and Turn Off Timing Symbol 800–2133 MHz Unit tODTon,min 1.5 ns tODTon,max 3.5 ns tODToff,min 1.5 ns tODToff,max 3.5 ns Table 186: Temperature Derating Parameters Data Rate Parameter Symbol Min/ Max DQS output access time from CK_t/ CK_c (derated) tDQSCKd Max tRCDd Min tRCD tRCd Min tRC tRASd Min tRAS Row precharge time (derated) tRPd Min tRP Active bank A to active bank B (derated) tRRD Min tRRD RAS-to-CAS delay (derated) ACTIVATE-to-ACTIVATE command period (same bank, derated) Row active time (derated) Note: 1600 3200 3733 3600 Unit ps + 1.875 ns + 3.75 ns + 1.875 ns + 1.875 + 1.875 1. Timing derating applies for the operation at 85°C to 105°C. 248 4267 ns ns 200b: x32 LPDDR4 SDRAM CA Rx Voltage and Timing CA Rx Voltage and Timing The command and address (CA), including CS input receiver compliance mask for voltage and timing, is shown in the CA Receiver (Rx) Mask figure below. All CA and CS signals apply the same compliance mask and operate in single data rate mode. The CA input Rx mask for voltage and timing is applied across all pins, as shown in the figure below. The Rx mask defines the area that the input signal must not encroach if the DRAM input receiver is expected to successfully capture a valid input signal; it is not the valid data eye. Figure 163: CA Receiver (Rx) Mask tcIVW_total Rx Mask VCENT_CA(pin mid) VcIVW Figure 164: Across Pin VREF (CA) Voltage Variation CAx CAy CAz VCENT_CAz VCENT_CAx VCENT_CAy VREF variation (component) VCENT_CA(pin mid) is defined as the midpoint between the largest V CENT_CA voltage level and the smallest V CENT_CA voltage level across all CA and CS pins for a given DRAM component. Each CA V CENT level is defined by the center, which is, the widest opening of the cumulative data input eye, as depicted in the figure above. This clarifies that any DRAM component level variation must be accounted for within the CA Rx mask. The component-level V REF will be set by the system to account for RON and ODT settings. 249 200b: x32 LPDDR4 SDRAM CA Rx Voltage and Timing Figure 165: CA Timings at the DRAM Pins CK, CK Data-in at DRAM Pin Minimum CA eye center aligned CK_c VcIVW CK_t Rx mask DRAM pin CA tcIVW TcIVW for all CA signals is defined as centered on the CK_t/CK_c crossing at the DRAM pin. Note: 1. All of the timing terms in above figure are measured from the CK_t/CK_c to the center(midpoint) of the TcIVW window taken at the VcIVW_total voltage levels centered around VCENT_CA(pin mid). Figure 166: CA tcIPW and SRIN_cIVW Definition (for Each Input Pulse) tr tf Rx Mask VcIVW VCENT_CA(pin mid) tcIPW Note: 1. SRIN_cIVW = VdIVW_total/(tr or tf); signal must be monotonic within tr and tf range. Figure 167: CA VIHL_AC Definition (for Each Input Pulse) VIHL(AC)min/2 VCENT_CA Rx Mask Rx Mask Rx Mask VcIVW VIHL(AC)min/2 250 200b: x32 LPDDR4 SDRAM CA Rx Voltage and Timing Table 187: DRAM CMD/ADR, CS UI = tCK(AVG)MIN DQ – 13337 DQ – 1600/1867 DQ – 3200/3733 DQ – 4267 Symbol Parameter Min Max Min Max Min Max Min Max Unit Notes VclVW Rx mask voltage peak-topeak – 175 – 175 – 155 – 145 mV 1, 2, 3 VIHL(AC) CA AC input pulse amplitude peak-to-peak 210 – 210 – 190 – 180 – mV 4, 6 1 7 1 7 1 7 1 7 V/ns 5 SRIN_clVW Input slew rate over VclVW Notes: 1. CA Rx mask voltage and timing parameters at the pin, including voltage and temperature drift. 2. Rx mask voltage VcIVW total (MAX) must be centered around VCENT_CA(pin mid). 3. Defined over the CA internal VREF range. The Rx mask at the pin must be within the internal VREF(CA) range irrespective of the input signal common mode. 4. CA-only input pulse signal amplitude into the receiver must meet or exceed VIHL(AC) at any point over the total UI. No timing requirement above level. VIHL(AC) is the peak-topeak voltage centered around VCENT_CA(pin mid), such that VIHL(AC)/2 (MIN) must be met both above and below VCENT_CA. 5. Input slew rate over VcIVW mask is centered at VCENT_CA(pin mid). 6. VIHL(AC) does not have to be met when no transitions are occurring. 7. The Rx voltage and absolute timing requirements apply for DQ operating frequencies at or below 1333 for all speed bins. For example the tcIVW(ps) = 450ps at or below 1333 operating frequencies. 251 200b: x32 LPDDR4 SDRAM DQ Tx Voltage and Timing DQ Tx Voltage and Timing DRAM Data Timing Figure 168: Read Data Timing Definitions – tQH and tDQSQ Across DQ Signals per DQS Group tQSH(DQS_t) DQS_c DQS_t tQH tDQSQ Associated DQ pins DQS_c DQS_t DQx tQW tQW DQy DQz tQW 252 tQSL(DQS_t) 200b: x32 LPDDR4 SDRAM DQ Rx Voltage and Timing DQ Rx Voltage and Timing The DQ input receiver mask for voltage and timing is applied per pin, as shown in the DQ Receiver (Rx) Mask figure below. The total mask (V dIVW_total, TdIVW_total) defines the area that the input signal must not encroach in order for the DQ input receiver to successfully capture an input signal. The mask is a receiver property, and it is not the valid data eye. Figure 169: DQ Receiver (Rx) Mask TdIVW_total Rx Mask VdIVW VCENT_DQ(pin mid) Figure 170: Across Pin VREF DQ Voltage Variation DQx DQz DQy VCENT_DQz VCENT_DQx VCENT_DQy VREF variation (component) VCENT_DQ(pin_mid) is defined as the midpoint between the largest V CENT_DQ voltage level and the smallest V CENT_DQ voltage level across all DQ pins for a given DRAM component. Each V CENT_DQ is defined by the center, which is the widest opening of the cumulative data input eye as shown in the figure above. This clarifies that any DRAM component level variation must be accounted for within the DRAM Rx mask. The componentlevel V REF will be set by the system to account for RON and ODT settings. 253 200b: x32 LPDDR4 SDRAM DQ Rx Voltage and Timing Figure 171: DQ-to-DQS tDQS2DQ and tDQDQ DQ, DQS Data-in at DRAM Latch DQS, DQs Data-in Skews at DRAM Internal componsite data-eye center aligned to DQS Nonminimum data-eye/maximum Rx mask DQS_c DQS_c DQS_t DQS_t DQx Rx mask DRAM pin tDQS2DQy2 All DQ signals center aligned to the strobe at the device internal latch DQy Rx mask DRAM pin VdIVW_total DQx, y, z VdIVW_total tDQS2DQ2 DQz Rx mask DRAM pin VdIVW_total tDQS2DQz2 tDQDQ Notes: 1. 2. 3. 4. These timings at the DRAM pins are referenced from the internal latch. is measured at the center (midpoint) of the TdIVW window. DQz represents the MAX tDQS2DQ in this example. DQy represents the MIN tDQS2DQ in this example. tDQS2DQ All of the timing terms in DQ to DQS_t are measured from the DQS_t/DQS_c to the center (midpoint) of the TdIVW window taken at the V dIVW_total voltage levels centered around V CENT_DQ(pin_mid). In figure above, the timings at the pins are referenced with respect to all DQ signals center-aligned to the DRAM internal latch. The data-to-data offset is defined as the difference between the MIN and MAX tDQS2DQ for a given component. 254 200b: x32 LPDDR4 SDRAM DQ Rx Voltage and Timing Figure 172: DQ tDIPW and SRIN_dIVW Definition for Each Input Pulse UI = tCK(AVG) MIN/2 tr tf Rx Mask VDIVW_total VCENT_DQ(pin mid) tDIPW Note: 1. SRIN_dIVW = VdIVW_total/(tr or tf) signal must be monotonic within tr and tf range. Figure 173: DQ VIHL(AC) Definition (for Each Input Pulse) VIHL(AC)min/2 VCENT_DQ Rx Mask Rx Mask VdIVW_total Rx Mask VIHL(AC)min/2 Table 188: DQs In Receive Mode Note UI = tCK(AVG)(MIN)/2 Symbol Parameter VdIVW_total Rx mask voltage – peak-topeak VIHL(AC) DQ AC input pulse amplitude peak-to-peak SRIN_dIVW Input slew rate over VdIVW_total Notes: 1600/1867 2133/2400 3200/3733 4267 Min Max Min Max Min Max Min Max Unit Notes – 140 – 140 – 140 – 120 mV 1, 2, 3 180 – 180 – 180 – 170 – mV 5, 7 1 7 1 7 1 7 1 7 V/ns 6 1. Data Rx mask voltage and timing parameters are applied per pin and include the DRAM DQ-to-DQS voltage AC noise impact for frequencies >20 MHz with a maximum voltage of 45mV peak-to-peak at a fixed temperature on the package. The voltage supply noise must comply to the component MIN/MAX DC operating conditions. 2. Rx mask voltage VdIVW_total (MAX) must be centered around VCENT_DQ(pin_mid). 3. Defined over the DQ internal VREF range. The Rx mask at the pin must be within the internal VREF DQ range irrespective of the input signal common mode. 4. Deterministic component of the total Rx mask voltage or timing. Parameter will be characterized and guaranteed by design. 5. DQ-only input pulse amplitude into the receiver must meet or exceed VIHL(AC) at any point over the total UI. No timing requirement above level. VIHL(AC) is the peak-to-peak voltage centered around VCENT_DQ(pin_mid), such that VIHL(AC)/2 (MIN) must be met both above and below VCENT_DQ. 6. Input slew rate over VdIVW mask centered at VCENT_DQ(pin_mid). 255 200b: x32 LPDDR4 SDRAM Clock Specification 7. VIHL(AC) does not have to be met when no transitions are occurring. Clock Specification The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating minimum or maximum values may result in device malfunction. Table 189: Definitions and Calculations Symbol tCK(avg) Description and nCK Calculation The average clock period across any consecutive 200-cycle window. Each clock period is calculated tCK(avg) = from rising clock edge to rising clock edge. Unit tCK(avg) represents the actual clock average tCK(avg) of the input clock under operation. Unit nCK represents one clock cycle of the input clock, counting from actual clock edge to actual clock edge. Notes N Ȉ tCKj /N j=1 Where N = 200 tCK(avg) can change no more than ±1% within a 100-clock-cycle window, provided that all jitter and timing specifications are met. tCK(abs) The absolute clock period, as measured from one rising clock edge to the next consecutive rising clock edge. tCH(avg) The average HIGH pulse width, as calculated across any 200 consecutive HIGH pulses. 1 N tCH(avg) = Ȉ tCHj /(N × tCK(avg)) j=1 Where N = 200 tCL(avg) The average LOW pulse width, as calculated across any 200 consecutive LOW pulses. N tCL(avg) = Ȉ tCL j /(N × tCK(avg)) j=1 Where N = 200 tJIT(per) The single-period jitter defined as the largest detJIT(per) = min/max of tCK – tCK(avg) i viation of any signal tCK from tCK(avg). 1 Where i = 1 to 200 tJIT(per),act The actual clock jitter for a given system. tJIT(per), The specified clock period jitter allowance. allowed tJIT(cc) The absolute difference in clock periods between t tJIT(cc) = max of tCK i + 1 – CKi two consecutive clock cycles. tJIT(cc) defines the cycle-to-cycle jitter. 1 tERR(nper) The cumulative error across n multiple consecutive cycles from tCK(avg). 1 i+n–1 tERR(nper) = Ȉ j=i tERR(nper),act The actual clock jitter over n cycles for a given system. 256 tCK – (n × tCK(avg)) j 200b: x32 LPDDR4 SDRAM Clock Period Jitter Table 189: Definitions and Calculations (Continued) Symbol Description tERR(nper), The specified clock jitter allowance over n cycles. Calculation Notes allowed tERR(nper),min The minimum tERR(nper). tERR(nper),min = (1 + 0.68LN(n)) × tJIT(per),min 2 tERR(nper),max The maximum tERR(nper). tERR(nper),max = (1 + 0.68LN(n)) × tJIT(per),max 2 tJIT(duty) Defined with absolute and average specifications tJIT(duty),min = for tCH and tCL, respectively. MIN((tCH(abs),min – tCH(avg),min), (tCL(abs),min – tCL(avg),min)) × tCK(avg) tJIT(duty),max = MAX((tCH(abs),max – tCH(avg),max), (tCL(abs),max – tCL(avg),max)) × tCK(avg) Notes: tCK(abs), tCH(abs), 1. Not subject to production testing. 2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value. and tCL(abs) These parameters are specified with their average values; however, the relationship between the average timing and the absolute instantaneous timing (defined in the following table) is applicable at all times. Table 190: tCK(abs), tCH(abs), and tCL(abs) Definitions Parameter Symbol Minimum Absolute clock period tCK(abs) tCK(avg),min + Absolute clock HIGH pulse width tCH(abs) tCH(avg),min + tJIT(duty),min2/tCK(avg)min tCK(avg) Absolute clock LOW pulse width tCL(abs) tCL(avg),min + tJIT(duty),min2/tCK(avg)min tCK(avg) Notes: Unit tJIT(per),min ps1 1. tCK(avg),min is expressed in ps for this table. 2. tJIT(duty),min is a negative value. Clock Period Jitter LPDDR4 devices can tolerate some clock period jitter without core timing parameter derating. This section describes device timing requirements with clock period jitter (tJIT(per)) in excess of the values found in the AC Timing table. Calculating cycle time derating and clock cycle derating are also described. Clock Period Jitter Effects on Core Timing Parameters Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) extend across multiple clock cycles. Clock period jitter impacts these parameters when measured in numbers of clock cycles. Within the specification limits, the device is characterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device operation where clock jitter is outside specification limits, the number of clocks, or tCK(avg), may need to be increased based on the values for each core timing parameter. 257 200b: x32 LPDDR4 SDRAM Clock Period Jitter Cycle Time Derating for Core Timing Parameters For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM),act exceed cycle time derating may be required for core timing parameters. tERR(tnPARAM),allowed, t t t t t CycleTimeDerating = max PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed – tCK(avg) , 0 tnPARAM Cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating required is the maximum of the cycle time deratings determined for each individual core timing parameter. Clock Cycle Derating for Core Timing Parameters For each core timing parameter and a given number of clocks (tnPARAM), clock cycle derating should be specified with tJIT(per). For a given number of clocks (tnPARAM), when tCK(avg) plus (tERR(tnPARAM),act) exceed the supported cumulative tERR(tnPARAM),allowed, derating is required. If the equation below results in a positive value for a core timing parameter (tCORE), the required clock cycle derating will be that positive value (in clocks). t t t t t ClockCycleDerating = RU PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed – tnPARAM tCK(avg) Cycle-time derating analysis should be conducted for each core timing parameter. Clock Jitter Effects on Command/Address Timing Parameters Command/address timing parameters (tIS, tIH, tISb, tIHb) are measured from a command/address signal (CS or CA[5:0]) transition edge to its respective clock signal (CK_t/ CK_c) crossing. The specification values are not affected by the tJIT(per) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. Clock Jitter Effects on READ Timing Parameters tRPRE When the device is operated with input clock jitter, tRPRE must be derated by the of the input clock that exceeds tJIT(per),allowed,max. Output deratings are relative to the input clock: tJIT(per),act,max tRPRE(min,derated) = 0.9 – tJIT(per),act,max – tJIT(per),allowed,max tCK(avg) For example, if the measured jitter into a LPDDR4 device has tCK(avg) = 625ps, tJIT(per),act,min = –xx, and tJIT(per),act,max = +xx ps, then tRPRE,min,derated = 0.9 (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (xx - xx)/xx = yy tCK(avg). 258 200b: x32 LPDDR4 SDRAM Clock Period Jitter tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) These parameters are measured from a specific clock edge to a data signal transition (DMn or DQm, where: n = 0,1; and m = 0–15, and specified timings must be met with respect to that clock edge. Therefore, they are not affected by tJIT(per). tQSH, tQSL These parameters are affected by duty cycle jitter, represented by tCH(abs)min and tCL(abs)min. These parameters determine the absolute data-valid window at the device pin. The absolute minimum data-valid window at the device pin = MIN {( tQSH(abs)min - tDQSQmax), (tQSL(abs)min - tDQSQmax)}. This minimum data valid window must be met at the target frequency regardless of clock jitter. tRPST tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min. Clock Jitter Effects on WRITE Timing Parameters tDS, tDH These parameters are measured from a data signal (DMIn or DQm, where n = 0, 1 and m = 0–15) transition edge to its respective data strobe signal (DQSn_t, DQSn_c: n = 0,1) crossing. The specification values are not affected by the amount of tJIT(per) applied, because the setup and hold times are relative to the data strobe signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. tDSS, tDSH These parameters are measured from a data signal (DQS_t, DQSn_c) crossing to its respective clock signal (CK_t, CK_c) crossing. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per)act of the input clock in excess of the allowed period jitter tJIT(per)allowed. tDQSS tDQSS is measured from a data strobe signal (DQSn_t, DQSn_c) crossing to its respective clock signal (CK_t, CK_c) crossing. When the device is operated with input clock jitter, this parameter must be derated by the actual tJIT(per),act of the input clock in excess of tJIT(per)allowed. tDQSS(min,derated) = 0.75 - tJIT(per),act,min – tJIT(per),allowed, min tCK(avg) tDQSS(max,derated) = 1.25 – tJIT(per),act,max – tJIT(per),allowed, max tCK(avg) For example, if the measured jitter into an LPDDR4 device has tCK(avg) = 625ps, = -xxps, and tJIT(per),act,max = +xx ps, then: tJIT(per),act,min tDQSS,(min,derated) = 0.75 - (-xx + yy)/625 = xxxx tCK(avg) tDQSS,(max,derated) = 1.25 - (xx – yy)/625 = xxxx tCK(avg) 259 200b: x32 LPDDR4 SDRAM Revision History Revision History Rev. D – 3/17 • Added QDP die • Added DS, DT, and NQ package codes • Added XT temperature range Rev. C – 11/16 • Added -053 speed grade Rev. B – 8/16 • Production release Rev. A – 5/16 • Initial Preliminary release (reference document: PDF: 09005aef865c23a1 366b_z0am_qdp_mobile_lpddr4.pdf – Rev. B 3/16 EN) 260