AS3415/AS3435
Integrated Active Noise Cancelling
Solution with Bypass Feature
General Description
The AS3415/35 are speaker drivers with Ambient Noise
Cancelling function for headsets, headphones or ear pieces.
They are intended to improve quality of e.g. music listening, a
phone conversation etc. by reducing background ambient
noise.
The fully analog implementation allows the lowest power
consumption, lowest system BOM cost and most natural
received voice enhancement otherwise difficult to achieve with
DSP implementations. The device is designed to be easily
applied to existing architectures.
An internal OTP-ROM can be optionally used to store the
microphones gain calibration settings. The AS3415/35 can be
used in different configurations for best trade-off of noise
cancellation, required filtering functions and mechanical
designs.
The simpler feed-forward topology is used to effectively reduce
frequencies typically up to 2-3 kHz. The feed-back topology
with either 1 or 2 filtering stages has its strengths especially at
very low frequencies. The typical bandwidth for a feed-back
system is from 20Hz up to 1 kHz which is lower than the
feed-forward systems.
The filter loop for both systems is determined by
measurements, for each specific headset individually, and
depends very much on mechanical designs. The gain and phase
compensation filter network is implemented with cheap
resistors and capacitors for lowest system costs.
Key Benefits & Features
The benefits and features of AS3415/35, Integrated Active Noise
Cancelling Solution with Bypass Feature are listed below:
Figure 1:
Added Value of Using AS3415/35
Benefits
Features
All ANC Topologies
Feed Forward, Feed Back and Hybrid
No mechanical audio bypass switch
Integrated depletion mode transistors
Music EQ functionality
Ultra flexible low power EQ circuit
Longest play time
10mW @1.5V stereo ANC; 2.5ms
Protocol
Figure 76:
I²C Serial Interface Symbol Definition
Symbol
Definition
RW
Note
S
Start condition after stop
R
1 bit
Sr
Repeated start
R
1 bit
DW
Device address for write
R
1000 1110b (8Eh)
DR
Device address for read
R
1000 1111b (8Fh)
WA
Word address
R
8 bit
A
Acknowledge
W
1 bit
N
No Acknowledge
R
1 bit
reg_data
Register data/write
R
8 bit
data (n)
Register data/read
W
8 bit
Stop condition
R
1 bit
Increment word address internally
R
during acknowledge
P
WA++
AS3421 AS3422 (=slave) receives data
AS3421 AS3422 (=slave) transmits data
Symbol Definition: The table shows the symbol definitions being used in the explanations for the data transfer
between master and slave.
AS3415/AS3435 – 58
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ams Datasheet, Confidential: 2013-Sep [1-10]
Detailed Description
Figure 77:
Byte Write
S
DW
A
WA
A
reg_data
A P
write register
WA++
Figure 78:
Page Write
S
DW
A
WA
A
reg_data 1
A
reg_data 2
write register
WA++
A
write register
WA++
...
reg_data n
A
P
write register
WA++
Byte Write and Page Write formats are used to write data to the
slave. The transmission begins with the START condition, which
is generated by the master when the bus is in IDLE state (the
bus is free). The device-write address is followed by the word
address. After the word address any number of data bytes can
be sent to the slave. The word address is incremented internally,
in order to write subsequent data bytes to subsequent address
locations.
For reading data from the slave device, the master has to change
the transfer direction. This can be done either with a repeated
START condition followed by the device-read address, or simply
with a new transmission START followed by the device-read
address, when the bus is in IDLE state. The device-read address
is always followed by the 1st register byte transmitted from the
slave. In Read Mode any number of subsequent register bytes
can be read from the slave. The word address is incremented
internally.
ams Datasheet, Confidential: 2013-Sep [1-10]
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AS3415/AS3435 – 59
Detailed Description
Figure 79:
Random Read
S
DW
A
WA
A Sr
DR
A
data
N P
read register
WA++
Random Read and Sequential Read are combined formats. The
repeated START condition is used to change the direction after
the data transfer from the master.
The word address transfer is initiated with a START condition
issued by the master while the bus is idle. The START condition
is followed by the device-write address and the word address.
In order to change the data direction a repeated START
condition is issued on the 1st SCL pulse after the acknowledge
bit of the word address transfer. After the reception of the
device-read address, the slave becomes the transmitter. In this
state the slave transmits register data located by the previous
received word address vector. The master responds to the data
byte with a not-acknowledge, and issues a STOP condition on
the bus.
Figure 80:
Sequential Read
S
DW
A
WA
A Sr
DR
A
read register
WA++
data
A
reg_data 2
read register
WA++
A
...
reg_data n
N P
read register
WA++
Sequential Read is the extended form of Random Read, as more
than one register-data bytes are transferred subsequently.
Different from the Random Read, for a sequential read, the
transferred register-data bytes are responded with an
acknowledge from the master. The number of data bytes
transferred in one sequence is unlimited (consider the behavior
of the word-address counter). To terminate the transmission the
master has to send a not-acknowledge following the last data
byte and then generate the STOP condition.
AS3415/AS3435 – 60
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Detailed Description
Figure 81:
Current Address Read
S
DR
A
data
read register
WA++
A
reg_data 2
read register
WA++
A
...
reg_data n
N P
read register
WA++
To keep the access time as short as possible, this format allows
a read access without the word address transfer in advance to
the data transfer. The bus is idle and the master issues a START
condition followed by the Device-Read address. Analogous to
Random Read, a single byte transfer is terminated with a
not-acknowledge after the 1st register byte. Analogous to
Sequential Read an unlimited number of data bytes can be
transferred, where the data bytes have to be responded with an
acknowledge from the master. For termination of the
transmission, the master sends a not-acknowledge following
the last data byte and a subsequent STOP condition.
Parameter
Figure 82:
I²C Serial Timing
TS
TSU
TH
THD
TL
TPD
CSDA
CSCL
1-7
Start
Address
Condition
8
9
R/W
ACK
ams Datasheet, Confidential: 2013-Sep [1-10]
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1-7
8
Data
9
ACK
1-7
Data
8
9
ACK
Stop
Condition
AS3415/AS3435 – 61
Detailed Description
VBAT ≥ 1.4V 1 , TA=25ºC, unless otherwise specified.
Figure 83:
I²C Serial Interface Parameter
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0
-
0.42
V
0.98
-
200
450
800
mV
-
-
0.4
V
50
100
-
ns
VCSL
CSCL, CSDA Low
Input Level
(Max. 30%VBAT )
VCSH
CSCL, CSDA High
Input Level
CSCL, CSDA (min 70%VBAT )
HYST
CSCL, CSDA Input
Hysteresis
VOL
CSDA Low Output
Level
Tsp
Spike insensitivity
TH
Clock high time
Max. 400kHz clock speed
500
ns
TL
Clock low time
Max. 400kHz clock speed
500
ns
TSU
CSDA has to change Tsetup
before rising edge of CSCL
250
-
-
ns
THD
No hold time needed for CSDA
relative to rising edge of CSCL
0
-
-
ns
TS
CSDA H hold time relative to
CSDA edge for
start/stop/rep_start
200
-
-
ns
TPD
CSDA prop delay relative to low
going edge of CSCL
At 3mA
50
V
ns
1. Serial interface operates down to VBAT = 1.0V but with 100kHz clock speed and degraded parameters.
AS3415/AS3435 – 62
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ams Datasheet, Confidential: 2013-Sep [1-10]
Register Description
Register Description
Figure 84:
Register Table Overview
Addr
Name
b7
b6
b5
b4
b3
b2
b1
b0
System Registers
20h
SYSTEM
21h
PWR_SET
2h-2Fh
reserved
DESIGN_VERSION 1100
LOW_BAT
EVAL_REG_ON
PWRUP
COMPLETE
HPH_ON
MIC_ON
PWR_HOLD
LIN_ON
MICS_CP_O
N
MICS_ON
OTP Registers
10h
ANC_L2
TEST_BIT_1
MICL_VOL_OTP2
Gain from MICL to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB
11h
ANC_R2
ALT2_ENABLE
MICR_VOL_OTP2
Gain from MICR to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB
12h
ANC_L3
TEST_BIT_2
MICL_VOL_OTP3
Gain from MICL to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB
13h
ANC_R3
ALT3_ENABLE
MICR_VOL_OTP3
Gain from MICR to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB
14h
ANC_MODE
HPH_MUX
0: MIC; 1: OP1;
2: OP2; 3: -
LIN_MUTE
MIX_ENABLE
OP2L_ON
15h
MON_MODE
MON_HPH_MUX
0: MIC; 1: OP1;
2: OP2; 3: -
MON_LIN_M
UTE
MON_MIX_E
NABLE
MON_LINE_ATT
0: 0dB 1: -24dB
2: -30dB 3: -36dB
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OP2R_ON
OP1L_ON
OP1R_ON
SLIDER_MO
N
DISABLE_MO
NITOR
AS3415/AS3435 – 63
Register Description
Addr
Name
16h
PBO_MODE
17h
b7
b6
b5
b4
b3
b2
b1
b0
PBO_MIX_EN
ABLE
PBO_OP2L_ON
PBO_OP2R_ON
PBO_OP1L_
ON
PBO_OP1R_O
N
ENABLE_HPH_
ECO
ENABLE_MIC_E
CO
ENABLE_LIN
_ECO
ENABLE_OPA
MP_ECO
TEST_BIT_4
NO_PBO
PBO_LIN_M
UTE
ECO
SLIDE_PWR_U
P
LOWBAT_100
ILED
0: OFF; 1: 25%;
2: 50%; 3: 100%
30h
ANC_L
TEST_BIT_3.1
MICL_VOL
Gain from MICL to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB
31h
ANC_R
TEST_BIT_6
MICR_VOL
Gain from MICR to QMICL or Mixer = 0dB...+31dB; MUTE and 63 steps of 0.5dB
32h
MIC_MON_L
MICL_MON
Gain from MICL to QMICL/R = 0dB...+31dB; MUTE and 63 steps of 0.5dB if MON_MODE is active
33h
MIC_MON_R
MICR_MON
Gain from MICL to QMICL/R = 0dB...+31dB; MUTE and 63 steps of 0.5dB if MON_MODE is active
34h
MODE_1
35h
MODE_2
MICS_CP_OFF
TEST_BIT_7
MICS_OFF
MIC_AGC_O
N
MIC_OFF
HP_RAMP_ON
NO_LOWBAT_
OFF
CP_OFF
HPH_OFF
LIN_OFF
MICS_DC_OFF
DELAY_HPH_M
UX
HPH_MODE
0: Stereo
1: Mono
Differential
I2C_MODE
MON_MODE
PBO_MODE
MICL_MUTE
MICR_MUTE
TM_REG30-33
OTP_MODE
0: READ; 1: LOAD;
2: WRITE; 3: BURN
Evaluation Registers
3Dh
EVAL
3Eh
CONFIG_1
3Fh
CONFIG_2
EVAL_ON
AS3415/AS3435 – 64
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MASTER_LIN
_MUTE
MASTER_MIX
_ENABLE
EXTBURNCLK
TM34
BURNSW
TM_REG34-35
ams Datasheet, Confidential: 2013-Sep [1-10]
Register Description
System Registers
Figure 85:
SYSTEM Register Description
Name
Address
Default Value
SYSTEM
0x20
81h
This register contains control bits for monitor mode, OTP register and power up/down functions.
Bit
7:4
3
2
0
Bit Name
Default
DESIGN_VERSION
EVAL_REG_ON
MONITOR_ON
PWR_HOLD
Access
Bit Description
R
Design version number to identify the design version
of the AS3415/35.
1010: For chip version 1v0
1011: For chip version 1v1
1100: For chip version 1v2
R/W
This register controls read and write access to the OTP
register banks.
0: Normal operation
1: Enables writing to register 0x3D, 0x3E and 0x3F to
configure the OTP and set the access mode.
R/W
This bit enables the monitor mode of AS3415/35
which can normally be enabled by pulling the MODE
pin to VBAT/2. In case an MCU is connected to the
device the Monitor mode can be enabled by setting
this bit.
0: Monitor mode deactivated
1: Monitor mode activated
R/W
This bit allows an MCU using the I²C interface a power
down of the AS3415/35. A start condition on the I²C
interface will wake up the device again. This function
works only if the I2C_MODE bit is set before you write
this register.
0: Power up hold is cleared and chip powers down
1: It is automatically set to on after power on
1100
0
0
1
Figure 86:
PWR_SET Register Description
Name
Address
Default Value
PWR_READ
0x21
20h
A readout of this register returns the status of each block of the chipset.
Bit
6
Bit Name
LOW_BAT
Default
x
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Access
R
Bit Description
VBAT supervisor status
0: VBAT is above brown out level
1: VBAT has reached brown out level
AS3415/AS3435 – 65
Register Description
Name
Address
Default Value
PWR_READ
0x21
20h
A readout of this register returns the status of each block of the chipset.
Bit
Bit Name
Default
Access
5
PWRUP_COMPLETE
x
R
Power-Up sequencer status
0: Power-up sequence incomplete
1: Power-up sequence completed
R
This register returns the power status of the
headphone amplifier.
0: Headphone amplifier switched off
1: Headphone amplifier switched on
R
This register returns the power status of the
microphone preamplifier.
0: Microphone preamplifier switched off
1: Microphone preamplifier switched on
R
This register returns the power status of the line
input amplifier.
0: Line input switched off
1: Line input switched on
R
This register returns the power status of the
microphone charge pump.
0: Microphone charge pump switched off
1: Microphone charge pump switched on
R
This register returns the power status of the
microphone supply (MICS).
0: Microphone supply switched off
1: Microphone supply switched on
4
3
2
1
0
HPH_ON
MIC_ON
LIN_ON
MICS_CP_ON
MICS_ON
AS3415/AS3435 – 66
Downloaded from DatasheetLib.com - datasheet search engine
0
0
0
0
0
Bit Description
ams Datasheet, Confidential: 2013-Sep [1-10]
Register Description
OTP Registers
Figure 87:
ANC_L2 Register Description
Name
Address
Default Value
ANC_L2
0x10
80h
The ANC_L2 Register configures the gain for the left microphone input. This register is the first alternative
microphone gain register for OTP programming in case the ANC_L register is already programmed.
Bit
Bit Name
Default
Access
7
TEST_BIT_1
1
R
5:0
MICL_VOL_OTP2
000 0000
R/W
Bit Description
Test register. Please do not write this register.
Volume settings for left microphone input,
adjustable in 63 steps of 0.5dB
00 0000: MUTE
00 0001: 0.5dB gain
00 0010: 1dB gain
00 0011: 1.5dB gain
…
11 1110: 30.5dB gain
11 1111: 31dB gain
Figure 88:
ANC_R2 Register Description
Name
Address
Default Value
ANC_R2
0x11
00h
The ANC_R2 Register configures the gain for the right microphone input. This register is the first alternative
microphone gain register for OTP programming in case the ANC_R register is already programmed.
Bit
7
Bit Name
ALT2_ENABLE
Default
0
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Access
Bit Description
R/W
In case the register is being used for microphone
programming this bit has to be set. The bit is being
used by the internal state machine of the
AS3415/35 to determine which alternative
microphone gain register has to be used during
startup.
0: Microphone registers 0x10 and 0x11 are not
active
1: Microphone registers 0x10 and 0x11 are active.
Gain settings in registers 0x30 and 0x31 are
ignored
AS3415/AS3435 – 67
Register Description
Name
Address
Default Value
ANC_R2
0x11
00h
The ANC_R2 Register configures the gain for the right microphone input. This register is the first alternative
microphone gain register for OTP programming in case the ANC_R register is already programmed.
Bit
5:0
Bit Name
MICR_VOL_OTP2
Default
Access
000 0000
R/W
Bit Description
Volume settings for left microphone input,
adjustable in 63 steps of 0.5dB
00 0000: MUTE
00 0001: 0.5dB gain
00 0010: 1dB gain
00 0011: 1.5dB gain
…
11 1110: 30.5dB gain
11 1111: 31dB gain
Figure 89:
ANC_L3 Register Description
Name
Address
Default Value
ANC_L3
0x12
80h
The ANC_L3 Register configures the gain for the left microphone input. This register is the second alternative
microphone gain register for OTP programming in case the ANC_L and ANC_L2 registers are already
programmed.
Bit
Bit Name
Default
Access
7
TEST_BIT_6
1
R
5:0
MICL_VOL_OTP3
AS3415/AS3435 – 68
Downloaded from DatasheetLib.com - datasheet search engine
000 0000
R/W
Bit Description
Test register. Please do not write this register.
Volume settings for left microphone input,
adjustable in 63 steps of 0.5dB
00 0000: MUTE
00 0001: 0.5dB gain
00 0010: 1dB gain
00 0011: 1.5dB gain
…
11 1110: 30.5dB gain
11 1111: 31dB gain
ams Datasheet, Confidential: 2013-Sep [1-10]
Register Description
Figure 90:
ANC_R3 Register Description
Name
Address
Default Value
ANC_R3
0x13
00h
The ANC_R3 Register configures the gain for the right microphone input. This register is the second alternative
microphone gain register for OTP programming in case the ANC_R and ANC_R2 registers are already
programmed.
Bit
7
5:0
Bit Name
ALT3_ENABLE
MICR_VOL_OTP3
Default
0
000 0000
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Access
Bit Description
R/W
In case the register is being used for microphone
programming this bit has to be set. The bit is being
used by the internal state machine of the
AS3415/35 to determine which alternative
microphone gain register has to be used during
startup.
0: Microphone registers 0x12 and 0x13 are not
active
1: Microphone registers 0x12 and 0x13 are active.
Gain settings in registers 0x30, 0x31, 0x10 and
0x11 are ignored.
R/W
Volume settings for left microphone input,
adjustable in 63 steps of 0.5dB
00 0000: 0dB
00 0001: 0.5dB gain
00 0010: 1dB gain
00 0011: 1.5dB gain
…
11 1110: 30.5dB gain
11 1111: 31dB gain
AS3415/AS3435 – 69
Register Description
Figure 91:
ANC_MODE Register Description
Name
Address
Default Value
ANC_MODE
0x14
00h
The ANC_MODE register controls various settings for the chipset in active noise cancelling mode like which
amplifiers are enabled as well as which audio inputs are active.
Bit
7:6
5
4
3
2
1
0
Bit Name
HPH_MUX
LIN_MUTE
MIX_ENABLE
OP2L_ON
OP2R_ON
OP1L_ON
OP1R_ON
AS3415/AS3435 – 70
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Default
00
0
0
0
0
0
0
Access
Bit Description
R/W
This register selects the ANC input source for the
headphone amplifier in ANC mode. Depending on the
register setting the outputs of microphone
preamplifier, OPAMP1, OPAMP2 can be connected to
the headphone amplifier input. It is also possible to
disconnect all ANC input sources which is sometimes
desired in monitor mode.
00: QMIC outputs are connected to HPH input
01: OP1 outputs are connected to HPH input
10: OP2 outputs are connected to HPH input
11: Nothing connected to HPH input except line input
and mixer input in case they are enabled.
R/W
This bit defines the status of the line input mute
switch in active noise cancelling mode. If the bit is set
to ‘1’ the line input amplifier is disconnected from the
headphone amplifier.
0: Line input connected to headphone amplifier
1: Line input not connected to headphone amplifier
R/W
This bit enables the headphone mixer input pin to mix
external signals to the headphone amplifier in active
noise cancelling mode.
0: HPH mixer input disabled
1: HPH mixer input enabled
R/W
This register enables the left channel of OPAMP 2 in
ANC mode.
0: Left OP2 is switched off
1: Left OP2 is switched on
R/W
This register enables the right channel of OPAMP 2 in
ANC mode.
0: Right OP2 is switched off
1: Right OP2 is switched on
R/W
This register enables the left channel of OPAMP 1 in
ANC mode.
0: Left OP1 is switched off
1: Left OP1 is switched on
R/W
This register enables the right channel of OPAMP 1 in
ANC mode.
0: Right OP1 is switched off
1: Right OP1 is switched on
ams Datasheet, Confidential: 2013-Sep [1-10]
Register Description
Figure 92:
MONITOR_MODE Register Description
Name
Address
Default Value
MONITOR_MODE
0x15
00h
The MONITOR_MODE register controls various settings for the chipset in monitor mode like line input monitor
mode attenuation as well as which audio inputs are active.
Bit
7:6
6
5
3:2
1
0
Bit Name
MON_HPH_MUX
MON_LIN_MUTE
MON_MIX_ENABLE
MON_LIN_ATT
SLIDER_MON
DISABLE_MONITOR
Default
00
0
0
00
0
0
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Access
Bit Description
R/W
This register selects the ANC input source for the
headphone amplifier in monitor mode. Depending
on the register setting the outputs of microphone
preamplifier, OPAMP1, OPAMP2 can be connected
to the headphone amplifier input.
00: QMIC outputs are connected to HPH input
01: OP1 outputs are connected to HPH input
10: OP2 outputs are connected to HPH input
11: Nothing connected to HPH input except line
input and mixer input in case they are enabled.
R/W
This bit defines the status of the line input mute
switch in monitor mode. If the bit is set to ‘1’ the
line input amplifier is disconnected from the
headphone amplifier.
0: Line Input Mute disabled
1: Line Input Mute enabled
R/W
This bit enables the headphone mixer input pin to
mix external signals to the headphone amplifier in
playback only mode.
0: HPH mixer input disabled
1: HPH mixer input enabled
R/W
This register controls the line put gain in monitor
mode. Per default the line input is muted. With this
register it can be attenuated from -30dB up to
-36dB in 6dB steps.
00: 0dB line input gain in monitor mode
01: -24dB line input gain in monitor mode
10: -30dB line input gain in monitor mode
11: -36dB line input gain in monitor mode
R/W
This bit enables the Full Slider Mode configuration.
Please mind that this bit must not be set without
setting SLIDE_PWR_UP to ‘1’.
0: Slider Mode activated
1: Full Slider Mode activated
R/W
This bit disables the monitor mode in push button
control mode.
0: Monitor mode enabled
1: Monitor mode disabled
AS3415/AS3435 – 71
Register Description
Figure 93:
PBO_MODE Register Description
Name
Address
Default Value
PBO_MODE
0x16
00h
The ANC_MODE register controls various settings for the chipset in playback mode like which amplifiers are
enabled as well as which audio inputs are active.
Bit
Bit Name
Default
Access
7
TEST_BIT_4
1
R
6
5
4
3
2
1
0
NO_PBO
PBO_LIN_MUTE
PBO_MIX_ENABLE
PBO_OP2L_ON
PBO_OP2R_ON
PBO_OP1L_ON
PBO_OP1R_ON
AS3415/AS3435 – 72
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0
0
0
0
0
0
0
Bit Description
Test register. Please do not write this register.
R/W
This bit disables the playback only mode function. No
external pull up resistor is required on ANC / CSDA pin
is necessary if this bit is set to ‘1’
0: Playback only mode enabled
1: Playback only mode disabled
R/W
This bit defines the status of the line input mute
switch in playback only mode. If the bit is set to ‘1’ the
line input amplifier is disconnected from the
headphone amplifier.
0: Line Input Mute disabled
1: Line Input Mute enabled
R/W
This bit enables the eco mode of the microphone
preamplifier.
0: Power save function disabled
1: Power save function enabled
R/W
This register enables the left channel of OPAMP 2 in
playback only mode.
0: Left OP2 is switched off
1: Left OP2 is switched on
R/W
This register enables the right channel of OPAMP 2 in
playback only mode.
0: Right OP2 is switched off
1: Right OP2 is switched on
R/W
This register enables the left channel of OPAMP 1 in
playback only mode.
0: Left OP2 is switched off
1: Left OP2 is switched on
R/W
This register enables the right channel of OPAMP 1 in
playback only mode.
0: Right OP2 is switched off
1: Right OP2 is switched on
ams Datasheet, Confidential: 2013-Sep [1-10]
Register Description
Figure 94:
ECO Register Description
Name
Address
Default Value
ECO
0x17
0x00
This register controls the economic (ECO) mode for all analog audio blocks. Furthermore it includes also LED
control and other general settings.
Bit
7
6
5:4
3
2
1
0
Bit Name
SLIDE_PWR_UP
LOWBAT _100
ILED
ENABLE_HPH_ECO
ENABLE_MIC_ECO
ENABLE_LIN_ECO
ENABLE_OPAMP_ECO
Default
0
0
00
0
0
0
0
ams Datasheet, Confidential: 2013-Sep [1-10]
Downloaded from DatasheetLib.com - datasheet search engine
Access
Bit Description
R/W
This bit enables the slide switch control mode of
the AS3515/35. If this bit is programmed the device
can be powered up and powered down via a slide
switch.
0: Slide switch control disabled
1: Slide switch control enabled
R/W
This bit increases the LED low battery indication
level by 100mV.
0: Default LED indication level (0.95V)
1: Increased LED indication level (1.05V)
R/W
This register defines the driving strength of the ILED
pin for LED control.
00: Current sink switched off
01: 25%
10: 50%
11: 100%
R/W
This bit enables the eco mode of the headphone
amplifier.
0: Power save function disabled
1: Power save function enabled
R/W
This bit enables the eco mode of the microphone
amplifier.
0: Power save function disabled
1: Power save function enabled
R/W
This bit enables the eco mode of the line input
amplifier.
0: Power save function disabled
1: Power save function enabled
R/W
This bit enables the eco mode of the operational
amplifier amplifiers for ANC filter design.
0: Power save function disabled
1: Power save function enabled
AS3415/AS3435 – 73
Register Description
Figure 95:
ANC_L Register Description
Name
Address
Default Value
ANC_L
0x30
80h
The ANC_L Register configures the gain for the left microphone input.
Bit
Bit Name
Default
Access
7
TEST_BIT_5
1
R/W
Please do not write this register.
R/W
Volume settings for left microphone input, adjustable
in 63 steps of 0.5dB
00 0000: MUTE
00 0001: 0.5dB gain
00 0010: 1dB gain
00 0011: 1.5dB gain
…
11 1110: 30.5dB gain
11 1111: 31dB gain
5:0
MICL_VOL
000 0000
Bit Description
Figure 96:
ANC_R Register Description
Name
Address
Default Value
ANC_R
0x31
0x80
The ANC_R Register configures the gain for the left microphone input.
Bit
Bit Name
Default
Access
7
TEST_BIT_6
1
R/W
Please do not write this register.
R/W
Volume settings for right microphone input,
adjustable in 63 steps of 0.5dB
00 0000: MUTE
00 0001: 0.5dB gain
00 0010: 1dB gain
00 0011: 1.5dB gain
…
11 1110: 30.5dB gain
11 1111: 31dB gain
5:0
MICR_VOL_OTP
AS3415/AS3435 – 74
Downloaded from DatasheetLib.com - datasheet search engine
000 0000
Bit Description
ams Datasheet, Confidential: 2013-Sep [1-10]
Register Description
Figure 97:
MIC_MON_L Register Description
Name
Address
Default Value
MIC_MON_L
0x32
0x00
This register controls the microphone gain in monitor mode for the left microphone channel.
Bit
5:0
Bit Name
MICL_MON
Default
Access
Bit Description
R/W
Monitor mode gain setting for left microphone input
adjustable in 63 steps of 0.5dB
00 0000: MUTE
00 0001: 0.5dB gain
00 0010: 1dB gain
00 0011: 1.5dB gain
…
11 1110: 30.5dB gain
11 1111: 31dB gain
00 0000
Figure 98:
MIC_MON_R Register Description
Name
Address
Default Value
MIC_MON_R
0x33
0x00
This register controls the microphone gain in monitor mode for the right microphone channel.
Bit
5:0
Bit Name
MICR_MON_OTP
Default
00 0000
ams Datasheet, Confidential: 2013-Sep [1-10]
Downloaded from DatasheetLib.com - datasheet search engine
Access
Bit Description
R/W
Monitor mode gain setting for right microphone
input adjustable in 63 steps of 0.5dB
00 0000: MUTE
00 0001: 0.5dB gain
00 0010: 1dB gain
00 0011: 1.5dB gain
…
11 1110: 30.5dB gain
11 1111: 31dB gain
AS3415/AS3435 – 75
Register Description
Figure 99:
MODE_1 Register Description
Name
Address
Default Value
MODE_1
0x34
0x00
This register controls miscellaneous settings of the AS3515/35.
Bit
7
6
Bit Name
MICS_CP_OFF
MICS_OFF
Default
0
0
Access
Bit Description
R/W
This bit controls the microphone supply charge pump.
The microphone charge pump has a second function
besides the bias voltage generation for microphones.
It is also used to disable the integrated music bypass
switch if the AS3415/35 is active. In case the integrated
bypass switch is used in an application the
MICS_CP_OFF bit must not be set to ‘1’.
0: Microphone supply charge pump enabled
1: Microphone supply charge pump disabled
R/W
This bit controls the microphone supply. In case this
bit is set to ‘1’ the MICS pin is disconnected from the
internal microphone supply.
0: Microphone supply switched on
1: Microphone supply switched off
5
MIC_AGC_ON
0
R/W
This bit disables the automatic gain control of the
microphone preamplifier.
0: AGC disabled
1: AGC enabled
4
MIC_OFF
0
R/W
This bit powers down the microphone preamplifier.
0: Microphone preamplifier enabled
1: Microphone preamplifier disabled
R/W
This bit disables the automatic power down function
of the device with a low battery condition.
0: Low battery shutdown enabled
1: Low battery shutdown disabled
R/W
This bit disables the VNEG charge pump in case there is
already a negative supply present in a system.
0: VNEG charge pump enabled
1: VNEG charge pump enabled
R/W
This bit allows the user to power down headphone
amplifier in case it is not used in the final application in
order to save system power.
0: Headphone amplifier enabled
1: Headphone amplifier disabled
R/W
This bit allows the user to power down the line input
preamplifier in case it is not used in the final
application in order to save system power.
0: Line Input amplifier enabled
1: Line Input amplifier disabled
3
2
1
0
NO_LOWBAT_OFF
CP_OFF
HPH_OFF
LIN_OFF
AS3415/AS3435 – 76
Downloaded from DatasheetLib.com - datasheet search engine
0
0
0
0
ams Datasheet, Confidential: 2013-Sep [1-10]
Register Description
Figure 100:
MODE_2 Register Description
Name
Address
Default Value
MODE_2
0x35
0x00
This register controls miscellaneous settings of the AS3515/35.
Bit
Bit Name
Default
Access
7
TEST_BIT_7
1
R/W
Test register. Please do not write this register.
R/W
This bit disables the internal microphone supply
discharge function if the microphone supply is
switched off.
0: MICS discharge enabled
1: MICS discharge disabled
R/W
With this bit it is possible to delay the HPH_MUX setting
during startup of the device to avoid unwanted pop
noise in case of long charging times of external
components.
0: HPH_MUX_OTP delay disabled
1: HPH_MUX_OTP delay enabled
3
2
MICS_DC_OFF
DELAY_HPH_MUX
0
0
Bit Description
1
HPH_MODE
0
R/W
This register controls the operating mode of the
headphone amplifier. The headphone amplifier
supports single ended mode and differential mode. In
differential output mode the right audio signal path is
the active input signal for the headphone amplifier.
0: Stereo single ended mode
1: Mono differential mode
0
I2C_MODE
0
R/W
This bit enables I²C power down of the AS3415/35.
0: I²C power down disabled
1: I²C power down enabled via PWR_HOLD bit.
ams Datasheet, Confidential: 2013-Sep [1-10]
Downloaded from DatasheetLib.com - datasheet search engine
AS3415/AS3435 – 77
Register Description
Evaluation Registers
Figure 101:
EVAL Register Description
Name
Address
Default Value
EVAL
0x3D
0x00
This register enables miscellaneous operating modes, that are typically controlled via slide switch or push
button, for evaluation purposes or MCU controlled applications.
Bit
Bit Name
Default
Access
7
EVAL_ON
0
R/W
Function to be defined.
R/W
This register is the master register for the line input
mute function. No matter in what operating mode
the device is working the LINE_MUTE bit overrules
any other setting in any operation mode.
0: Line Input master mute disabled
1: Line Input master mute enabled
R/W
This register is the master register for the mixer input
function. No matter in what operating mode the
device is working the MASTER_MIX_ENABLE bit
overrules any other setting in any operation mode.
0: Line Input master mute disabled
1: Line Input master mute enabled
R/W
This bit enables the monitor mode of AS3415/35
which can normally be enabled by pulling the MODE
pin to VBAT/2. In case an MCU is connected to the
device the Monitor mode can be enabled by setting
this bit.
0: Monitor mode deactivated
1: Monitor mode activated
R/W
This bit enables the playback mode of AS3415/35
which can normally be enabled by pulling the ANC
pin to 0V. In case an MCU is connected to the device
the Monitor mode can be enabled by setting this bit.
0: Monitor mode deactivated
1: Monitor mode activated
R/W
This register is the master mute register for the left
microphone amplifier. No matter in what operating
mode the device is working the MICL_MUTE bit
overrules any other setting in any operation mode.
0: Mute disabled
1: Mute enabled
R/W
This register is the master mute register for the left
microphone amplifier. No matter in what operating
mode the device is working the MICR_MUTE bit
overrules any other setting in any operation mode.
0: Mute disabled
1: Mute enabled
5
4
3
2
1
0
MASTER_LIN_MUTE
MASTER_MIX_ENABLE
MON_MODE
PBO_MODE
MICL_MUTE
MICR_MUTE
AS3415/AS3435 – 78
Downloaded from DatasheetLib.com - datasheet search engine
0
0
0
0
0
0
Bit Description
ams Datasheet, Confidential: 2013-Sep [1-10]
Register Description
Figure 102:
CONFIG_1 Register Description
Name
Address
Default Value
CONFIG_1
0x3E
0x00
This bit controls the OTP programming clock source.
Bit
3
Bit Name
Default
EXTBURNCL
Access
0
R/W
Bit Description
This register controls the clock source for OTP
programming. Typically the internal clock is being
used for OTP programming.
0: External burn clock disabled
1: External burn clock enabled
Figure 103:
CONFIG_2 Register Description
Name
Address
Default Value
CONFIG_2
0x3F
0x00
This register controls the register access to all OTP registers. In order to get access to these registers it is
necessary to set REG3F_ON bit to ‘1’.
Bit
5
4
3
2
Bit Name
TM34
BURNSW
TM_REG34-35
TM_REG30-33
Default
0
0
0
0
ams Datasheet, Confidential: 2013-Sep [1-10]
Downloaded from DatasheetLib.com - datasheet search engine
Access
Bit Description
R/W
This Register defines the register bank selection for
register 0x30-0x35 and 0x10-0x17. Depending on
TM34 you can select either between Register bank
0x10-0x17 or 0x30h-0x34.
0: Test mode Registers 14h-17h and 10h-13h
disabled test mode Registers 30h-33h and 34h37h enabled
1: Test mode Registers 14h-17h and 10h-13h enabled
test mode Registers 30h-33h and 34h-37h disabled
R/W
This register controls the internal buffer switch from
line input to VNEG for VNEG buffering during OTP
programming.
0: BURN switch disabled
1: BURN switch enabled
R/W
0: Register 34h-35h disabled
Register 14h-17h disabled
1: Register 34h-35h enabled
Register 14h-17h enabled
R/W
0: Register 30h-33h disabled
Register 10h-13h disabled
1: Register 30h-33h enabled
Register 10h-13h enabled
AS3415/AS3435 – 79
Register Description
Name
Address
Default Value
CONFIG_2
0x3F
0x00
This register controls the register access to all OTP registers. In order to get access to these registers it is
necessary to set REG3F_ON bit to ‘1’.
Bit
1:0
Bit Name
OTP_MODE
AS3415/AS3435 – 80
Downloaded from DatasheetLib.com - datasheet search engine
Default
00
Access
R/W
Bit Description
This register controls the OTP access.
00: READ
01: LOAD
10: WRITE
11: BURN
ams Datasheet, Confidential: 2013-Sep [1-10]
Application Information
Application Information
Figure 104:
AS3435 Stereo Feedback Application Example
C1
Vneg
10 uF
Left ANC
Vpo s
Feedback Fi lter
Vpos
GND
CPP
C2
CPN
Vn eg
1 uF
Expose d Pa d
U2
+
GND
29
28
31
30
32
34
33
36
35
37
10uF
-
BPL
C3
U1
AS3 435
Mu s i c By pas s n
i O FF m o d e
AGND
R4
10k
7
8
15 0R
9
HPR
T RSDA
26
HPL
QL INR
BPL
ANC/CSDA
Le ft Sp eaker
22
21
BPL
20
AGND
19
IOP2 R
QOP1R
18
Ri ght A NC
C7
AGND
Vpos
R8
C8
C9
It i s n ot po s si b l e to o pera te b oth m o de s n
i p a ra l e l .
2 k2
J1
Con trol Mod e Se e
l ction
IOP1R
17
ILED
C6
s ld
i e sw ti c h co n tro l o r p u sh b utto n c on tro l .
GND
Net T ie Grounds
10uF
10uF
C AUTION :
T1
AGND
Feedback Fi lter
AGND
N ote th at on l y o ne op e ra tio n m ode i s p o ss i ble . Ei the r
QMICR16
MICACR
15
MICR 14
MICS 13
ILED
12
Po s i ti o n b: AN C d i sab e
l d
Battery Socket
23
QOP2R
M ODE/CSCL
Right Speake r
24
M IXL
L INR
GND
BPR
25
M IXR
AS3435
T RSCL
MICL 11
Posi tio n a: ANC e n ab e
l d
a
ANC Contr ol
GND
BPR
L INL
MICACL
10
ANC Control
S1
b
10 k
QL INL
GND
27
VBAT
AGND
Vpos
R7
GND
15 0R
AGND
47 0nF
R6
6
CPP
R5
5
VNEG
3
CPN
10 k
2
QOP2L
R3
10k
QOP1L
10 k
4
C5
R 2
GND 1
U3
Line Inpu t
R2
IOP2L
L
470 nF
3
AGND
QMICL
R1
C4
1
IOP1L
AGND
VNEG
BPR
1 0uF
10uF
R10
AGND
2k2
R1 1
2k2
R9
D1
2 k2
L ED
AGND
C1 0
Right ANC M IC
10uF
R12
10k
AGND
AGND
AGND
Power LED
S2
b
a
1
S4
R14
1
10k
Vpos
ILED
R13
ILED
Lef t ANC MIC
On/Off Switch
Vpos
2
10 k
S3
Push Button Co ntrol
Monitor Mode
2
GND
GND
Slide Switch Control
Push Button Control
AS3435 Stereo Feedback Example: This application example shows a single AS3435 in feedback configuration with activated music bypass mode in off mode.
ams Datasheet, Confidential: 2013-Sep [1-10]
Downloaded from DatasheetLib.com - datasheet search engine
AS3415/AS3435 – 81
Application Information
Figure 105:
AS3415 Stereo Feed Forward Application Example
Vneg
C1
Left ANC
10uF
Feedback Filter
Vpos
CPP
CPN
GND
C2
Vpos
1uF
AGND
U2
+
Exposed Pad
7
8
BPR
HPR
TRSCL
HPL
ANC/CSDA
BPL
MODE/CSCL
Left Speaker
18
BPL
17
AGND
IOP1R
ILED
MICS
MICR
T1
AGND
16
14
15
11
13
12
GND
Net Tie Grounds
10uF
ILED
10uF
Right ANC
C7
C6
AGND
Battery Socket
21
Position b: ANC disabled
a
ANC Control
GND
10
9
ANC Control
10k
Position a: ANC enabled
MICL
R7
S1
b
Right Speaker
19
QOP1R
QMICR
AGND
GND
BPR
20
MIXL
QLINR
Vpos
23
22
MIXR
AS3415
LINR
10uF
GND
24
VBAT
TRSDA
C3
U1
AS3415
-
6
CPP
10k
25
5
R4
GND
LINL
MICACR
AGND
10k
GND
150R
4
R3
CPN
150R
470nF
26
R6
QLINL
MICACL
AGND
R5
27
C5
R 2
GND 1
28
3
VNEG
2
QOP1L
1
IOP1L
10k
10k
29
R2
30
U3
Line Input
470nF
3
QMICL
R1
C4
L
AGND
VNEG
BPR
31
Music Bypass in OFF mode
32
Vneg
33
BPL
Feedback Filter
AGND
CAUTION:
Vpos
Note that only one operation mode is possible. Either
slide switch control or push button control.
R8
2k2
J1
Control Mode Selection
C8
C9
It is not possible to operate both modes in parallel.
10uF
10uF
R10
AGND
2k2
R11
2k2
R9
D1
2k2
LED
AGND
C10
Right ANC MIC
10uF
ILED
Left ANC MIC
R12
AGND
AGND
AGND
Power LED
S3
b
R14
a
1
S4
10k
S2
1
10k
Vpos
ILED
R13
On/Off Switch
2
10k
Vpos
Push Button Control
Monitor Mode
2
GND
Slide Switch Control
GND
Push Button Control
AS3415 Stereo Feed-forward Example: This application example shows a single AS3415 in feed-forward configuration with activated music bypass mode in off mode.
AS3415/AS3435 – 82
Downloaded from DatasheetLib.com - datasheet search engine
ams Datasheet, Confidential: 2013-Sep [1-10]
Application Information
Figure 106:
AS3435 Hybrid Application Example
MIXR_LEFT
C1
C2
Vneg
Vpos
Vpos
GND
1uF
Exposed Pad
Vneg
10uF
CPP
CPN
Feedforward
Filter
U2
+
28
29
30
31
QOP1R
MICS
MICR
IOP1R
QMICR
MICACR
AGND
16
15
18
14
17
10uF
10uF
ILED
Feedback Filter
C7
C6
AGND
AGND
R8
R9
C8
C9
2k2
10uF
10uF
R10
AGND
-
CPP
GND
CPN
VNEG
QOP2L
IOP2L
10
12
AGND
13
AGND
19
IOP2R
11
150R
MODE/CSCL
ILED
150R
20
QOP2R
MICL
R6
MICACL
AGND
R5
32
MODE/CSCL
R 2
GND 1
U3
Line Input
21
BPL
ANC/CSDA
9
Speaker Left
22
HPL
QLINR
8
Battery Socket
MIXR_LEFT
23
MIXL
LINR
7
GND
BPR_LEFT
24
MIXR
AS3435
TRSCL
6
ANC/CSDA
33
10k
10k
QOP1L
R2
IOP1L
470nF
QMICL
VNEG
5
R1
C4
3
GND
25
HPR
TRSDA
10uF
26
BPR
LINL
C3
U1
AS3435
27
VBAT
QLINL
3
4
L
34
AGND
2
AGND
35
Music Bypass in OFF mode
BPR_RIGHT
36
37
1
BPR_LEFT
GND
2k2
R11
2k2
2k2
Analog and digital ground should be connected
together close to the negative battery terminal.
AGND
C10
Feed Forward MIC
Feedback MIC
10uF
T1
AGND
AGND
AGND
AGND
C2
BPR
LINL
HPL
QLINR
BPL
ANC/CSDA
low battery condition the LED starts flashing.
C7
10uF
D1
C8
10uF
10uF
R10
2k2
R11
2k2
2k2
AGND
ILED
Feedback MIC
10uF
AGND
AGND
LED
R9
C10
Feed Forward MIC
Vpos
ILED
Push Button Control
LED is on during normal operation. In case of a
18
14
17
15
16
10uF
GND
AGND
AGND
R8
AGND
19
QOP1R
MICR
IOP1R
QMICR
MICACR
C6
2
GND
11
AGND
2k2
Speaker Right
21
20
Feedback Filter
C9
Monitor Mode
Slide Switch Control
13
10
Push Button Control
12
2
10k
Vpos
MIXR_RIGHT
23
IOP2R
ILED
S3
b
On/Off Switch
24
22
QOP2R
MODE/CSCL
BPR_RIGHT
25
MIXL
LINR
10uF
26
MIXR
AS3435
C3
GND
27
HPR
TRSDA
MICL
S2
R14
a
1
S4
1
10k
10k
Vpos
28
QLINL
MICS
R13
CPP
VBAT
TRSCL
Vpos
GND
U1
AS3435
AGND
MICACL
R12
29
9
GND
ANC/CSDA
MODE/CSCL
J1
Control Mode Selection
CPN
8
VNEG
7
QOP2L
It is not possible to operate both modes in parallel.
10k
IOP2L
Note that only one operation mode is possible. Either
slide switch control or push button control.
6
R4
30
MODE/CSCL
10k
31
5
470nF
32
3
4
C5
33
AGND
R3
CAUTION:
QOP1L
2
IOP1L
GND
QMICL
VNEG
ANC Control
1
34
ANC/CSDA
35
Position b: ANC disabled
a
ANC Control
36
Position a: ANC enabled
S1
b
10k
10uF
GND
1uF
37
R7
CPP
CPN
Vpos
Vneg
C1
Feedforward
Filter
Vneg
Exposed Pad
GND
Net Tie Grounds
MIXR_RIGHT
Power LED
AGND
AS3435 Hybrid Example: This application example shows two AS3435 in hybrid configuration with activated music bypass mode in off mode.
ams Datasheet, Confidential: 2013-Sep [1-10]
Downloaded from DatasheetLib.com - datasheet search engine
AS3415/AS3435 – 83
PCB Layout Recommendation
PCB Layout Recommendation
Charge Pump
The Printed Circuit Board (PCB) layout of the charge pump is
essential for good audio performance. The layout
recommendation shown in Figure 107 shows the most
important components of the charge pump. These are C VBAT,
CFLY, C VNEG and the battery terminal. To guarantee lowest
output noise all three capacitors must be placed as close as
possible to the related pin on the AS3435/15 as shown in
Figure 1 & Figure 107. Additionally, it is recommended that the
ground pins on C VNEG, C VBAT and the AS3435/15 charge pump
pin (GND) have a short connection to each other. This will avoid
distribution of high frequency switching currents over the PCB.
All the ground pins should be connected with a single ground
plane or at least a strong connection directly to the battery
terminal. The layout example shown in Figure 107 makes use of
a ground plane on the top layer that is directly connected to
the negative battery terminal to feature a star shaped ground
concept.
Figure 107:
Charge Pump Layout Recommendation
BAT
GND
~
BOARD OUTLINE
SILK SCREEN TOP LAYER
TOP LAYER
CPP
GND
CPN
VNEG
C FLY
VBAT
AS3435
C VBAT
CVNEG
~
AS3435 Charge Pump Layout Recommendation: This diagram shows the layout recommendation of the
AS3435 charge pump.
Charge Pump Ground Layout:
It is important to minimize the ground loops between all charge pump components and AGND pin.
A dedicated ground plane with a connection back to the negative battery terminal should be used.
AS3415/AS3435 – 84
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PCB Layout Recommendation
Microphone
For the microphone preamplifier layout the designer must pay
special attention; the combination of bad layout and gain
values up to +20dB can cause unwanted noise. To minimize
noise, a layout example is shown in Figure 108 which is based
on the schematic shown in Figure 20. All microphone related
components which include DC blocking capacitors, bias
resistors as well as high pass filter components should be placed
according to Figure 108. Once the component placement is
done it is important to route the different ground connections
of all components correctly. For the microphone preamplifier a
local star shaped ground concept should be used, with AGND
pin defined as star point. Basically we have two important
ground pairs. The first are the microphone grounds next to MICR
and MICL terminals. These ground pins need a separate ground
connection back to the AS3515/35 AGND pin. A separate left
and right ground line is recommended rather than using a
single microphone ground line back to the star point at AGND.
The second important connections are the ground terminals of
C AC and R MICIN. They should be fed back to the AGND pin.
Figure 108 shows the separation of left and right channel. The
ground pads of CAC and R MICIN are connected together and
routed back to AGND pin of AS3415/35.
Figure 108:
Microphone Layout Recommendation
~
~
Connection to negative
battery terminal
Star point for microphone
ground connection
AGND
CAC
ILED
RMICIN
MICL
MICR
MICACR
MICS
CMICS
C MIC
R MICIN
R BIAS
Microphone ground
terminal right microphone
D
N R
AG ICICL
M
M ND
AG
Combined CAC and RMICIN
COMMENT LAYER
ground back to AGND pin.
BOARD OUTLINE
SILK SCREEN TOP LAYER
TOP LAYER
BOTTOM LAYER
C MIC
C AC
MICACL
AS3435
R BIAS
Microphone ground
terminal left microphone
AS3415/35 Microphone Layout Recommendation: This diagram shows the layout recommendation for the
AS3415/35 microphone preamplifier with all necessary peripheral components for operation.
Microphone Ground Layout:
Use separate ground connections for microphone inputs back to the AGND pin. The ground connection of CAC
and RMICIN should also make use of a dedicated connection back to AGND pin of AS3415/35.
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AS3415/AS3435 – 85
PCB Layout Recommendation
Line Input and Headphone
The line input- and the headphone amplifier are blocks with
higher system currents; therefore it is important to separate
these high input and output currents from the rest of the
system. The example shown in Figure 109 demonstrates how to
do a proper ground layout for boths blocks. To separate the
headphone amplifier from the rest of the system it is
recommended to route a dedicated ground connection from
the headphone amplifier terminal back to the battery ground
terminal of the device. With this separate ground connection
the high output currents of the headphone amplifier do not
influence the sensitive analog ground of the chipset. The same
layout technique is applicable for the line input amplifier. The
line input amplifier also has higher input currents because of
the 150Ω termination resistors (R TERM) connected to the line
input terminal shown in Figure 10. To avoid unwanted ground
currents influencing the sensitive analog system ground of the
AS3415/35, it is recommended to route a dedicated ground
connection from the line input terminal back to the negative
battery terminal of the PCB. The example shows a local ground
plane from the battery, to the line input terminals. Such a plane
should be used for more complicated line input filters. Thus, all
line input related components like R TERM, C HP, R 1 and R 2 as well
as other additional filter components should be connected to
this ground plane. The ground plane must be connected to the
battery terminal, at a single point, for best grounding effect.
Another important connection is the bypass connection from
line input terminal to the BPL and BPR pins of the AS3415/35.
This connection is active if the chip is in off mode or if the device
has run out of battery. It is important to use wide signal lines
for these connections. The wider these connections are, the
better it is for the application. The same is true for the ground
connections of the headphone amplifier and the line input
amplifier. A weak signal line can directly influence the channel
separation of the system. A minimum signal width of 1mm is
typically recommended for the left and right audio channels
and 2mm for the audio ground signals.
AS3415/AS3435 – 86
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PCB Layout Recommendation
Figure 109:
Line Input and Headphone Layout Recommendation
GND
GND
COMMENT LAYER
BOARD OUTLINE
SILK SCREEN TOP LAYER
TOP LAYER
BOTTOM LAYER
T1
Dedicated headphone
ground connection from
headphone terminal back to
battery ground terminal.
RTERM
Dedicated lien input ground
connection from line input
terminal back to
battery ground terminal.
CHP
R2
R1
QLINL
BPR
LINL
HPR
TRSDA
TRSCL
LINR
RTERM
L
R
BAT
CHP
~
QLINR
AS3435
HPL
BPL
R1
R2
Line input ground plane for all line
input related components.
GND
HPL
HPR
~
AS3415/35 Line Input and HPH Layout recommendation: This diagram shows the layout recommendation of
the AS3415/35 line input amplifier and the headphone amplifier.
Headphone Layout:
Use wide signal lines for line input ground, headphone ground and signal lines as well as for the music bypass
lines. A weak signal line on any of these connections can influence channel separation of the device.
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AS3415/AS3435 – 87
PCB Layout Recommendation
AS3435 Complete Layout Example
The combination of all layout recommendations given in the
previous chapters are shown in Figure 110. It also includes a
push button for on/off control and a status indication LED. It is
important to say that all layout recommendations are also
applicable for the AS3515.
Layout Recommendations:
All layout recommendations given in the
examples are also applicable for the
AS3415!
Figure 110:
AS3435 Over the Ear Layout Example
GND
BAT
GND
T1
R1
AS3435
R1
CAC
CMICS
BOARD OUTLINE
SILK SCREEN TOP LAYER
TOP LAYER
BOTTOM LAYER
RMICIN
C MIC
ff
O
n/
O
R BIAS
GND
HPL
HPR
D
N R
AG IC ICL
M
M ND
AG
R MICIN
R M-Up
R ANC
R2
C AC
CHP
R2
MIC
CHP
RTERM
L
R
RTERM
C FLY
C VBAT
CVNEG
R BIAS
D
LE
1
AS3435 over the ear layout example: This diagram shows the combination of all layout recommendations of a
PCB. The PCB outline is based on an over the ear headset.
AS3415/AS3435 – 88
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P C B Pa d L a y o u t
PCB Pad Layout
Figure 111:
AS3435 PCB Pad Layout Recommendation
3.5mm
3.5mm
0.2mm
0.4mm
RECOMMENDED LAND PATTERN TOP VIEW
LOW COMPONENT DENSITY
0.75mm
5.9mm
3.5mm
3.5mm
0.2mm
0.4mm
RECOMMENDED LAND PATTERN TOP VIEW
MEDIUM COMPONENT DENSITY
0.65mm
5.7mm
3.5mm
3.5mm
0.2mm
0.4mm
RECOMMENDED LAND PATTERN TOP VIEW
HIGH COMPONENT DENSITY
0.55mm
5.5mm
AS3435 PCB Pad Layout: This drawing shows the PCB footprint layout recommendation for three different
component density levels.
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AS3415/AS3435 – 89
PCB Pad Layout
Figure 112:
AS3415 PCB Pad Layout Recommendation
3.5mm
0.5mm
3.5mm
0.2mm
RECOMMENDED LAND PATTERN TOP VIEW
LOW COMPONENT DENSITY
0.75mm
5.9mm
3.5mm
3.5mm
0.2mm
0.5mm
RECOMMENDED LAND PATTERN TOP VIEW
MEDIUM COMPONENT DENSITY
0.65mm
5.7mm
3.5mm
3.5mm
0.2mm
0.5mm
RECOMMENDED LAND PATTERN TOP VIEW
HIGH COMPONENT DENSITY
0.55mm
5.5mm
AS3415 PCB Pad Layout: This drawing shows the PCB footprint layout recommendation for three different
component density levels.
AS3415/AS3435 – 90
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Pa c k a g e D r a w i n g s & M a r k i n g s
Package Drawings & Markings
Figure 113:
QFN Marking
YYWWXZZ
AS3415
@
YYWWXZZ
AS3435
@
QFN Marking: Shows the package marking of the QFN product version.
Figure 114:
Package Code YYWWIZZ
YY
Last two digits of the year
WW
Manufacturing week
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X
Plant identifier
ZZ
Free choice/ traceability code
AS3415/AS3435 – 91
Pack age Drawings & Mark ings
Figure 115:
AS3435, 36-pin QFN, 0.4mm Pitch
D
A
D1
36
PIN #1 I.D
B
Symbol
Min
Nom
Max
A
0.80
0.90
1.00
A1
0
0.02
0.05
A2
-
0.65
1.00
28
27
1
A3
9
2X
aaa C
2X
aaa C
19
10
L
0.35
0.40
0.45
Θ
0º
-
14º
b
0.15
0.20
0.25
18
(DATUM A )
D2
fff
C A B
0.60 MAX
28
fff
0.20 REF.
E
E1
36
PIN #1 I.D
C A B
27
1
0.60 MAX
E2
(DATUM B )
9
19
18
10
e
NX L
NX b
bbb
ddd
C A B
C
D
5.00 BSC.
E
5.00 BSC.
e
0.40 BSC.
D2
3.20
3.30
3.40
E2
3.20
3.30
3.40
D1
4.75 BSC.
E1
4.75 BSC.
aaa
-
0.10
-
bbb
-
0.07
-
ccc
-
0.10
-
ddd
-
0.05
-
eee
-
0.08
-
fff
-
0.10
-
N
A2
A
Θ
ccc C
A3
SEATING PLANE
NX
3
eee C
36
A1
3
C
Note(s) and/or Footnote(s):
1. Dimensioning & toleranceing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Coplanarity applies to the exposed heat slug as well as the terminal.
4. Radius on terminal is optional.
5. N is the total number of terminals.
AS3415/AS3435 – 92
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Pa c k a g e D r a w i n g s & M a r k i n g s
Figure 116:
AS3415, 32-pin QFN, 0.5mm Pitch
D
D1
Min
Nom
Max
A
0.80
0.90
1.00
A1
0
0.02
0.05
A2
-
0.65
1.00
B
25
32
PIN #1 I.D
Symbol
A
1
24
A3
E1
aaa C
2X
aaa C
9
D2
fff
C A B
0.60 MAX
25
C A B
L
0.35
0.40
0.45
Θ
0º
-
14º
b
0.18
0.25
0.30
16
(DATUM A )
fff
0.20 REF
17
8
2X
E
32
1
24
0.60 MAX
PIN #1 I.D
D
5.00 BSC
E
5.00 BSC
e
0.50 BSC
D2
3.40
3.50
3.60
E2
3.40
3.50
3.60
D1
4.75 BSC
E1
4.75 BSC
aaa
-
0.15
-
bbb
-
0.10
-
ccc
-
0.10
-
ddd
-
0.05
-
eee
-
0.08
-
fff
-
0.10
-
E2
(DATUM B)
17
8
9
16
e
NX L
NX b
bbb
ddd
C A B
C
N
A2
A
Θ
ccc C
A3
SEATING PLANE
NX
3
eee C
32
A1
3
C
Note(s) and/or Footnote(s):
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Coplanarity applies to the exposed heat slug as well as the terminal.
4. Radius on terminal is optional.
5. N is the total number of terminals.
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AS3415/AS3435 – 93
RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS: The term RoHS compliant means that ams products fully
comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams knowledge and belief as of the date
that it is provided. ams bases its knowledge and belief on
information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams has taken and continues to
take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams
and ams suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
AS3415/AS3435 – 94
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Ordering & Contac t Information
Ordering & Contact Information
Figure 117:
Ordering Information
Ordering Code
Description
Delivery Form
Package
AS3415-EQFP
Enhanced Low Noise Active Noise
Cancelling Speaker Driver
Tape & Reel dry pack
with 4000 pcs per reel
QFN 32 [5.0x5.0x0.9mm]
0.5mm pitch
AS3415-EQFM
Enhanced Low Noise Active Noise
Cancelling Speaker Driver
Tape & Reel dry pack
with 500 pcs per reel
QFN 32 [5.0x5.0x0.9mm]
0.5mm pitch
AS3435-EQFP
Enhanced Low Noise Active Noise
Cancelling Speaker Driver
Tape & Reel dry pack
with 4000 pcs per reel
QFN 36 [5.0x5.0x0.9mm]
0.4mm pitch
AS3435-EQFM
Enhanced Low Noise Active Noise
Cancelling Speaker Driver
Tape & Reel dry pack
with 500 pcs per reel
QFN 36 [5.0x5.0x0.9mm]
0.4mm pitch
Ordering Information: Shows the ordering information of the different packaging versions of the AS3415 and
AS3435.
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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AS3415/AS3435 – 95
Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141
Unterpremstaetten, Austria-Europe. Trademarks Registered. All
rights reserved. The material herein may not be reproduced,
adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its Term of Sale. ams
AG makes no warranty, express, statutory, implied, or by
description regarding the information set forth herein. ams AG
reserves the right to change specifications and prices at any
time and without notice. Therefore, prior to designing this
product into a system, it is necessary to check with ams AG for
current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This Product is provided by ams “AS IS” and
any express or implied warranties, including, but not limited to
the implied warranties of merchantability and fitness for a
particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
AS3415/AS3435 – 96
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Reference Guide
Reference Guide
ams Datasheet, Confidential: 2013-Sep [1-10]
Downloaded from DatasheetLib.com - datasheet search engine
1
1
2
2
General Description
Key Benefits & Features
Applications
Block Diagram
4
5
7
9
Pin Assignment
Pin Description
Absolute Maximum Ratings
Electrical Characteristics
11
11
11
12
14
17
20
21
24
27
28
29
30
35
36
37
38
41
41
42
43
44
45
46
47
47
48
49
49
51
52
56
58
61
Detailed Description
Audio Line Input
Line Input Gain Setting
High Pass EQ Function
Bass Boost EQ Function
Parameter
Microphone Inputs
Input Capacitor Selection
Parameter
Microphone Supply
Parameter
Headphone Amplifier
Parameter
Integrated Music Bypass Switch
Parameter
Operational Amplifier
Parameter
System
Power Up/Down Conditions
Start-Up Sequence
Modes of Operation
Full Slider Mode
Slider Mode
Push Button Mode
Playback Only Mode
LED Status Indication
VNEG Charge Pump
Parameter
OTP Memory & Internal Registers
OTP Read/Write and Load Access
OTP Fuse Storing
2-Wire Serial Interface
Protocol
Parameter
63
65
67
78
Register Description
System Registers
OTP Registers
Evaluation Registers
81
Application Information
AS3415/AS3435 – 97
Reference Guide
AS3415/AS3435 – 98
Downloaded from DatasheetLib.com - datasheet search engine
84
84
85
86
88
PCB Layout Recommendation
Charge Pump
Microphone
Line Input and Headphone
AS3435 Complete Layout Example
89
91
94
95
96
PCB Pad Layout
Package Drawings & Markings
RoHS Compliant & ams Green Statement
Ordering & Contact Information
Copyrights & Disclaimer
ams Datasheet, Confidential: 2013-Sep [1-10]
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