NAU85L40YG

NAU85L40 Quad Audio ADC with Integrated FLL and Microphone Preamplifier Description The NAU85L40 is a low power, high quality, 4-channel ADC for microphone array application. The NAU85L40 integrates programmable gain preamplifiers for quad differential microphones, significantly reducing external component requirements. A fractional FLL is available to accurately generate any audio sample rate using any commonly available system clock source from 8KHz through 33MHz. Audio data can be directed to two I2S data out lines or onto a single time division multiplexed (TDM) PCM data output. The NAU85L40 operates with analog supply voltages from 1.6V to 2V, while the digital core can operate down to 1.2V to conserve power. Internal register controls enable flexible power saving modes by powering down subsections of the chip under software control. The NAU85L40 is specified for operation from -40°C to +85°C, and is available in a 28-lead QFN package. Features  101dB SNR (A-weighted) @ 0dB gain,       Supports sample rates from 8 kHz to 48 kHz at 24- VDDA=1.8V, Fs = 48 kHz, OSR=128x 91dB THD+N @ 0dB gain, 0.8Vrms in, VDDA=1.8V, Fs=48 kHz, OSR=128x -124dB Channel Crosstalk @ 0dB gain, 0.9Vrms in, VDDA=1.8V, Fs=48 kHz, OSR=128x Integrated programmable gain microphone amplifier On-chip FLL I2C Serial control interface with read/write capability bit resolution  Two separate microphone bias supplies for low noise microphone biasing.  Standard audio data bus interfaces: I2S, Left or Right justified, TDM (4 channel), Two’s compliment, MSB first  32-bit audio sub frames  Package: Pb free 28L-QFN  Temperature range: -40 to 85° VSSA VREF VDDA VSSD VDDB VDDC MICREF MICVDD Block Diagram BCLK MIC1P ADC MIC1N MIC2P Digital Core HPF NF ALC u/A Law Compres sion ADC MIC2N MIC3P ADC MIC3N MIC4P ADC MIC4N Audio Interface I2S/PCM FS DO12 DO34/TDM SCLK Audio Interface I2S/PCM SDIO CSB MODE MICBIAS2 MICBIAS 2 FLL Nuvoton Technology Corporation America Tel: 1-408-544-1718 Fax: 1-408-544-1787 MCLKO MICBIAS 1 MCLKI MICBIAS1 Rev. 1.1: October 14, 2015 1 NAU85L40 Table of Contents BLOCK DIAGRAM ........................................................................................................................................ 1 PIN DIAGRAM .............................................................................................................................................. 3 PIN DESCRIPTION....................................................................................................................................... 3 ELECTRICAL CHARACTERISTICS ............................................................................................................. 4 1 GENERAL DESCRIPTION.................................................................................................................. 6 2 ANALOG INPUTS ............................................................................................................................... 6 2.1 ADC and Digital Signal Processing ..............................................................................................................7 2.2 ADC Digital Block .........................................................................................................................................7 2.2.1 Input Limiter / Automatic Level Control (ALC) .......................................................................................8 2.2.2 ADC Digital Volume Control ................................................................................................................ 10 2.2.3 Programmable Notch Filter ................................................................................................................. 10 2.3 3 Digital Interfaces ........................................................................................................................................ 11 POWER SUPPLY .............................................................................................................................. 11 3.1 3.2 4 5 Power on and off reset ............................................................................................................................... 11 Reference Voltage Generation ................................................................................................................... 11 CLOCKING AND SAMPLE RATES .................................................................................................. 12 CONTROL INTERFACES ................................................................................................................. 12 5.1 Selection of Control Mode .......................................................................................................................... 12 2 5.2 2-Wire-Serial Control Mode (I C Style Interface) ........................................................................................ 12 5.3 2-Wire Protocol Convention ....................................................................................................................... 12 5.4 2-Wire Write Operation............................................................................................................................... 13 5.5 2-Wire Read Operation .............................................................................................................................. 13 5.6 SPI Serial Control (3-wire interface) ........................................................................................................... 14 5.6.1 16-bit Write Operation (SPI 3-Wire Write) ........................................................................................... 14 6 DIGITAL AUDIO INTERFACE........................................................................................................... 15 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 Right-Justified Audio Data .......................................................................................................................... 15 Left-Justified Audio Data ............................................................................................................................ 15 I2S Audio Data Mode ................................................................................................................................. 16 PCM A Audio Data ..................................................................................................................................... 16 PCM B Audio Data ..................................................................................................................................... 17 PCM Time Slot Audio Data ........................................................................................................................ 17 TDM Right Justified Audio Data ................................................................................................................. 18 TDM Left Justified Audio Data .................................................................................................................... 18 TDM I2S Audio Data .................................................................................................................................. 19 TDM PCM A Audio Data ............................................................................................................................ 19 TDM PCM B Audio Data ............................................................................................................................ 20 TDM PCM Offset Audio Data ..................................................................................................................... 20 7 TYPICAL APPLICATION DIAGRAM ................................................................................................. 21 8 PACKAGE INFORMATION ............................................................................................................... 23 9 ORDERING INFORMATION ............................................................................................................. 24 VERSION HISTORY ................................................................................................................................... 24 Nuvoton Technology Corporation America Tel: 1-408-544-1718 Fax: 1-408-544-1787 Rev. 1.1: October 14, 2015 2 NAU85L40 MIC1P/LIN1 MIC1N VSSA VDDA MODE SDA SCL 21 20 19 18 17 16 15 Pin Diagram MIC2N 22 14 CSB MIC2P/LIN2 23 13 MCLKI MICBIAS1 24 12 FS MICVDD 25 11 BCLK MICBIAS2 26 10 DO12 MIC3P/LIN3 27 9 DO34/TDM MIC3N 28 8 MCLKO 2 3 4 5 6 7 VREF MICREF VDDC VSSD VDDB MIC4P/LIN4 MIC4N 1 NAU85L40 QUAD AUDIO ADC QFN 28-Pin Pin Description Pin # Name Type 1 2 3 4 5 6 7 8 9 MIC4P/LIN4 MIC4N VREF MICREF VDDC VSSD VDDB MCLKO DO34 Analog Input Analog Input Reference Analog Output Supply Supply Supply Digital Output Digital Output 10 DO12 Digital Output 11 12 13 14 BCLK FS MCLKI CSB Digital I/O Digital I/O Digital Input Digital Input 15 SCL Digital Input 16 SDA Digital I/O 17 MODE Digital Input 18 19 20 VDDA VSSA MIC1N Supply Supply Analog Input Nuvoton Technology Corporation America Tel: 1-408-544-1718 Fax: 1-408-544-1787 Functionality MICP Input 4 / Line In Input 4 MICN Input 4 Decoupling for Mid-rail Reference Voltage Decoupling for MIC Reference Voltage Digital Core Supply Digital Ground Digital Buffer (Input/Output) Supply Output from PLL Digital Audio ADC Data Output for ADC 3 and 4 or TDM Digital Audio ADC Data Output for ADC 1 and 2 Digital Audio Bit Clock Digital Audio Frame Sync Master Clock Input SPI 3-Wire MPU Chip Select/I2C address LSB SPI 3-Wire MPU Clock Input/I2C Clock (SCL). SPI 3-Wire MPU Data Input/I2C Data I/O (SDA). Control Interface Mode Selection Pin (I2C=1, SPI=0) Analog Power Supply Analog Ground MICN Input 1 Rev. 1.1: October 14, 2015 3 NAU85L40 21 22 23 24 MIC1P/LIN1 MIC2N MIC2P/LIN2 MICBIAS1 Analog Input Analog Input Analog Input Analog Output 25 26 MICVDD MICBIAS2 Supply Analog Output 27 28 MIC3P/LIN3 MIC3N Analog Input Analog Input MICP Input 1 / Line In Input 1 MICN Input 2 MICP Input 2 / Line In Input 2 Microphone Bias for Microphone ADC 1 and 2 Microphone Supply Microphone Bias for Microphone ADC 3 and 4 MICP Input 3 / Line In Input 3 MICN Input 3 Electrical Characteristics Conditions: VDDA = VDDC=1.8V, VDDB = 3.3V, MICVDD=3.3V, MCLK = 12.88MHz, TA = +25°C, 1 kHz signal, Fs = 48 kHz, 24-bit audio data, with differential inputs unless otherwise stated. Symbol Parameter Conditions Typical Limit Units (Limit) ADC THD+N ADC Total Harmonic Distortion + Noise SNR Signal to Noise Ratio MIC Input, MIC_GAIN = 6dB, VIN = 0.8Vrms, f=1KHz, Fs = 16KHz, OSR=128X 90 dB Reference= @ 0dB gain, 0.8Vrms in, VDDA=1.8V, Fs=48 kHz, OSR=128x 91 dB Reference = VOUT(0dBFS), AWeighted, MIC Input, MIC Gain = 0dB,fs = 8KHz, Mono Differential Input 100 dB Reference = VOUT(0dBFS), AWeighted, MIC Input, MIC Gain = 6dB,fs = 8KHz, Mono Differential Input 98 dB Reference = VOUT(0dBFS), AWeighted, Quad Input, Gain = 12dB,fs = 16KHz 96 dB Reference= MIC Gain= 0dB gain, (Aweighted) VDDA=1.8V, Fs = 48 kHz, OSR=128x VRIPPLE = 200mVP_P applied to AVDD, fRIPPLE = 217Hz, Input Referred, MIC_GAIN = 0dB Differential Input 101 dB 65 dB -124 dB 1 VRMS 2.5 V PSRR Power Supply Rejection Ratio Xtalk ADC channel cross talk MIC Input, MIC_GAIN = 0dB, VIN = 0.8Vrms, f=1KHz, Fs = 48KHz , Channel 1(3) to Channel 2 (4) FSADC ADC Full Scale Input Level AVDD = 1.8V VBIAS Output Voltage Programmable 2.1V to 2.8V in 0.1V Steps IOUT Output Current MICBIAS Nuvoton Technology Corporation America Tel: 1-408-544-1718 Fax: 1-408-544-1787 4 mA Rev. 1.1: October 14, 2015 4 NAU85L40 eOS Output Noise A-weighted 20Hz-20kHz -115 dBV Notes 1. Full Scale input level is relative to the magnitude of VDDA and can be calculated as FS = 1V rms*VDDA/1.8. 2. Distortion is measured in the standard way as the combined quantity of distortion products plus noise. The signal level for distortion measurements is at 3dB below full scale, unless otherwise noted. 3. Unused analog input pins should be left as no-connection. 4. Unused digital input pins should be tied to ground. Digital I/O Parameter Symbol Input LOW level VIL Input HIGH level Comments/Conditions Output LOW level Max Units VDDB = 1.8V 0.33 * VDDB VDDB = 3.3V 0.37 * VDDB V VIH Output HIGH level Min VDDB = 1.8V 0.57 * VDDB VDDB = 3.3V 0.63 * VDDB V ILoad = 1mA VDDB = 1.8V 0.9 * VDDB VOH VDDB = 3.3V 0.95 * VDDB ILoad = 1mA VDDB = 1.8V 0.1 * VDDB VOL VDDB = 3.3V 0.05 * VDDB V V Recommended Operating Conditions Condition Symbol Min Typical Max Units Digital Supply Range with sample rate > 48 kHz or FLL enabled VDDC 1.62 1.8 1.98 V Digital Supply Range with sample rate