74LVC16240ADGG,512

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74LVC16240A 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state Rev. 4 — 3 November 2011 Product data sheet 1. General description The 74LVC16240A is a 16-bit inverting buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits          5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V  JESD8-5A (2.3 V to 2.7 V  JESD8-C/JESD36 (2.7 V to 3.6 V ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and from 40 C to +125 C. 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC16240ADGG 40 C to +125 C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74LVC16240ADL 40 C to +125 C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 4. Functional diagram 1A0 1A1 1A2 1A3 1OE 2A0 2A1 2A2 2A3 2OE 47 2 46 3 44 5 43 6 1Y0 3A0 1Y1 3A1 1Y2 3A2 1Y3 3A3 1 3OE 41 8 40 9 38 11 37 12 48 2Y0 4A0 2Y1 4A1 2Y2 4A2 2Y3 4A3 4OE 36 13 35 14 33 16 32 17 3Y0 3Y1 3Y2 3Y3 25 30 19 29 20 27 22 26 23 4Y0 4Y1 4Y2 4Y3 24 001aaa439 Fig 1. Logic symbol 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state 1OE 2OE 3OE 4OE 1A0 1A1 1A2 1A3 2A0 2A1 2A2 2A3 3A0 3A1 3A2 3A3 4A0 4A1 4A2 4A3 1 48 25 24 47 1EN 2EN 3EN 4EN 1 1 2 46 3 44 5 43 6 41 1 2 8 40 9 38 11 37 12 36 13 1 3 35 14 33 16 32 17 30 1 4 19 29 20 27 22 26 23 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3 001aaa442 Fig 2. IEC logic symbol 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state 5. Pinning information 5.1 Pinning 74LVC16240A 1OE 1 48 2OE 1Y0 2 47 1A0 1Y1 3 46 1A1 GND 4 45 GND 1Y2 5 44 1A2 1Y3 6 43 1A3 VCC 7 42 VCC 2Y0 8 41 2A0 2Y1 9 40 2A1 GND 10 39 GND 2Y2 11 38 2A2 2Y3 12 37 2A3 3Y0 13 36 3A0 3Y1 14 35 3A1 GND 15 34 GND 3Y2 16 33 3A2 3Y3 17 32 3A3 VCC 18 31 VCC 4Y0 19 30 4A0 4Y1 20 29 4A1 GND 21 28 GND 4Y2 22 27 4A2 4Y3 23 26 4A3 4OE 24 25 3OE 001aaa440 Fig 3. Pin configuration SSOP48 and TSSOP48 5.2 Pin description Table 2. Pin description Name Pin Description 1OE 1 output enable input (active LOW) 2OE 48 output enable input (active HIGH) 3OE 25 output enable input (active HIGH) 4OE 24 output enable input (active LOW) GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 supply voltage 1Y[0:3] 2, 3, 5, 6 data output 2Y[0:3] 8, 9, 11, 12 data output 3Y[0:3] 13, 14, 16, 17 data output 4Y[0:3] 19, 20, 22, 23 data output 1A[0:3] 47, 46, 44, 43 data input 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state Table 2. Pin description …continued Name Pin Description 2A[0:3] 41, 40, 38, 37 data input 3A[0:3] 36, 35, 33, 32 data input 4A[0:3] 30, 29, 27, 26 data input 6. Functional description Table 3. Function table[1] Input Output nOE nAn nYn L L H L H L H X Z [1] H = HIGH voltage level L = LOW voltage level X = don’t care Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V VI input voltage IOK output clamping current VO > VCC or VO < 0 V - 50 mA VO output voltage output HIGH or LOW state [2] 0.5 VCC + 0.5 V output 3-state [2] 0.5 +6.5 V - 50 mA IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot Tamb = 40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K. 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage functional VI input voltage VO output voltage Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V 40 - +125 C Tamb ambient temperature in free air t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 3.6 V - - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Product data sheet 40 C to +125 C Max Min Unit Max VCC = 1.2 V 1.08 - - 1.08 - V VCC = 1.65 V to 1.95 V 0.65  VCC - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V - 0.12 V VCC = 1.2 V - - 0.12 VCC = 1.65 V to 1.95 V - - 0.35  VCC - 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V IO = 100 A; VCC = 1.65 V to 3.6 V VCC  0.2 - - VCC  0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V VI = VIH or VIL VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V 0.1 5 - 20 A input leakage VCC = 3.6 V; VI = 5.5 V or GND current 74LVC16240A Typ[1] All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Typ[1] Min 40 C to +125 C Max Min Unit Max IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND; - 0.1 5 - 20 A IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 20 - 80 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC  0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6. Symbol Parameter tpd propagation delay Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - 12.0 - - - ns VCC = 1.65 V to 1.95 V 1.0 5.1 11.0 1.0 11.7 ns VCC = 2.3 V to 2.7 V 0.5 2.7 5.5 0.5 6.1 ns VCC = 2.7 V 1.0 2.7 5.2 1.0 6.5 ns 1.0 2.3 4.2 1.0 5.5 ns - 18.0 - - - ns VCC = 1.65 V to 1.95 V 1.5 6.6 12.8 1.5 13.5 ns VCC = 2.3 V to 2.7 V 1.0 3.8 6.8 1.0 7.5 ns VCC = 2.7 V 1.5 3.5 5.8 1.5 7.5 ns VCC = 3.0 V to 3.6 V 1.0 3.0 5.0 1.0 6.5 ns - 11.0 - - - ns nAn to nYn; see Figure 4 [2] VCC = 1.2 V VCC = 3.0 V to 3.6 V ten enable time nOE to nYn; see Figure 5 [2] VCC = 1.2 V tdis disable time nOE to nYn; see Figure 5 [2] VCC = 1.2 V VCC = 1.65 V to 1.95 V 2.9 4.7 9.2 2.9 9.7 ns VCC = 2.3 V to 2.7 V 1.0 2.6 5.0 1.0 5.6 ns VCC = 2.7 V 1.5 3.5 5.1 1.5 6.5 ns 1.5 3.2 4.9 1.5 6.5 ns - - 1.0 - 1.5 ns VCC = 3.0 V to 3.6 V tsk(o) output skew time 74LVC16240A Product data sheet VCC = 3.0 V to 3.6 V [3] All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6. Symbol Parameter CPD [1] [2] power dissipation capacitance Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max [4] per input; VI = GND to VCC VCC = 1.65 V to 1.95 V - 4.8 - - - pF VCC = 2.3 V to 2.7 V - 8.3 - - - pF VCC = 3.0 V to 3.6 V - 11.4 - - - pF Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL  VCC2  fo) = sum of the outputs 11. Waveforms VI nAn input VM VM GND tPHL tPLH VOH nYn output VM VM VOL mgu781 VM = 1.5 V at VCC  2.7 V; VM = 0.5  VCC at VCC < 2.7 V. VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. The input nAn to output nYn propagation delays 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled mna362 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Table 8. 3-state enable and disable times Measurement points Supply voltage Input Output VCC VM VM VX VY 1.2 V 0.5  VCC 0.5  VCC VOL + 0.1 V VOH  0.1 V 1.65 V to 1.95 V 0.5  VCC 0.5  VCC VOL + 0.1 V VOH  0.1 V 2.3 V to 2.7 V 0.5  VCC 0.5  VCC VOL + 0.1 V VOH  0.1 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 6. Table 9. Test circuit for measuring switching times Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC  2 ns 30 pF 1 k open 2  VCC GND 1.65 V to 1.95 V VCC  2 ns 30 pF 1 k open 2  VCC GND 2.3 V to 2.7 V VCC  2 ns 30 pF 500  open 2  VCC GND 2.7 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state 12. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 Fig 7. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Package outline SOT362-1 (TSSOP48) 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) θ pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 Fig 8. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Package outline SOT370-1 (SSOP48) 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC16240A v.4 20111103 Product data sheet - 74LVC16240A v.3 Modifications: 74LVC16240A v.3 • The format of this document has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7, and Table 9: values added for lower voltage ranges. 20040305 Product specification - 74LVC16240A v.2 74LVC16240A v.2 19970729 Product specification - 74LVC16240A v.1 74LVC16240A v.1 19951226 Product specification - - 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 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No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2011 © NXP B.V. 2011. All rights reserved. 15 of 16 74LVC16240A NXP Semiconductors 16-bit buffer/line driver; 5V tolerant; inverting; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 November 2011 Document identifier: 74LVC16240A