NSI6602A-DSWR

NSi6602 High Reliability Isolated Dual-Channel Gate Driver Datasheet (EN) 1.7 Product Overview NSi6602 is a family of high reliability isolated dualchannel gate driver ICs which can be designed to drive power transistor up to 2MHz switching frequency. Each output could source 4A and sink 6A peak current with fast 25ns propagation delay and 5ns maximum delay matching. The NSi6602 provides 2500Vrms isolation per UL1577 in 5-mm x 5-mm LGA13 package, 3000Vrms isolation in SOP16 (150mil) package, and 5700Vrms isolation in SOP16 (300mil) or SOP14 (300mil) package. System robustness is supported by 150kV/us typical commonmode transient immunity (CMTI). The driver operates with a maximum supply voltage of 25V, while the input-side accepts from 2.7V to 5V supply voltage. Under voltage lock-out (UVLO) protection is supported by all the power supply voltage pins. Safety Regulatory Approvals  UL recognition:  LGA13: 2500Vrms for 1 minute per UL1577  SOP16/SOP14(300mil): 5700Vrms for 1 minute per UL1577  SOP16(150mil): 3000Vrms for 1 minute per UL1577  DIN VDE V 0884-11:2017-01  CSA component notice 5A  CQC certification per GB4943.1-2011 Key Features Applications  Isolated dual channel driver  Isolated DC-DC and AC-to-DC power supplies in server, telecom, and industry  Driver side supply voltage: up to 25V with UVLO  4A peak source and 6A peak sink output  High CMTI: ±150kV/us typical  25ns typical propagation delay  5ns maximum delay matching  6ns maximum pulse width distortion  Programmable deadtime  Accepts minimum input pulse width 15ns  Operation temperature: -40℃~125℃  DC-to-AC solar inverters  Motor drives and EV charging  UPS and battery chargers Functional Block Diagram VDDI VDDA INA MOD DEMOD UVLO DT DIS INB OUTA GNDA UVLO, Disable & Dead-Time Isolation barrier  Input side supply voltage: 2.7V to 5.5V Functional Isolation VDDB MOD DEMOD UVLO GNDI OUTB GNDB Figure 0.1 NSi6602 Block Diagram Copyright © 2022, NOVOSENSE Page 1 NSi6602 Datasheet (EN) 1.7 INDEX 1. PIN CONFIGURATION AND FUNCTIONS ........................................................................................................... 3 2. ABSOLUTE MAXIMUM RATINGS ...................................................................................................................... 5 3. RECOMMENDED OPERATING CONDITIONS ...................................................................................................... 6 4. THERMAL INFORMATION ............................................................................................................................... 6 5. SPECIFICATIONS .......................................................................................................................................... 7 5.1. 5.2. 5.3. 5.4. 6. ELECTRICAL CHARACTERISTICS...................................................................................................................................... 7 SWITCHING CHARACTERISTICS ...................................................................................................................................... 8 TYPICAL PERFORMANCE CHARACTERISTICS .................................................................................................................. 9 PARAMETER MEASUREMENT INFORMATION ................................................................................................................ 13 HIGH VOLTAGE FEATURE DESCRIPTION ........................................................................................................ 15 6.1. 6.2. 6.3. 7. INSULATION CHARACTERISTICS ................................................................................................................................... 15 SAFETY-LIMITING VALUES ............................................................................................................................................. 16 SAFETY-RELATED CERTIFICATIONS ............................................................................................................................... 19 FUNCTION DESCRIPTION ............................................................................................................................ 20 7.1. OVERVIEW ...................................................................................................................................................................... 20 7.2. UNDER VOLTAGE LOCK OUT (UVLO) ............................................................................................................................. 20 7.3. INPUT AND OUTPUT LOGIC TABLE ............................................................................................................................... 21 7.4. PROGRAMMABLE DEADTIME (DT PIN) .......................................................................................................................... 21 7.4.1. PULLING THE DT PIN TO VDDI ............................................................................................................................... 21 7.4.2. DT PIN LEFT OPEN OR CONNECTED TO A PROGRAMMING RESISTOR BETWEEN DT AND GND PINS .................. 21 7.5. ESD PROTECTION .......................................................................................................................................................... 22 8. APPLICATION NOTE .................................................................................................................................... 23 8.1. 8.2. 9. TYPICAL APPLICATION CIRCUIT .................................................................................................................................... 23 PCB LAYOUT .................................................................................................................................................................. 23 PACKAGE INFORMATION ............................................................................................................................. 24 10. ORDERING INFORMATION ........................................................................................................................ 29 11. TAPE AND REEL INFORMATION ................................................................................................................. 30 12. REVISION HISTORY ................................................................................................................................. 32 Copyright © 2022, NOVOSENSE Page 2 NSi6602 Datasheet (EN) 1.7 1. Pin Configuration and Functions GNDI 1 13 VDDA INA 2 12 OUTA INB 3 11 GNDA VDDI 4 DIS 5 10 VDDB DT 6 9 OUTB VDDI 7 8 GNDB Figure 1.1 NSi6602 LGA13 Package INA 1 16 VDDA INB 2 15 OUTA VDDI 3 14 GNDA GNDI 4 13 NC DIS 5 12 NC DT 6 11 VDDB NC 7 10 OUTB VDDI 8 9 GNDB Figure 1.2 NSi6602 SOW16 Package INA 1 14 VDDA INB 2 13 OUTA VDDI 3 12 GNDA GNDI 4 DIS 5 DT 6 11 VDDB NC 7 10 OUTB VDDI 8 9 GNDB Figure 1.3 NSi6602 SOW14 Package Copyright © 2022, NOVOSENSE Page 3 NSi6602 Datasheet (EN) 1.7 INA 1 16 VDDA INB 2 15 OUTA VDDI 3 14 GNDA GNDI 4 13 NC DIS 5 12 NRC DT 6 11 VDDB NC 7 10 OUTB VDDI 8 9 GNDB Figure 1.4 NSi6602 SOP16 Package Copyright © 2022, NOVOSENSE Page 4 NSi6602 Datasheet (EN) 1.7 Table 1.1 NSi6602 Pin Configuration and Description PIN NO. SYMBOL FUNCTION LGA13 SOW16 SOP16 SOW14 1 4 4 4 GND Input-side ground reference. 2 1 1 1 INA TTL/CMOS compatible input signal for channel A with internal pull down to GND. It is recommended to connect this pin to GND if not used. 3 2 2 2 INB TTL/CMOS compatible input signal for channel B with internal pull down to GND. It is recommended to connect this pin to GND if not used. 4, 7 3, 8 3, 8 3, 8 VDDI Input-side supply voltage. It is recommended to place a bypass capacitor from this pin to GND as close as possible. 5 5 5 5 DISABLE 6 6 6 6 DT 8 9 9 9 GNDB Ground for output channel B 9 10 10 10 OUTB Output gate driver for channel B 10 11 11 11 VDDB Supply voltage for channel B 11 14 14 12 GNDA Ground for output channel A 12 15 15 13 OUTA Output gate driver for channel A 13 16 16 14 VDDA Supply voltage for channel A / 7,12,13 7, 13 7 NC Not connected / / 12 / NRC Internally connected to GNDB, not recommend connecting in circuit. Disables the isolator inputs and driver outputs if asserted high, enables if asserted low or left open. It is recommended to connect this pin to GND if not used. Programmable deadtime control. To allow the outputs overlapping by connecting DT to VDDI. Place a 1kΩ to 200kΩ resistor (RDT) between DT and GND to adjust deadtime following: tDT (ns) = 10 x RDT (kΩ). It is recommended to parallel a low ESR capacitor, e.g., 2.2nF or above. 2. Absolute Maximum Ratings Parameters Input Side Supply Voltage Output Side Supply Voltage Input Signal Voltage Output Signal Voltage Copyright © 2022, NOVOSENSE Symbol Min Max Unit VDDI to GNDI -0.3 6 V VDDA to GNDA, VDDB to GNDB -0.3 30 V INA, INB, DIS, DT to GNDI -0.3 VVDDI+0.3 V INA, INB, DIS, DT to GNDI, Transient for 50ns -5 VVDDI+0.3 V OUTA to GNDA, OUTB to GNDB -0.3 VVDDA+0.3 V Page 5 NSi6602 Datasheet (EN) 1.7 Parameters Symbol Min Max Unit VVDDB+0.3 OUTA to GNDA, OUTB to GNDB, Transient for 200ns Channel A to Channel B Voltage -2 VVDDA+0.3 V VVDDB+0.3 GNDA to GNDB in LGA13 package 700 V GNDA to GNDB in SOP16&SOW16 package 1500 V GNDA to GNDB in SOW14 package 1850 V Junction Temperature TJ -40 150 °C Storage Temperature Tstg -65 150 °C HBM (all pins) -4000 4000 V CDM -1500 1500 V Electrostatic discharge 3. Recommended Operating Conditions Parameters Symbol Min Max Unit VDDI to GNDI 3 5.5 V VDDA to GNDA, VDDB to GNDB (NSi6602A) 7 25 V VDDA to GNDA, VDDB to GNDB (NSi6602B) 9.4 25 V VDDA to GNDA, VDDB to GNDB (NSi6602C) 14.2 25 V INA, INB, DIS, DT 0 VVDDI V Ta -40 125 °C Input Side Supply Voltage Driver Side Supply Voltage Input Signal Voltage Ambient Temperature 4. Thermal Information Parameters Symbol LGA13 SOW16/SOW14 SOP16 Unit Junction-to-ambient thermal resistance1) RJA 209.5 97.0 150.5 °C/W Junction-to-case(top) thermal resistance2) RJC（top） 48.4 23.3 21.2 °C/W Junction-to-top characterization parameter3) ΨJT 41.8 35.8 52.3 °C/W Junction-to-board characterization parameter3) ΨJB 31.9 39.0 55.6 °C/W 1) Standard JESD51-3 Low Effective Thermal Conductivity Test Board (1s) in an environment described in JESD51-2a. 2) Standard JESD51-3 Low Effective Thermal Conductivity Test Board (1s) by transient dual interface test method described in JESD51-14. 3) Obtained by Simulating in an environment described in JESD51-2a. Copyright © 2022, NOVOSENSE Page 6 NSi6602 Datasheet (EN) 1.7 5. Specifications 5.1. Electrical Characteristics VDDI=3.3V or 5V, VDDA=VDDB=12V for NSi6602A/B, VDDA=VDDB=15V for NSi6602C, Ta=-40℃ to 125℃. Unless otherwise noted, Typical values are at Ta=25℃ Parameter Symbol Min Typ Max Unit Comments 2 mA INA=0, INB=0 mA Input frequency 500kHz, COUTA/B=15pF Input Side Supply VDDI Quiescent Current IVDDIQ 0.75 VDDI Operating Current IVDDI 1.8 VDDI UVLO Rising Threshold VVDDI_ON 2.35 2.55 2.75 V VDDI UVLO Falling Threshold VVDDI_OFF 2.15 2.35 2.55 V VDDI UVLO Hysteresis VVDDI_HYS 0.2 V Output Side Supply Output Side Supply Voltage VVDDA, VVDDB VDDA/B Quiescent Current, per Channel IVDDAQ, IVDDBQ 1.6 VDDA/B Operation Current, per Channel IVDDA, IVDDB 3.2 25 V Minimum defined by UVLO 2.5 mA INA=0, INB=0, VDDx=12V for 6V,8V UVLO; VDDx=15V for 13V UVLO mA 100pF, 500kHz, VDDx=12V for 6V,8V UVLO; VDDx=15V for 13V UVLO VDDA/B UVLO Rising Threshold VVDDA_ON, VVDDB_ON 5.7 6.15 6.5 V VDDA/B UVLO Falling Threshold VVDDA_OFF, VVDDB_OFF 5.4 5.85 6.2 V VDDA/B UVLO Hysteresis VVDDA_HYS, VVDDB_HYS VDDA/B UVLO Rising Threshold VVDDA_ON, VVDDB_ON 8.1 8.5 8.9 V VDDA/B UVLO Falling Threshold VVDDA_OFF, VVDDB_OFF 7.6 8.0 8.4 V VDDA/B UVLO Hysteresis VVDDA_HYS, VVDDB_HYS VDDA/B UVLO Rising Threshold VVDDA_ON, VVDDB_ON 12.7 13.2 13.7 V VDDA/B UVLO Falling Threshold VVDDA_OFF, VVDDB_OFF 11.7 12.2 12.7 V VDDA/B UVLO Hysteresis VVDDA_HYS, VVDDB_HYS 1 V Input Pin Pull Down Resistance, INA, INB RINA_PD, RINB_PD 100 kΩ Input Pin Pull Down Resistance, DIS (EN) RDIS_PD 100 kΩ VINA_H, VINB_H, VDIS_H 1.7 0.3 NSi6602A (6V) V 0.5 NSi6602B (8V) V NSi6602C (13V) Input Side Characteristic Logic High Input Threshold Copyright © 2022, NOVOSENSE 2 V Page 7 NSi6602 Parameter Datasheet (EN) 1.7 Symbol Min Typ VINA_L, VINB_L, VDIS_L 0.8 1.1 V VINA_HYS, VINB_HYS, VDIS_HYS 0.6 V Logic High Output Voltage VVDDA-VOUTA_H, VVDDBVOUTB_H 0.34 V Iout = 100mA Logic Low Output Voltage VOUTA_L, VOUTB_L 55 mV Iout = -100mA Output Source Resistance 1) ROUTA_H, ROUTB_H 3.4 Ω Iout = 100mA Output Sink Resistance ROUTA_L, ROUTB_L 0.55 Ω Iout = -100mA Peak Output Source Current IOUTA+, IOUTB+ 4 A Peak Output Sink Current IOUTA-, IOUTB- 6 A Logic Low Input Threshold Input Hysteresis Max Unit Comments Output Side Characteristic 1) The output source structure features a P-channel MOSFET and an N-channel MOSFET in parallel. The on-resistance of this Nchannel MOSFET is approximately 1.1Ω . 5.2. Switching Characteristics VDDI=3.3V or 5V, VDDA=VDDB=12V for NSi6602A/B, VDDA=VDDB=15V for NSi6602C, Ta=-40℃ to 125℃. Parameter Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPDLH-tPDHL| Channel to Channel Delay Matching Symbol Min Typ Max Unit 10 15 ns 25 35 ns tPWD 6 ns tDMLH, tDMHL 5 ns 200 240 ns tDT(ns)=10*R(kΩ); Test for R = 20kΩ tPWmin tPDHL, tPDLH 10 COUTA/B = 0 pF Programmed Deadtime tDT Output Rise Time (20% to 80%) tR 7 16 ns COUTA/B=1.8nF, verified by design Output Fall Time (90% to 10%) tF 6 12 ns COUTA/B=1.8nF, verified by design Shutdown Time from Disable True tDIS 40 ns Recovery Time from Disable False tEN 40 ns VDDI Power-up Time Delay 160 Comments tstart_VDDI 8.5 15 us INA or INB tied to VDDI tstart_VDDA, tstart_VDDB 18 30 us INA or INB tied to VDDI (Time from VDDI = VDDI_ON to OUTA/B = INA/B) VDDA/B Power-up Time Delay (Time from VDDA/B = 2V to OUTA/B = INA/B) Common Mode Transient Immunity Copyright © 2022, NOVOSENSE CMTI COUTA/B=1.8nF 100 150 kV/us verified by design Page 8 NSi6602 Datasheet (EN) 1.7 5.3. Typical Performance Characteristics 1 0.9 0.8 0.7 VDDI=3.3V 0.6 VDDI=5V 0.5 -40 -20 0 20 40 60 80 100 120 140 VDDI Operating Current (mA) VDDI Quiescent Current (mA) VDDI = 3.3 V, VDDA=VDDB=12V for NSi6602A/B, VDDA=VDDB=15V for NSi6602C, TA = 25°C. Output has no load unless otherwise noted. 1.7 1.65 1.6 1.55 1.5 Freq=100kHz Freq=500kHz Freq=1MHz 1.45 1.4 -40 -20 Ambient Temperature (°C) 2.4 2.2 2 1.8 1.6 VDDA/B=12V 1.2 VDDA/B=25V 1 -40 -20 0 6 5 4 3 2 Freq=100kHz Freq=500kHz Freq=1MHz 1 0 20 40 60 80 100 120 140 -40 -20 Ambient Temperature (°C) 8 2.5 2 1.5 1 Output High Output Low 0 5 10 15 20 Output High 7 Output Low 6 5 4 3 2 1 0 25 VDDA/B Supply Voltage (V) Figure 5.5 VDDA/B Quiescent Current vs Supply Voltage Copyright © 2022, NOVOSENSE 20 40 60 80 100 120 140 Figure 5.4 VDDA/B Operating Current vs Temperature Output Resistance (Ω) VDDA/B Quiescent Current (mA) 0 Ambient Temperature (°C) Figure 5.3 VDDA/B Quiescent Current vs Temperature 0.5 20 40 60 80 100 120 140 Figure 5.2 VDDI Operating Current vs Temperature VDDA/B Operating Current (mA) VDDA/B Quiescent Current (mA) Figure 5.1 VDDI Quiescent Current vs Temperature 1.4 0 Ambient Temperature (°C) -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature(°C) Figure 5.6 Output Resistance vs Temperature Page 9 Datasheet (EN) 1.7 16 14 12 10 8 Rising 6 Falling 4 -40 -20 0 Output Peak Current (A) Rising and Falling Time (ns) NSi6602 10 8 6 4 2 Source Sink 0 5 20 40 60 80 100 120 140 Ambient Temperature(°C) 2.8 2.6 2.4 2.2 Turn On Turn Off 2 -40 -20 0 0.19 0.18 0.17 0.16 0.15 -40 -20 6 5.5 Turn On Turn Off 5 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature(°C) Figure 5.11 6V VDDA/B UVLO Threshold vs Temperature Copyright © 2022, NOVOSENSE 0 20 40 60 80 100 120 140 Ambient Temperature(°C) Figure 5.10 VDDI UVLO Hysteresis vs Temperature VDDI UVLO Hysteresis (V) VDDI UVLO Threshold (V) 6.5 25 0.2 Ambient Temperature(°C) 7 20 Figure 5.8 Output Peak Current vs VDDA/B Supply Voltage 20 40 60 80 100 120 140 Figure 5.9 VDDI UVLO Threshold vs Temperature 15 VDDA/B Supply Voltage (V) VDDI UVLO Hysteresis (V) VDDI UVLO Threshold (V) Figure 5.7 Typical Rise Time & Fall Time vs Temperature 10 0.35 0.34 0.33 0.32 0.31 0.3 0.29 0.28 0.27 0.26 0.25 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature(°C) Figure 5.12 6V VDDA/B UVLO Hysteresis vs Temperature Page 10 Datasheet (EN) 1.7 9 VDDI UVLO Hysteresis (V) VDDI UVLO Threshold (V) NSi6602 8.5 8 7.5 Turn On Turn Off 7 -40 -20 0 0.6 0.595 0.59 0.585 0.58 0.575 0.57 0.565 0.56 0.555 0.55 20 40 60 80 100 120 140 -40 -20 Ambient Temperature(°C) 1.5 1 0.5 -40 -20 0 VIL Figure 5.14 8V VDDA/B UVLO Hysteresis vs Temperature VDDI UVLO Hysteresis (V) VDDI UVLO Threshold (V) 2 VIH 0.7 0.68 0.66 0.64 0.62 0.6 0.58 0.56 0.54 0.52 0.5 20 40 60 80 100 120 140 -40 -20 Ambient Temperature(°C) Figure 5.15 INA/INB/DIS Threshold vs Temperature 0 20 40 60 80 100 120 140 Ambient Temperature(°C) Figure 5.16 INA/INB/DIS Hysteresis vs Temperature 27 28 26 24 Rising edge Falling edge 22 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature(°C) Figure 5.17 Propagation Delay vs Temperature Copyright © 2022, NOVOSENSE Propagation Delay (ns) 30 Propagation Delay (ns) 20 40 60 80 100 120 140 Ambient Temperature(°C) Figure 5.13 8V VDDA/B UVLO Threshold vs Temperature 0 0 26 25 24 Rising Edge 23 Falling Edge 22 5 10 15 20 25 VDDA/B Supply Voltage (V) Figure 5.18 Propagation Delay vs VDDA/B Page 11 Datasheet (EN) 1.7 4 2 0 -2 Rising edge Falling edge -4 -40 -20 0 Pulse Width Distortion (ns) Propagation Delay Matching (ns) NSi6602 4 2 0 -2 -4 20 40 60 80 100 120 140 -40 -20 Ambient Temperature(°C) 40 35 30 25 Disable Enable 20 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature(°C) Output Peak Current (A) Figure 5.21 Disable & Enable Time vs Temperature 20 40 60 80 100 120 140 Ambient Temperature(°C) Figure 5.20 Pulse Width Distortion vs Temperature Programmed Deadtime (ns) Disable & Enable Time (ns) Figure 5.19 Propagation Delay Matching vs Temperature 0 250 230 210 190 170 150 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature(°C) Figure 5.22 Deadtime (RDT=20kΩ) vs Temperature 10 8 6 4 2 Source Sink 0 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature(℃) a 1 Figure 5.23 Output Peak Current vs Temperature Copyright © 2022, NOVOSENSE Page 12 NSi6602 Datasheet (EN) 1.7 5.4. Parameter Measurement Information Figure 5.23 Propagation Delay and Channel to Channel Delay Match Time, connect DT to VDDI VCC2 INA VDDA INB OUTA Probe1 VCC1 VDDI DT Input Logic Isolation barrier GNDA VDDB DIS OUTB GNDI GNDB Probe2 Figure 5.24 Channel to Channel Delay Match Test Circuit Figure 5.25 Disable Time and Enable Time Copyright © 2022, NOVOSENSE Page 13 NSi6602 Datasheet (EN) 1.7 Figure 5.26 Deadtime, Determined by RDT VCC1 VCC2 INA VDDA INB OUTA Probe1 VDDI DT Input Logic Isolation barrier GNDA VDDB DIS OUTB GNDI GNDB Probe2 Common Mode Surge Generator Figure 5.27 Common-Mode Transient Immunity Test Circuit Copyright © 2022, NOVOSENSE Page 14 NSi6602 Datasheet (EN) 1.7 6. High Voltage Feature Description 6.1. Insulation Characteristics Description Test Condition Symbol Value Unit LGA 13 SOW16/14 SOP16 Min. External Air Gap (Clearance) CLR 3.5 8 4 mm Min. External Tracking (Creepage) CPG 3.5 8 4 mm Distance through the Insulation DTI 32 CTI >600 Comparative Tracking Index DIN EN 60112 (VDE 0303-11) Material Group IEC 60664-1 um V I Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150Vrms I to III I to IV I to IV For Rated Mains Voltage ≤ 300Vrms I to II I to IV I to III For Rated Mains Voltage ≤ 600Vrms I I to IV I to II For Rated Mains Voltage ≤ 1000Vrms / I to III / Insulation Specification per DIN VDE V 0884-11:2017-011) Climatic Category 40/125/21 Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Isolation Voltage AC voltage 2 VIOWM 560 1000 700 VRMS 792 1414 990 VDC VIORM 792 1414 990 Vpeak Vpd (m) 1188 / 1485 Vpeak Vpd (m) / 2652 / Vpeak V pd (m) 1030 / 1287 Vpeak V pd (m) / 2263 / Vpeak V pd (m) 950 1697 1188 Vpeak DC voltage Maximum Voltage Repetitive Isolation Input to Output Test Voltage, Method B1 Vini. b = VIOTM, Vpd(m) = VIORM × 1.5, tini = tm = 1 sec, qpd ≤ 5 pC, 100% production test Vini. b = VIOTM, Vpd(m) = VIORM × 1.875, tini = tm =1 sec, qpd≤ 5 pC, 100% production test Input to Output Test Voltage, Method A. After Environmental Tests Subgroup 1 Vini. a = VIOTM, Vpd(m) = VIORM × 1.3, tini = 60 sec, tm = 10 sec, qpd ≤ 5 pC Vini. a = VIOTM, Vpd(m) = VIORM × 1.6, tini = 60 sec, tm = 10 sec, qpd ≤ 5 pC Input to Output Test Voltage, Method A. After Input and Output Safety Test Subgroup 2 and Subgroup 3 Copyright © 2022, NOVOSENSE Vini. a = VIOTM, Vpd(m) = VIORM × 1.2, tini = 60 sec, tm = 10 sec, qpd ≤ 5 pC Page 15 NSi6602 Datasheet (EN) 1.7 Description Test Condition Symbol Value Unit Maximum Transient Isolation Voltage t = 60 sec VIOTM 3535 8000 4242 Vpeak Maximum Surge Isolation Voltage Test method per IEC62368-1, VIOSM 3500 / 6000 Vpeak / 6250 / Vpeak 1.2/50us waveform, VTEST = 1.3 × VIOSM Test method per IEC62368-1, 1.2/50us waveform, VTEST = 1.6 × VIOSM Isolation Resistance VIO = 500 V, Tamb = TS RIO VIO = 500 V, 100 °C ≤ Tamb ≤ 125 °C Isolation Capacitance f = 1MHz CIO VTEST = 1.2 × VISO, t = 1 sec, VISO >109 Ω >1011 Ω 1.2 pF Insulation Specification per UL1577 Withstand Isolation Voltage 2500 5700 3000 Vrms 100% production test 1) This coupler is suitable for “safe electrical insulation” only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. 6.2. Safety-Limiting Values Basic isolation safety-limiting values as outlined in VDE-0884-11 of NSi6602x-xLAR (LGA13) Description Safety Supply Power Safety Supply Current Test Condition Side Value Input 12 mW Driver A, Driver B 293 mW Total 598 mW RθJA = 209.5 °C/ W1), VDDA/B = 12V, TJ = 150 °C, TA = 25 °C Driver A, Driver B 24.4 mA RθJA = 209.5 °C/ W1), VDDA/B = 25V, TJ = 150 °C, TA = 25 °C Driver A, Driver B 11.7 mA 150 °C RθJA = 209.5 °C/W1), TJ = 150 °C, TA = 25 °C Safety Temperature2) Unit 1) Calculate with the junction-to-air thermal resistance, RθJA, of LGA13 package (Thermal Information Table) which is that of a device installed on a low effective thermal conductivity test board (1s) according to JESD51-3. 2) The maximum safety temperature has the same value as the maximum junction temperature (TJ) specified for the device. Copyright © 2022, NOVOSENSE Page 16 Datasheet (EN) 1.7 700 600 500 400 300 200 100 0 0 50 100 150 200 Safety Limiting Current per Channel (mA) Safety Limiting Power (mW) NSi6602 30 IVDDA/B for VDD=25V 25 IVDDA/B for VDD=12V 20 15 10 5 0 0 Ambient Temperature (°C) 50 100 150 200 Ambient Temperature (°C) Figure 6.1 NSi6602x-DLAR Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11 Reinforced isolation safety-limiting values as outlined in VDE-0884-11 of NSi6602x-xSWxR (SOW16/SOW14) Description Safety Supply Power Safety Supply Current Test Condition Side Value Input 12 mW Driver A, Driver B 638 mW Total 1288 mW RθJA = 97 °C/ W1), VDDA/B = 12V, TJ = 150 °C, TA = 25 °C Driver A, Driver B 53.1 mA RθJA = 97 °C/ W1), VDDA/B = 25V, TJ = 150 °C, TA = 25 °C Driver A, Driver B 25.5 mA 150 °C RθJA = 97 °C/W1), TJ = 150 °C, TA = 25 °C Safety Temperature2) Unit Calculate with the junction-to-air thermal resistance, RθJA, of SOW16/SOW14 package (Thermal Information Table) which is that of a device installed on a low effective thermal conductivity test board (1s) according to JESD51-3. 2) The maximum safety temperature has the same value as the maximum junction temperature (TJ) specified for the device. 1400 1200 1000 800 600 400 200 0 0 50 100 150 200 Ambient Temperature (°C) Safety Limiting Current per Channel (mA) Safety Limiting Power (mW) 1) 60 IVDDA/B for VDD=25V 50 IVDDA/B for VDD=12V 40 30 20 10 0 0 50 100 150 200 Ambient Temperature (°C) Figure 6.2 NSi6602x-DSWR Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11 Basic isolation safety-limiting values as outlined in VDE-0884-11 of NSi6602x-xSPNR (SOP16) Description Copyright © 2022, NOVOSENSE Test Condition Side Value Unit Page 17 NSi6602 Datasheet (EN) 1.7 Safety Supply Power Safety Supply Current Input 12 mW Driver A, Driver B 409 mW Total 830 mW RθJA = 150.5 °C/ W1), VDDA/B = 12V, TJ = 150 °C, TA = 25 °C Driver A, Driver B 34.0 mA RθJA = 150.5 °C/ W1), VDDA/B = 25V, TJ = 150 °C, TA = 25 °C Driver A, Driver B 16.3 mA 150 °C RθJA = 150.5 °C/W1), TJ = 150 °C, TA = 25 °C Safety Temperature2) 2) The maximum safety temperature has the same value as the maximum junction temperature (TJ) specified for the device. 900 800 700 600 500 400 300 200 100 0 0 50 100 150 Ambient Temperature (°C) 200 Safety Limiting Current per Channel (mA) Calculate with the junction-to-air thermal resistance, RθJA, of SOP16 package (Thermal Information Table) which is that of a device installed on a low effective thermal conductivity test board (1s) according to JESD51-3. Safety Limiting Power (mW) 1) 40 IVDDA/B for VDD=25V 35 IVDDA/B for VDD=12V 30 25 20 15 10 5 0 0 50 100 150 200 Ambient Temperature (°C) Figure 6.3 NSi6602x-DSPNR Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN VDE V 0884-11 Copyright © 2022, NOVOSENSE Page 18 NSi6602 Datasheet (EN) 1.7 6.3. Safety-Related Certifications The NSi6602x-xLAR(LGA13) are approved or pending approval by the organizations listed in table. CUL UL1577 Component Recognition Program Single Protection, 2500Vrms Isolation voltage VDE CQC Approved under CSA Component Acceptance Notice 5A DIN VDE V 0884-11: 2017-01 Certified by CQC11-4715432012 Single Protection,2500Vrms Isolation voltage Basic Insulation at GB4943.1-2011 Basic insulation VIORM=792VPEAK VIOSM=3500VPEAK VIOTM=3535VPEAK E500602 E500602 File (pending) CQC21001289933 The NSi6602x-xSWxR(SOW16/SOW14) are approved or pending approval by the organizations listed in table. CUL UL 1577 Component Recognition Program Single Protection, 5700Vrms Isolation voltage VDE CQC Approved under CSA Component Acceptance Notice 5A DIN VDE V 0884-11: 2017-01 Certified by CQC11-4715432012 Single Protection, 5700Vrms Isolation voltage Reinforced insulation at GB4943.1-2011 Reinforced insulation VIORM=1414VPEAK VIOSM=6250VPEAK VIOTM=8000VPEAK E500602 E500602 Certification No. 40052820 CQC20001264939 The NSi6602x-xSPNR(SOP16) are approved or pending approval by the organizations listed in table. CUL UL 1577 Component Recognition Program Single Protection, 3000Vrms Isolation voltage VDE CQC Approved under CSA Component Acceptance Notice 5A DIN VDE V 0884-11(VDE V 0884-11):2017-01 Certified by CQC11-4715432012 Single Protection, 3000Vrms Isolation voltage Basic insulation at GB4943.1-2011 Basic insulation VIORM=990VPEAK VIOSM=6000VPEAK VIOTM=4242VPEAK E500602 Copyright © 2022, NOVOSENSE E500602 File (pending) CQC21001289931 Page 19 NSi6602 Datasheet (EN) 1.7 7. Function Description 7.1. Overview NSi6602 is a high reliability dual channel isolated gate driver which could be designed in variety switching power and motor drive topologies. NSi6602 has some useful protections, such as under voltage lock-out (UVLO) for both input and output supply, a disable pin, dead-time control, default low output as input is floating. The functional circuit block diagram is shown as below: VDDI VDDA UVLO UVLO DIS MOD Isolation barrier INA DEMOD Control Logic INB Driver Logic OUTA GNDA Functional Isolation VDDB UVLO DT DeadTime Control MOD DEMOD Driver Logic GNDI OUTB GNDB Figure 7.1 Functional Block Diagram 7.2. Under Voltage Lock Out (UVLO) The NSi6602 has an internal under voltage lock out (UVLO) protection on both input and output supply circuit blocks. The driver output is held low by an active clamp circuit when the supply voltage of VDDI or VDDA/VDDB is lower than VVDD_ON at power-up status or lower than VVDD_OFF after power-up, regardless of the status of the input pins. The VDDI and VDDA/B ULVO protections have hysteresis (VVDD_HYS) to prevent chatter noise from VDD supply and allow small drops in supply power which are usually happened in startup. Copyright © 2022, NOVOSENSE Page 20 NSi6602 Datasheet (EN) 1.7 7.3. Input and Output Logic Table When the device is power up, setting the DIS pin high can shut down both outputs simultaneously. Left open or grounding the DIS pin can allow the device operating normally. Table 7.1 Output status vs. Input and Power status VDDI status VDDA/B status DIS PU PU PU IN OUT NOTE1) A B A B L or O L H L H PU L or O H L H L PU PU L or O H H H H DT pin is pulled to VDDI. PU PU L or O H H L L DT is left open or programmed with RDT. PU PU L or O L L L L PU PU L or O O O L L PU PU H X X L L PU PD X X X L L PD PU X X X L L 1) If Deadtime function is used, output transits to high after the deadtime expires. PD= Power Down; PU= Power Up; H= Logic High; L= Logic Low; O= Left Open; X= Irrelevant. 7.4. Programmable Deadtime (DT pin) 7.4.1. Pulling the DT Pin to VDDI This allows outputs match inputs completely and no deadtime is asserted. 7.4.2. DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins If the DT pin is left open, the deadtime duration (tDT) is set to