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ASDM30DN40E-R

ASDM30DN40E-R

  • 厂商:

    ASDSEMI(安森德)

  • 封装:

    PDFN8_3.3X3.3MM

  • 描述:

    MOSFETs Dual N-沟道 30V 40A 8mΩ@10V 20W PDFN8_3.3X3.3MM

  • 数据手册
  • 价格&库存
ASDM30DN40E-R 数据手册
ASDM30DN40E 30V Dual N-Channel Power MOSFET Features Product Summary  Enhancement mode V DS 30 V  Fast Switching and High efficiency R DS(on),TYP@ VGS=10 V 8 mΩ  Pb-free lead plating; RoHS compliant ID 40 A  Low on-resistance RDS(on) @ VGS=4.5 V PDFN 3.3x3.3-8 NMOS Maximum ratings, at T A=25 °C, unless otherwise specified Symbol V(BR)DSS Parameter Unit 30 V ±20 V TA=25°C 40 A TC =25°C 40 A TC =100°C 19 A Drain-Source breakdown voltage VGS Gate-Source voltage IS Diode continuous forward current ID Continuous drain current @VGS=10V IDM Pulse drain current tested ① IDSM Continuous drain current @VGS=10V EAS Avalanche energy, single pulsed PD Maximum power dissipation PDSM Maximum power dissipation ③ TSTG , TJ Rating TC =25°C 160 A TA=25°C 11 A TA=70°C 9 A 16 mJ TC =25°C 20 W TC =100°C 8 W TA=25°C 2.8 W TA=70°C 1.8 W -55 to 150 °C Typical Unit ② Storage and junction temperature range Thermal Characteristics Symbol Parameter RθJC Thermal Resistance, Junction-to-Case 6.2 °C/W Rθ JA Thermal Resistance, Junction-to-Ambient 45 °C/W NOV 2018 Version1.0 1/7 Ascend Semicondutor Co.,Ltd ASDM30DN40E 30V Dual N-Channel Power MOSFET Electrical Characteristics Symbol Parameter Condition Min. Typ. Max. Unit Static Electrical Characteristics @ Tj = 25°C (unless otherwise stated) Drain-Source Breakdown Voltage VGS=0V, ID=250μA 30 -- -- V Zero Gate Voltage Drain Current(Tj=25℃) VDS=30V,VGS=0V -- -- 1 μA Zero Gate Voltage Drain Current(Tj=125℃) VDS=30V,VGS=0V -- -- 100 μA IGSS Gate-Body Leakage Current VGS=±20V,VDS=0V -- -- ±100 nA VGS(TH) Gate Threshold Voltage VDS=VGS,ID=250μA 1.3 1.5 2.4 V VGS=10V, ID=20A -- 8 10 mΩ VGS=4.5V, ID=10A -- 12 14 mΩ -- 13 -- mΩ V(BR)DSS IDSS RDS(ON) Drain-Source On-State Resistance ④ Tj=100℃ Dynamic Electrical Characteristics @ T j= 25°C (unless otherwise stated) Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance Qg (10V) Total Gate Charge Qg (4.5V) Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge -- 830 -- pF -- 110 -- pF -- 105 -- pF -- 4.7 -- Ω -- 23 -- nC VDS=15V,ID=20A, -- 11 -- nC VGS=10V -- 4.2 -- nC -- 5.6 -- nC -- 5.8 -- ns VDS=15V,VGS=0V, f=1MHz f=1MHz Switching Characteristics t d(on) Turn-on Delay Time tr Turn-on Rise Time ID=20A, -- 56 -- ns t d(off) Turn-Off Delay Time RG=3Ω, -- 26 -- ns tf Turn-Off Fall Time -- 12 -- ns VDD=15V, VGS=10V Source- Drain Diode Characteristics@ Tj = 25°C (unless otherwise stated) VSD Forward on voltage ISD=20A,VGS=0V -- 0.9 1.2 V t rr Reverse Recovery Time Tj=25℃,Isd=20A, -- 6.8 -- ns Qrr Reverse Recovery Charge -- 2.0 -- nC VGS=0V di/dt=100A/μs NOTE: ① Repetitive rating; pulse width limited by max junction temperature. ② Limited by TJmax, starting TJ = 25°C, L = 0.5mH, RG = 25Ω, IAS = 8A, VGS =10V. Part not recommended for use above this value ③ The power dissipation PDSM is based on RθJA and the maximum allowed junction temperature of 150°C. ④ Pulse width ≤ 300μs; duty cycle≤ 2%. NOV 2018 Version1.0 2/7 Ascend Semicondutor Co.,Ltd ASDM30DN40E 30V Dual N-Channel Power MOSFET ID, Drain-Source Current (A) Normalized Threshold Voltage (Vth) Typical Characteristics Fig1. Typical Output Characteristics Fig2. Normalized Threshold Voltage Vs. Temperature Normalized On Resistance Tj - Junction Temperature (°C) ID, Drain-Source Current (A) VDS, Drain -Source Voltage (V) Fig3. Typical Transfer Characteristics Fig4. Normalized On-Resistance Vs. Temperature ID - Drain Current (A) Tj - Junction Temperature (°C) ISD, Reverse Drain Current (A) VGS, Gate -Source Voltage (V) VSD, Source-Drain Voltage (V) VDS, Drain -Source Voltage (V) Fig5. Typical Source-Drain Diode Forward Voltage NOV 2018 Version1.0 3/7 Fig6. Maximum Safe Operating Area Ascend Semicondutor Co.,Ltd ASDM30DN40E 30V Dual N-Channel Power MOSFET C, Capacitance (pF) VGS, Gate-Source Voltage (V) Typical Characteristics Qg - Total Gate Charge (nC) VDS, Drain-Source Voltage (V) Fig8. Typical Gate Charge Vs. Gate-Source Thermal Resistance) ZθJC Normalized Transient Fig7. Typical Capacitance Vs. Drain-Source Voltage Pulse Width (s) Fig9. Normalized Maximum Transient Thermal Impedance Fig10. Unclamped Inductive Test Circuit and waveforms NOV 2018 Version1.0 4/7 Fig11. Switching Time Test Circuit and waveforms Ascend Semicondutor Co.,Ltd ASDM30DN40E 30V Dual N-Channel Power MOSFET Ordering and Marking Information Ordering Device No. Marking ASDM30DN40E-R 30DN40 Package PDFN3.3*3.3-8 Quantity Tape&Reel 5000/Reel MARKING PACKAGE PDFN3.3*3.3-8 NOV 2018 Version1.0 Packing 30DN40 5/7 Ascend Semicondutor Co.,Ltd ASDM30DN40E 30V Dual N-Channel Power MOSFET Dual PDFN3.3*3.3 Package Outline Data Symbol Dimensions (unit: mm) Min Typ Max A 0.70 0.75 0.80 Notes: b 0.25 0.30 0.35 1. Refer to JEDEC MO-240 variation CA. c 0.10 0.15 0.25 2. Dimensions "D1" and "E1" do NOT include mold flash D 3.25 3.35 3.45 protrusions or gate burrs. D1 3.00 3.10 3.20 3. Dimensions "D1" and "E1" include interterminal flash or D2 1.78 1.88 1.98 protrusion. Interterminal flash or protrusion shall not exceed D3 -- 0.13 -- E 3.20 3.30 3.40 E1 3.00 3.15 3.20 E2 2.39 2.49 2.59 e 0.25mm per side. 0.65 BSC H 0.30 0.39 0.50 L 0.30 0.40 0.50 L1 -- 0.13 -- K 0.30 -- -- θ -- 10° 12° M * * 0.15 * Not Specified NOV 2018 Version1.0 6/7 Ascend Semicondutor Co.,Ltd ASDM30DN40E 30V Dual N-Channel Power MOSFET IMPORTANT NOTICE Xi‘an Ascend Semiconductor incorporated MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Xi‘an Ascend Semiconductor Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. Xi‘an Ascend Semiconductor Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Xi‘an Ascend Semiconductor Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume . all risks of such use and will agree to hold Ascendsemi Incorporated and all the companies whose products are represented on Xi‘an Ascend Semiconductor Incorporated website, harmless against all damages. Xi‘an Ascend Semiconductor Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel. Should Customers purchase or use Xi‘an Ascend Semiconductor Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Xi‘an Ascend Semiconductor Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application. www.ascendsemi.com NOV 2018 Version1.0 7/7 Ascend Semicondutor Co.,Ltd
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