ADS807E/1KG4

ADS807 ADS 807 E SBAS072A – JANUARY 1999 – REVISED JULY 2002 12-Bit, 53MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● SPURIOUS-FREE DYNAMIC RANGE: 82dB at 10MHz fIN ● HIGH SNR: 67.5dB (2Vp-p), 69dB (3Vp-p) ● LOW POWER: 335mW ● INTERNAL OR EXTERNAL REFERENCE ● LOW DNL: 0.5LSB ● FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p ● SSOP-28 PACKAGE The ADS807 is a high-speed, high dynamic range, 12-bit pipelined Analog-to-Digital (A/D) converter. This converter includes a high-bandwidth track-and-hold that gives excellent spurious performance up to and beyond the Nyquist rate. The differential nature of this track-and-hold and A/D converter circuitry minimizes even-order harmonics and gives excellent common-mode noise immunity. The track-and-hold can also be operated single-ended. APPLICATIONS ● COMMUNICATIONS IF PROCESSING ● COMMUNICATIONS BASESTATIONS ● TEST EQUIPMENT ● MEDICAL IMAGING ● VIDEO DIGITIZING ● CCD DIGITIZING The ADS807 provides for setting the full-scale range of the converter without any external reference circuitry. The internal reference can be disabled allowing low drive, internal references to be used for improved tracking in multichannel systems. The ADS807 provides an over-range indicator flag to indicate an input signal that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of front end gain control circuitry. There is also an output enable pin to allow for multiplexing and testability on a PC board. The ADS807 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. CLK ADS807 Timing Circuitry +3V +2.5V IN +2V +3V +2.5V T/H IN (Opt.) Pipelined A/D Converter +2V Error Correction Logic 3-State Outputs D0 • • • D11 Internal Reference CM Optional External Reference INT/EXT FSSEL OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +VS ....................................................................................................... +6V Analog Input ........................................................... (–0.3V) to (+VS + 0.3V) Logic Input ............................................................. (–0.3V) to (+VS + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS807E ADS807E/1K Tube, 50 Tape and Reel, 1000 PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) ADS807E SSOP-28 DB –40°C to +85°C ADS807E " " " " " NOTE: (1) For the most current specifications and package information refer to our web site at www.ti.com. PIN CONFIGURATION PIN DESCRIPTIONS Top View SSOP GND 1 28 VDRV Bit 1 (MSB) 2 27 +VS Bit 2 3 26 GND Bit 3 4 25 IN Bit 4 5 24 IN Bit 5 6 23 CM Bit 6 7 22 REFT ADS807E 2 Bit 7 8 21 REFB Bit 8 9 20 GND Bit 9 10 19 OE Bit 10 11 18 INT/EXT Bit 11 12 17 OTR Bit 12 (LSB) 13 16 FSSEL CLK 14 15 +VS PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 CLK +VS FSSEL OTR INT/EXT 19 20 21 22 23 24 25 26 27 28 OE GND REFB REFT CM IN IN GND +VS VDRV DESCRIPTION Ground Data Bit 1 (MSB) Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Data Bit 8 Data Bit 9 Data Bit 10 Data Bit 11 Data Bit 12 (LSB) Convert Clock +5V Supply HI = 3V, LO = 2V Out-of-Range Indicator Reference Select: HIGH or Floating = External LOW = Internal 50kΩ pull-up. Output Enable Ground Bottom Reference/Bypass Top Reference/Bypass Common-Mode Voltage Output Complementary Analog Input Analog Input Ground +5V Supply Logic Driver Supply Voltage ADS807 www.ti.com SBAS072A ELECTRICAL CHARACTERISTICS At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted. ADS807E PARAMETER CONDITIONS MIN Ambient Air –40 +85 °C 2 1.5 1.75 1 3 3.5 3.25 4 V V V V µA MHz MΩ || pF 53M Samples/s Clock Cycles ±1.0 ±1.0 LSB LSB ±4.0 LSBs RESOLUTION MAX 12 Tested SPECIFIED TEMPERATURE RANGE ANALOG INPUT 2V Full-Scale Input Range 2V Full-Scale Input Range 3V Full-Scale Input Range 3V Full-Scale Input Range Analog Input Bias Current Analog Input Bandwidth Input Impedance TYP (Differential) (Single-Ended) (Differential) (Single-Ended) 2Vp-p, 2Vp-p, 3Vp-p, 3Vp-p, INT INT INT INT or or or or EXT EXT EXT EXT Ref Ref Ref Ref DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz f = 10MHz No Missing Codes No MIssing Codes Integral Nonlinearity Error, f = 1MHz Spurious-Free Dynamic Range(1) f = 1MHz (–1dB input) f = 10MHz (–1dB input) f = 20MHz (–1dB input) f = 40MHz (undersampling) f = 1MHz to 10MHz, fS = 40MHz 10k 6 ±0.5 ±0.5 Tested Tested ±2.0 fS = 40MHz fS = 50MHz,TA = +25°C fS = 40MHz, Full Temp 67 2Vp-p, Single-Ended Input 62 2-Tone Intermodulation Distortion(3) f = 12MHz and 13MHz (–7dB each tone) Signal-to-Noise Ratio (SNR) f = 1MHz (–1dB input) f = 10MHz (–1dB input) f = 20MHz (–dB input) f = 40MHz (undersampling) f = 1MHz to 10MHz, fS = 40MHz f = 1MHz to 10MHz, fS = 40MHz f = 1MHz (–1dB input) f = 10MHz (–1dB input) Signal-to-(Noise + Distortion) (SINAD)(4) f = 1MHz (–1dBFS input) f = 10MHz (–1dBFS input) f = 20MHz (–1dBFS input) f = 1MHz to 10MHz, fS = 40MHz f = 1MHz to 10MHz, fS = 40MHz Bits 1 270 1.25 || 3 CONVERSION CHARACTERISTICS Sample Rate Data Latency 63 63 2Vp-p, Single-Ended Input 63 60 3Vp-p 3Vp-p 61 61 2Vp-p, Single-Ended Input 63 60 UNITS 83 82 76 76 69 dBFS(2) dBFS dBFS dBFS dBFS 71 dBc 68 68 66 67 67.5 67 dB dB dB dB dB dB 69 69 dB dB 67 67 67 67 64 dB dB dB dB dB f = 1MHz (–1dBFS input) f = 10MHz (–dBFS Input) 3Vp-p 3Vp-p 69 69 dB dB Output Noise Aperture Delay Time Aperture Jitter Over-Voltage Recovery Time Input Grounded 0.2 2 1.2 2 LSBs rms ns ps rms ns DIGITAL INPUTS Logic Family Convert Command High Level Input Current(5) (VIN = 5V) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance +2.4 +1.0 5 ADS807 SBAS072A CMOS Rising Edge of Convert Clock +50 +10 Start Conversion www.ti.com µA µA V V pF 3 ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, differential input range = 2V to 3V for each input, sampling rate = 50MHz, unless otherwise noted. ADS807E PARAMETER DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA) Low Output Voltage, (IOL = 1.6mA) High Output Voltage, (IOH = 50µA) High Output Voltage, (IOH = 0.5mA) Low Output Voltage, (IOL = 50µA) High Output Voltage, (IOH = 50µA) 3-State Enable Time 3-State Disable Time Output Capacitance CONDITIONS POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation: VDRV = 5V VDRV = 3V VDRV = 5V VDRV = 3V Thermal Resistance, θJA SSOP-28 TYP MAX UNITS +0.1 +0.2 V V V V V V ns ns pF CMOS Straight Offset Binary VDRV = 5V VDRV = 5V VDRV = 5V VDRV = 5V VDRV = 3V VDRV = 3V OE = L(5) OE = H(5) ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted) Zero Error (Referred to –FS) at 25°C Zero Error Drift (Referred to –FS) at 25°C Gain Error(6) Gain Error Drift(6) Gain Error(7) at 25°C Gain Error Drift(7) Power-Supply Rejection of Gain ∆VS = ±5% REFT Tolerance 2V Full-Scale Deviation From Ideal 3.0V 3V Full-Scale Deviation From Ideal 3.25V REFB Tolerance 2V Full-Scale 3V Full-Scale External REFT Voltage Range External REFB Voltage Range Reference Input Resistance MIN +4.9 +4.8 +0.1 +2.8 50 Deviation From Ideal 2.0V Deviation From Ideal 1.75V REFB + 0.4 1.70 Operating Operating External Reference External Reference Internal Reference Internal Reference +4.75 20 2 5 40 10 ±1.0 16 ±1.5 66 ±1.0 23 70 ±2.0 ±2.5 ±1.5 %FS ppm/°C %FS ppm/°C %FS ppm/°C dB ±10 ±20 ±65 ±100 mV mV ±10 ±20 3 2 1 ±65 ±100 VS – 1.70 REFT – 0.4 mV mV V V kΩ +5.0 60 305 290 350 335 +5.25 V mA mW mW mW mW 50 360 350 390 380 °C/W NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (4) Effective number of bits (ENOB) is defined by as (SINAD – 1.76)/6.02. (5) A 50kΩ pull-down resistor is inserted internally on OE pin. (6) Includes internal reference. (7) Excludes internal reference. 4 ADS807 www.ti.com SBAS072A TIMING DIAGRAM N+2 N+1 Analog In N+4 N+3 N tD N+5 tL tCONV N+7 N+6 tH Clock 6 Clock Cycles t2 Data Out N–6 N–5 N–4 N–3 N–2 N–1 N Data Invalid SYMBOL tCONV tL tH tD t1 (1) t2 (1) N+1 t1 DESCRIPTION MIN Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 18.87 9.4 9.4 TYP MAX UNITS 100µs ns ns ns ns ns ns tCONV/2 tCONV/2 2 2.7 12 NOTE: (1) t1 and t2 times are valid for VDRV voltages of +2.7V to +5V. ADS807 SBAS072A www.ti.com 5 TYPICAL CHARACTERISTICS At TA = full specified temperature range, differential input range = 2V to 3V, sampling rate = 50MHz, and internal reference, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 1MHz SNR = 68dBFS SFDR = 83dBFS –10 –20 Magnitude (dBFS) Magnitude (dBFS) –20 fIN = 10MHz SNR = 68dBFS SFDR = 82dBFS –10 –30 –40 –50 –60 –70 –80 –30 –40 –50 –60 –70 –80 –90 –90 –100 –100 0 5 10 15 20 25 0 5 10 Frequency (MHz) fIN = 21MHz SNR = 68dBFS SFDR = 77dBFS f1 = 12MHz f2 = 13MHz IMD(3) = –71dBc –20 Magnitude (dBc) Magnitude (dBFS) 25 0 –20 –40 –60 –40 –60 –80 –80 –100 –100 0 5 10 15 20 0 25 5 10 15 20 Frequency (MHz) Frequency (MHz) SPECTRAL PERFORMANCE (Sampling Frequency = 27MHz) SPECTRAL PERFORMANCE (Single-Ended, 2Vp-p) 0 25 0 fIN = 10MHz SNR = 68dBFS SFDR = 81dBFS fIN = 10MHz SNR = 68dBFS SFDR = 62dBFS –20 Magnitude (dBFS) –20 Magnitude (dBFS) 20 2-TONE INTERMODULATION DISTORTION SPECTRAL PERFORMANCE 0 –40 –60 –80 –40 –60 –80 –100 –100 0 4.5 9.0 13.5 0 Frequency (MHz) 6 15 Frequency (MHz) 4.5 9.0 13.5 Frequency (MHz) ADS807 www.ti.com SBAS072A TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, differential input range = 2V to 3V, sampling rate = 50MHz, and internal reference, unless otherwise noted. SPECTRAL PERFORMANCE (Sampling Frequency = 53MHz) UNDERSAMPLING (Sampling Frequency = 27MHz) 0 0 fIN = 21MHz SNR = 68dBFS SFDR = 72dBFS –20 Magnitude (dBFS) Magnitude (dBFS) –20 fIN = 50MHz SNR = 65dBFS SFDR = 73dBFS –40 –60 –40 –60 –80 –80 –100 –100 0 5.3 10.6 15.9 21.2 26.5 0 4.5 Frequency (MHz) 9.0 13.5 Frequency (MHz) SWEPT POWER SFDR OUTPUT NOISE HISTOGRAM (DC INPUT) 100 800k fIN = 10MHz dBFS 3V Full-Scale 80 SFDR (dBFS, dBc) Counts 600k 400k 200k 60 dBc 40 20 0 N–2 0 N–1 N N+1 N+2 0 –10 –20 Code –30 –40 –50 –60 Input Amplitude (dBFS) DYNAMIC PERFORMANCE vs SAMPLING FREQUENCY (Differential Input) SINAD vs SAMPLING FREQUENCY (Differential Input) 75 90 fIN = 5MHz fIN = 5MHz 85 70 80 SINAD (dB) SFDR, SNR (dB) SFDR (2Vp-p) SFDR (3Vp-p) 75 SNR (3Vp-p) 3Vp-p 2Vp-p 65 70 60 65 SNR (2Vp-p) 55 60 35 40 45 50 55 60 ADS807 SBAS072A 35 40 45 50 55 60 Sampling Frequency (MHz) Sampling Frequency (MHz) www.ti.com 7 TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, differential input range = 2V to 3V, sampling rate = 50MHz, and internal reference, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR INTEGRAL LINEARITY ERROR 2.0 2.0 fIN = 1MHz fIN = 1MHz 1.5 1.0 1.0 0.5 0.5 ILE (LSB) DLE (LSB) 1.5 0 –0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 1024 2048 3072 4096 0 1024 Output Codes 4096 2.0 fIN = 10MHz fIN = 10MHz 1.5 1.5 1.0 1.0 0.5 0.5 ILE (LSB) DLE (LSB) 3072 INTEGRAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR 2.0 0 –0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 0 1024 2048 3072 0 4096 1024 2048 3072 Output Codes Output Codes DIFFERENTIAL LINEARITY ERROR (Single-Ended, Input Sampling Frequency = 40MHz) INTEGRAL LINEARITY ERROR (Sampling Frequency = 40MHz) 1.000 4096 2.0 fIN = 10MHz fIN = 10MHz 1.5 0.500 1.0 ILE (LSB) DLE (LSB) 2048 Output Codes 0 0.5 0 –0.5 –1.0 –0.500 –1.5 –2.0 –1.000 0 1024 2048 3072 4096 8 0 1024 2048 3072 4096 Output Codes Output Codes ADS807 www.ti.com SBAS072A • improves the noise immunity based on the converter’s common-mode input rejection APPLICATION INFORMATION THEORY OF OPERATION The ADS807 is a high-speed, CMOS A/D converter which employs a pipelined converter architecture consisting of 12 internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential linearity and no missing codes at the 12-bit level. The output data becomes valid after the rising clock edge (see Timing Diagram). The pipeline architecture results in a data latency of 6 clock cycles. The analog input of the ADS807 consists of a differential track-and-hold circuit. The differential topology along with tightly matched poly-poly capacitors produce a high level of AC performance at high sampling rates and in undersampling applications. Both inputs (IN, IN) require external biasing using a common-mode voltage that is typically at the mid-supply level (+VS/2). DRIVING THE ANALOG INPUTS The analog inputs of the ADS807 are a very high impedance. They should be driven through an R-C network designed to pass the highest frequency of interest. This prevents highfrequency noise in the input from affecting SFDR and SNR. The ADS807 can be used in a wide variety of applications and deciding on the best performing analog interface circuit depends on the type of application. The circuit definition should include considerations of input frequency spectrum and amplitude, single-ended or differential drive, and available power supplies. For example, communication (frequency domain) applications process frequency bands not including DC. In imaging (time domain) applications, the input DC component must be maintained into the A/D converter. Features of the ADS807, including full-scale select (FSSEL), external reference, and CM output provide flexibility to accommodate a wide range of applications. The ADS807 should be configured to meet application objectives while observing the headroom requirements of the driving amplifiers to yield the best overall performance. The ADS807 input structure allows it to be driven either single-ended or differentially. Differential operation of the ADS807 requires an in-phase input signal and a 180° out-ofphase part simultaneously applied to the inputs (IN, IN). The differential operation offers a number of advantages which, in most applications, will be instrumental in achieving the best dynamic performance of the ADS807: • the signal swing is half of that required for the singleended operation and therefore, is less demanding to achieve while maintaining good linearity performance from the signal source • the reduced signal swing allows for more headroom in the interface circuitry and therefore, a wider selection of the best suitable driver op amp • even-order harmonics are minimized Using the single-ended mode, the signal is applied to one of the inputs, while the other input is biased with a DC voltage to the required common-mode level. Both inputs are equal in terms of their impedance and performance, except that applying the signal to the complementary input (IN) instead of the IN input will invert the input signal relative to the output code. For example, in case the input driver operates in inverting mode, using IN as the signal input will restore the phase of the signal to its original orientation. Time-domain applications may benefit from a single-ended interface configuration and its reduced circuit complexity. While maintaining good SNR, driving the ADS807 with a single-ended signal will result in a reduction of the distortion performance. Employing dual-supply amplifiers and AC-coupling will usually yield the best results, while DC-coupling and/or singlesupply amplifiers impose additional design constraints due to their headroom requirements, especially when selecting the 3Vp-p input range. However, single-supply amplifiers have the advantage of inherently limiting their output swing to within the supply rails. Alternatively, a voltage-limiting amplifier, like the OPA688, may be considered to set fixed-signal limits and avoid any severe over-range condition for the A/D converter. The full-scale input range of the ADS807 is defined by the reference voltages. For example, setting the range select pin to FSSEL = LOW, and using the internal references (REFT = +3.0V and REFTB = +2.0V), the full-scale range is defined to: FSR = 2 • (REFT – REFB) = 2Vp-p. The trade-off of the differential input configuration versus the single-ended is its higher complexity. In either case, the selection of the driver amplifier should be such that the amplifier’s performance will not degrade the A/D converter’s performance. The ADS807 operates on a single power supply, which requires a level shift to a ground-based bipolar input signals to comply with its input voltage range requirements. The input of the ADS807 is of a capacitive nature and the driving source needs to provide the current to charge or discharge the input sampling capacitor while the track-andhold is in track mode. This effectively results in a dynamic input impedance which depends on the sampling frequency. It most applications, it is recommended to add a series resistor, typically 20Ω to 50Ω, between the drive source and the converter inputs. This will isolate the capacitive input from the source, which can be crucial to avoid gain peaking when using wideband operational amplifiers. Secondly, it will create a 1st-order, low-pass filter in conjunction with the specified input capacitance of the ADS807. Its cutoff frequency can be adjusted even further by adding an external shunt capacitor from each signal input to ground. The optimum values of this R-C network depend on a variety of factors which include the ADS807 sampling rate, the selected op amp, the interface configuration, and the particular application (time domain versus frequency domain). Generally, increasing the size of the series resistor and/or capacitor ADS807 SBAS072A www.ti.com 9 will improve the SNR performance, but depending on the signal source, large resistor values may be detrimental to achieving good harmonic distortion. In any case, optimizing the R-C values for the specific application is encouraged. Transformer Coupled, Single-Ended to Differential Configuration If the application requires a signal conversion from a singleended source to drive the ADS807 differentially, an RF transformer might be a good solution. The selected transformer must have a center tap in order to apply the commonmode DC voltage necessary to bias the converter inputs. ACgrounding the center tap will generate the differential signal swing across the secondary winding. Consider a step-up transformer to take advantage of a signal amplification without the introduction of another noise source. Furthermore, the reduced signal swing from the source may lead to improved distortion performance. The differential input configuration provides a noticeable advantage of achieving good SFDR over a wide range of input frequencies. In this mode, both inputs of the ADS807 see matched impedances. Figure 1 shows the schematic for the suggested transformer coupled interface circuit. The component values of the R-C low-pass may be optimized depending on the desired roll-off frequency. The resistor across the secondary side (RT) should be calculated using the equation RT = n2 • RG to match the source impedance (RG) for good power transfer and VSWR. The circuit example of Figure 1 shows the voltage-feedback amplifier OPA680 driving the RF transformer, which converts the single-ended signal into a differential one. The OPA680 can be employed for either single- or dual-supply operation. For details on how to optimize its frequency response, refer to the OPA680 data sheet (SBOS083), available at www.ti.com. With the 49.9Ω series output resistor, the amplifier emulates a 50Ω source (RG). Any DC content of the signal can be easily blocked by a capacitor (0.1µF) and to also to avoid DC loading of the op amp’s output stage. AC-Coupled, Single-Ended-to-Differential Interface with Dual-Supply Op Amps Communications applications, in particular, demand a very high dynamic range and low levels of intermodulation distortion, but usually allow the input signal to be AC-coupled into the A/D converter. Appropriate driver amplifiers need to be selected to maintain the excellent distortion performance of the ADS807. Often, these op amps deliver the lowest distortion with a small, ground-centered signal swing that requires dual power supplies. Because of the AC-coupling, this requirement can be easily accomplished and the needed level shifting of the input signal can be implemented without affecting the driver circuit. See Figure 2 for an example of such an interface circuit specifically designed to maximize the dynamic performance. The voltage feedback amplifier, OPA642, maintains an excellent distortion performance for input frequencies of up to 15MHz. The two amplifiers (A1, A2) are configured as an inverting and noninverting gain stage to convert the input signal from single-ended to differential. The nominal gain for this stage is set to +2V/V. The outputs of the OPA642s are AC-coupled to the converter’s differential inputs. This will keep the distortion performance at its best since the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. Four resistors located between the top (REFT) and bottom (REFB) reference shift the input signal to a common-mode voltage of approximately +2.5V. The interface circuit of Figure 2 can be modified to extend the bandwidth to approximately 25MHz by replacing the OPA642 with its decompensated version, the OPA643. The OPA643 provides the necessary slew rate for a low distortion front end to the ADS807. With a minimum gain stability of +3, the gain resistors have to be modified, as well as optimizing the series resistor and shunt capacitance at each of the converter inputs. RG VIN 49.9Ω 0.1µF 1:n 24.9Ω IN OPA680 47pF R1 ADS807E RT 24.9Ω R2 IN CM +2.5V 47pF + 10µF 0.1µF FIGURE 1. Converting a Single-Ended Input Signal into a Differential Signal Using a RF-Transformer. 10 ADS807 www.ti.com SBAS072A 402Ω 200Ω VIN A1 OPA642 1.82kΩ 0.1µF 16.5Ω 1.82kΩ REFT IN 100pF 402Ω ADS807E 402Ω A2 OPA642 0.1µF 16.5Ω IN 100pF 1.82kΩ REFB 1.82kΩ FIGURE 2. AC-Coupled Differential Driver Interface with OPA642. RF 499Ω 0.1µF RIN 249Ω RS 24.9Ω VIN A1 IN RP 499Ω 499Ω 68pF VCM = +2.5V ADS807E CM 0.1µF +5V RS 24.9Ω A2 OPA2681 IN 68pF RF 499Ω RG 499Ω RP 499Ω 0.1µF FIGURE 3. AC-Coupled, Differential Interface for Single-Supply Operation. AC-Coupled, Single-Ended-to-Differential Interface for Single-Supply Operation The previously discussed interface circuit can be modified if the system only allows for a single-supply operation, e.g., VS = +5V. Single-supply operation requires the driver amplifier to be biased as well in order to process a bipolar input signal. Typically, single-supply amplifiers do not achieve distortion performance as well as dual-supply op amps. The driver amplifier’s output swing must exceed the full-scale input range of the converter. In addition, dual op amps, such as the current-feedback OPA2681, should be considered since they provide the closest open-loop gain and phase matching between the two channels. Shown in Figure 3 is a single-supply interface circuit for an AC-coupled input signal. With the ADS807 set to the 2Vp-p input range, the top and bottom references (REFT, REFB) provide an output voltage of +3.0V and +2.0V, respectively. The CM output of the ADS807 is used to bias the inputs of the driving amplifiers. Using the OPA2681 on a single +5V supply, its ideal common-mode point is +2.5V, which coincides with the recom- mended common-mode input level for the ADS807, thus obviating the need for coupling capacitors between the amplifiers and the converter. The addition of a small series resistor (RS) between the output of the op amps and the input of the ADS807 will be beneficial in almost all interface configurations. It will decouple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100Ω. Furthermore, the series resistor in combination with the shunt capacitor, establishes a passive low-pass filter limiting the bandwidth for the wideband noise, thus improving the SNR. The spurious-free dynamic range of this single-supply front end is limited by the 2nd-harmonic distortion. An improvement of several dB may be realized by adding a pull-down resistor (RP) at the output of each amplifier. This pulls a DC bias current out of the output stage of the amplifier. It is set to approximately 5mA in Figure 3, but will vary depending on the amplifier used. ADS807 SBAS072A www.ti.com 11 Single-Ended, AC-Coupled, Dual-Supply Interface DC-Coupled, Differential Driver with Level Shift The circuit provided in Figure 4 shows typical connections for using the ADS807 in a single-ended input configuration. The bias requirements for AC-coupling are provided by a single resistor to the CM output lead. The single-ended mode of operation should be considered for ease of interface complexity and applications where the dynamic performance can be compromised. The series resistor RS, along with the shunt capacitance, provide the means to adjust the bandwidth and optimize the performance towards good signal-to-noise ratio. In addition, the amplifier configuration can be easily modified for an anti-aliasing filter based on a 2nd-order Sallen-Key or Multiple-Feedback topology. Several applications will require that the bandwidth of the signal path include DC, in which case, the signal has to be DC-coupled to the A/D converter. An op amp based interface circuit can be configured to scale and level shift the input signal to be compatible with the selected input range of the A/D converter. The circuit shown in Figure 5 employs a dual op amp, OPA2681, to drive the input of the ADS807 differentially. The single-supply, general-purpose op amp OPA234 is added to buffer the common-mode voltage of +2.5V, available at the CM pin, and apply it to the input of the driver amplifier. This sets the correct DC voltage to bias the inputs of the ADS807. It should be noted that any DC voltage differences between the IN and IN inputs of the ADS807 will result in an offset error. The interface example shown in Figure 4 operates with the full-scale range of the ADS807 set to 2Vp-p, leaving sufficient headroom for the output of the OPA642 to drive the converter and maintain low signal distortion. Using the OPA2681, this circuit can be operated either with a single or a dual ±5V supply. +5V RS 16.5Ω VIN 0.1µF IN OPA642 68pF –5V ADS807E RF 402Ω 1.82kΩ CM IN 0.1µF RG 402Ω FIGURE 4. AC-Coupling the Dual-Supply Amplifier OPA642 to the ADS807 for a 2Vp-p Full-Scale Input Range. 499Ω 249Ω 24.9Ω VIN IN OPA2681 22pF 499Ω 249Ω ADS807E 499Ω IN 249Ω 24.9Ω CM 22pF 499Ω 24.9Ω OPA234 249Ω 0.1µF 0.1µF 0.1µF 1kΩ FIGURE 5. DC-Coupled Input Driver with Level Shifting. 12 ADS807 www.ti.com SBAS072A REFERENCE OPERATION USING EXTERNAL REFERENCES The internal reference consists of a bandgap voltage reference, the drivers for the top and bottom reference, and the resistive reference ladder. The bandgap reference circuit includes logic functions that allow setting the analog input swing of the ADS807 to a differential full-scale range of either 2Vp-p or 3Vp-p by simply tying the FSSEL pin to a LOW or HIGH potential, respectively. While operating the ADS807 in the external reference mode, the buffer amplifiers for the REFT and REFB are disabled. The ADS807 has an internal 50kΩ pull-down resistor at the range select pin (RSEL). Therefore, this pin can be either hardwired to ground or left unconnected, which will default the converter to a 2Vp-p fullscale input range (FSR). While set for the 2Vp-p range, the top and bottom reference voltages will be REFT = +3.0V and REFB = +2.0V. Switching to the 3Vp-p range changes those voltages to REFT = +3.25V and REFB = +1.75V. The reference buffers can be utilized to supply up to 1mA (sink and source) to external circuitry. To ensure proper operation with any reference configuration, it is necessary to provide solid bypassing at all reference pins in order to keep the clock feedthrough to a minimum, as shown in Figure 6. Good performance requires using 0.1µF low inductance capacitors. All bypassing capacitors should be located as close to their respective pins as possible. For even more design flexibility, the internal reference can be disabled and an external reference voltage used. The utilization of an external reference may be considered for applications requiring higher accuracy, improved temperature performance, or a wide adjustment range of the converter’s full-scale range. In multichannel applications, the use of a common external reference has the benefit of obtaining better matching and drift of the full-scale range between converters. Figure 7 gives an example of an external reference circuit using a single-supply, low-power, dual op amp (OPA2234). (1) CM REFB (1) + 0.1µF 10µF (1) + + 0.1µF 10µF The logic level applied to the INT/EXT pin of the ADS807 determines if the converter operates with either the built-in reference or external reference voltages. Because this function pin has an internal 50kΩ pull-up resistor, the default configuration is external reference mode. Grounding this pin will activate the internal reference option. The input track-and-hold amplifier is differential. A positive 1Vp-p on the IN and its compliment, a negative 1Vp-p, on the IN (see Figure 3) results in 2Vp-p on the output of the track-and-hold. Likewise, 2Vp-p on the IN and 0Vp-p on the IN (see Figure 4) results in 2Vp-p on the output of the track-and-hold. Therefore, the reference voltages, REFT and REFB, are the same for both differential and single-ended inputs, see Table I. ADS807 REFT The external references can vary as long as the value of the external top reference (REFT EXT) stays within the range of VS – 1.70V and REFB + 0.4V, and the external bottom reference (REFB EXT) stays within 1.70V and REFT – 0.4V. Note that the function of the range selector pin (FSSEL) is disabled while the converter operates in external reference mode. Setting the ADS807 for external reference mode requires the INT/EXT pin (pin 18) to be HIGH. 0.1µF 10µF NOTE: (1) Optional. FIGURE 6. Recommended Bypassing for the Reference Pins. The external references may be changed for different tasks. The ADS807 will follow the external references with a latency of 8 to 10 clock cycles. If it is desired to use INT/EXT and FSSEL to change the configuration of a circuit for different tasks, a large amount of time must be allowed. This time could be hundreds of microseconds. Refer to the diagram on the front page. Note that there is no disconnect for external references. +5V +5V OPA2234 A1 4.7kΩ < 3.30V Top Reference R3 R4 R1 REF1004 +2.5V + 10µF R2 0.1µF OPA2234 A2 > 1.70V Bottom Reference FIGURE 7. Example for an External Reference Driver Using the Dual, Single-Supply Op Amp, OPA2234. ADS807 SBAS072A www.ti.com 13 INPUT REFERENCE IN (Pin-25) IN (Pin-24) 2Vp-p Differential 1Vp-p Times 2 Inputs Internal or External 2V to 3V 3V to 2V REFT REFB +3V +2V 2Vp-p Single-Ended 2Vp-p Times 1 Input Internal or External 1.5V to 3.5V 2.5VDC +3V +2V 3Vp-p Differential 1.5Vp-p Times 2 Inputs Internal or External 3Vp-p Single-Ended 3Vp-p Times 1 Input Internal or External 1.75V to 3.35V 3.25V to 1.75V +3.25V +1.75V 1V to 4V 2.5VDC SINGLE-ENDED INPUT (IN = CM, Pin-23) STRAIGHT OFFSET BINARY (SOB) +FS – 1LSB (IN = CMV + FSR/2) 1111 1111 1111 +1/2 FS 1100 0000 0000 Bipolar Zero (IN = VCM) 1000 0000 0000 –1/2 FS 0100 0000 0000 –FS (IN = CMV – FSR/2) 0000 0000 0000 +3.25V +1.75V TABLE II. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage. TABLE I. Reference Voltages for Input Signal Ranges. If it is desired to switch between internal and external references, disconnect switches must be added between the external references and the ADS807. DIGITAL INPUTS AND OUTPUTS Clock Input Requirements Clock jitter is critical to the SNR performance of high-speed, high-resolution A/D converters. Clock jitter leads to aperture jitter (tA), which adds noise to the signal being converted. The ADS807 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by the following equation. If this value is near your system requirements, input clock jitter must be reduced. Jitter SNR = 20 log 1 rms signal to rms noise 2π ƒ IN t A where: ƒIN is input signal frequency tA is rms clock jitter STRAIGHT OFFSET BINARY (SOB) +FS – 1LSB (IN = +3V, IN = +2V) 1111 1111 1111 +1/2 FS 1100 0000 0000 Bipolar Zero (IN = IN = VCM) 1000 0000 0000 –1/2 FS 0100 0000 0000 –FS (IN = +2V, IN = +3V) 0000 0000 0000 TABLE III. Coding Table for Single-Ended Input Configuration with IN Tied to the Common-Mode Voltage. loading will cause larger dynamic currents as the digital outputs are changing. Those high current surges can feed back to the analog portion of the ADS807 and affect the performance. If necessary, external buffers or latches close to the converter’s output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS807 from high-frequency digital noise on the bus coupling back into the converter. Digital Output Driver Supply (VDRV) Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have 50% duty cycle (tH = tL), along with fast rise and fall times of 2ns or less. Over-Range Indicator (OTR) If the analog input voltage exceeds the set full-scale range, an over-range condition exists. The ‘OTR’ pin of the ADS807 can be used to monitor any such out-of-range condition. This ‘OTR’ output is updated along with the data output corresponding to the particular sampled analog input voltage. Therefore, the OTR data is subject to the same pipeline delay as the digital data. The OTR output is LOW when the input voltage is within the defined input range. It will go to HIGH if the applied signal exceeds the full-scale range. Data Outputs The output data format of the ADS807 is in positive Straight Offset Binary code, as shown in Table II and Table III. This format can easily be converted into the Binary Two’s Complement code by inverting the MSB. It is recommended that the capacitive loading on the data lines be as low as possible (< 15pF). Higher capacitive 14 DIFFERENTIAL INPUT The ADS807 features a dedicated supply pin for the output logic drivers, VDRV, which is not internally connected to the other supply pins. Setting the voltage at VDRV to +5V or +3V, the ADS807 produces corresponding logic levels and can directly interface to the selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS807 with +3V logic supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line which may affect the AC performance of the converter. In some applications, it might be advantageous to decouple the VDRV pin with additional capacitors or a pi-filter. GROUNDING AND DECOUPLING Proper grounding, bypassing, short trace lengths, and the use of power and ground planes are particularly important for high-frequency designs. Multilayer PC boards are recommended for best performance since they offer distinct advantages such as minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS807 should be treated as an analog component. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable ADS807 www.ti.com SBAS072A performance. All ground connections on the ADS807 are internally joined together eliminating the need for split ground planes. The ground pins (1, 20, 26) should directly connect to an analog ground plane which covers the PC board area under the converter. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog signal path. Because of the its high sampling rate, the ADS807 generates high frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. This requires that all supply and reference pins are sufficiently bypassed. Figure 8 shows the recommended decoupling scheme for the ADS807. In most cases, 0.1µF ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as possible. If system supplies are not a low enough impedance, adding a small tantalum capacitor will yield the best results. ADS807 +VS 1, 20 +VS GND 15 0.1µF 0.1µF VDRV 26 28 0.1µF 10µF(1) + NOTE: (1) Optional. +5V +3V/+5V FIGURE 8. Recommended Bypassing for the Supply Pins. ADS807 SBAS072A GND 27 www.ti.com 15 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADS807E ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS807E ADS807E/1K ACTIVE SSOP DB 28 1000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS807E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of