VBL1203M
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Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Fast Switching
• Ease of Paralleling
• Simple Drive Requirements
• Compliant to RoHS Directive 2002/95/EC
200
RDS(on) ()
VGS = 10 V
0.30
Qg (Max.) (nC)
43
Qgs (nC)
7.0
Qgd (nC)
23
Single
Configuration
D
D2PAK (TO-263)
K
G
D
S
G
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
SYMBOL
LIMIT
Drain-Source Voltage
PARAMETER
VDS
200
Gate-Source Voltage
VGS
± 20
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
IDM
UNIT
V
10
6.7
A
36
Linear Derating Factor
0.59
Linear Derating Factor (PCB Mount)e
0.025
W/°C
Single Pulse Avalanche Energyb
EAS
250
mJ
Repetitive Avalanche Currenta
IAR
9.0
A
EAR
7.4
mJ
Repetitive Avalanche
Energya
Maximum Power Dissipation
TC = 25 °C
Maximum Power Dissipation (PCB Mount)e
TA = 25 °C
PD
74
3.0
W
* Pb containing terminations are not RoHS compliant, exemptions may apply
Peak Diode Recovery dV/dtc
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dV/dt
5.0
V/ns
1
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ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
TJ, Tstg
- 55 to + 150
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
UNIT
°C
300d
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 4.6 mH, Rg = 25 , IAS = 9.0 A (see fig. 12).
c. ISD 9.0 A, dI/dt 120 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
.
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
(PCB Mount)c
RthJA
-
-
40
Maximum Junction-to-Ambient
RthJA
-
-
62
Maximum Junction-to-Case (Drain)
RthJC
-
-
1.7
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
VDS
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VGS = 0, ID = 250 μA
200
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.24
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 200 V, VGS = 0 V
-
-
25
VDS = 160V, VGS = 0 V, TJ = 125 °C
-
-
250
-
0.30
-
3.8
-
-
S
-
800
-
-
240
-
-
76
-
-
-
43
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 5.4 Ab
VGS = 10 V
VDS = 50 V, ID = 5.4
Ab
μA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 10 V
ID = 5.9 A, VDS = 160 V
see fig. 6 and 13b
VDD = 100 V, ID = 5.9 A
Rg = 12 , RD= 16
see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
-
-
7.0
-
-
23
-
9.4
-
-
28
-
-
39
-
-
20
-
-
4.5
-
-
7.5
-
pF
nC
ns
nH
G
S
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SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
-
-
9.0
UNIT
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward
IS
Currenta
ISM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
-
-
36
VSD
TJ = 25 °C, IS = 9.0 A, VGS = 0 Vb
-
-
2.0
V
Body Diode Reverse Recovery Time
trr
-
170
340
ns
Body Diode Reverse Recovery Charge
Qrr
TJ = 25 °C, IF = 5.9 A,
dI/dt = 100 A/μsb
-
1.1
2.2
μC
Forward Turn-On Time
ton
Body Diode Voltage
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
c. When mounted on 1" square PCB (FR-4 or G-10 material).
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
101
100
4.5 V
91032_01
101
100
Fig. 1 - Typical Output Characteristics, TC = 25 °C
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10-1
10-1
101
VDS, Drain-to-Source Voltage (V)
4.5 V
100
20 µs Pulse Width
TC = 25 °C
10-1
10-1
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
Top
ID, Drain Current (A)
ID, Drain Current (A)
Top
91032_02
20 µs Pulse Width
TC = 150 °C
100
101
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C
3
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1600
Capacitance (pF)
ID, Drain Current (A)
101
150 °C
25 °C
100
1200
Ciss
800
Coss
400
4
5
6
7
8
9
0
100
10
VGS, Gate-to-Source Voltage (V)
91032_03
Crss
20 µs Pulse Width
VDS = 50 V
10-1
2.5
20
ID = 5.9 A
VGS = 10 V
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20 0
91032_04
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
VGS, Gate-to-Source Voltage (V)
RDS(on), Drain-to-Source On Resistance
(Normalized)
3.0
101
VDS, Drain-to-Source Voltage (V)
91032_05
Fig. 3 - Typical Transfer Characteristics
ID = 5.9 A
VDS = 160 V
16
VDS = 100 V
VDS = 40 V
12
8
4
For test circuit
see figure 13
0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
4
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
0
91032_06
10
20
30
40
50
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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ISD, Reverse Drain Current (A)
10
ID, Drain Current (A)
101
150 °C
25 °C
100
8
6
4
2
VGS = 0 V
0.5
0.7
0.9
VSD, Source-to-Drain Voltage (V)
91032_07
0
1.5
1.3
1.1
25
50
VGS
5
150
RD
D.U.T.
Rg
Operation in this area limited
by RDS(on)
125
Fig. 9 - Maximum Drain Current vs. Case Temperature
VDS
103
100
TC, Case Temperature (°C)
91032_09
Fig. 7 - Typical Source-Drain Diode Forward Voltage
75
+
- VDD
ID, Drain Current (A)
2
10 V
102
5
10 µs
2
10
100 µs
Fig. 10a - Switching Time Test Circuit
5
1 ms
2
10 ms
1
5
VDS
TC = 25 °C
TJ = 150 °C
Single Pulse
2
0.1
0.1
91032_08
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
2
5
1
2
5
10
2
90 %
5
102
2
5
103
2
5
VDS, Drain-to-Source Voltage (V)
104
10 %
VGS
td(on)
Fig. 8 - Maximum Safe Operating Area
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
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Thermal Response (ZthJC)
10
1
0 − 0.5
0.2
PDM
0.1
0.05
0.1
t1
0.02
0.01
t2
Single Pulse
(Thermal Response)
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5
10-4
10-3
10-2
0.1
1
10
t1, Rectangular Pulse Duration (s)
91032_11
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
Rg
D.U.T.
+
-
IAS
V DD
VDS
10 V
tp
0.01 Ω
IAS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
EAS, Single Pulse Energy (mJ)
600
ID
4.0 A
5.7 A
Bottom 9.0 A
Top
500
400
300
200
100
0
VDD = 50 V
25
91032_12c
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
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Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
0.2 µF
12 V
0.3 µF
QGS
+
QGD
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
Fig. 13a - Basic Gate Charge Waveform
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
+
-
-
Rg
•
•
•
•
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L2
B
A1
L4
Detail “A”
Rotated 90° CW
scale 8:1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
4
E1
Section B - B and C - C
Scale: none
View A - A
MILLIMETERS
INCHES
MIN.
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
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