23A256/23K256
256-Kbit SPI Bus Low-Power Serial SRAM
Device Selection Table
Part Number
VCC Range
Page Size
Temperature Ranges
Packages
23K256
2.7V-3.6V
32 Byte
I, E
P, SN, ST
23A256
1.5V-1.95V
32 Byte
I
P, SN, ST
Features
Description
• Maximum Clock 20 MHz
• Low-Power CMOS Technology:
- Read Current: 3 mA at 1 MHz
- Standby Current: 4 µA maximum at +85°C
• 32,768 x 8-bit Organization
• 32-Byte Page
• HOLD Pin
• Flexible Operating Modes:
- Byte read and write
- Page mode (32-Byte Page)
- Sequential mode
• Sequential Read/Write
• High Reliability
• Temperature Ranges Supported:
- Industrial (I):
-40C to +85C
-40C to +125C
- Extended (E):
The Microchip Technology Inc. 23X256 are 256-Kbit
Serial SRAM devices. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
Note:
23X256 is used in this document as a
generic
part
number
for
the
23A256/23K256 devices.
• Pb-Free and RoHS Compliant, Halogen Free
Packages
• Automotive AEC-Q100 Qualified
• 8-lead PDIP
• 8-lead SOIC
• 8-lead TSSOP
Pin Function Table
Name
Function
Package Types (not to scale)
CS
Chip Select Input
SO
Serial Data Output
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
CS
1
8
VCC
HOLD
Hold Input
SO
2
7
HOLD
VCC
Supply Voltage
NC
3
6
SCK
VSS
4
5
SI
2008-2022 Microchip Technology Inc. and its subsidiaries
PDIP/SOIC/TSSOP
DS20002100G-page 1
23A256/23K256
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................4.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +0.3V
Storage temperature ............................................................................................................................... -65°C to +150°C
Ambient temperature under bias............................................................................................................. -40°C to +125°C
ESD protection on all pins........................................................................................................................................... 2kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
TA = -40°C to +85°C
TA = -40°C to +125°C
DC CHARACTERISTICS
Industrial (I):
Extended (E):
Param.
Symbol
No.
Minimum Typical(1) Maximum Units
Characteristic
Test Conditions
D001
VCC
Supply Voltage
1.5
—
1.95
V
23A256 (I-Temp)
D001
VCC
Supply Voltage
2.7
—
3.6
V
23K256 (I,E-Temp)
D002
VIH
High-Level Input
Voltage
0.7 VCC
—
VCC +0.3
V
D003
VIL
Low-Level Input
Voltage
-0.3
—
0.2xVCC
V
-0.3
—
0.15xVCC
V
23K256 (E-Temp)
D004
VOL
Low-Level Output
Voltage
—
—
0.2
V
IOL = 1 mA
D005
VOH
High-Level Output
Voltage
VCC -0.5
—
—
V
IOH = -400 µA
D006
ILI
Input Leakage
Current
—
—
±0.5
A
CS = VCC, VIN = VSS OR VCC
D007
ILO
Output Leakage
Current
—
—
±0.5
A
CS = VCC, VOUT = VSS OR VCC
—
—
3
mA
FCLK = 1 MHz; SO = O
D008
ICC Read Operating Current
—
—
6
mA
FCLK = 10 MHz; SO = O
—
—
10
mA
FCLK = 20 MHz; SO = O
—
0.2
1
µA
CS = VCC = 1.8V, Inputs tied to
VCC or VSS
—
1
4
µA
CS = VCC = 3.6V, Inputs tied to
VCC or VSS
—
5
10
µA
CS = VCC = 3.6V, Inputs tied to
VCC or VSS @ +125°C
7
pF
VCC = 0V, f = 1 MHz, Ta = +25°C
(Note 1)
—
V
Note 2
D009
ICCS
Standby Current
D010
CINT
Input Capacitance
D011
VDR
RAM Data
Retention Voltage
Note 1:
2:
—
1.2
This parameter is periodically sampled and not 100% tested. Typical measurements taken at room
temperature (+25°C).
This is the limit to which VDD can be lowered without losing RAM data. This parameter is periodically
sampled and not 100% tested.
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 2
23A256/23K256
TABLE 1-2:
AC CHARACTERISTICS
Param.
Symbol
No.
1
2
3
4
5
FCLK
TCSS
TCSH
TCSD
Tsu
TA = -40°C to +85°C
TA = -40°C to +125°C
Industrial (I):
Extended (E):
AC CHARACTERISTICS
Characteristic
Minimum Maximum
Clock Frequency
CS Setup Time
CS Hold Time
CS Disable Time
Data Setup Time
Units
Test Conditions
—
10
MHz
VCC 1.5V (I-Temp)
—
16
MHz
VCC 1.8V (I-Temp)
—
16
MHz
VCC 3.0V (E-Temp)
—
20
MHz
VCC 3.0V (I-Temp)
50
—
ns
VCC 1.5V (I-Temp)
32
—
ns
VCC 1.8V (I-Temp)
32
—
ns
VCC 3.0V (E-Temp)
25
—
ns
VCC 3.0V (I-Temp)
50
—
ns
VCC 1.5V (I-Temp)
50
—
ns
VCC 1.8V (I-Temp)
50
—
ns
VCC 3.0V (E-Temp)
50
—
ns
VCC 3.0V (I-Temp)
50
—
ns
VCC 1.5V (I-Temp)
32
—
ns
VCC 1.8V (I-Temp)
32
—
ns
VCC 3.0V (E-Temp)
25
—
ns
VCC 3.0V (I-Temp)
10
—
ns
VCC 1.5V (I-Temp)
10
—
ns
VCC 1.8V (I-Temp)
10
—
ns
VCC 3.0V (E-Temp)
10
—
ns
VCC 3.0V (I-Temp)
10
—
ns
VCC 1.5V (I-Temp)
10
—
ns
VCC 1.8V (I-Temp)
10
—
ns
VCC 3.0V (E-Temp)
6
THD
Data Hold Time
10
—
ns
VCC 3.0V (I-Temp)
7
TR
CLK Rise Time
—
2
us
Note 1
8
TF
CLK Fall Time
—
2
us
Note 1
50
—
ns
VCC 1.5V (I-Temp)
32
—
ns
VCC 1.8V (I-Temp)
32
—
ns
VCC 3.0V (E-Temp)
25
—
ns
VCC 3.0V (I-Temp)
50
—
ns
VCC 1.5V (I-Temp)
32
—
ns
VCC 1.8V (I-Temp)
32
—
ns
VCC 3.0V (E-Temp)
25
—
ns
VCC 3.0V (I-Temp)
50
—
ns
VCC 1.5V (I-Temp)
32
—
ns
VCC 1.8V (I-Temp)
32
—
ns
VCC 3.0V (E-Temp)
25
—
ns
VCC 3.0V (I-Temp)
9
10
11
Note 1:
THI
TLO
TCLD
Clock High Time
Clock Low Time
Clock Delay Time
This parameter is periodically sampled and not 100% tested.
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 3
23A256/23K256
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Param.
Symbol
No.
Characteristic
12
TV
Output Valid from Clock Low
13
THO
Output Hold Time
14
TDIS
TA = -40°C to +85°C
TA = -40°C to +125°C
Industrial (I):
Extended (E):
AC CHARACTERISTICS
Minimum Maximum
Output Disable Time
Units
—
50
ns
VCC 1.5V (I-Temp)
—
32
ns
VCC 1.8V (I-Temp)
—
32
ns
VCC 3.0V (E-Temp)
—
25
ns
VCC 3.0V (I-Temp)
0
—
ns
Note 1
—
20
ns
VCC 1.5V (I-Temp)
—
20
ns
VCC 1.8V (I-Temp)
—
20
ns
VCC 3.0V (E-Temp)
—
20
ns
VCC 3.0V (I-Temp)
15
THS
HOLD Setup Time
10
—
ns
16
THH
HOLD Hold Time
10
—
ns
17
THZ
HOLD Low to Output High-Z
10
—
ns
18
THV
HOLD High to Output Valid
—
50
ns
Note 1:
Test Conditions
This parameter is periodically sampled and not 100% tested.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform:
Input pulse level
0.1 VCC to 0.9 VCC
Input rise/fall time
5 ns
Operating temperature
CL = 100 pF
-40°C to +125°C
—
Timing Measurement Reference Level:
Input
0.5 VCC
Output
0.5 VCC
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 4
23A256/23K256
FIGURE 1-1:
HOLD TIMING
CS
16
15
16
15
SCK
17
SO
n+2
SI
n+2
n+1
n
17
High-Impedance
n
5
Don’t Care
n+1
n-1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
7
3
8
11
SCK
5
SI
6
MSb in
LSb in
High-Impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
9
3
10
SCK
12
SO
SI
13
MSb out
14
LSb out
Don’t Care
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 5
23A256/23K256
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 23X256 is a 32,768-byte Serial SRAM designed to
interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC® microcontrollers. It
may also interface with microcontrollers that do not
have a built-in SPI port by using discrete I/O lines
programmed properly in firmware to match the SPI
protocol.
The 23X256 contains an 8-bit instruction register. The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 23X256 in ‘HOLD’ mode.
After releasing the HOLD pin, operation will resume
from the point when the HOLD was asserted.
2.2
Modes of Operation
The 23A256/23K256 has three modes of operation that
are selected by setting bits 7 and 6 in the STATUS
register. The modes of operation are Byte, Page and
Burst.
Byte Operation – is selected when bits 7 and 6 in the
STATUS register are set to 00. In this mode, the
read/write operations are limited to only one byte. The
Command followed by the 16-bit address is clocked into
the device and the data to/from the device is transferred
on the next 8 clocks (see Figure 2-1, Figure 2-2).
Page Operation – is selected when bits 7 and 6 in the
STATUS register are set to 10. The 23A256/23K256 has
1024 pages of 32 bytes. In this mode, the read and write
operations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (see Figure 2-3, Figure 2-4).
Sequential Operation – is selected when bits 7 and 6
in the STATUS register are set to 01. Sequential
operation allows the entire array to be written to and
read from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to 0x0000 (see
Figure 2-5, Figure 2-6).
2008-2022 Microchip Technology Inc. and its subsidiaries
2.3
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 23X256 followed
by the 16-bit address, with the first MSb of the address
being a “don’t care” bit. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin.
If operating in Page mode, after the first byte of data is
shifted out, the next memory location on the page can
be read out by continuing to provide clock pulses. This
allows for 32 consecutive address reads. After the 32nd
address read the internal address counter wraps back
to the byte 0 address in that page.
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (7FFFh),
the address counter rolls over to address 0000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS pin
(see Figure 2-1).
2.4
Write Sequence
Prior to any attempt to write data to the 23X256, the
device must be selected by bringing CS low.
Once the device is selected, the Write command can
be started by issuing a WRITE instruction, followed by
the 16-bit address, with the first MSb of the address
being a “don’t care” bit and then the data to be written.
A write is terminated by the CS being brought high.
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 bytes) before data will start to be overwritten.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is
automatically incremented. When the Address Pointer
reaches the highest address (7FFFh), the address
counter rolls over to (0000h). This allows the operation
to continue indefinitely, however, previous data will be
overwritten.
DS20002100G-page 6
23A256/23K256
TABLE 2-1:
INSTRUCTION SET
Instruction Name
Instruction Format
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
RDSR
0000 0101
Read STATUS register
WRSR
0000 0001
Write STATUS register
FIGURE 2-1:
Description
BYTE READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
0
SI
0
0
0
0
16-bit Address
0
1
1 15 14 13 12
2
1
0
Data Out
High-Impedance
7
SO
FIGURE 2-2:
6
5
4
3
2
1
0
BYTE WRITE SEQUENCE
CS
0
1
2
0
0
0
3
4
8
5
6
7
9 10 11
0
1
0 15 14 13 12
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
16-bit Address
Data Byte
2
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 7
23A256/23K256
FIGURE 2-3:
PAGE READ SEQUENCE
CS
0
1
2
0
0
0
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
16-bit Address
0 1
2
1 15 14 13 12
1
0
Page X, Word Y
Page X, Word Y
High-Impedance
SO
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39
SCK
SI
Page X, Word Y+1
7
SO
6
FIGURE 2-4:
5
4
3
2
1
Page X, Word 31
0
7
6
5
4
3
2
Page X, Word 0
1
0
7
6
5
4
3
2
1
0
PAGE WRITE SEQUENCE
CS
0
1
2
0
0
0
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
Page X, Word Y
16-bit Address
0 1
0 15 14 13 12
2
1
0
7
6
5
4
3
2
1
0
Page X, Word Y
CS
32 33 34 35 36 37 38 39
SCK
Page X, Word Y+1
SI
7
6
5
4
3
2
1
Page X, Word 31
0
7
2008-2022 Microchip Technology Inc. and its subsidiaries
6
5
4
3
2
Page X, Word 0
1
0
7
6
5
4
3
2
1
0
DS20002100G-page 8
23A256/23K256
FIGURE 2-5:
SEQUENTIAL READ SEQUENCE
CS
0
1
2
0
0
0
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
16-bit Address
0 1
2
1 15 14 13 12
1
0
Page X, Word Y
7
SO
6
5
4
3
2
1
0
CS
SCK
SI
Page X, Word 31
SO
7
6
5
4
3
2
Page X+1, Word 0
1
0
7
6
5
4
3
2
1
Page X+1, Word 1
0
7
6
5
4
3
2
1
0
CS
SCK
SI
Page X+1, Word 31
SO
7
6
5
4
3
2
Page X+n, Word 1
1
0
7
6
2008-2022 Microchip Technology Inc. and its subsidiaries
5
4
3
2
Page X+n, Word 31
1
0
7
6
5
4
3
2
1
0
DS20002100G-page 9
23A256/23K256
FIGURE 2-6:
SEQUENTIAL WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0 1
Data Byte 1
2
0 15 14 13 12
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2
SI
7
6
5
4
3
2
Data Byte 3
1
0
7
6
2008-2022 Microchip Technology Inc. and its subsidiaries
5
4
3
2
Data Byte n
1
0
7
6
5
4
3
2
1
0
DS20002100G-page 10
23A256/23K256
2.5
Read Status Register Instruction
(RDSR)
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
0 0 = Byte mode (default operation)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time. The STATUS register is
formatted as follows:
TABLE 2-2:
0 1 = Sequential mode
1 1 = Reserved
Write and read commands are shown in Figure 2-7 and
Figure 2-8.
STATUS REGISTER
7
6
5
4
3
2
1
0
W/R
W/R
–
–
–
–
–
W/R
0
0
0
0
0
HOLD
MODE MODE
Note 1:
1 0 = Page mode
The HOLD bit enables the Hold pin functionality. It must
be set to a ‘0’ before HOLD pin is brought low for HOLD
function to work properly. Setting HOLD to ‘1’ disables
the feature.
W/R = writable/readable.
Bits 1 through 5 are reserved and should always be set
to ‘0’.
See Figure 2-7 for the RDSR timing sequence.
FIGURE 2-7:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
1
0
High-Impedance
SO
2008-2022 Microchip Technology Inc. and its subsidiaries
1
Data from STATUS Register
7
6
5
4
3
2
DS20002100G-page 11
23A256/23K256
2.6
Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the bits in the STATUS register as
shown in Table 2-2. This allows for setting of the Device
operating mode. Several of the bits in the STATUS
register must be cleared to ‘0’. See Figure 2-8 for the
WRSR timing sequence.
FIGURE 2-8:
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS Register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
2.7
Power-On State
The 23X256 powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• A high-to-low-level transition on CS is required to
enter active state
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 12
23A256/23K256
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Name
PIN FUNCTION TABLE
PDIP
SOIC
TSSOP
CS
1
1
1
Chip Select Input
SO
2
2
2
Serial Data Output
VSS
4
4
4
Ground
SI
5
5
5
Serial Data Input
SCK
6
6
6
Serial Clock Input
HOLD
7
7
7
Hold Input
VCC
8
8
8
Supply Voltage
3.1
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
When the device is deselected, SO goes to the
high-impedance state, allowing multiple parts to share
the same SPI bus. After power-up, a low level on CS is
required, prior to any sequence being initiated.
3.2
Serial Output (SO)
The SO pin is used to transfer data out of the 23X256.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
3.3
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
3.4
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a host and the 23X256. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2008-2022 Microchip Technology Inc. and its subsidiaries
3.5
Function
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
23X256 while in the middle of a serial sequence without
having to retransmit the entire sequence again. It must
be held high any time this function is not being used.
Once the device is selected and a serial sequence is
underway, the HOLD pin may be pulled low to pause
further serial communication without resetting the
serial sequence. The HOLD pin must be brought low
while SCK is low, otherwise the HOLD function will not
be invoked until the next SCK high-to-low transition.
The 23X256 must remain selected during this
sequence. The SI, SCK and SO pins are in a
high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
Hold functionality is disabled by the STATUS register
bit.
DS20002100G-page 13
23A256/23K256
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
8-Lead PDIP
XXXXXXXX
T/XXXNNN
YYWW
Example
23K256
I/P e3 13F
2206
8-Lead SOIC (3.90 mm)
Example
XXXXXXXT
XXXXYYWW
NNN
23K256I
SN e3 2206
13F
8-Lead TSSOP
Example
XXXX
TYWW
NNN
Legend: XX...X
T
Y
YY
WW
NNN
e3
K256
I206
13F
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 14
23A256/23K256
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
C
A2
A
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 15
23A256/23K256
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(NOTE 5)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
Number of Pins
N
e
Pitch
Top to Seating Plane
A
Molded Package Thickness
A2
Base to Seating Plane
A1
Shoulder to Shoulder Width
E
Molded Package Width
E1
Overall Length
D
Tip to Seating Plane
L
c
Lead Thickness
b1
Upper Lead Width
b
Lower Lead Width
eB
Overall Row Spacing
§
MIN
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
INCHES
NOM
8
.100 BSC
.130
.310
.250
.365
.130
.010
.060
.018
-
MAX
.210
.195
.325
.280
.400
.150
.015
.070
.022
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
5. Lead design above seating plane may vary, based on assembly vendor.
Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 16
23A256/23K256
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
NOTE 1
2
1
e
NX b
0.25
B
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
4X ș1
ș2
h
R1
h
R
H
L
SEE VIEW C
VIEW A–A
c
ș
(L1)
4X ș1
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev H Sheet 1 of 2
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 17
23A256/23K256
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
c
Lead Thickness
b
Lead Width
Lead Bend Radius
R
Lead Bend Radius
R1
Foot Angle
ș
Mold Draft Angle
ș1
Lead Angle
ș2
MIN
–
1.25
0.10
0.25
0.40
0.17
0.31
0.07
0.07
0°
5°
0°
MILLIMETERS
NOM
8
1.27 BSC
–
–
–
6.00 BSC
3.90 BSC
4.90 BSC
–
–
1.04 REF
–
–
–
–
–
–
–
MAX
1.75
0.25
0.50
1.27
0.25
0.51
–
–
8°
15°
8°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev H Sheet 2 of 2
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 18
23A256/23K256
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev H
2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 19
23A256/23K256
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2008-2022 Microchip Technology Inc. and its subsidiaries
DS20002100G-page 20
23A256/23K256
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