25AA040A/25LC040A
4K SPI Bus Serial EEPROM
Device Selection Table
Part Number
VCC Range
Page Size
Temp. Ranges
Packages
25AA040A
1.8-5.5V
16 Bytes
I
P, MS, SN, ST, MN, MC, OT
25LC040A
2.5-5.5V
16 Bytes
I, E
P, MS, SN, ST, MN, MC, OT
Features:
Description:
• Max. Clock 10 MHz
• Low-Power CMOS Technology:
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 5 A at 5.5V
• 512 x 8-Bit Organization
• Write Page mode (up to 16 bytes)
• Sequential Read
• Self-timed Erase and Write Cycles (5 ms max.)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1,000,000 Erase/Write cycles
- Data retention: >200 years
- ESD protection: >4000V
• Temperature Ranges Supported:
- Industrial (I):
-40C to +85C
- Automotive (E):
-40C to +125C
The Microchip Technology Inc. 25XX040A* is a 4 Kbit
Serial Electrically Erasable Programmable Read-Only
Memory (EEPROM). The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
• Pb-Free and RoHS Compliant
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25XX040A is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packages including 8-lead MSOP, 8-lead TSSOP
and rotated TSSOP, 8-lead 2x3 DFN and TDFN, and
6-lead SOT-23.
Package Types (not to scale)
CS
(P, SN)
(ST, MS)
CS
SO
WP
VSS
Pin Function Table
Name
PDIP/SOIC
TSSOP/MSOP
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
1
2
8
7
VCC
HOLD
WP
3
6
SCK
VSS
4
5
SI
DFN/TDFN
SOT-23
Function
Chip Select Input
SO
Serial Data Output
WP
Write-Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
Hold Input
VCC
Supply Voltage
2003-2012 Microchip Technology Inc.
(MC, MN)
(OT)
SCK
1
6
VDD
2
5
CS
CS 1
SO 2
8 VCC
VSS
SI
3
4
SO
WP 3
6 SCK
VSS 4
5 SI
7 HOLD
X-Rotated TSSOP
(X/ST)
HOLD
VCC
CS
SO
1
2
3
4
8
7
6
5
SCK
SI
VSS
WP
*25XX040A is used in this document as a generic part number
for the 25AA040A and the 25LC040A.
DS21827H-page 1
25AA040A/25LC040A
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias ...............................................................................................................-40°C to 125°C
ESD protection on all pins ..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
TA = -40°C to +85°C
TA = -40°C to +125°C
Industrial (I):
Automotive (E):
Min.
Max.
Units
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Test Conditions
D001
VIH1
High-level Input
Voltage
0.7 VCC
VCC +1
V
D002
VIL1
-0.3
0.3 VCC
V
VCC2.7V (Note 1)
D003
VIL2
Low-level Input
Voltage
-0.3
0.2 VCC
V
VCC < 2.7V (Note 1)
D004
VOL
—
0.4
V
IOL = 2.1 mA
D005
VOL
Low-level Output
Voltage
—
0.2
V
IOL = 1.0 mA, VCC = 2.5V
D006
VOH
High-level Output
Voltage
VCC -0.5
—
V
IOH = -400 A
D007
ILI
Input Leakage
Current
—
±1
A
CS = VCC, VIN = VSS or VCC
D008
ILO
Output Leakage
Current
—
±1
A
CS = VCC, VOUT = VSS or VCC
D009
CINT
Internal Capacitance
(all inputs and
outputs)
—
7
pF
TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note 1)
D010
ICC Read
—
5
mA
—
2.5
mA
VCC = 5.5V; FCLK = 10.0 MHz;
SO = Open
VCC = 2.5V; FCLK = 5.0 MHz;
SO = Open
—
—
5
3
mA
mA
VCC = 5.5V
VCC = 2.5V
—
5
A
—
1
A
CS = VCC = 5.5V, Inputs tied to VCC or
VSS, TA = +125°C
CS = VCC = 2.5V, Inputs tied to VCC or
VSS, TA = +85°C
Operating Current
D011
ICC Write
D012
ICCS
Standby Current
Note 1: This parameter is periodically sampled and not 100% tested.
DS21827H-page 2
2003-2012 Microchip Technology Inc.
25AA040A/25LC040A
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Industrial (I):
TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Min.
Max.
Units
Test Conditions
—
—
—
10
5
3
MHz
MHz
MHz
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
1
FCLK
Clock Frequency
2
TCSS
CS Setup Time
50
100
150
—
—
—
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
3
TCSH
CS Hold Time
100
200
250
—
—
—
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
4
TCSD
CS Disable Time
50
—
ns
—
5
Tsu
Data Setup Time
10
20
30
—
—
—
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
6
THD
Data Hold Time
20
40
50
—
—
—
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
7
TR
CLK Rise Time
—
100
ns
(Note 1)
8
TF
CLK Fall Time
—
100
ns
(Note 1)
9
THI
Clock High Time
50
100
150
—
—
—
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
10
TLO
Clock Low Time
50
100
150
—
—
—
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
11
TCLD
Clock Delay Time
50
—
ns
—
12
TCLE
Clock Enable Time
50
—
ns
—
13
TV
Output Valid from Clock
Low
—
—
—
50
100
160
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
14
THO
Output Hold Time
0
—
ns
(Note 1)
15
TDIS
Output Disable Time
—
—
—
40
80
160
ns
ns
ns
4.5V VCC 5.5V (Note 1)
2.5V VCC 4.5V (Note 1)
1.8V VCC 2.5V (Note 1)
16
THS
HOLD Setup Time
20
40
80
—
—
—
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site:
www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
2003-2012 Microchip Technology Inc.
DS21827H-page 3
25AA040A/25LC040A
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Industrial (I):
TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
AC CHARACTERISTICS
Param.
Sym.
No.
Characteristic
Min.
Max.
Units
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Test Conditions
17
THH
HOLD Hold Time
20
40
80
—
—
—
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
18
THZ
HOLD Low to Output
High-Z
30
60
160
—
—
—
ns
ns
ns
4.5V VCC 5.5V (Note 1)
2.5V VCC 4.5V (Note 1)
1.8V VCC 2.5V (Note 1)
19
THV
HOLD High to Output
Valid
30
60
160
—
—
—
ns
ns
ns
4.5V VCC 5.5V
2.5V VCC 4.5V
1.8V VCC 2.5V
20
TWC
Internal Write Cycle Time
(byte or page)
—
5
ms
(Note 3)
21
—
Endurance
1M
—
E/W 25°C, VCC = 5.5V (Note 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site:
www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
VHI
= VCC - 0.2V
VHI = 4.0V
—
(Note 1)
(Note 2)
CL = 100 pF
—
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC 4.0V
2: For VCC 4.0V
DS21827H-page 4
2003-2012 Microchip Technology Inc.
25AA040A/25LC040A
FIGURE 1-1:
HOLD TIMING
CS
17
16
17
16
SCK
18
SO
n+2
SI
n+2
n+1
n
19
High-Impedance
n
5
Don’t Care
n+1
n-1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
7
Mode 1,1
8
3
12
11
SCK Mode 0,0
5
SI
6
MSB in
LSB in
High-Impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 1,1
SCK
Mode 0,0
13
SO
14
MSB out
SI
2003-2012 Microchip Technology Inc.
15
ISB out
Don’t Care
DS21827H-page 5
25AA040A/25LC040A
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 25XX040A is a 512-byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25XX040A contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX040A in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
2.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX040A
followed by a 9-bit address. The MSb (A8) is sent to the
slave during the instruction sequence. See Figure 2-1
for more details.
After the correct READ instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. Data stored in the memory
at the next address can be read sequentially by
continuing to provide clock pulses to the slave. The
internal Address Pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(1FFh), the address counter rolls over to address 000h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin
(Figure 2-1).
2.3
Write Sequence
Prior to any attempt to write data to the 25XX040A, the
write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX040A. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch.
DS21827H-page 6
If the write operation is initiated immediately after the
WREN instruction without CS driven high, data will not
be written to the array since the write enable latch was
not properly set.
After setting the write enable latch, the user may
proceed by driving CS low, issuing a WRITE instruction,
followed by the remainder of the address, and then the
data to be written. Keep in mind that the Most
Significant address bit (A8) is included in the instruction
byte for the 25XX040A. Up to 16 bytes of data can be
sent to the device before a write cycle is necessary.
The only restriction is that all of the bytes must reside
in the same page. Additionally, a page address begins
with ‘XXXX 0000’ and ends with ‘XXXX 1111’. If the
internal address counter reaches ‘XXXX 1111’ and
clock signals continue to be applied to the chip, the
address counter will roll back to the first address of the
page and over-write any data that previously existed in
those locations.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 2-2 and Figure 2-3 for more
detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the write
is in progress, the STATUS register may be read to
check the status of the WPEN, WIP, WEL, BP1 and
BP0 bits (Figure 2-6). Attempting to read a memory
array location will not be possible during a write cycle.
Polling the WIP bit in the STATUS register is recommended in order to determine if a write cycle is in progress. When the write cycle is completed, the write
enable latch is reset.
2003-2012 Microchip Technology Inc.
25AA040A/25LC040A
BLOCK DIAGRAM
STATUS
Register
HV Generator
Memory
Control
Logic
I/O Control
Logic
EEPROM
Array
X
Dec
Page Latches
SI
SO
Y Decoder
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
TABLE 2-1:
INSTRUCTION SET
Instruction Name
Instruction Format
READ
0000 A8011
Read data from memory array beginning at selected address
WRITE
0000 A8010
Write data to memory array beginning at selected address
WRDI
0000 x100
Reset the write enable latch (disable write operations)
WREN
0000 x110
Set the write enable latch (enable write operations)
RDSR
0000 x101
Read STATUS register
0000 x001
Write STATUS register
WRSR
Note:
A8 is the
9th
Description
address bit, which is used to address the entire 512 byte array.
x = don’t care.
FIGURE 2-1:
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction+Address MSb
SI
0
0
0
0
A8 0
1
Lower Address Byte
1 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High-Impedance
SO
2003-2012 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS21827H-page 7
25AA040A/25LC040A
FIGURE 2-2:
BYTE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
8
Twc
SCK
Lower Address Byte
Instruction+Address MSb
0
SI
0
0
0
Data Byte
0 A7 A6 A5 A4 A3 A2 A1 A0 7
A8 0 1
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 2-3:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Lower Address Byte
Instruction+Address MSb
SI
0
0
0
0
A8 0 1
Data Byte 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
7
DS21827H-page 8
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n (16 max.)
1
0
7
6
5
4
3
2
1
0
2003-2012 Microchip Technology Inc.
25AA040A/25LC040A
2.4
Write Enable (WREN) and Write
Disable (WRDI)
The following is a list of conditions under which the
write enable latch will be reset:
•
•
•
•
•
The 25XX040A contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 2-4:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
WP pin is brought low
WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
1
1
0
High-Impedance
SO
FIGURE 2-5:
0
WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
10
0
High-Impedance
SO
2003-2012 Microchip Technology Inc.
DS21827H-page 9
25AA040A/25LC040A
2.5
Read Status Register Instruction
(RDSR)
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Read Status Register instruction (RDSR) provides
access to the STATUS register. See Figure 2-6 for the
RDSR timing sequence. The STATUS register may be
read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is shown in Figure 2-7. These bits are nonvolatile and
are described in more detail in Table 2-3.
STATUS REGISTER
7
6 5 4
3
2
1
–
– – – W/R W/R
R
X
X X X BP1 BP0 WEL
W/R = writable/readable. R = read-only.
0
R
WIP
The Write-In-Process (WIP) bit indicates whether the
25XX040A is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.
FIGURE 2-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
High-Impedance
SO
DS21827H-page 10
1
0
1
Data from STATUS Register
7
6
5
4
3
2
2003-2012 Microchip Technology Inc.
25AA040A/25LC040A
2.6
Write Status Register Instruction
(WRSR)
TABLE 2-3:
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS register as shown in Table 2-2. See Figure 2-7 for the WRSR
timing sequence. Four levels of protection for the array
are selectable by writing to the appropriate bits in the
STATUS register. The user has the ability to write-protect
none, one, two or all four of the segments of the array as
shown in Table 2-3.
FIGURE 2-7:
ARRAY PROTECTION
BP1
BP0
Array Addresses
Write-Protected
0
0
none
0
1
upper 1/4
(180h-1FFh)
1
0
upper 1/2
(100h-1FFh)
1
1
all
(000h-1FFh)
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS Register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
Note:
An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
2003-2012 Microchip Technology Inc.
DS21827H-page 11
25AA040A/25LC040A
2.7
Data Protection
2.8
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
TABLE 2-4:
Power-On State
The 25XX040A powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
WRITE-PROTECT FUNCTIONALITY MATRIX
WP
(pin 3)
WEL
(SR bit 1)
Protected Blocks
Unprotected Blocks
STATUS Register
0 (low)
x
Protected
Protected
Protected
1 (high)
0
Protected
Protected
Protected
1 (high)
1
Protected
Writable
Writable
x = don’t care
DS21827H-page 12
2003-2012 Microchip Technology Inc.
25AA040A/25LC040A
3.0
PIN DESCRIPTIONS
TABLE 3-1:
The descriptions of the pins are listed in Table 3-1.
PIN FUNCTION TABLE
Name
PDIP
SOIC
MSOP
TSSOP
DFN(1)
TDFN(1)
Rotated
TSSOP
SOT-23
Function
CS
1
1
1
1
1
1
3
5
SO
2
2
2
2
2
2
4
4
Serial Data Output
WP
3
3
3
3
3
3
5
—
Write-Protect Pin
VSS
4
4
4
4
4
4
6
2
Ground
SI
5
5
5
5
5
5
7
3
Serial Data Input
SCK
6
6
6
6
6
6
8
1
Serial Clock Input
HOLD
7
7
7
7
7
7
1
—
Hold Input
8
8
8
8
8
8
2
6
Supply Voltage
VCC
Note 1:
3.1
The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence
being initiated.
3.2
Serial Output (SO)
The SO pin is used to transfer data out of the
25XX040A. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
3.3
Chip Select Input
Write-Protect (WP)
The WP pin is a hardware write-protect input pin.
When it is low, all writes to the array or STATUS
registers are disabled, but any other operations
function normally. When WP is high, all functions,
including nonvolatile writes, operate normally. At any
time, when WP is low, the write enable reset latch will
be reset and programming will be inhibited. However,
if a write cycle is already in progress, WP going low will
not change or disable the write cycle. See Table 2-4 for
the Write-Protect Functionality Matrix.
2003-2012 Microchip Technology Inc.
3.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
3.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX040A. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX040A while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-tolow transition. The 25XX040A must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
DS21827H-page 13
25AA040A/25LC040A
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
8-Lead PDIP
Example:
XXXXXXXX
T/XXXNNN
YYWW
25AA040A
I/P e3 1L7
0627
8-Lead SOIC
Example:
25AA04AI
SN e3 0627
1L7
XXXXXXXT
XXXXYYWW
NNN
Example:
8-Lead TSSOP
XXXX
TYWW
NNN
5A4A
I627
1L7
8-Lead MSOP (150 mil)
Example:
5L4AI
6271L7
XXXXXT
YWWNNN
Part Number
1st Line Marking Codes
TSSOP
25AA040A
25LC040A
Note:
MSOP
Standard
Rotated
5A4A
A4AX
5A4AT
5L4A
L4AX
5L4AT
T = Temperature grade (I, E)
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS21827H-page 14
SOT-23
DFN
TDFN
I Temp.
E Temp.
I Temp
E. Temp
I Temp.
E. Temp
32NN
—
421
—
C21
—
35NN
36NN
424
425
C24
C25
NN = Alphanumeric traceability code
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2003-2012 Microchip Technology Inc.
25AA040A/25LC040A
Package Marking Information (continued)
8-Lead 2X3 DFN
XXX
YWW
NN
8-Lead 2X3 TDFN
XXX
YWW
NN
6-Lead SOT-23
XXNN
2003-2012 Microchip Technology Inc.
Example:
421
627
L7
Example:
C24
627
L7
Example:
32L7
DS21827H-page 15
25AA040A/25LC040A
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