25LC080C/25LC080D/25LC160C/
25LC160D/25LC320A/25LC640A/
25LC128/25LC256
8K-256K SPI Serial EEPROM High Temp Family Data Sheet
Features
• Maximum Clock: 5 MHz
• Low-Power CMOS Technology:
- Write current: 5 mA at 5.5V (maximum)
- Read current: 5 mA at 5.5V, 5 MHz
- Standby current: 10 μA at 5.5V
• 1,024 x 8 through 32,768 x 8-bit Organization
• Byte and Page-Level Write Operations
• Self-Timed Erase and Write Cycles
(6 ms maximum)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential Read
• High Reliability:
- Endurance: >1,000,000 erase/write cycles
- Data retention: >200 years
- ESD protection: >4000V
• Temperature Range Supported:
- Extended (H):
-40°C to +150°C
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
Note 1: 25LCXXX is used in this document as a
generic part number for the 25LC080C/
25LC080D/25LC160C/25LC160D/
25LC320A/25LC640A/25LC128/
25LC256 devices.
Packages
• 8-Lead SOIC
Package Types (not to scale)
8-Lead SOIC
(Top View)
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
• RoHS Compliant
• Automotive AECQ-100 Qualified
Description
Pin Function Table
Name
25LCXXX(1)
Microchip Technology Inc.
devices are
Mid-density 8- through 256-Kbit Serial Electrically
Erasable PROMs (EEPROM). The devices are
organized in blocks of x8-bit memory and support the
Serial Peripheral Interface (SPI) compatible serial bus
architecture. Byte-level and page-level functions are
supported. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
CS
Chip Select Input
SO
Serial Data Output
WP
Write-Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
VCC
2009-2018 Microchip Technology Inc.
Function
Hold Input
Supply Voltage
DS20002131D-page 1
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
DEVICE SELECTION TABLE
Part Number
Density
(bits)
Organization
VCC Range
25LC080C
8K
1,024 x 8
2.5V-5.5V
Max. Speed Page Size
(MHz)
(Bytes)
5
16
Temp.
Range
Package
H
SN
25LC080D
8K
1,024 x 8
2.5V-5.5V
5
32
H
SN
25LC160C
16K
2,048 x 8
2.5V-5.5V
5
16
H
SN
25LC160D
16K
2,048 x 8
2.5V-5.5V
5
32
H
SN
25LC320A
32K
4,096 x 8
2.5V-5.5V
5
32
H
SN
25LC640A
64K
8,192 x 8
2.5V-5.5V
5
32
H
SN
25LC128
128K
16,384 x 8
2.5V-5.5V
5
64
H
SN
25LC256
256K
32,768 x 8
2.5V-5.5V
5
64
H
SN
2009-2018 Microchip Technology Inc.
DS20002131D-page 2
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +155°C
Ambient temperature under bias ......................................................................................................... -40°C to +150°C(1)
ESD protection on all pins..........................................................................................................................................4 kV
Note 1: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which
the total operating time between +125°C and +150°C will be greater than 1,000 hours is not warranted
without prior written approval from Microchip Technology Inc.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Electrical Characteristics:
Extended (H):
TA = -40°C to +150°C
Min.
Max.
Units
D001
VIH1
High-Level Input
Voltage
0.7 VCC
VCC + 1
V
D002
VIL1
Low-Level Input
Voltage
-0.3
0.3VCC
V
D003
VIL2
D004
VOL1
D005
VOL2
D006
VOH
D007
ILI
D008
ILO
D009
CINT
D010
ICC
Read
VCC = 2.5V to 5.5V
Test Conditions
VCC≥2.7V
-0.3
0.2VCC
V
VCC < 2.7V
Low-Level Output
Voltage
—
0.4
V
IOL = 2.1 mA
—
0.2
V
IOL = 1.0 mA
High-Level Output
Voltage
VCC – 0.5
—
V
IOH = -400 μA
Input Leakage Current
—
±2
μA
CS = VCC, VIN = VSS OR VCC
Output Leakage Current
—
±2
μA
CS = VCC, VOUT = VSS OR VCC
Internal Capacitance
(all inputs and outputs)
—
7
pF
TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note 1)
Operating Current
—
5
mA
VCC = 5.5V; FCLK = 5.0 MHz;
SO = Open
—
2.5
mA
VCC = 2.5V; FCLK = 3.0 MHz;
SO = Open
5
mA
VCC = 5.5V
D011
ICC
Write
Operating Current
—
—
3
mA
VCC = 2.5V
D012
ICCS
Standby Current
—
10
μA
CS = VCC = 5.5V,
Inputs tied to VCC or VSS, +150°C
Note 1: This parameter is periodically sampled and not 100% tested.
2009-2018 Microchip Technology Inc.
DS20002131D-page 3
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Electrical Characteristics:
Extended (H):
TA = -40°C to +150°C
Min.
Max.
Units
—
5
MHz
VCC = 2.5V to 5.5V
Test Conditions
1
FCLK
Clock Frequency
—
3
MHz
2.5V ≤ Vcc < 4.5V
2
TCSS
CS Setup Time
100
—
ns
4.5V ≤Vcc ≤ 5.5V
150
—
ns
2.5V ≤Vcc < 4.5V
3
TCSH
CS Hold Time
200
—
ns
4.5V ≤ Vcc ≤ 5.5V
250
—
ns
2.5V ≤ Vcc < 4.5V
4
TCSD
CS Disable Time
50
—
ns
—
5
Tsu
Data Setup Time
20
—
ns
4.5V ≤ Vcc ≤ 5.5V
30
—
ns
2.5V ≤ Vcc < 4.5V
40
—
ns
4.5V ≤ Vcc ≤ 5.5V
50
—
ns
2.5V ≤ Vcc < 4.5V
6
THD
Data Hold Time
4.5V ≤ Vcc ≤ 5.5V
7
TR
CLK Rise Time
—
2
μs
Note 1
8
TF
CLK Fall Time
—
2
μs
Note 1
9
THI
Clock High Time
100
—
ns
4.5V ≤ Vcc ≤ 5.5V
150
—
ns
2.5V ≤ Vcc < 4.5V
100
—
ns
4.5V ≤ Vcc ≤ 5.5V
150
—
ns
2.5V ≤ Vcc < 4.5V
10
TLO
Clock Low Time
11
TCLD
Clock Delay Time
50
—
ns
12
TCLE
Clock Enable Time
50
—
ns
13
TV
Output Valid from Clock
Low
—
100
ns
4.5V ≤ Vcc ≤ 5.5V
—
160
ns
2.5V ≤ Vcc < 4.5V
14
THO
Output Hold Time
0
—
ns
Note 1
15
TDIS
Output Disable Time
—
80
ns
4.5V ≤ Vcc ≤ 5.5V (Note 1)
—
160
ns
2.5V ≤ Vcc < 4.5V (Note 1)
16
THS
HOLD Setup Time
40
—
ns
4.5V ≤ Vcc ≤ 5.5V
80
—
ns
2.5V ≤ Vcc < 4.5V
17
THH
HOLD Hold Time
40
—
ns
4.5V ≤ Vcc ≤ 5.5V
80
—
ns
2.5V ≤ Vcc < 4.5V
18
THZ
HOLD Low to Output
High Z
—
60
ns
4.5V ≤ Vcc ≤ 5.5V (Note 1)
—
160
ns
2.5V ≤ Vcc < 4.5V (Note 1)
19
THV
HOLD High to Output
Valid
—
60
ns
4.5V ≤ Vcc ≤ 5.5V
—
160
ns
2.5V ≤ Vcc < 4.5V
20
TWC
Internal Write Cycle Time
—
6
ms
Note 2
1,000,000
—
21
Endurance
E/W Page mode, 25°C, VCC = 5.5V (Note 3)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our website:
www.microchip.com.
2009-2018 Microchip Technology Inc.
DS20002131D-page 4
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
TABLE 1-3:
AC Waveform
VLO = 0.2V
VH I = VCC – 0.2V
Note 1
VH I = 4.0V
Note 2
CL = 50 pF
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
FIGURE 1-1:
HOLD TIMING
CS
17
16
17
16
SCK
18
SO
n+2
SI
n+2
n+1
n
19
High-Impedance
n
5
Don’t Care
n+1
n-1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
7
Mode 1,1
8
3
12
11
SCK Mode 0,0
5
SI
6
MSB in
SO
2009-2018 Microchip Technology Inc.
LSB in
High-Impedance
DS20002131D-page 5
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 1,1
SCK
Mode 0,0
13
SO
14
MSB out
SI
2009-2018 Microchip Technology Inc.
15
LSB out
Don’t Care
DS20002131D-page 6
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
PIN FUNCTION TABLE
Name
Pin Number
Function
CS
1
Chip Select Input
SO
2
Serial Data Output
WP
3
Write-Protect Pin
VSS
4
Ground
SI
5
Serial Data Input
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
SCK
6
Serial Clock Input
7
Hold Input
2.5
VCC
8
Supply Voltage
The SCK is used to synchronize the communication
between a master and the 25LCXXX. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
Chip Select (CS)
Serial Output (SO)
The SO pin is used to transfer data out of the
25LCXXX. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
2.3
2.4
HOLD
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence
being initiated.
2.2
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25LCXXX in a system with WP pin grounded
and still be able to write to the STATUS register. The
WP pin functions will be enabled when the WPEN bit is
set high.
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the
STATUS register is disabled. All other operations
function normally. When WP is high, all functions,
including writes to the nonvolatile bits in the STATUS
register operate normally. If the WPEN bit is set, WP
low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write
cycle has already begun, WP going low will have no
effect on the write.
2009-2018 Microchip Technology Inc.
2.6
Serial Clock (SCK)
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25LCXXX while in the middle of a serial sequence
without having to retransmit the entire sequence
again. It must be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-tolow transition. The 25LCXXX must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored.
To resume serial communication, HOLD must be
brought high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
DS20002131D-page 7
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
3.0
FUNCTIONAL DESCRIPTION
3.1
Principles of Operation
Block Diagram
STATUS
Register
The 25LCXXX are Mid-Density Serial EEPROMs
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
firmware to match the SPI protocol.
The 25LCXXX contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred Most Significant
bit (MSb) first, Least Significant bit (LSb) last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25LCXXX in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
TABLE 3-1:
WRITE
WRDI
WREN
RDSR
WRSR
Memory
Control
Logic
EEPROM
Array
X
Dec
Page Latches
SI
SO
Y Decoder
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
INSTRUCTION SET
Instruction Name
READ
I/O Control
Logic
HV Generator
Instruction Format
0000
0000
0000
0000
0000
0000
2009-2018 Microchip Technology Inc.
0011
0010
0100
0110
0101
0001
Description
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read STATUS register
Write STATUS register
DS20002131D-page 8
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
3.2
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, and then the data
to be written. Depending upon the density, a page of
data that ranges from 16 bytes to 64 bytes can be sent
to the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25LCXXX
followed by the 16-bit address. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin. The data stored in the memory at the next
address can be read sequentially by continuing to
provide clock pulses. The internal Address Pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
address 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by raising
the CS pin (Figure 3-1).
3.3
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Note:
Write Sequence
Prior to any attempt to write data to the 25LCXXX, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting CS low
and then clocking out the proper instruction into the
25LCXXX. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
FIGURE 3-1:
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
1
1 15 14 13 12
2
1
0
Data Out
High-Impedance
SO
2009-2018 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS20002131D-page 9
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
FIGURE 3-2:
BYTE WRITE SEQUENCE
CS
Twc
0
1
2
3
4
5
6
8
7
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
0 15 14 13 12
1
Data Byte
2
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 3-3:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0 1
0 15 14 13 12
Data Byte 1
2
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2
SI
7
6
5
4
3
2
2009-2018 Microchip Technology Inc.
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n (16/32/64 max)
1
0
7
6
5
4
3
2
1
0
DS20002131D-page 10
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
3.4
The following is a list of conditions under which the
write enable latch will be reset:
Write Enable (WREN) and Write
Disable (WRDI)
•
•
•
•
The 25LCXXX contains a write enable latch. See
Table 5-1 for the write-protect functionality matrix. This
latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 3-4:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
1
1
0
High-Impedance
SO
FIGURE 3-5:
0
WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
10
0
High-Impedance
SO
2009-2018 Microchip Technology Inc.
DS20002131D-page 11
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
3.5
The Write-In-Process (WIP) bit indicates whether the
25LCXXX is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
Read STATUS Register Instruction
(RDSR)
The Read STATUS Register instruction (RDSR)
provides access to the STATUS register. The STATUS
register may be read at any time, even during a write
cycle. The STATUS register is formatted as seen in
Table 3-2.
TABLE 3-2:
7
W/R
WPEN
6
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set
to a ‘1’, the latch allows writes to the array, when set
to a ‘0’, the latch prohibits writes to the array. The state
of this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 3-4 and Figure 3-5.
STATUS REGISTER
3
2
1
0
— — —
5
4
W/R
W/R
R
R
X
BP1
BP0
WEL
WIP
X
X
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 3-3. See
Figure 3-6 for the RDSR timing sequence.
W/R = writable/readable. R = read-only.
FIGURE 3-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
High-Impedance
SO
2009-2018 Microchip Technology Inc.
1
0
1
Data from STATUS Register
7
6
5
4
3
2
DS20002131D-page 12
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
3.6
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature.
Hardware write protection is enabled when WP pin is
low and the WPEN bit is high. Hardware write
protection is disabled when either the WP pin is high or
the WPEN bit is low. When the chip is hardware writeprotected, only writes to nonvolatile bits in the STATUS
register are disabled. See Table 5-1 for a matrix of
functionality on the WPEN bit. See Figure 3-7 for the
WRSR timing sequence.
Write Status Register Instruction
(WRSR)
The Write STATUS Register instruction (WRSR) allows
the user to write to the nonvolatile bits in the STATUS
register as shown in Table 3-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 3-3.
TABLE 3-3:
ARRAY PROTECTION
BP1
BP0
0
0
1
1
0
1
0
1
TABLE 3-4:
Array Addresses
Write-Protected
Array Addresses
Unprotected
None
All
Upper 1/4
Lower 3/4
Upper 1/2
Lower 1/2
All
None
ARRAY PROTECTED ADDRESS LOCATIONS
Density
Upper 1/4
Upper 1/2
All
8K
16K
32K
64K
128K
256K
300h-3FFh
600h-7FFh
C00h-FFFh
1800h-1FFFh
3000h-3FFFh
6000h-7FFFh
200h-3FFh
000h-3FFh
400h-7FFh
000h-7FFh
FIGURE 3-7:
800h-FFFh
000h-FFFh
1000h-1FFFh
0000h-1FFFh
2000h-3FFFh
0000h-3FFFh
4000h-7FFFh
0000h-7FFFh
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS Register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
Note:
An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
2009-2018 Microchip Technology Inc.
DS20002131D-page 13
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
4.0
DATA PROTECTION
5.0
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
TABLE 5-1:
POWER-ON STATE
The 25LCXXX powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
WPEN
(SR bit 7)
WP
(pin 3)
Protected Blocks
Unprotected Blocks
STATUS Register
0
x
x
Protected
Protected
Protected
1
0
x
Protected
Writable
Writable
1
1
0 (low)
Protected
Writable
Protected
1
1
1 (high)
Protected
Writable
Writable
x = don’t care
2009-2018 Microchip Technology Inc.
DS20002131D-page 14
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead SOIC
Example
XXXXXXXT
XXXXYYWW
NNN
25LC32AH
SN e3 1837
13F
1st Line Marking Codes
Part Number
SOIC
Note:
25LC080C
25LC08CT
25LC080D
25LC08DT
25LC160C
25LC16CT
25LC160D
25LC16DT
25LC320A
25LC32AT
25LC640A
25L640AT
25LC128
25LC128T
25LC256
25LC256T
T = Temperature Grade (H).
Legend: XX...X
Y
YY
WW
NNN
e3
*
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
JEDEC designator for Matte Tin (Sn)
This package is RoHS compliant. The JEDEC designator ( e3 )
can be found on the outer packaging for this package.
* Custom marking available.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2018 Microchip Technology Inc.
DS20002131D-page 15
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
2009-2018 Microchip Technology Inc.
DS20002131D-page 16
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
2009-2018 Microchip Technology Inc.
DS20002131D-page 17
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev B
2009-2018 Microchip Technology Inc.
DS20002131D-page 18
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
REVISION HISTORY
Revision A (01/2009)
Initial release of this document.
Revision B (04/2009)
Revised part number from 25XX to 25LCXXX; Added
Note 1 to Electrical Characteristics.
Revision C (06/2009)
Revised Features: Endurance and Package; Revised
Table 1-2, Para. 21.
Revision D (09/2018)
Removed Preliminary status; Minor typographical
corrections.
2009-2018 Microchip Technology Inc.
DS20002131D-page 19
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata, application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the website
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
2009-2018 Microchip Technology Inc.
DS20002131D-page 20
25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/
25LC128/25LC256
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X]
PART NO.
Device
Device:
(1)
Tape and Reel
Option
-X
/XX
Temperature
Range
Package
25LC080C = 8-Kbit SPI Serial EEPROM
25LC080D = 8-Kbit SPI Serial EEPROM
25LC160C = 16-Kbit SPI Serial EEPROM
25LC160D = 16-Kbit SPI Serial EEPROM
25LC320A = 32-Kbit SPI Serial EEPROM
25LC640A = 64-Kbit SPI Serial EEPROM
25LC128 = 128-Kbit SPI Serial EEPROM
25LC256 = 256-Kbit SPI Serial EEPROM
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Temperature
Range:
H
= -40C to +150C (Extended)
Package:
SN
Examples:
a)
b)
c)
d)
e)
f)
g)
= 8-Lead Plastic Small Outline – Narrow, 3.90 mm
Body SOIC
h)
25LC080CT-H/SN = Tape and Reel, Extended
Temp., 16-Byte Page,
2.5V-5.5V, SOIC package.
25LC080D-H/SN = Extended Temp., 32-Byte
Page, 2.5V-5.5V, SOIC
package.
25LC160CT-H/SN = Tape and Reel, Extended
Temp. 16-Byte Page, 2.5V5.5V, SOIC Package.
25LC160D-H/SN = Extended Temp., 32-Byte
Page, 2.5V-5.5V, SOIC
Package.
25LC320AT-H/SN = Tape and Reel, Extended
Temp. 32-Byte Page, 2.5V5.5V, SOIC Package.
25LC640A-H/SN = Extended Temp. 32-Byte
Page, 2.5V-5.5V, SOIC
Package.
25LC128T-H/SN = Tape and Reel, Extended
Temp. 64-Byte Page, 2.5V5.5V, SOIC Package.
25LC256-H/SN = Extended Temp. 64-Byte
Page, 2.5V-5.5V, SOIC
Package.
Note
2009-2018 Microchip Technology Inc.
1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes
and is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
2:
Contact Microchip for Automotive grade
ordering part numbers.
DS20002131D-page 21
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3536-5
2009-2018 Microchip Technology Inc.
DS20002131D-page 22
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Finland - Espoo
Tel: 358-9-4520-820
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
China - Qingdao
Tel: 86-532-8502-7355
Philippines - Manila
Tel: 63-2-634-9065
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Germany - Rosenheim
Tel: 49-8031-354-560
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Israel - Ra’anana
Tel: 972-9-744-7705
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
2009-2018 Microchip Technology Inc.
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
DS20002131D-page 23
08/15/18
工商网监
湘ICP备2023018690号
