APT7F120B

APT7F120B APT7F120S 1200V, 7A, 2.4Ω Max, trr ≤190ns N-Channel FREDFET Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET. This 'FREDFET' version has a drain-source (body) diode that has been optimized for high reliability in ZVS phase shifted bridge and other circuits through reduced trr, soft recovery, and high recovery dv/dt capability. Low gate charge, high gain, and a greatly reduced ratio of Crss/Ciss result in excellent noise immunity and low switching loss. The intrinsic gate resistance and capacitance of the poly-silicon gate structure help control di/dt during switching, resulting in low EMI and reliable paralleling, even when switching at very high frequency. TO -24 7 D 3 PAK APT7F120B APT7F120S D Single die FREDFET G S TYPICAL APPLICATIONS FEATURES • Fast switching with low EMI • ZVS phase shifted and other full bridge • Low trr for high reliability • Half bridge • Ultra low Crss for improved noise immunity • PFC and other boost converter • Low gate charge • Buck converter • Avalanche energy rated • Single and two switch forward • RoHS compliant • Flyback Absolute Maximum Ratings Symbol ID Parameter Unit Ratings Continuous Drain Current @ TC = 25°C 7 Continuous Drain Current @ TC = 100°C 5 A IDM Pulsed Drain Current VGS Gate-Source Voltage ±30 V EAS Single Pulse Avalanche Energy 2 575 mJ IAR Avalanche Current, Repetitive or Non-Repetitive 3 A 1 28 Thermal and Mechanical Characteristics Typ Max Unit W PD Total Power Dissipation @ TC = 25°C 335 RθJC Junction to Case Thermal Resistance 0.37 RθCS Case to Sink Thermal Resistance, Flat, Greased Surface TJ,TSTG Operating and Storage Junction Temperature Range TL Soldering Temperature for 10 Seconds (1.6mm from case) WT Package Weight Torque Mounting Torque ( TO-247 Package), 6-32 or M3 screw Microsemi Website - http://www.microsemi.com 0.11 -55 150 300 °C/W °C 0.22 oz 6.2 g 10 in·lbf 1.1 N·m Rev D 8-2011 Min Characteristic 050-8144 Symbol Static Characteristics TJ = 25°C unless otherwise specified Symbol Parameter Test Conditions Min VBR(DSS) Drain-Source Breakdown Voltage VGS = 0V, ID = 250μA 1200 ∆VBR(DSS)/∆TJ Drain-Source On Resistance VGS(th) Gate-Source Threshold Voltage ∆VGS(th)/∆TJ VGS = 10V, ID = 3A 3 Zero Gate Voltage Drain Current IGSS Gate-Source Leakage Current Dynamic Characteristics VDS = 1200V Forward Transconductance Ciss Input Capacitance Crss Reverse Transfer Capacitance Coss Output Capacitance Typ Max 1.41 1.57 4 -10 2.4 5 TJ = 25°C VGS = 0V 250 1000 ±100 TJ = 125°C VGS = ±30V Unit V V/°C Ω V mV/°C μA nA TJ = 25°C unless otherwise specified Parameter gfs 2.5 VGS = VDS, ID = 1mA Threshold Voltage Temperature Coefficient IDSS Symbol Reference to 25°C, ID = 250μA Breakdown Voltage Temperature Coefficient RDS(on) APT7F120B_S Min Test Conditions VDS = 50V, ID = 3A 4 Effective Output Capacitance, Charge Related Co(er) 5 Effective Output Capacitance, Energy Related Max 8 2565 31 190 VGS = 0V, VDS = 25V f = 1MHz Co(cr) Typ Unit S pF 75 VGS = 0V, VDS = 0V to 800V 38 Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge td(on) Turn-On Delay Time Resistive Switching Current Rise Time VDD = 800V, ID = 3A tr td(off) tf 80 13 37 14 8 45 13 VGS = 0 to 10V, ID = 3A, VDS = 600V RG = 4.7Ω 6 , VGG = 15V Turn-Off Delay Time Current Fall Time nC ns Source-Drain Diode Characteristics Symbol IS ISM VSD Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Reverse Recovery Time Qrr Reverse Recovery Charge Irrm Reverse Recovery Current Peak Recovery dv/dt Min Typ D MOSFET symbol showing the integral reverse p-n junction diode (body diode) Diode Forward Voltage trr dv/dt Test Conditions A 28 S TJ = 25°C 1.0 190 TJ = 125°C 325 TJ = 25°C diSD/dt = 100A/μs TJ = 125°C VDD = 100V TJ = 25°C Unit 7 G ISD = 3A, TJ = 25°C, VGS = 0V ISD = 3A 3 Max TJ = 125°C ISD ≤ 3A, di/dt ≤1000A/μs, VDD = 800V, TJ = 125°C 0.64 1.45 7.5 10.7 V ns μC A 25 V/ns 1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature. 050-8144 Rev D 8-2011 2 Starting at TJ = 25°C, L = 127.78mH, RG = 4.7Ω, IAS = 3A. 3 Pulse test: Pulse Width < 380μs, duty cycle < 2%. 4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of VDS less than V(BR)DSS, use this equation: Co(er) = -1.17E-7/VDS^2 + 1.42E-8/VDS + 2.01E-11. 6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452) Microsemi reserves the right to change, without notice, the specifications and information contained herein. APT7F120B_S 20 V 18 GS 6 = 10V T = 125°C J TJ = -55°C 14 ID, DRIAN CURRENT (A) GS 12 10 8 TJ = 25°C 6 4 5V 3 2 4.5V 1 TJ = 125°C 2 4 TJ = 150°C 0 0 5 10 15 20 25 30 VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V) 0 Figure 2, Output Characteristics 30 NORMALIZED TO VGS = 10V @ 3A 2.5 2.0 1.5 1.0 0 -55 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 3, RDS(ON) vs Junction Temperature 20 TJ = -55°C 15 TJ = 25°C 10 TJ = 125°C 0 0 1 2 3 4 5 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (V) Figure 4, Transfer Characteristics 4,000 Ciss 1,000 8 C, CAPACITANCE (pF) TJ = -55°C TJ = 25°C 6 TJ = 125°C 4 100 Coss 10 2 0 16 1 2 3 ID, DRAIN CURRENT (A) Figure 5, Gain vs Drain Current 200 400 600 800 1000 1200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 6, Capacitance vs Drain-to-Source Voltage 12 VDS = 240V 10 VDS = 600V 8 6 VDS = 960V 4 2 0 0 30 ID = 3A 14 0 1 4 20 40 60 80 100 120 Qg, TOTAL GATE CHARGE (nC) Figure 7, Gate Charge vs Gate-to-Source Voltage 25 20 TJ = 25°C 15 TJ = 150°C 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 VSD, SOURCE-TO-DRAIN VOLTAGE (V) Figure 8, Reverse Drain Current vs Source-to-Drain Voltage Rev D 8-2011 0 Crss ISD, REVERSE DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE 250μSEC. PULSE TEST @ ID(ON) x RDS(ON) MAX. 25 ID, DRAIN CURRENT (A) RDS(ON), DRAIN-TO-SOURCE ON RESISTANCE Figure 1, Output Characteristics 3.0 5 10 15 20 25 30 VDS, DRAIN-TO-SOURCE VOLTAGE (V) 050-8144 ID, DRAIN CURRENT (A) 16 0 = 6, 7, 8 & 9V V 5 APT7F120B_S 40 IDM 10 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 40 13μs 100μs 1 1ms Rds(on) 10ms 0.1 Rds(on) 1 0.1 DC line Scaling for Different Case & Junction Temperatures: ID = ID(T = 25°C)*(TJ - TC)/125 DC line 10 100 1200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 9, Forward Safe Operating Area 13μs 100μs 1ms 10ms 100ms TJ = 150°C TC = 25°C 100ms TJ = 125°C TC = 75°C 1 IDM 10 C 1 10 100 1200 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Figure 10, Maximum Forward Safe Operating Area 0.35 D = 0.9 0.30 0.7 0.25 0.20 0.5 Note: P DM ZθJC, THERMAL IMPEDANCE (°C/W) 0.40 0.15 t1 0.3 t2 0.10 t Duty Factor D = 1 /t2 Peak T J = P DM x Z θJC + T C 0.1 0.05 0 t1 = Pulse Duration SINGLE PULSE 0.05 10-5 10-4 10-3 10-2 10-1 RECTANGULAR PULSE DURATION (seconds) Figure 11. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration D3PAK Package Outline TO-247 (B) Package Outline e3 100% Sn Plated 15.49 (.610) 16.26 (.640) Drai n 6.15 (.242) BSC 5.38 (.212) 6.20 (.244) Drai n (Heat Sink) e1 SAC: Tin, Silver, Copper 4.69 (.185) 5.31 (.209) 1.49 (.059) 2.49 (.098) 1.0 4.98 (.196) 5.08 (.200) 1.47 (.058) 1.57 (.062) 15.95 (.628) 16.05(.632) Revised 4/18/95 20.80 (.819) 21.46 (.845) 1.04 (.041) 1.15(.045) 13.79 (.543) 13.99(.551) 13.41 (.528) 13.51(.532) Revised 8/29/97 11.51 (.453) 11.61 (.457) 3.50 (.138) 3.81 (.150) 050-8144 Rev D 8-2011 0.46 (.018) 0.56 (.022) {3 Plcs} 4.50 (.177) Max. 0.40 (.016) 1.016(.040) 1.65 (.065) 2.13 (.084) 19.81 (.780) 20.32 (.800) 1.01 (.040) 1.40 (.055) 2.21 (.087) 2.59 (.102) 2.87 (.113) 3.12 (.123) 5.45 (.215) BSC 2-Plcs. Dimensions in Millimeters (Inches) Gate Drai n Source 0.020 (.001) 0.178 (.007) 2.67 (.105) 2.84 (.112) 1.27 (.050) 1.40 (.055) 1.22 (.048) 1.32 (.052) 1.98 (.078) 2.08 (.082) 5.45 (.215) BSC {2 Plcs. } Source Drai n Gate Dimensions in Millimeters (Inches) 3.81 (.150) 4.06 (.160) (Base of Lead) Heat Sink (Drain) and Leads are Plated