AT24C01BN-SH-T

Features • Low-voltage and Standard-voltage Operation • • • • • • • • • • • • • – 1.8 (VCC = 1.8V to 5.5V) Internally Organized 128 x 8 (1K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility Write Protect Pin for Hardware Data Protection 8-byte Page (1K) Write Modes Partial Page Writes Allowed Self-timed Write Cycle (5 ms max) High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages Lead-free/Halogen-free Die Sales: Wafer Form and Tape and Reel Description The AT24C01B provides 1024 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01B is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the AT24C01B is available in 1.8V (1.8V to 5.5V) version. Table 0-1. Pin Name A0 - A2 1K (128 x 8) AT24C01B Not Recommended for New Design. Replaced by AT24C01C. Pin Configuration Function Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect GND Ground VCC Power Supply Note: Two-wire Serial EEPROM 8-lead Ultra Thin Mini-MAP (MLP 2x3) VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND 8-ball dBGA2 VCC WP SCL SDA Bottom View 1 2 3 4 8 7 6 5 VCC WP SCL SDA For use of 5-lead SOT23, the soft5-lead SOT23 ware A2, A1, and A0 bits in the WP SCL 1 5 device address word must be set 2 to zero to properly communicate. GND SDA 3 4 1 A0 7 2 A1 6 3 A2 5 4 GND Bottom View 8-lead TSSOP A0 A1 A2 GND 8 VCC 8-lead SOIC A0 A1 A2 GND 1 2 3 4 VCC WP SCL SDA 8 7 6 5 8-lead PDIP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 5156E–SEEPR–10/08 Absolute Maximum Ratings Operating Temperature ................................ –55C to +125C *NOTICE: Storage Temperature.................................... –65C to +150C Voltage on Any Pin with Respect to Ground ....................................–1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Figure 0-1. Block Diagram VCC GND WP START STOP LOGIC SERIAL CONTROL LOGIC LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W EN H.V. PUMP/TIMING COMP LOAD DATA RECOVERY INC DATA WORD ADDR/COUNTER Y DEC X DEC SCL SDA EEPROM SERIAL MUX DOUT/ACK LOGIC DIN DOUT 2 AT24C01B 5156E–SEEPR–10/08 AT24C01B 1. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01B. As many as eight 1K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). WRITE PROTECT (WP): The AT24C01B has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when connected to ground (GND). When the write protect pin is connected to VCC, the write protection feature is enabled and operates as shown in Table 1-1. Table 1-1. Write Protect Part of the Array Protected WP Pin Status 24C01B At VCC Full (1K) Array At GND Normal Read/Write Operations 2. Memory Organization AT24C01B, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K requires an 7-bit data word address for random word addressing. (See Figure 8-2 on page 10) 3 5156E–SEEPR–10/08 Table 2-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V Symbol Test Condition CI/O CIN Note: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. Table 2-2. DC Characteristics Applicable over recommended operating range from: TAI = –40C to +85C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol Parameter VCC1 Supply Voltage VCC2 Max Units 1.8 5.5 V Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 2.7 5.5 V VCC4 Supply Voltage 4.5 5.5 V ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 µA ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 1.4 4.0 µA ISB3 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA ISB4 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA VIL Input Low Level(1) –0.6 VCC x 0.3 V VIH Input High Level (1) VCC x 0.7 VCC + 0.5 V VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V Note: 4 Test Condition Min Typ 1. VIL min and VIH max are reference only and are not tested. AT24C01B 5156E–SEEPR–10/08 AT24C01B Table 2-3. AC Characteristics Applicable over recommended operating range from TAI = –40C to +85C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 1.8, 2.5, 2.7 Min Max 5.0-volt Symbol Parameter Min fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 1.2 0.4 µs tHIGH Clock Pulse Width High 0.6 0.4 µs tI Noise Suppression Time tAA Clock Low to Data Out Valid 0.1 tBUF Time the bus must be free before a new transmission can start 1.2 0.5 µs tHD.STA Start Hold Time 0.6 0.25 µs tSU.STA Start Setup Time 0.6 0.25 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Setup Time 100 100 ns 400 50 (1) 0.9 0.05 Max Units 1000 kHz 40 ns 0.55 µs tR Inputs Rise Time 0.3 0.3 µs tF Inputs Fall Time(1) 300 100 ns tSU.STO Stop Setup Time 0.6 .25 µs tDH Data Out Hold Time 50 50 ns tWR Write Cycle Time Endurance(1) 5.0V, 25C, Byte Mode Note: 5 5 1 Million ms Write Cycles 1. This parameter is ensured by characterization only. 5 5156E–SEEPR–10/08 3. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5-2 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5-3 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5-3 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT24C01B features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations. 2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) Clock 9 cycles, (c) Create another start bit followed by a stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Dummy Clock Cycles Start bit SCL 1 2 3 Start bit 8 Stop bit 9 SDA 6 AT24C01B 5156E–SEEPR–10/08 AT24C01B 4. Bus Timing SCL: Serial Clock, SDA: Serial Data I/O® Figure 4-1. tHIGH tF tR tLOW SCL tSU.STA tLOW tHD.STA tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT 5. Write Cycle Timing Figure 5-1. SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK WORDn twr STOP CONDITION Note: (1) START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 7 5156E–SEEPR–10/08 Figure 5-2. Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE Figure 5-3. Start and Stop Definition SDA SCL START Figure 5-4. STOP Output Acknowledge 1 SCL 8 9 DATA IN DATA OUT START 8 ACKNOWLEDGE AT24C01B 5156E–SEEPR–10/08 AT24C01B 6. Device Addressing The 1K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 8-1). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 1K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. 7. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page 10). PAGE WRITE: The 1K EEPROM is capable of an 8-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 8-3 on page 11). The data word address lower three bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. 9 5156E–SEEPR–10/08 8. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 8-4 on page 11). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-5 on page 11). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-6 on page 12). Figure 8-1. Device Address 1K Figure 8-2. Byte Write * 10 AT24C01B 5156E–SEEPR–10/08 AT24C01B Figure 8-3. Page Write * (* = Don’t Care Bit) Figure 8-4. Current Address Read Figure 8-5. Random Read * (* = Don’t Care Bit) 11 5156E–SEEPR–10/08 Figure 8-6. 12 Sequential Read AT24C01B 5156E–SEEPR–10/08 AT24C01B AT24C01B Ordering Information Ordering Code Package Voltage Range AT24C01B-PU (Bulk form only) 8P3 1.8V to 5.5V AT24C01BN-SH-B(1) (NiPdAu Lead Finish) 8S1 1.8V to 5.5V 8S1 1.8V to 5.5V (NiPdAu Lead Finish) 8A2 1.8V to 5.5V AT24C01B-TH-T(2) (NiPdAu Lead Finish) 8A2 1.8V to 5.5V 8Y6 1.8V to 5.5V 5TS1 1.8V to 5.5V (2) AT24C01BN-SH-T (1) AT24C01B-TH-B (NiPdAu Lead Finish) -T(2) AT24C01BY6-YH (NiPdAu Lead Finish) -T(2) AT24C01B-TSU -T(2) AT24C01BU3-UU 8U3-1 1.8V to 5.5V AT24C01B-W-11(3) Die Sale 1.8V to 5.5V Notes: Operation Range Lead-free/Halogen-free/ Industrial Temperature (–40C to 85C) Industrial Temperature (–40C to 85C) 1. “-B” denotes bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini MAP, SOT 23 and dBGA2 = 5K per reel. 3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Please contact Serial Interface Marketing. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y6 8-lead, 2.0 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 5TS1 5-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23) 8U3-1 8-ball, die Ball Grid Array Package (dBGA2) 13 5156E–SEEPR–10/08 9. Part Marking Scheme 8-PDIP Seal Year TOP MARK | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L U Y W W |---|---|---|---|---|---|---|---| 0 1 B 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) U = Material Set Y = Seal Year WW = Seal Week 01B = Device V = Voltage Indicator *Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 14 AT24C01B 5156E–SEEPR–10/08 AT24C01B 8-SOIC Seal Year TOP MARK | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W |---|---|---|---|---|---|---|---| 0 1 B 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) H = Material Set Y = Seal Year WW = Seal Week 01B = Device 1 = Voltage Indicator *Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 8-TSSOP TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 0 1 B 1 |---|---|---|---|---| H = Material Set Y = Seal Year WW = Seal Week 01B = Device 15 5156E–SEEPR–10/08 1 = Voltage Indicator BOTTOM MARK |---|---|---|---|---|---|---| X X |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| |---|---|---|---|---| 1 B 1 W U |---|---|---|---|---| * | Pin 1 Indicator (Dot) 1B = Device 1 = Voltage Indicator W = Write Protect Feature U = Material Set BOTTOM MARK |---|---|---|---| Y M T C |---|---|---|---| Y = One Digit Year Code M = Seal Month TC = Trace Code 16 AT24C01B 5156E–SEEPR–10/08 AT24C01B ULTRA THIN MINI MAP TOP MARK |---|---|---| 0 1 B |---|---|---| H 1 |---|---|---| Y T C |---|---|---| * | Pin 1 Indicator (Dot) 01B = Device H = Material Set 1 = Voltage Indicator Y = Year of Assembly TC = Trace Code dBGA2 TOP MARK LINE 1-------> LINE 2-------> 01BU YMTC |