AT28LV010-20JU-319

Features • Single 3.3V ± 10% Supply • Fast Read Access Time – 200 ns • Automatic Page Write Operation • • • • • • • • – Internal Address and Data Latches for 128 Bytes – Internal Control Timer Fast Write Cycle Time – Page Write Cycle Time – 10 ms Maximum – 1 to 128-Byte Page Write Operation Low Power Dissipation – 15 mA Active Current – 20 µA CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 105 Cycles – Data Retention: 10 Years JEDEC Approved Byte-Wide Pinout Industrial Temperature Range Green (Pb/Halide-free) Packaging Option Only 1-Megabit (128K x 8) Low Voltage Paged Parallel EEPROMs AT28LV010 1. Description The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Programmable Read-Only Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA. The AT28LV010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s 28LV010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. Software data protection is implemented to guard against inadvertent writes. The device also includes an extra 128 bytes of EEPROM for device identification or tracking. 0395F–PEEPR–08/09 AT28LV010 2. Pin Configurations 2.2 Function A0 - A16 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect 2.1 32-lead PLCC Top View A11 A9 A8 A13 A14 NC WE VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 4 3 2 1 32 31 30 A12 A15 A16 DC VCC WE NC Pin Name 32-lead TSOP Top View 2 0395F–PEEPR–08/09 AT28LV010 3. Block Diagram 4. Device Operation 4.1 Read The AT28LV010 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. 4.2 Write The write operation of the AT28LV010 allows 1 to 128 bytes of data to be written into the device during a single internal programming period. Each write operation must be preceded by the software data protection (SDP) command sequence. This sequence is a series of three unique write command operations that enable the internal write circuitry. The command sequence and the data to be written must conform to the software protected write cycle timing. Addresses are latched on the falling edge of WE or CE, whichever occurs last and data is latched on the rising edge of WE or CE, whichever occurs first. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28LV010 will cease accepting data and commence the internal programming operation. If more than one data byte is to be written during a single programming operation, they must reside on the same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition during the page write operation, A7 - A16 must be the same. The A0 to A6 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 3 0395F–PEEPR–08/09 4.3 DATA Polling The AT28LV010 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. 4.4 Toggle Bit In addition to DATA Polling the AT28LV010 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. 4.5 Data Protection If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel® has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.5.1 Hardware Protection Hardware features protect against inadvertent writes to the AT28LV010 in the following ways: (a) VCC power-on delay – once VCC has reached 2.0V (typical) the device will automatically time out 5 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. 4.5.2 Software Data Protection The AT28LV010 incorporates the industry standard software data protection (SDP) function. Unlike standard 5-volt only EEPROM’s, the AT28LV010 has SDP enabled at all times. Therefore, all write operations must be preceded by the SDP command sequence. The data in the 3-byte command sequence is not written to the device; the addresses in the command sequence can be utilized just like any other location in the device. Any attempt to write to the device without the 3-byte sequence will start the internal timers. No data will be written to the device. However, for the duration of tWC, read operations will effectively be polling operations. 4 AT28LV010 0395F–PEEPR–08/09 AT28LV010 5. DC and AC Operating Range Operating Temperature (Case) AT28LV010-20 AT28LV010-25 -40°C - 85°C -40°C - 85°C 3.3V ± 5% 3.3V ± 10% Ind. VCC Power Supply 6. Operating Modes Mode CE OE WE I/O Read VIL VIL VIH DOUT Write(2) VIL VIH VIL DIN High Z Standby/Write Inhibit (1) VIH X X Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X Notes: High Z 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 7. Absolute Maximum Ratings* Temperature Under Bias................................ -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V 8. DC Characteristics Symbol Parameter Condition ILI Input Load Current ILO Min Max Units VIN = 0V to VCC 1 µA Output Leakage Current VI/O = 0V to VCC 1 µA ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 50 µA ICC VCC Active Current f = 5 MHz; IOUT = 0 mA; VCC = 3.6V 15 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage VOL Output Low Voltage IOL = 1.6 mA; VCC = 3.0V VOH Output High Voltage IOH = -100 μA; VCC = 3.0V Ind. 2.0 V 0.45 2.4 V V 5 0395F–PEEPR–08/09 9. AC Read Characteristics AT28LV010-20 Symbol Parameter tACC Min Max Units Address to Output Delay 200 ns tCE(1) CE to Output Delay 200 ns tOE(2) OE to Output Delay 0 80 ns tDF(3)(4) CE or OE to Output Float 0 55 ns tOH Output Hold from OE, CE or Address, Whichever Occurred First 0 ns tCEPH(5) CE Pulse High Time 50 ns 10. AC Read Waveforms(1)(2)(3)(4) tCEPH Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 5. If CE is de-asserted, it must remain de-asserted for at least 50ns during read operations otherwise incorrect data may be read. 6 AT28LV010 0395F–PEEPR–08/09 AT28LV010 11. Input Test Waveforms and Measurement Level tR, tF < 5 ns 12. Output Test Load 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol CIN COUT Note: Typ Max Units Conditions 4 6 pF VIN = 0V 8 12 pF VOUT = 0V 1. This parameter is characterized and is not 100% tested. 7 0395F–PEEPR–08/09 14. AC Write Characteristics(1) Symbol Parameter tAS, tOES Address, OE Set-up Time tAH Address Hold Time tCS Min Max Units 0 ns 100 ns Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 200 ns tDS Data Set-up Time 100 ns Data, OE Hold Time 10 ns tDH, tOEH Note: 1. All write operations must be preceded by the SDP command sequence. 15. AC Write Waveforms 15.1 WE Controlled 15.2 CE Controlled 8 AT28LV010 0395F–PEEPR–08/09 AT28LV010 16. Software Protected Write Characteristics Symbol Parameter tWC Write Cycle Time tAS Address Set-up Time tAH Min Max Units 10 ms 0 ns Address Hold Time 100 ns tDS Data Set-up Time 100 ns tDH Data Hold Time 10 ns tWP Write Pulse Width 200 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High 150 100 µs ns 17. Programming Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(3) LOAD LAST BYTE TO LAST ADDRESS(3) Notes: ENTER DATA PROTECT STATE 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Data protect state will be re-activated at the end of program cycle. 3. 1 to 128 bytes of data are loaded. 18. Software Protected Program Cycle Waveforms(1)(2)(3) Notes: 1. A0 - A14 must conform to the addressing sequence for the first three bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16) must be the same for each high to low transition of WE (or CE). 3. OE must be high only when WE and CE are both low. 9 0395F–PEEPR–08/09 19. Data Polling Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time Typ Max ns 10 ns OE to Output Delay tWR Write Recovery Time Units 10 (2) tOE Notes: Min ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics 20. Data Polling Waveforms 21. Toggle Bit Characteristics(1) Symbol Parameter Min tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns (2) tOE OE to Output Delay tOEHP OE High Pulse tWR Write Recovery Time Notes: Typ Max Units ns 150 ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics 22. Toggle Bit Waveforms Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 10 AT28LV010 0395F–PEEPR–08/09 AT28LV010 23. Ordering Information 23.1 Green Package Option (Pb/Halide-free) tACC (ns) 200 Note: ICC (mA) Active 15 Standby 0.05 Package Operation Range AT28LV010-20JU Ordering Code 32J AT28LV010-20TU 32T Industrial (-40° to 85° C) To receive product with the SDP feature temporarily disabled, order with SL319. Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32T 32-lead, Plastic Thin Small Outline Package (TSOP) 23.2 Die Products Contact Atmel Sales for die sales options. 11 0395F–PEEPR–08/09 24. Packaging Information 24.1 32J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 E E2 B1 B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) D2 Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 12 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 32J B AT28LV010 0395F–PEEPR–08/09 AT28LV010 24.2 32T – TSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e NOTE 0.50 BASIC 10/18/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. REV. 32T B 13 0395F–PEEPR–08/09 Revision History 14 Doc. Rev. Date Comments 0395F 08/2009 Implemented Revision History and updated AC Characterisitics and ordering information. 0395F 07/2009 Add a revision history page and update this version ‘F’ with the changes. Update AC Characateristics. AT28LV010 0395F–PEEPR–08/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support p_eeprom@atmel.com Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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