AT9917TS-G

AT9917 Automotive LED Driver IC with High Current Accuracy Features General Description • Switch Mode Controller for Boost, SEPIC and Buck Converters • Closed-Loop Control of Output Current • High PWM Dimming Ratio • Internal 40V Linear Regulator • Internal 3% Voltage Reference • Constant Frequency Operation with Programmable Slope Compensation • Linear and PWM Dimming • Programmable Jitter to Reduce EMI • +/–1A MOSFET Gate Driver • Output Short-Circuit Protection • Output Overvoltage Protection • Programmable Hiccup Timer • Soft Start • Temperature Foldback with External NTC Resistor • AEC-Q100 Compliant The AT9917 is an advanced fixed frequency PWM IC designed to control single-switch, boost, SEPIC and buck LED drivers in a Constant Current mode. The controller uses a Peak Current-mode control scheme with programmable slope compensation and includes an internal transconductance amplifier to control the output current with high accuracy. The IC includes a +/–1A gate driver that makes the AT9917 suitable for high-power applications. An internal 40V linear regulator powers the IC, eliminating the need for a separate power supply for the device. The IC provides a Fault output, which can be used to disconnect the LEDs in case of a Fault condition (such as an alternator load dump in automobiles) using an external disconnect FET. The AT9917 also provides a TTL-compatible, low-frequency PWM dimming input that can accept an external control signal with a duty ratio of 0% to 100% and a frequency of up to several kilohertz. Temperature foldback of the output current is possible, using an external NTC resistor. Applications The AT9917-based LED driver is suited for automotive LED driver applications. The AT9917-based LED lamp drivers can achieve efficiencies in excess of 90% when buck or boost topologies are used. • Automotive LED Driver Applications Package Type 24-lead TSSOP (Top view) 1 See Table 2-1 for pin information.  2018 Microchip Technology Inc. VIN AVDD PVDD GATE PGND GND JTR RT CS OVP T2 T1 24 REF EN NC NC FDBK IREF COMP SS PWMD FLT DIV NTC DS20005557A-page 1 AT9917 Typical Application D1 D2 (Optional) CIN L1 CIN1 CPVDD Q1 PVDD AVDD VIN RCS CSC CAVDD ROVP2 RSC GATE CS PGND OVP FLT GND EN FDBK AT9917 COMP PWMD RT RT SS CSS JTR NTC DIV CJTR CO ROVP1 RR1 R1 RNTC R3 CREF Q2 CC RS IREF REF T2 T1 R4 RR2 R2 DS20005557A-page 2  2018 Microchip Technology Inc. AT9917 Functional Block Diagram Linear Regulator VIN Vbg REF GATE + - AVDD 4.25V/4.50V EN 0.8V/2V POR POR PVDD FC GATE + - HCP PGND RT Clock S Q FLT FC HCP R Blanking + - GATE 14R OVPD + CS 1.25V/1.125V - JTR OVP R COMP GND DIS SCD OTP SS POR - gm POR HCP 0.7V + PWMD OVPD + - S Q DIS R Q FC TBLANK FDBK 2 + - 4 IFDBK = (I - 3ITI) 30 NTC - 250mV DIS Jitter IT1 INTC NTC SCD OTP JTR Current Mirror IREF + DIV T1 HCP IT2 T2 JTR   2018 Microchip Technology Inc. DS20005557A-page 3 AT9917 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VIN to GND ................................................................................................................................................–0.5V to +45V PVDD, AVDD to GND....................................................................................................................................–0.3V to +6V GATE to GND............................................................................................................................... –0.3V to (PVDD+0.3V) All other pins to GND ...................................................................................................................–0.3V to (AVDD +0.3V) Continuous Power Dissipation (TA= +25°C)..................................................................................................... 1000 mW Junction Temperature Range, TJ ......................................................................................................... –40°C to +150°C Storage Temperature Range, TS ......................................................................................................... –65°C to +150°C † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise noted, specifications are at TA = 25°C. VIN = 12V, PVDD = AVDD EN = PWMD = AVDD, GATE = OPEN, CREF = 0.1 μF, CAVDD = CPVDD = 1 μF, RT = 200 kΩ, IT1 = IT2 = 100 μA. Parameter Sym. Min. Typ. Max. Unit Conditions INPUT Input DC Supply Voltage Range VINDC 5.3 — 40 V DC input voltage Shutdown Mode Supply Current IINDIS — — 100 µA EN = 0.8V, PWMD = GND (Note 1) Input Current when Enabled IINEN — — 2 mA EN = 2V, GATE OPEN, PWMD = GND (Note 1) AVDD 4.65 5 5.35 V VIN = 6V–40V, GATE OPEN, PWMD = GND, IDD = 0 mA – 20 mA (Note 1) AVDDUV,R 4.25 — 4.85 V AVDD rising (Note 1) ∆AVDDUV — 250 — mV AVDD falling VEN(LO) VEN(HI) REN — 2 — — — 100 0.8 — — V V kΩ Note 1 Note 1 V mV IREF = 0 mA (Note 1) IREF = 0 mA, EN = GND mV IREF = 0 mA –1 mA INTERNAL REGULATOR Internally Regulated Voltage AVDD Undervoltage Lockout Upper Threshold AVDD Undervoltage Lockout Hysteresis ENABLE INPUT Enable Input Low Voltage Enable Input High Voltage Pull-Down Resistor at EN REFERENCE REF Pin Voltage REF Pin Voltage when Disabled Load Regulation of Reference Voltage GATE VREF VREF,DIS ∆VREF 1.210 1.250 1.290 — 0 — 0 — 2 CGATE = 4 nF, VIN = AVDD = PVDD = 5V CGATE = 4 nF, GATE Output Fall Time TFALL — 20 35 ns VIN = AVDD = PVDD = 5V Maximum Duty Cycle DMAX 87 — 93 % Note 1 Note 1: Specifications apply over the full operating ambient temperature range of –40ºC < TA < +125ºC. Guaranteed by design and characterization. 2: Specifications are determined by characterization and are not 100% tested. GATE Output Rise Time DS20005557A-page 4 TRISE — 20 35 ns  2018 Microchip Technology Inc. AT9917 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, specifications are at TA = 25°C. VIN = 12V, PVDD = AVDD EN = PWMD = AVDD, GATE = OPEN, CREF = 0.1 μF, CAVDD = CPVDD = 1 μF, RT = 200 kΩ, IT1 = IT2 = 100 μA. Parameter Sym. Min. Typ. Max. Unit — 2 — — — 200 0.8 — — V V kΩ Note 1 Note 1 1.15 — 1.25 0.125 1.35 — V V OVP rising (Note 1) OVP falling 100 — 250 ns — — 150 ns –10 — 10 mV Note 1 VCOMP = AVDD = PVDD = 5V, VCS = 0 mV – 400 mV step Note 1 GBW 1 — — MHz AV VCM VCOMP gm VOFFSET ICOMP,SINK ICOMP,SRC IBIAS,AMP 65 –0.3 0.7 — –9 0.2 –0.2 — — — — 950 — — — 0.5 — 3 AVDD — 9 — — 1 dB V — µA/V mV mA mA nA fOSC1 fOSC2 fOSC 90 427 100 105 505 — 120 583 800 kHz kHz kHz RT = 1 MΩ (Note 1) RT = 200 kΩ (Note 1) Note 1 FJTR — — 50 500 — — Hz Hz CJTR = 100 nF CJTR = 10 nF PWM DIMMING PWMD Input Low Voltage VPWMD(LO) PWMD Input High Voltage VPWMD(HI) PWMD Pull-Down Resistance RPWMD OVER VOLTAGE PROTECTION Overvoltage Rising Trip Point VOVP,RISING Overvoltage Hysteresis VOVP,HYST CURRENT SENSE Leading Edge Blanking TBLANK,CS Delay to Output of Comparator TDELAY1 Comparator Offset Voltage VOFFSET INTERNAL TRANSCONDUCTANCE OP-AMP Gainbandwidth Product Open-Loop DC Gain Input Common Mode Range Output Voltage Range Transconductance Input Offset Voltage COMP Sink Current COMP Source Current Input Bias Current OSCILLATOR Oscillator Frequency Output Frequency Range JITTER Jitter Frequency Conditions 150 pF capacitance at COMP pin (Note 1) COMP OPEN Note 1 Note 1 Note 1 VFB = 0.1V, VCOMP = 0V (Note 1) VFB = –0.1V, VCOMP = AVDD (Note 1) Note 1 Change in the Switching ∆F ±4.5 — — kHz Frequency HICCUP TIMER Hiccup Charging Current IHICCUP — 10 — µA Voltage Swing for Hiccup Timer ∆V — 0.6 — V TEMPERATURE FOLDBACK CIRCUIT NTC Source Current Range INTC — — 1 mA Note 1 IFDBK/INTC Current Gain NNTC — 0.13 — — INTC = 0.5 mA INTC/IT1 Current Gain NT1 — 3 — — INTC = 0.5 mA INTC/IT2 Current Gain NT2 — 6 — — INTC = 0.5 mA T1 and T2 Reference Voltage VT1, VT2 — 3.5 — V OUTPUT SHORT CIRCUIT Amplifier Gain at IREF Pin GFAULT 1.8 2 2.2 — VIREF = 400 mV Note 1: Specifications apply over the full operating ambient temperature range of –40ºC < TA < +125ºC. Guaranteed by design and characterization. 2: Specifications are determined by characterization and are not 100% tested.  2018 Microchip Technology Inc. DS20005557A-page 5 AT9917 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, specifications are at TA = 25°C. VIN = 12V, PVDD = AVDD EN = PWMD = AVDD, GATE = OPEN, CREF = 0.1 μF, CAVDD = CPVDD = 1 μF, RT = 200 kΩ, IT1 = IT2 = 100 μA. Parameter Propagation Time for Short-Circuit Detection Sym. Min. Typ. Max. Unit TD,SHORT — — 250 ns Conditions VIREF = 400 mV, VFDBK steps from 0V –1V, VFLT goes from high to low 330 pF capacitor at FLT pin 330 pF capacitor at FLT pin Fault Output Rise Time TRISE,FAULT — — 300 ns — — 200 ns Fault Output Fall Time TFALL,FAULT Minimum Voltage at the Output 250 — — mV VIREF = 0V (Note 1) VMIN of the Amplifier PWMD Blanking Time TBLANK,PWMD 200 — 900 ns Note 1 SOFT START 10 15 25 µA Soft-Start Charging Current ISS,CHG 1.0 — — mA VSS = 5V Soft-Start Discharging Current ISS,DIS Soft-Start Reset Voltage VSS,RST — — 100 mV SLOPE COMPENSATION On-Resistance of FET at CS — — 200 Ω Note 1 RON,DFETCS Pin Note 1: Specifications apply over the full operating ambient temperature range of –40ºC < TA < +125ºC. Guaranteed by design and characterization. 2: Specifications are determined by characterization and are not 100% tested. TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Units TA –40 — +125 °C Conditions TEMPERATURE RANGES Operating Ambient Temperature Maximum Junction Temperature TJ — — +150 °C Storage Temperature TS –65 — +150 °C JA — 125 — °C/W PACKAGE THERMAL RESISTANCE 24-lead TSSOP Note 1: Note 1 Mounted on an FR 4 board, 25 mm x 25 mm x 1.57 mm. DS20005557A-page 6  2018 Microchip Technology Inc. AT9917 2.0 PIN DESCRIPTION The details on the pins of AT9917 are listed in Table 2-1. Refer to Package Type for the location of pins. TABLE 2-1: PIN FUNCTION TABLE Pin Number Symbol Description 1 VIN 2 AVDD This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to GND (at least 0.1 μF). 3 PVDD This is the power supply pin for the gate driver. It should be connected externally to AVDD and bypassed with a low ESR capacitor to PGND (at least 0.1 μF). 4 GATE This pin is the output of gate driver for an external logic level N-channel power MOSFET. 5 PGND Ground return for the gate drive circuitry 6 GND Ground return for all the low-power analog internal circuitry. This pin must be connected to the return path from the input. 7 JTR This pin controls the jitter of the clock programmed by a capacitor connected at this pin. This capacitor also determines the hiccup time. 8 RT This pin sets the frequency of the power circuit. A resistor between RT and GND programs the circuit in Constant Frequency mode. 9 CS This pin is used to sense the source current of the external power FET. It includes a built-in 100 ns (minimum) blanking time. Slope compensation is implemented by connecting an RC network to this pin as shown in the Typical Application. 10 OVP This pin is the comparator input of the overvoltage protection circuit for the converter. When the voltage at this pin exceeds 1.25V, the gate output of the AT9917 is turned off and FLT goes low. Switching is enabled when the voltage at this pin goes below 1.125V. 11 T2 This pin programs the temperature at which the driver is shut off due to Overtemperature condition for the LED when using an external NTC resistor at the NTC pin. 12 T1 This pin programs the break temperature threshold which determines the start of the current derating when using an external NTC resistor at the NTC pin. 13 NTC Users may connect an external NTC resistor to this pin for temperature fold back of the output current and overtemperature shutdown. The NTC pin should be connected to AVDD when output current thermal derating is not required. 14 DIV This pin programs the voltage input for the transconductance at NTC pin. 15 FLT This pin is pulled to ground when there is an Output Short-circuit condition or Output Overvoltage condition. This pin can be used to drive an external MOSFET in the case of boost converter configuration to disconnect the LED load from the power source. It is also controlled by the PWM dimming input to provide excellent PWM dimming response. 16 PWMD When this pin is pulled to GND (or left open), switching of the AT9917 is disabled. When an external TTL high level is applied to it, switching will resume. 17 SS Connecting a capacitor from this pin to GND programs the soft start time of the LED driver. 18 COMP This pin is the output of the error amplifier. Stable closed-loop control can be accomplished by connecting a compensation network between COMP and GND. This pin is pulled internally to GND upon detection of a Fault condition and on startup. 19 IREF The voltage at this pin sets the output current level. The current reference voltage can be set using a resistor divider from the REF pin to GND pin. 20 FDBK This pin provides output current feedback to the AT9917 by using a current sense resistor. A resistor connected between the FDBK pin and the LED current sense resistor can be used to reduce the current at elevated temperatures. 21 NC 22 NC This pin is the input of a 40V high-voltage regulator. No connection  2018 Microchip Technology Inc. DS20005557A-page 7 AT9917 TABLE 2-1: PIN FUNCTION TABLE Pin Number Symbol Description 23 EN Pulling EN to GND causes the AT9917 to go into a low-current Standby mode. A voltage greater than 2V enables the IC. 24 REF This pin provides accurate reference voltage. It must be bypassed with a 0.01 µF to 0.1 µF capacitor to GND. DS20005557A-page 8  2018 Microchip Technology Inc. AT9917 3.0 DETAILED DESCRIPTION 3.1 Power Topology The AT9917 is a closed-loop, Switch-mode LED driver designed to control a buck, boost or SEPIC converter in a Constant Frequency mode. The IC includes an internal linear regulator, which operates from input voltages from 6V to 40V. It also possesses features typically required in LED drivers, such as open LED protection, output short-circuit protection, linear and PWM dimming, and accurate LED current control. In addition, the device includes a thermal derating circuit which can be used to reduce the LED current at high temperatures to prevent a thermal runaway. A high-current gate drive output enables the controller to be used in high power converters. 3.2 Power Supply to the IC (VIN, AVDD, PVDD) The AT9917 can be powered directly from its VIN pin that takes a voltage up to 40V. When a voltage is applied to the VIN pin, the AT9917 tries to maintain a constant 5V (typical) at the AVDD pin. The regulator also has a built-in undervoltage lockout which shuts off the IC if the voltage at the AVDD pin falls below the UVLO lower threshold. This linear regulator also provides the power supply to the built-in gate driver. The AVDD pin must be bypassed by a low ESR capacitor (≥0.1 µF) to provide a low impedance path for the high-frequency current of the output gate driver. The PVDD pin is used to provide power to the gate driver. It should also be bypassed with a low-ESR capacitor (≥0.1 µF) and should be shorted to the AVDD pin. The input current drawn from the external power supply (or VIN pin) is the sum of the 2 mA (maximum) current drawn by the all the internal circuitry and the current drawn by the gate driver. The current drawn by the gate driver depends on the switching frequency and the gate charge of the external FET. Refer to Equation 3-1. EQUATION 3-1: Where: I IN = 2mA + Q G  f S fS = Switching frequency of the converter QG = Gate charge of the external FET  (can be obtained from the FET data sheet) The EN pin is a TTL-compatible input used to disable the IC. Pulling the EN pin to GND shuts down the IC and reduces the quiescent current drawn by the IC to be less than 100 μA. If the enable function is not required, the EN pin can be connected to AVDD.  2018 Microchip Technology Inc. 3.3 Reference Voltage (REF) The AT9917 provides a 1.25V reference voltage at the REF pin. This voltage is used to derive the various internal voltages required by the IC and set the LED current externally. It should be bypassed with a low-impedance capacitor (0.01 µF to 0.1 µF). 3.4 Timing Resistor (RT) The switching frequency of the converter is set by connecting a resistor between RT and GND. The resistor value can be determined with Equation 3-2. EQUATION 3-2: 1 R T = ------------------------f S  9.5pF 3.5 Current Sense (CS) The CS input is used to sense the source current of the switching FET. The CS input of the AT9917 includes a built-in 100 ns (minimum) blanking time to prevent spurious turn-off due to the initial current spike when the FET turns on. The IC includes an internal resistor divider network, which steps down the voltage at the COMP pins by a factor of 15. This voltage is used as the reference for the current sense comparators. Since the maximum voltage of the COMP pin is AVDD, this voltage determines the maximum reference current for the current sense comparator and thus the maximum inductor current. The switch current sense resistor RCS should be chosen so that the input inductor current is limited to below the saturation current level of the input inductor. For Discontinuous Conduction mode of operation, no slope compensation is necessary. In this case, the current sense resistor is calculated with Equation 3-3. EQUATION 3-3: AV DD – 0.8V R CS = -------------------------------15  I SAT Where ISAT is the maximum desired peak inductor current For Continuous Conduction mode converters operating in Constant Frequency mode, slope compensation becomes necessary to ensure stability of the Peak Current mode controller when the operating duty cycle is greater than 0.5. This factor must also be accounted for when determining RCS as discussed in Section 3.6 “Slope Compensation”. DS20005557A-page 9 AT9917 3.6 Slope Compensation EQUATION 3-6: Choosing a slope compensation, which is one-half of the down slope of the inductor current, ensures that the converter is stable for all duty cycles. As shown in Figure 3-1, slope compensation in AT9917 can be programmed by two external components. A resistor from AVDD sets a current (which is almost constant since the AVDD voltage is much larger than the voltage at the CS pin). This current flows into the capacitor and produces a ramp voltage across the capacitor. The voltage at the CS pin is then the sum of the voltage across the capacitor and the voltage across the current sense resistor, with the voltage across the capacitor providing the required slope compensation. When the GATE turns off, an internal pull-down FET discharges the capacitor, so that the capacitor can be charged up again to produce the same ramp voltage across the capacitor at each time the GATE turns on in each cycle + GATE FIGURE 3-1: AVDD CS RCS Slope Compensation. The 200Ω maximum resistance of the internal FET will prevent the voltage at the CS pin from going all the way to zero. The minimum value of the voltage is computed in Equation 3-4: EQUATION 3-4: AV DD V CS MIN = ---------------  200 R SC The slope compensation capacitor is chosen so that it can be completely discharged by the internal 200Ω (maximum) FET at the CS pin during the time the FET is off. Assuming the worst case switch duty cycle of 93%, CSC is computed with Equation 3-5. EQUATION 3-5: 0.07 C SC = --------------------------------3  200  f S Assuming that there is a down slope of DS (A/μs) for the inductor current, the switch current sense resistor and the slope compensation resistor are calculated as shown in Equation 3-6 and Equation 3-7, respectively. DS20005557A-page 10 EQUATION 3-7: 2  AV DD R SC = -----------------------------------------------------6 DS  10  C SC  R CS 3.7 Gate Driver Output (GATE, PGND) The GATE output of the AT9917 is used to drive the gate of the switching FET. The PGND pin should be connected to the GND connection of the current sense resistor. In addition, the two grounds of the IC, PGND and GND, should be connected together at the input GND connection to minimize noise. 3.8 RSC CSC AV DD – 0.8V 1 R CS = --------------------------------  --------------------------------------------------------------15 6  DS  10  0.93  -  + I SAT  -------------------------------------2  fS   FLT Output The FLT pin is used to drive a disconnect FET while operating in boost or SEPIC converter configuration. In the case of boost converters, when there is a short-circuit fault at the output, there is a direct path from the input source to ground which can cause high currents to flow. The disconnect switch is used to interrupt this path and prevent damage to the converter. The disconnect switch also helps to disconnect the output filter capacitors from the LED load in the boost or SEPIC converter configuration during PWM dimming without discharging the output filter capacitors. This enables a very high PWM dimming ratio. 3.9 Control of the LED Current (IREF, FDBK and COMP) The LED current in the AT9917 is controlled in a closed-loop manner. The current reference voltage at the IREF pin which sets the LED current is programmed using a resistor divider from the REF pin to the GND pin. The current reference voltage can also be set externally with a low-voltage source. This reference voltage is compared to the voltage at the FDBK pin, which senses the LED current through the LED current sense resistor. The AT9917 includes a 1 MHz transconductance amplifier with a tri-state output, which is used to close the feedback loops and provide accurate current control. The compensation network is connected from the COMP pin to the GND pin. The output of the op-amp is buffered and connected to the current sense comparator using a 14R:1R resistor divider.  2018 Microchip Technology Inc. AT9917 The output of the op-amp is also controlled by the signal applied to the PWMD pin. When PWMD is high, the output of the op-amp is connected to the COMP pin. When PWMD is low, the output is left open. This enables the integrating capacitor to hold the charge when the PWMD signal has turned off the gate drive. When the IC is enabled, the voltage on the integrating capacitor almost instantaneously forces the converter into a steady state. 3.10 Linear Dimming Linear dimming can be accomplished by varying the voltages at the IREF pin. Note that since the AT9917 is a Peak Current mode controller, it has a minimum on-time for the GATE output. This minimum on-time will prevent the converter from completely turning off even when the IREF pin is pulled to GND. Thus, linear dimming in this device cannot accomplish true zero-LED current. To get zero-LED current, PWM dimming has to be used. Due to the offset voltage of the short-circuit comparator and the non-linearity of the X2 gain stage, pulling the IREF pin very close to GND might cause the internal short-circuit comparator to trigger and shut down the IC. To overcome this, the output of the gain stage is limited to 250 mV (minimum), allowing the IREF pin to be pulled all the way to 0V without triggering the short-circuit comparator. Therefore, the minimum voltage for a short-circuit detection is 250 mV. 3.11 PWM Dimming (PWMD) PWM dimming in the AT9917 can be accomplished using a TTL-compatible square wave source at the PWMD pin. When the PWM signal is high, the GATE and FLT pins are enabled and the output of the transconductance op-amp is connected to the external compensation network. Thus, the internal amplifier controls the output current. When the PWMD signal goes low, the output of the transconductance amplifier is disconnected from the compensation network. Thus, the integrating capacitor maintains the voltage across it. The GATE is disabled, so the converter stops switching and the FLT pin goes low, turning off the disconnect switch. Note that disconnecting the LED load during PWM dimming causes the energy stored in the inductor to be dumped into the output capacitor. The filter capacitor that is chosen should be large enough so that it can absorb the inductor energy without a significant change in voltage across it. If the capacitor voltage change is significant, it would cause a turn-on spike in the inductor current when PWMD goes high.  2018 Microchip Technology Inc. 3.12 Jitter and Hiccup Timer (JTR) The JTR pin is a multipurpose pin on the AT9917. It is used to set the jitter frequency, wherein the switching frequency swings between its limits. It is also used to set the hiccup time for Fault conditions. The value of the capacitor required for the jitter frequency is derived with Equation 3-8. EQUATION 3-8: 5F C JTR = -----------------------F JTR  Hz  Note that the jitter frequency must be chosen to be significantly lower than the crossover frequency of the closed-loop control. If not, the controller will not be able to reject the jitter frequency, and the LED current will have a current ripple at the jitter frequency. The same capacitor is used to determine the hiccup time. Equation 3-9 illustrates the computation for hiccup time. EQUATION 3-9: C JTR  0.6V t HICCUP = -----------------------------10A If the actual hiccup time is lower than desired, the capacitor at the pin can be increased at the cost of a lower jitter frequency. 3.13 Fault Conditions The AT9917 is a robust controller which can protect the LEDs and the LED driver in case of Fault conditions. The device includes both open LED protection and output short-circuit protection. In both cases, the AT9917 shuts down and attempts to restart. The hiccup time is programmed by the capacitor at the JTR pin. When a Fault condition is detected, both GATE and FLT outputs are disabled, while the COMP pins and JTR pins are pulled to GND. Once the voltage at the JTR pin falls below 0.1V and the Fault condition(s) has disappeared, the capacitor at the JTR pin is released and is charged slowly by a 10 µA current source. Once the capacitor is charged to 0.7V, the COMP pins are released and GATE and FLT pins are allowed to turn on. If the hiccup time is long enough, it ensures that the compensation networks are all completely discharged and that the converters start at minimum duty cycle. DS20005557A-page 11 AT9917 3.14 Short-Circuit Protection When a Short-circuit condition is detected (output current becomes higher than twice the Steady-state current), the GATE and FLT outputs are pulled low. As soon as the disconnect FET is turned off, the output current goes to zero and the Short-circuit condition disappears. At this time, the hiccup timer is started. Once the timing is complete, the converter attempts to restart. If the Fault condition still persists, the converter shuts down and goes through the cycle again. If the Fault condition is cleared due to a momentary output short, the converter just resumes the normal output regulation. This allows the LED driver to recover from accidental shorts without having to reset the IC. During Short-circuit conditions, there conditions that determine the hiccup time. are two Note that the power rating of the LED current sense resistor has to be chosen properly if it has to survive a persistent Fault condition. The power rating can be determined as shown in Equation 3-14. EQUATION 3-14: 2 I SAT  R S  t FALL FAULT + t OFF  P RS  --------------------------------------------------------------------------------t HICCUP Where ISAT is the saturation current of the disconnect FET. For AT9917, “tFALL,FAULT + tOFF” is 450 ns (maximum) 3.15 False Triggering of the Short-Circuit Comparator During PWM Dimming The first is the time required to discharge the compensation capacitors. Assuming a pole-zero R-C network at the COMP pin (series combination of RZ and CZ in parallel with CC), tCOMP is computed as shown in Equation 3-10. During PWM dimming, the parasitic capacitance of the LED string might cause a spike in the output current when the disconnect FET is turned on. If this spike is detected by the short-circuit comparator, it will cause the IC to falsely detect an Over Current condition and shut down. EQUATION 3-10: To prevent false trigger, there is a built-in 500 ns blanking network for the short-circuit comparator. This blanking network is activated when the PWMD input goes high. Thus, the short-circuit comparator will not see the spike in the LED current during the PWM dimming turn-on transition. Once the blanking timer has completed its task, the short-circuit comparator will start monitoring the output current. Thus, the total delay time for detecting a short circuit will depend on the condition of the PWMD input. t COMP = 3  R Z  C Z In case the compensation networks are only type 1 (single capacitor), Equation 3-11 should be used. EQUATION 3-11: t COMP = 3  300  C C The second is the time required for the inductors to completely discharge following a short circuit. This time can be computed as demonstrated in Equation 3-12. If the output short circuit exists before the PWM dimming signal goes high, the total detection time is computed as demonstrated in Equation 3-15. EQUATION 3-12: EQUATION 3-15:  t IND = ---- L  C O 4 t DETECT = t PWMD + t FALL FAULT + t OFF  950ns  max  Where L and CO are the input inductor and output capacitor of the power stage If short circuit occurs when the PWM dimming signal is already high, the time to detect is calculated as shown in Equation 3-16: The hiccup time is then chosen as indicated in Equation 3-13. EQUATION 3-13: EQUATION 3-16: t DETECT = t FALL FAULT + t OFF  450ns  max  t HICCUP  max  t COMP t IND  DS20005557A-page 12  2018 Microchip Technology Inc. AT9917 3.16 Overvoltage Protection The AT9917 provides hysteretic overvoltage protection, allowing the IC to recover in case the LED load is momentarily disconnected. When the load is disconnected from a boost converter, the output voltage rises as the output capacitor starts charging with the inductor's stored energy dump. When the output voltage reaches the OVP rising threshold, the AT9917 detects an Overvoltage condition and turns off the converter. The converter is turned back on only when the output voltage falls below the OVP falling threshold, which is 10% lower than the rising threshold. The OVP and recovery time duration is mostly dictated by the R-C time constant of the output capacitor CO and the resistor network used to sense over voltage (ROVP1 + ROVP2). In case of a persistent Open Circuit condition, this cycle repeats and maintains the output voltage within a 10% band. In most designs, the lower threshold voltage of the over voltage protection (VOVP –10%) at which the AT9917 attempts to restart will be more than the LED string voltage. Thus, when the LED load is reconnected to the output of the converter, the voltage differential between the actual output voltage and the LED string voltage will cause a spike in the output current. This causes a short circuit to be detected and the device triggers short-circuit protection. This behavior continues until the output voltage becomes lower than the LED string voltage, at which point no fault will be detected and normal operation of the circuit will commence. 3.17 The output LED current IO without thermal derating or output LED current I1 with thermal derating enabled at temperature below T1 in the thermal derating curve can be calculated with Equation 3-17. EQUATION 3-17: R r2 V REF I O = I 1 = -------------  ----------------------RS R r1 + R r2 Where IO is the output LED current without thermal derating, I1 is the output LED current at temperature below T1 in the thermal derating curve, VREF is the reference voltage at REF pin, and RS is the LED current sense resistor. When thermal derating needs to be implemented, four resistors are used to set the various points to obtain the thermal derating curve shown in Figure 3-3. ISHORT I1 ILED I2 T1 Thermal Derating The reference voltage used to set the LED current is programmed using two resistors—Rr1 and Rr2, which are connected as shown in Figure 3-2. IO FDBK RS FIGURE 3-3: Thermal Derating Curve. When an external NTC resistor is connected as illustrated in Figure 3-4, both temperatures T1 and T2, as well as the current I2 can be accurately programmed to optimize the light output of the LED lamp for safe operation over the entire operating temperature range. REF Rr1 Rr2 IO IREF RS NTC REF Rr1 RNTC No Thermal Derating. Thermal derating is programmed using four pins— NTC, DIV, T1 and T2. When no temperature foldback is required, NTC and T1 should be connected to AVDD, and DIV should be connected to GND. T2 still requires a resistor to GND (10 kΩ ~100 kΩ). No pins should be left floating as shown in Figure 3-2.  2018 Microchip Technology Inc. IREF Rr2 T1 T2 FIGURE 3-2: FDBK R4 DIV AVDD T2 NTC DIV R2 R1 T1 T2 R3 FIGURE 3-4: With Thermal Derating. DS20005557A-page 13 AT9917 The ratio of the resistor divider R2/(R1 + R2) programs the voltage at the NTC pin. The voltage VT1 at T1 pin is approximately 3.5V. The current sourced by NTC pin and T1 pin is mirrored out of FDBK pin in accordance with Equation 3-18. approximately equal to the voltage at T1 pin which is 3.5V. The turn-off of the converter at the desired thermal shutdown temperature T2 is programmed using R3 connected from the T2 pin to GND pin. Refer to Equation 3-22. EQUATION 3-18: EQUATION 3-22: When: 4 I FDBK = ------  I NTC – 3I T1  30 6  R1 + R2  R 3 = -------------------------------------- R2  –3  ---------------------R  NTC  T2   I NTC  I T1 IFDBK, INTC, and IT1 are the currents sourced from pins FDBK, NTC, and T1, respectively. Temperature T1 is programmed by selecting R2 as demonstrated in Equation 3-19. EQUATION 3-19: R 2 = 3  R NTC  T1  Where RNTC(T1) is the resistance of the NTC resistor at temperature T1. As illustrated in Equation 3-20, R1 can be computed using the maximum current (≤1 mA) that will flow through the NTC resistor at temperature T2. EQUATION 3-20: V T1  R2  R 1 = ------------------------   ----------------------  – R 2 I NTC MAX  R NTC  T2   Where INTC,MAX is the maximum NTC current, and RNTC(T2) is the resistance of the NTC resistor at temperature T2. Further reduction of the NTC resistance RNTC will create a proportional offset of the current feedback reference voltage at FDBK, and hence will cause a drop in LED current. To program the desired LED current I2 at the temperature T2, resistor R4 at FDBK should be calculated as shown in Equation 3-21. The overtemperature recovery threshold is independent of the current at the T2 pin. AT9917 recovers from thermal shutdown at the break temperature T1 when the current from the NTC pin INTC < 3IT1. 3.18 Soft Start (SS) The soft-start feature controls the initial ramp-up of the error voltage at the COMP pin. Connecting a single soft-start capacitor between SS pin and GND pin can program the soft-start time. Upon the first applying voltage to the AVDD pin, a current source of typical 15 µA is supplied from the SS pin, gradually charging the soft-start capacitor. The COMP pin voltage tracks the SS pin voltage until regulation of the output current is reached. When AVDD voltage falls below the undervoltage lower threshold, the soft-start capacitor is discharged rapidly by an internal MOSFET. The soft-start time can be estimated by the Equation 3-23. EQUATION 3-23: C SS  V COMP t SS = --------------------------------I SS CHG Where CSS is the capacitance of the soft-start capacitor, VCOMP is the COMP pin voltage at normal regulation, (VCOMP ≈ 2.5V), and ISS,CHG is the soft-start charging current. EQUATION 3-21:  I1 – I2   RS   R1 + R2  R 4 = ------------------------------------------------------------- 4  R2 V T1  ------  ---------------------- – 3  30  R NTC  T2   Where VT1 is the voltage at the T1 pin (VT1 = 3.5V), and RNTC(T2) is the resistance of the NTC resistor at temperature T2. The overtemperature shutdown is triggered at temperature T2 when the current from the NTC pin INTC > [3 x IT1 + 6 x IT2]. The voltage at T2 pin is DS20005557A-page 14  2018 Microchip Technology Inc. AT9917 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 24-lead TSSOP XXXXXXXX e3 YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: Example AT9917TS e3 1815 367 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.  2018 Microchip Technology Inc. DS20005557A-page 15 AT9917 24-Lead TSSOP Package Outline (TS) 7.80x4.40mm body, 1.20mm height (max), 0.65mm pitch D 24 θ1 E1 E Note 1 (Index Area) L2 L e 1 L1 b Top View θ View B Gauge Plane Seating Plane View B A A A2 Seating Plane A1 Side View View A-A A Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. Note: 1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU a printed indicator. Symbol Dimension (mm) A A1 A2 b D E E1 MIN 0.85* 0.05 0.80 0.19 7.70 6.20* 4.30 NOM - - 1.00 - 7.80 6.40 4.40 MAX 1.20 0.15 1.15† 0.30 7.90 6.60* 4.50 e L L1 L2 0.65 BSC 0.60 0.75 ș ș 0O 0.45 1.00 REF 0.25 BSC - 12O REF 8O JEDEC Registration MS-153, Variation AD, Issue F, May 2001. 7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ ‚7KLVGLPHQVLRQGLIIHUVIURPWKH-('(&GUDZLQJ Drawings are not to scale. DS20005557A-page 16  2018 Microchip Technology Inc. AT9917 APPENDIX A: REVISION HISTORY Revision A (September 2018) • Converted Supertex Doc #s DSFP-AT9917 to Microchip DS20005557A • Created a Detailed Description section and included Section 3.18 “Soft Start (SS)” • Made minor text changes throughout the document  2018 Microchip Technology Inc. DS20005557A-page 17 AT9917 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. PART NO. Device Device: XX - Package Options X - Environmental AT9917 = X Media Type Example: a) AT9917TS-G: Automotive LED Driver IC with High Current Accuracy, 24-lead TSSOP Package, 2500/Reel Automotive LED Driver IC with High Current Accuracy Package: TS = 24-lead TSSOP Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = 2500/Reel for TS Package DS20005557A-page 18  2018 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3571-6 == ISO/TS 16949 ==  2018 Microchip Technology Inc. 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