ATA6616C/ATA6617C
8K/16K Flash Microcontroller with LIN Transceiver, 5V
Regulator and Watchdog
DATASHEET
General Features
● Single-package high performance, low power AVR® 8-bit microcontroller with LIN
transceiver, 5V regulator (85mA current capability) and watchdog
● Very low current consumption in sleep mode
● 8Kbytes/16Kbytes flash memory for application program
(Atmel® ATA6616C/ATA6617C)
● Supply voltage up to 40V
● Operating voltage: 5V to 27V
● Temperature range: Tcase –40°C to +125°C
● QFN38, 5mm 7mm package
Description
Atmel ATA6616C/ATA6617C is a System-in-Package (SiP) product, which is particularly
suited for complete LIN-bus node applications. It consists of two ICs in one package supporting highly integrated solutions for in-vehicle LIN networks. The first chip is the LINsystem-basis-chip (LIN-SBC) ATA6624, which has an integrated LIN transceiver, a 5V regulator (85mA) and a window watchdog. The second chip is an automotive microcontroller
from Atmel’s series of AVR 8-bit microcontroller with advanced RISC architecture, the
Atmel ATtiny87 with 8-Kbytes and the Atmel ATtiny167 with 16-Kbytes flash memory.
All pins of the LIN system basis chip as well as all pins of the AVR microcontroller are
bonded out to provide customers the same flexibility for their applications as they have
when using discrete parts.
In Section 1. “Atmel ATA6616C/ATA6617C LIN System in Package Solution (SIP)” on page
3 you will find the pin configuration for the complete SiP. In Section 3. “LIN System-basischip Block” on page 7 the LIN SBC is described, and in Section 4. “Atmel
ATtiny87/ATtiny167 Microcontroller Block for Atmel ATA6616C/ATA6617C” on page 26 the
AVR is described in detail.
9132J-AUTO-01/15
Figure 1.
Application Diagram
LIN-bus
Atmel ATA6616C/ATA6617C
MCU
Atmel
ATtiny 87/167
2
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
LIN-SBC
Atmel
ATA6624
1.
Atmel ATA6616C/ATA6617C LIN System in Package Solution (SIP)
1.1
Pinning Atmel ATA6616C/ATA6617C
Table 1-1.
WAKE
LIN
GND
PA3
AVCC
AGND
PA4
PA5
PA6
PA7
PB7
PB6
Figure 1-1. Pinning QFN38
PB5
31 30 29 28 27 26 25 24 23 22 21 20
32
19
NTRIG
PB4
33
18
EN
VCC
34
17
VS
GND
35
16
VCC
GND
36
15
PVCC
GND
37
14
KL15
PB3
38
3
4
5
6
7
8
PB1
PB0
PA0
PA1
PA2
RXD
INH
TXD
MODE
TM
2
NRES
WD_OSC
1
13
9 10 11 12
PB2
Atmel
ATA6616C/ATA6617C
Pin Description
Pin
Symbol
1
PB2
Port B 2 I/O line (PCINT10/OC1AV/USCK/SCL)
2
PB1
Port B 1 I/O line (PCINT9/OC1BU/DO)
3
PB0
Port B 0 I/O line (PCINT8/OC1AU/DI/SDA)
4
PA0
Port A 0 I/O line (PCINT0/ADC0/RXD/RXLIN)
5
PA1
Port A 1 I/O line (PCINT1/ADC1/TXD/TXLIN)
6
PA2
Port A 2 I/O line (PCINT2/ADC2/OC0A/DO/MISO)
7
(1)
Receive data output
(1)
Battery-related output for controlling an external voltage regulator
RXD
8
INH
9
TXD(1)
10
NRES(1)
11
12
Function
WD_OSC
Transmit data input; active low output (strong pull down) after a local wake-up
request
(1)
(1)
TM
Output undervoltage and watchdog reset (open drain)
External resistor for adjustable watchdog timing
For factory testing only (tie to ground)
13
MODE(1)
14
(1)
Ignition detection (edge sensitive)
(1)
5V regulator sense input pin
15
16
KL_15
PVCC
(1)
VCC
17
VS(1)
18
(1)
19
20
21
Note:
1.
EN
For debug mode: Low watchdog is on; high watchdog is off
5V regulator output/driver pin
Battery supply
Enables the device into normal mode
(1)
Low level watchdog trigger input from microcontroller
(1)
High voltage input for local wake-up request; if not needed connect to VS
NTRIG
WAKE
GND(1)
System Ground LIN-SBC
This identifies the pins of the LIN SBC Atmel® ATA6624
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
3
Table 1-1.
Pin Description (Continued)
Pin
Note:
4
Symbol
(1)
Function
22
LIN
LIN bus line input/output
23
PA3
Port A 3 I/O line (PCINT3/ADC3/ISRC/INT0)
24
MCUAVCC
25
AGND
26
PA4
Port A 4 I/O line (PCINT4/ADC4/ICP1/DI/SDA/MOSI)
27
PA5
Port A 5 I/O line (PCINT5/ADC5/T1/USCK/SCL)
28
PA6
Port A 6 I/O line (PCINT6/ADC6/AIN0/SS)
29
PA7
Port A 7 I/O line (PCINT7/ADC7/AIN1)
30
PB7
Port B 7 I/O line (PCINT15/ADC10/OC1BX / RESET)
31
PB6
Port B 6 I/O line (PCINT14/ADC9/OC1AX/INT0)
32
PB5
Port B 5 I/O line (PCINT13/ADC8/OC1BW/XTAL2/CLKO)
33
PB4
Port B 4 I/O line (PCINT12/OC1AW/XTAL1/CLKI)
34
MCUVCC
35
GND
System ground
36
GND
Ground (optional)
37
GND
Ground (optional)
38
PB3
Port B 3 I/O line (PCINT11/OC1BV)
39
1.
Microcontroller analog supply voltage (referred to as AVCC pin in
Section 4. on page 26)
Analog ground
Microcontroller supply voltage (referred to as VCC pin in Section 4. on page 26)
Backside
Heat slug is connected to GND
This identifies the pins of the LIN SBC Atmel® ATA6624
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
2.
Absolute Maximum Ratings
Table 2-1.
Maximum Ratings of the SiP
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
±2
KV
CDM ESD STM 5.3.1
±1
KV
Machine Model ESD AEC-Q100-Rev.F (003)
±150
V
ESD according to IBEE LIN EMC
Test Spec. 1.0 following IEC 61000-4-2
- Pin VS, LIN, KL_15 (47k/100nF) to GND
- Pin WAKE (33 k serial resistor) to GND
±6
±5
KV
KV
±6
KV
ESD HBM following STM5.1 with 1.5k 100pF
- Pin VS, LIN, KL_15, WAKE to GND
Storage temperature
Operating temperature
(1)
Ts
–55
+150
°C
Tcase
–40
+125
°C
Thermal resistance junction to heat slug
Rthjc
Thermal resistance junctiion to ambient
Rthja
5
K/W
25
K/W
Thermal shutdown of VCC regulator
150
165
170
°C
Thermal shutdown of LIN output
150
165
170
°C
Thermal shutdown hysteresis
10
°C
Note:
1. Tcase means the temperature of the heat slug (backside). It is mandatory that this backside temperature is ≤ 125°C in
the application.
Table 2-2.
Maximum Ratings of the LIN-SBC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Supply voltage VS
VS
–0.3
Pulse time ≤ 500ms; Ta = 25°C
Output current IVCC ≤ 85mA
Pulse time ≤ 2min; Ta = 25°C
Output current IVCC ≤ 85mA
WAKE (with 33k serial resistor)
KL_15 (with 47k/100nF)
DC voltage
Transient voltage due to ISO7637 (coupling 1nF)
INH
- DC voltage
Typ.
Max.
Unit
+40
V
VS
+40
V
VS
27
V
–1
–150
+40
+100
V
V
–0.3
VS + 0.3
V
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
5
Table 2-2.
Maximum Ratings of the LIN-SBC (Continued)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
V
LIN
- DC voltage
–27
+40
Logic pins (RXD, TXD, EN, NRES, NTRIG,
WD_OSC, MODE, TM)
–0.3
+5.5
Output current NRES
INRES
PVCC DC voltage
VCC DC voltage
Table 2-3.
–0.3
–0.3
V
+2
mA
+5.5
+6.5
V
V
Maximum Ratings of the Microcontroller
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
Voltage on any pin except RESET with respect to
Ground
–0.5
MCUVCC + 0.5
V
Voltage on RESET with respect to GND
–0.5
13.0
V
Voltage on MCUVCC with respect to GND
–0.5
6.0
V
DC current per I/O pin
40.0
mA
DC current MCUVCC and GND pins
200.0
mA
Injection current at MCUVCC = 0V to 5V(2)
Notes: 1. Maximum current per port = ±30mA
±5.0
mA
2.
6
Functional corruption may occur
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
3.
LIN System-basis-chip Block
3.1
Features
●
●
●
●
●
●
Master and slave operation possible
Supply voltage up to 40V
Operating voltage VS = 5V to 27V
Typically 10µA supply current during sleep mode
Typically 57µA supply current in silent mode
Linear Low-drop voltage regulator, 85mA current capability:
●
Normal, fail-safe, and silent mode
●
In sleep mode VCC is switched off
●
●
●
●
●
●
●
●
●
●
●
●
●
3.2
VCC = 5.0V ±2%
VCC undervoltage detection (4ms reset time) and watchdog reset logical combined at open drain output NRES
Negative trigger input for watchdog
Boosting the voltage regulator possible with an external NPN transistor
LIN physical layer according to LIN 2.0, 2.1 specification and SAEJ2602-2
Wake-up capability via LIN-bus, wake pin, or Kl_15 pin
INH output to control an external voltage regulator or to switch off the master pull-up resistor
TXD time-out timer
Bus pin is overtemperature and short-circuit protected versus GND and battery
Adjustable watchdog time via external resistor
Advanced EMC and ESD performance
Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev.1.0”
Interference and damage protection according to ISO7637
Description
The LIN-SBC is a fully integrated LIN transceiver, which complies with the LIN 2.0, 2.1 and SAEJ2602-2 specifications. It
has a low-drop voltage regulator with a 5V/85mA output and a window watchdog. The voltage regulator is able to source up
to 85mA, but if necessary the output can be boosted by an external NPN transistor.
The LIN-SBC is designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics.
Improved slope control at the LIN-driver ensures secure data communication up to 20kBaud. Sleep mode and silent mode
guarantee very low current consumption.
ATA6616C/ATA6617C [DATASHEET]
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Figure 3-1. Block Diagram
VS
Normal and
Fail-safe
Mode
INH
PVCC
Normal
Mode
Receiver
RXD
+
RF Filter
LIN
WAKE
KL_15
PVCC
TXD
Edge
Detection
Wake-up
Bus Timer
Slew Rate Control
TXD
Time-out
Timer
Control Unit
EN
Short Circuit and
Overtemperature
Protection
Debounce
Time
Normal/Silent/
Fail-safe Mode
5V
Undervoltage
Reset
OUT
Watchdog
GND
PVCC
8
TM
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
PVCC
Mode Select
Internal Testing
Unit
MODE
VCC
NTRIG
NRES
Adjustable
Watchdog
Oscillator
WD_OSC
3.3
Functional Description
3.3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical
layer according to revision 2.x can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN
1.0, LIN 1.1, LIN 1.2, LIN 1.3), without any restrictions.
3.3.2
Supply Pin (VS)
The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS
falls below VSth < 4V in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the
voltage regulator is switched on (i.e., output capability).
The supply current is typically 10µA in sleep mode and 57µA in silent mode.
3.3.3
Ground Pin (GND)
The IC does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS.
The mandatory system ground is pin 5.
3.3.4
Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads up to 85mA. It is able to supply the microcontroller and other ICs
on the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore,
the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold
Vthun. To boost the maximum load current, an external NPN transistor with its base connected to the VCC pin and its emitter
connected to PVCC can be used.
3.3.5
Voltage Regulator Sense Pin (PVCC)
The PVCC is the sense input pin of the voltage regulator. For normal applications (i.e., when only using the internal output
transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected
to the output of this transistor, i.e., its emitter terminal.
3.3.6
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN
2.x specification are implemented. The allowed voltage range is between –27V and +40V. Reverse currents from the LIN
bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible
with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to
recessive bus state are slope controlled.
3.3.7
Input/Output Pin (TXD)
In normal mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to
ground in order to have a low LIN bus. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is
turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output. It is current-limited to < 8mA.
and is latched to low if the last wake-up event was from pin WAKE or KL_15.
3.3.8
TXD Dominant Time-out Function
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in
dominant state. If TXD is forced to low for longer than tDOM > 6ms, the LIN-bus driver is switched to recessive state.
To reactivate the LIN-bus driver, switch TXD to high (> 10µs).
ATA6616C/ATA6617C [DATASHEET]
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3.3.9
Output Pin (RXD)
The Output pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at
RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically
5k to VCC. The AC characteristics can be defined with an external load capacitor of 20pF.
The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V).
3.3.10 Enable Input Pin (EN)
The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in normal mode with transmission
paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 5V/85mA output
capability.
If EN is switched to low while TXD is still high, the device is forced to silent mode. No data transmission is then possible, and
the current consumption is reduced to IVS typ. 57µA. The VCC regulator has its full functionality.
If EN is switched to low while TXD is low, the device is forced to sleep mode. No data transmission is possible, and the
voltage regulator is switched off.
3.3.11 Wake Input Pin (WAKE)
The Wake Input pin is a high-voltage input used to wake up the device from sleep mode or silent mode. It is usually
connected to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10µA, is
implemented.
If a local wake-up is not needed for the application, connect the Wake pin directly to the VS pin.
3.3.12 Mode Input Pin (MODE)
Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of
the connected microcontroller, connect the MODE pin to VCC and the watchdog is switched off.
3.3.13 TM Input Pin
The TM pin is used for final production measurements at Atmel. In normal application, it must always be connected to GND.
3.3.14 KL_15 Pin
The KL_15 pin is a high-voltage input used to wake up the device from Sleep or silent mode. It is an edge-sensitive pin (lowto-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is
switched on. Although KL_15 pin is at high voltage (VBatt), it is possible to switch the IC into Sleep or silent mode. Connect
the KL_15 pin directly to GND if you do not need it. A debounce timer with a typical TdbKL_15 of 160µs is implemented.
The input voltage threshold can be adjusted by varying the external resistor due to the input current IKL_15. To protect this pin
against voltage transients, a serial resistor of 47k and a ceramic capacitor of 100nF are recommended. With this RC
combination you can increase the wake-up time TwKL_15 and, therefore, the sensitivity against transients on the ignition
KL_15.
The wake-up time can also be increased by using external capacitors with higher values.
3.3.15 INH Output Pin
The INH Output pin is used to switch on an external voltage regulator during Normal or Fail-safe Mode. The INH pin is
switched off in Sleep or silent mode. It is possible to switch off the external 1k master resistor via the INH pin for master
node applications. The INH pin is switched off during VCC undervoltage reset.
3.3.16 Reset Output Pin (NRES)
The Reset Output pin, an open-drain output, switches to low during VCC undervoltage or a watchdog failure.
3.3.17 WD_OSC Output Pin
The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34k
and 120k to adjust the watchdog oscillator time.
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ATA6616C/ATA6617C [DATASHEET]
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3.3.18 NTRIG Input Pin
The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers
the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger.
3.3.19 Wake-up Events from Sleep or Silent Mode
●
●
●
●
3.4
LIN-bus
WAKE pin
EN pin
KL_15
Modes of Operation
Figure 3-2. Modes of Operation
a: VS > 5V
Unpowered Mode
VBatt = 0V
b: VS < 4V
c: Bus wake-up event
d: Wake up from WAKE or KL_15 pin
a
b
e: NRES switches to low
b
Fail-safe Mode
VCC: 5V
With undervoltage monitoring
Communication: OFF
Watchdog: ON
b
e
EN = 1
b
c+d+e
EN = 1
c+d
Go to silent command
EN = 0
Silent Mode
TXD = 1
Normal Mode
VCC: 5V
With undervoltage monitoring
Communication: OFF
Watchdog: OFF
Local wake-up event
EN = 1
VCC: 5V
With undervoltage
monitoring
Go to sleep command
Communication: ON
Watchdog: ON
Table 3-1.
EN = 0
Sleep Mode
TXD = 0
VCC: switched off
Communication: OFF
Watchdog: OFF
Modes of Operation
Mode of
Operation
Transceiver
VCC
Watchdog
WD_OSC
INH
RXD
LIN
Fail-safe
Off
5V
On
1.23V
On
High, except
after wake up
Recessive
Normal
On
5V
On
1.23V
On
LIN
depending
TXD depending
Silent
Off
5V
Off
0V
Off
High
Recessive
Sleep
Off
0V
Off
0V
Off
0V
Recessive
ATA6616C/ATA6617C [DATASHEET]
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3.4.1
Normal Mode
This is the normal transmitting and receiving mode of the LIN interface in acoordance with the LIN specification LIN 2.x. The
voltage regulator is active and can source up to 85mA. The undervoltage detection is activated. The watchdog needs a
trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to fail-safe Mode.
3.4.2
Silent Mode
A falling edge at EN when TXD is high switches the IC into silent mode. The TXD Signal has to be logic high during the Mode
Select window (see Figure 3-3). The transmission path is disabled in silent mode. The overall supply current from VBatt is a
combination of the IVSsi = 57µA plus the VCC regulator output current IVCC.
The internal slave termination between the LIN pin and the VS pin is disabled in silent mode. Only a weak pull-up current
(typically 10µA) between the LIN pin and the VS pin is present. silent mode can be activated independently from the actual
level on the LIN, WAKE, or KL_15 pins. If an undervoltage condition occurs, NRES is switched to low, and the IC changes its
state to Fail-safe Mode.
A voltage lower than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on
the internal slave termination between the LIN pin and the VS pin.
Figure 3-3. Switch to Silent Mode
Normal Mode
Silent Mode
EN
TXD
Mode select window
td = 3.2μs
NRES
VCC
Delay time silent mode
td_silent = maximum 20μs
LIN
LIN switches directly to recessive mode
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and followed by a
rising edge at the LIN pin (see Figure 3-4 on page 13) results in a remote wake-up request. The device switches from silent
mode to Fail-safe Mode. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the
microcontroller (see Figure 3-4 on page 13). EN high can be used to switch directly to normal mode.
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ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Figure 3-4. LIN Wake-up from Silent Mode
Bus wake-up filtering time
tbus
Fail-safe mode
Normal mode
LIN bus
Node in silent mode
RXD
High
Low
High
TXD
Watchdog
VCC
voltage
regulator
Watchdog off
Start watchdog lead time td
Silent mode 5V
Fail safe mode 5V
Normal mode
EN High
EN
NRES
3.4.3
Undervoltage detection active
Sleep Mode
A falling edge at EN when TXD is low switches the IC into sleep mode. The TXD Signal has to be logic low during the Mode
Select window (Figure 3-5 on page 14). In order to avoid any influence to the LIN-pin during switching into sleep mode it is
possible to switch the EN up to 3.2µs earlier to LOW than the TXD. Therefore, the best and easiest way are two falling edges
at TXD and EN at the same time.The transmission path is disabled in sleep mode. The supply current IVSsleep from VBatt is
typically 10µA.
The VCC regulator and the INH output are switched off. NRES and RXD are low. The internal slave termination between the
LIN pin and VS pin is disabled, only a weak pull-up current (typically 10µA) between the LIN pin and the VS pin is present.
sleep mode can be activated independently from the current level on the LIN, WAKE, or KL_15 pin.
A voltage lower than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on
the internal slave termination between the LIN pin and the VS pin.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and followed by a
rising edge at pin LIN results in a remote wake-up request. The device switches from sleep mode to Fail-safe Mode.
The VCC regulator is activated, and the remote wake-up request is indicated by a low level at the RXD pin to interrupt the
microcontroller (see Figure 3-6 on page 15).
ATA6616C/ATA6617C [DATASHEET]
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Figure 3-5. Switch to Sleep Mode
Normal Mode
Sleep Mode
EN
Mode select window
TXD
td = 3.2μs
NRES
VCC
Delay time sleep mode
td_sleep = maximum 20μs
LIN
LIN switches directly to recessive mode
3.4.4
Fail-safe Mode
The device automatically switches to Fail-safe Mode at system power up and the voltage regulator is switched on (see
Figure 3-7 on page 17).The NRES output switches to low for tres = 4ms and gives a reset to the microcontroller. LIN
communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to normal mode.
A power down of VBatt (VS < 4V) during Silent or sleep mode switches the IC into Fail-safe Mode. A low level at NRES
switches into Fail-safe Mode directly. During fail-safe Mode the TXD pin is an output and signals the last wake-up source.
3.4.5
Unpowered Mode
If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor
(see Figure 3-7 on page 17). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from
Unpowered Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends
on the VCC capacitor and the load.
The NRES is low for the reset time delay treset. During this time, treset, no mode change is possible.
14
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Figure 3-6. LIN Wake-up from Sleep Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
Normal Mode
LIN bus
RXD
Low
TXD
VCC
voltage
regulator
On state
Off state
Regulator wake-up time
EN High
EN
Reset
time
NRES
Microcontroller
start-up time delay
Watchdog
Watchdog off
3.5
Wake-up Scenarios from Silent or Sleep Mode
3.5.1
Remote Wake-up via Dominant Bus State
Start watchdog lead time td
A voltage lower than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver.
A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain time period (> tBUS) and
followed by a rising edge at pin LIN result in a remote wake-up request. The device switches from Silent or sleep mode to
Fail-safe Mode. The VCC voltage regulator is/remains activated, the INH pin is switched to high, and the remote wake-up
request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller. A low level at the LIN pin in
the normal mode starts the bus wake-up filtering time, and if the IC is switched to Silent or sleep mode, it will receive a
wake-up after a positive edge at the LIN pin.
3.5.2
Local Wake-up via Pin WAKE
A falling edge at the WAKE pin followed by a low level maintained for a certain time period (> tWAKE) results in a local wakeup request. The device switches to fail-safe mode. The local wake-up request is indicated by a low level at the RXD pin to
generate an interrupt in the microcontroller and a strong pull down at TXD. When the WAKE pin is low, it is possible to switch
to Silent or sleep mode via pin EN. In this case, the wake-up signal has to be switched to high > 10µs before the negative
edge at WAKE starts a new local wake-up request.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
15
3.5.3
Local Wake-up via Pin KL_15
A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> tKL_15) results in a local wake-up
request. The device switches into the Fail-safe Mode. The extra long wake-up time ensures that no transients at KL_15
create a wake-up. The local wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the
microcontroller and a strong pull down at TXD. During high-level voltage at pin KL_15, it is possible to switch to Silent or
sleep mode via pin EN. In this case, the wake-up signal has to be switched to low > 250µs before the positive edge at KL_15
starts a new local wake-up request. With external RC combination, the time is even longer.
3.5.4
Wake-up Source Recognition
The device can distinguish between a local wake-up request (Wake or KL_15 pins) and a remote wake-up request (via LIN
bus). The wake-up source can be read on the TXD pin in Fail-safe Mode. A high level indicates a remote wake-up request
(weak pull up at the TXD pin); a low level indicates a local wake-up request (strong pull down at the TXD pin). The wake-up
request flag (signalled on the RXD pin) as well as the wake-up source flag (signalled on the TXD pin) is immediately reset if
the microcontroller sets the EN pin to high (see Figure 3-3 on page 12 and Figure 3-4 on page 13) and the IC is in normal
mode. The last wake-up source flag is stored and signalled in fail-safe mode at the TXD pin.
3.5.5
Fail-safe Features
●
During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the
chip temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of
Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off,
the VCC regulator works independently.
●
During a short-circuit from LIN to GND the IC can be switched into Sleep or silent mode. If the short-circuit
disappears, the IC starts with a remote wake-up.
●
The reverse current is very low < 2µA at the LIN pin during loss of VBatt. This is optimal behavior for bus systems
where some slave nodes are supplied from battery or ignition.
●
During a short circuit at VCC, the output limits the output current to IVCC_lin. Due to undervoltage, NRES switches to
low and sends a reset to the microcontroller. The IC switches into Fail-safe Mode. If the chip temperature exceeds the
value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on
again. Because of the Fail-safe Mode, the VCC voltage will switch on again even though EN is switched off from the
microcontroller. The microcontroller can start with its normal operation.
●
●
●
●
●
EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.
●
16
RXD pin is set floating if VBatt is disconnected.
TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected.
If TXD is short-circuited to GND, it is possible to switch to sleep mode via ENABLE after tdom > 20ms.
If the WD_OSC pin has a short-circuit to GND and the NTRIG signal has a period time > 27ms, the watchdog runs
with an internal oscillator and guarantees a reset after the second NTRIG signal at the latest.
If the resistor at WO_OSC pin is disconnected, the watchdog runs with an internal oscillator and guarantees a reset
after the second NTRIG signal at the latest.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Voltage Regulator
The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the
microcontroller. It is recommended to use an electrolythic capacitor with C ≥ 1.8µF and a ceramic capacitor with C = 100nF.
The values of these capacitors can be varied by the customer, depending on the application.
The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application. In
Figure 3-8 on page 17 the safe operating area of the Atmel® ATA6616C/ATA6617C is shown.
Figure 3-7. VCC Voltage Regulator: Ramp-up and Undervoltage Detection
VS
12V
5.5V
t
VCC
5V
Vthun
tVCC
tres_f
tReset
t
NRES
5V
t
Figure 3-8. Power Dissipation: Safe Operating Area VCC Output Current versus Supply Voltage VS at Different
Ambient Temperatures
90
80
Tamb = 100°C
70
IVCC (mA)
3.5.6
60
Tamb = 105°C
50
Tamb = 110°C
40
30
Tamb = 115°C
20
10
0
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
VS (V)
For programming purposes of the microcontroller it is potentially necessary to supply the VCC output via an external power
supply while the VS Pin of the system basis chip is disconnected. This will not affect the system basis chip.
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
17
3.6
Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window
of Twd. The trigger signal must exceed a minimum time ttrigmin > 200ns. If a triggering signal is not received, a reset signal will
be generated at output NRES. After a watchdog reset, the IC starts with the lead time. The timing basis of the watchdog is
provided by the internal oscillator. Its time period, Tosc, is adjustable via the external resistor Rwd_osc (34k to 120k).
During Silent or sleep mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as
lead time td. After wake up from Sleep or silent mode, the lead time td starts with the negative edge of the RXD output.
3.6.1
Typical Timing Sequence with RWD_OSC = 51k
The trigger signal Twd is adjustable between 20ms and 64ms using the external resistor RWD_OSC.
For example, with an external resistor of RWD_OSC = 51k ±1%, the typical parameters of the watchdog are as follows:
tosc = 0.405 RWD_OSC – 0.0004 (RWD_OSC)2 (RWD_OSC in k; tosc in µs)
tOSC = 19.6µs due to 51k
td = 7895 19.6µs = 155ms
t1 = 1053 19.6µs = 20.6ms
t2 = 1105 19.6µs = 21.6ms
tnres = constant = 4 ms
After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES stays low for the time treset
(typically 4ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead
time, td, follows the reset and is td = 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the
trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a
watchdog reset with tNRES = 4ms will reset the microcontroller after td = 155ms. The times t1 and t2 have a fixed relationship
between each other. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 21.6ms. To avoid
false triggering from glitches, the trigger pulse must be longer than tTRIG,min > 200ns. This slope serves to restart the
watchdog sequence. If the triggering signal fails in this open window t2, the NRES output will be drawn to ground. A
triggering signal during the closed window t1 immediately switches NRES to low.
Figure 3-9. Timing Sequence with RWD_OSC = 51k
VCC
Undervoltage Reset
NRES
Watchdog Reset
tnres = 4ms
treset = 4ms
td = 155ms
t1
t1 = 20.6ms
t2 = 21ms
twd
NTRIG
ttrig > 200ns
18
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
t2
3.6.2
Worst Case Calculation with RWD_OSC = 51 k
The internal oscillator has a tolerance of 20%. This means that t1 and t2 can vary by 20%. The worst case calculation for the
watchdog period twd is calculated below.
The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum t2.
t1,min = 0.8 t1 = 16.5ms, t1,max = 1.2 t1 = 24.8ms
t2,min = 0.8 t2 = 17.3ms, t2,max = 1.2 t2 = 26ms
twdmax = t1min + t2min = 16.5ms + 17.3ms = 33.8ms
twdmin = t1max = 24.8ms
twd = 29.3ms ±4.5ms (±15%)
A microcontroller with an oscillator tolerance of ±15% is sufficient to correctly supply the trigger inputs.
Table 3-2.
3.7
Typical Watchdog Timings
RWD_OSC
k
Oscillator
Period
tosc/µs
Lead
Time
td/ms
Closed
Window
t1/ms
Open Window
t2/ms
Trigger Period from
Microcontroller twd/ms
Reset Time
tnres/ms
34
13.3
105
14.0
14.7
19.9
4
51
19.61
154.8
20.64
21.67
29.32
4
91
33.54
264.80
35.32
37.06
50.14
4
120
42.84
338.22
45.11
47.34
64.05
4
Electrical Characteristics
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
1
1.1
1.2
1.3
Parameters
Test Conditions
Pin
Symbol
Min.
VS
VS
5
Sleep mode
VLIN > VS – 0.5V
VS < 14V (Tj = 25°C)
VS
IVSsleep
3
Sleep mode
VLIN > VS – 0.5V
VS < 14V (Tj = 125°C)
VS
IVSsleep
Bus recessive
VS < 14V (Tj = 25°C)
Without load at VCC
VS
Bus recessive
VS < 14V (Tj = 125°C)
Without load at VCC
Typ.
Max.
Unit
Type*
27
V
A
10
14
µA
B
5
11
16
µA
A
IVSsi
47
57
67
µA
B
VS
IVSsi
56
66
76
µA
A
VS Pin
Nominal DC voltage
range
Supply current in sleep
mode
Supply current in silent
mode
1.4
Bus recessive
Supply current in normal
VS < 14V
mode
Without load at VCC
VS
IVSrec
0.3
0.8
mA
A
1.5
Bus dominant
Supply current in normal
VS < 14V
mode
VCC load current 50mA
VS
IVSdom
50
53
mA
A
1.6
Supply current in failsafe Mode
VS
IVSfail
250
550
µA
A
Bus recessive
VS < 14V
Without load at VCC
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
19
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
1.7
1.8
2
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS undervoltage
threshold
VS
VSth
3.7
4.4
5
V
A
VS undervoltage
threshold hysteresis
VS
VSth_hys
V
A
RXD
IRXD
8
mA
A
0.4
V
A
7
k
A
0.2
RXD Output Pin
Normal mode
VLIN = 0V
VRXD = 0.4V
2.1
Low-level output sink
current
2.2
Low-level output voltage IRXD = 1mA
RXD
VRXDL
2.3
Internal resistor to VCC
RXD
RRXD
3
3
TXD Input/Output Pin
1.3
2.5
5
3.1
Low-level voltage input
TXD
VTXDL
–0.3
+0.8
V
A
3.2
High-level voltage input
TXD
VTXDH
2
VCC +
0.3V
V
A
3.3
Pull-up resistor
VTXD = 0V
TXD
RTXD
125
400
k
A
3.4
High-level leakage
current
VTXD = VCC
TXD
ITXD
–3
+3
µA
A
3.5
Fail-safe Mode
Low-level output sink
V = VS
current at local wake-up LIN
VWAKE = 0V
request
VTXD = 0.4V
TXD
ITXDwake
2
8
mA
A
EN
VENL
–0.3
+0.8
V
A
VCC +
0.3V
V
A
200
k
A
4
4.1
2.5
EN Input Pin
Low-level voltage input
4.2
High-level voltage input
4.3
Pull-down resistor
4.4
Low-level input current
5
250
EN
VENH
2
VEN = VCC
EN
REN
50
VEN = 0V
EN
IEN
–3
+3
µA
A
125
NTRIG Watchdog Input Pin
5.1
Low-level voltage input
NTRIG
VNTRIGL
–0.3
+0.8
V
A
5.2
High-level voltage input
NTRIG
VNTRIGH
2
VCC +
0.3V
V
A
5.3
Pull-up resistor
VNTRIG = 0V
NTRIG
RNTRIG
125
400
k
A
5.4
High-level leakage
current
VNTRIG = VCC
NTRIG
INTRIG
–3
+3
µA
A
6
250
Mode Input Pin
6.1
Low-level voltage input
MODE
VMODEL
–0.3
+0.8
V
A
6.2
High-level voltage input
MODE
VMODEH
2
VCC +
0.3V
V
A
6.3
Leakage current
MODE
IMODE
–3
+3
µA
A
VMODE = VCC or
VMODE = 0V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
20
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
7
Parameters
Pin
Symbol
Min.
IINH = –15mA
INIT
VINHH
VS –
0.75
INIT
RINH
INIT
IINHL
Typ.
Max.
Unit
Type*
VS
V
A
50
A
+3
µA
A
INH Output Pin
7.1
High-level voltage
7.2
Switch-on resistance
between VS and INH
7.3
Leakage current
8
Test Conditions
Sleep mode
VINH = 0V/27V, VS = 27V
30
–3
LIN Bus Driver: Bus Load Conditions:
Load 1 (Small): 1nF, 1k; Load 2 (Large): 10nF, 500; RRXD = 5k; CRXD = 20pF;
Load 3 (Medium): 6.8nF, 660 Characterized on Samples; 10.6 and 10.7 Specifies the Timing Parameters for Proper
Operation at 20Kbit/s, 10.8 and 10.9 at 10.4Kbit/s.
8.1
Driver recessive output
Load1/Load2
voltage
LIN
VBUSrec
8.2
Driver dominant voltage
VVS = 7V
Rload = 500
LIN
8.3
Driver dominant voltage
VVS = 18V
Rload = 500
8.4
Driver dominant voltage
8.5
0.9 VS
VS
V
A
V_LoSUP
1.2
V
A
LIN
V_HiSUP
2
V
A
VVS = 7.0V
Rload = 1000
LIN
V_LoSUP_1k
0.6
V
A
Driver dominant voltage
VVS = 18V
Rload = 1000
LIN
V_HiSUP_1k
0.8
V
A
8.6
Pull-up resistor to VS
The serial diode is
mandatory
LIN
RLIN
20
60
k
A
8.7
Voltage drop at the
serial diodes
In pull-up path with Rslave
ISerDiode = 10mA
LIN
VSerDiode
0.4
1.0
V
D
8.8
LIN current limitation
VBUS = VBatt_max
LIN
IBUS_LIM
40
120
200
mA
A
8.9
Input leakage current at
the receiver including
pull-up resistor as
specified
Input leakage current
Driver off
VBUS = 0V
VBatt = 12V
LIN
IBUS_PAS_do
–1
–0.35
mA
A
8.10
Leakage current LIN
recessive
Driver off
8V < VBatt < 18V
8V < VBUS < 18V
VBUS ≥ VBatt
LIN
IBUS_PAS_rec
8.11
Leakage current when
control unit
disconnected from
ground.
Loss of local ground
must not affect
communication in the
residual network.
GNDDevice = VS
VBatt = 12V
0V < VBUS < 18V
LIN
IBUS_NO_gnd
30
m
–10
10
20
µA
A
+0.5
+10
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
21
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
8.12
Leakage current at a
disconnected battery.
Node has to sustain the
VBatt disconnected
current that can flow
VSUP_Device = GND
under this condition.
0V < VBUS < 18V
Bus must remain
operational under this
condition.
Pin
Symbol
LIN
IBUS_NO_bat
LIN
VBUS_CNT
Min.
Typ.
Max.
Unit
Type*
0.1
2
µA
A
0.5
VS
0.525
VS
V
A
0.4 VS
V
A
V
A
0.175
VS
V
A
9
LIN Bus Receiver
9.1
Center of receiver
threshold
9.2
Receiver dominant state VEN = 5V
LIN
VBUSdom
9.3
Receiver recessive
state
VEN = 5V
LIN
VBUSrec
0.6 VS
9.4
Receiver input
hysteresis
Vhys = Vth_rec – Vth_dom
LIN
VBUShys
0.028
VS
9.5
Pre_Wake detection LIN
High-level input voltage
LIN
VLINH
VS – 2V
VS +
0.3V
V
A
9.6
Pre_Wake detection LIN
Activates the LIN receiver
Low-level input voltage
LIN
VLINL
–27
VS –
3.3V
V
A
10
Internal Timers
VBUS_CNT =
(Vth_dom + Vth_rec)/2
0.475
VS
0.1 VS
10.1
Dominant time for wakeVLIN = 0V
up via LIN bus
LIN
tbus
30
90
150
µs
A
10.2
Time delay for mode
change from Fail-safe
into normal mode via
EN pin
VEN = 5V
EN
tnorm
5
15
20
µs
A
10.3
Time delay for mode
change from normal
V = 0V
mode to sleep mode via EN
EN pin
EN
tsleep
2
7
12
µs
A
10.4
TXD dominant time-out
VTXD = 0V
time
TXD
tdom
6
13
20
ms
A
10.5
Time delay for mode
change from silent
V = 5V
mode into normal mode EN
via EN
EN
ts_n
5
15
40
µs
A
Duty cycle 1
THRec(max) = 0.744 VS
THDom(max) = 0.581 VS
VS = 7.0V to 18V
tBit = 50µs
D1 = tbus_rec(min)/(2 tBit)
LIN
D1
0.396
Duty cycle 2
THRec(min) = 0.422 VS
THDom(min) = 0.284 VS
VS = 7.6V to 18V
tBit = 50µs
D2 = tbus_rec(max)/(2 tBit)
LIN
D2
10.6
10.7
A
0.581
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
A
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Duty cycle 3
THRec(max) = 0.778 VS
THDom(max) = 0.616 VS
VS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min)/(2 tBit)
LIN
D3
0.417
10.9
Duty cycle 4
THRec(min) = 0.389 VS
THDom(min) = 0.251 VS
VS = 7.6V to 18V
tBit = 96µs
D4 = tbus_rec(max)/(2 tBit)
LIN
D4
10.10
Slope time falling and
rising edge at LIN
VS = 7.0V to 18V
LIN
tSLOPE_fall
tSLOPE_rise
10.8
11
Max.
Unit
Type*
A
0.590
3.5
A
22.5
µs
A
6
µs
A
+2
µs
A
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions CRXD = 20pF
11.1
Propagation delay of
V = 7.0V to 18V
receiver (Figure 3-10 on S
trx_pd = max(trx_pdr , trx_pdf)
page 25)
RXD
trx_pd
11.2
Symmetry of receiver
V = 7.0V to 18V
propagation delay rising S
trx_sym = trx_pdr – trx_pdf
edge minus falling edge
RXD
trx_sym
12
Typ.
–2
NRES Open Drain Output Pin
12.1
Low-level output voltage
VS ≥ 5.5V
INRES = 1mA
NRES
VNRESL
0.14
V
A
12.2
Low-level output low
10k to 5V
VCC = 0V
NRES
VNRESLL
0.14
V
A
12.3
Undervoltage reset time
VS ≥ 5.5V
CNRES = 20pF
NRES
treset
2
6
ms
A
12.4
Reset debounce time
for falling edge
VS ≥ 5.5V
CNRES = 20pF
NRES
tres_f
1.5
10
µs
A
13
Watchdog Oscillator
IWD_OSC = –200µA
VVS ≥ 4V
WD_
OSC
VWD_OSC
1.13
1.33
V
A
WD_
OSC
ROSC
34
120
k
A
4
13.1
Voltage at WD_OSC in
normal mode
13.2
Possible values of
resistor
13.3
Oscillator period
ROSC = 34k
tOSC
10.65
13.3
15.97
µs
A
13.4
Oscillator period
ROSC = 51k
tOSC
15.68
19.6
23.52
µs
A
13.5
Oscillator period
ROSC = 91k
tOSC
26.83
33.5
40.24
µs
A
13.6
Oscillator period
ROSC = 120k
tOSC
34.2
42.8
51.4
µs
A
14
1.23
Watchdog Timing Relative to tOSC
14.1
Watchdog lead time
after reset
td
7895
cycles
A
14.2
Watchdog closed
window
t1
1053
cycles
A
14.3
Watchdog open window
t2
1105
cycles
A
14.4
Watchdog reset time
NRES
ms
A
NRES
tnres
3.2
4
4.8
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA6616C/ATA6617C [DATASHEET]
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23
3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
15
KL_15 Pin
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
15.1
High-level input voltage Positive edge initializes a
RV = 47 k
wake-up
KL_15
VKL_15H
4
VS +
0.3V
V
A
15.2
Low-level input voltage
RV = 47 k
KL_15
VKL_15L
–1
+2
V
A
15.3
KL_15 pull-down
current
VS < 27V
VKL_15 = 27V
KL_15
IKL_15
50
65
µA
A
15.4
Internal debounce time
Without external capacitor
KL_15
TdbKL_15
80
160
250
µs
A
15.5
KL_15 wake-up time
RV = 47k, C = 100nF
KL_15
TwKL_15
0.4
2
4.5
ms
C
16
WAKE Pin
16.1
High-level input voltage
WAKE
VWAKEH
VS – 1V
VS +
0.3V
V
A
16.2
Low-level input voltage
Initializes a wake-up signal WAKE
VWAKEL
–1
VS –
3.3V
V
A
16.3
WAKE pull-up current
VS < 27V
VWAKE = 0V
WAKE
IWAKE
–30
µA
A
16.4
High-level leakage
current
VS = 27V
VWAKE = 27V
WAKE
IWAKEL
–5
+5
µA
A
16.5
Time of low pulse for
wake-up via WAKE pin
VWAKE = 0V
WAKE
IWAKEL
30
150
µs
A
5.5V < VS < 18V
(0mA to 50mA)
VCC
VCCnor
4.9
5.1
V
A
6V < VS < 18V
(0mA to 85mA)
VCC
VCCnor
4.9
5.1
V
C
VS – VD
5.1
V
A
250
mV
A
600
mV
A
200
mV
A
17
17.1
–10
70
VCC Voltage Regulator, PVCC = VCC
Output voltage VCC
17.2
Output voltage VCC at
low VS
4V < VS < 5.5V
VCC
VCClow
17.3
Regulator drop voltage
VS > 4V
IVCC = –20mA
VS,
VCC
VD1
17.4
Regulator drop voltage
VS > 4V
IVCC = –50mA
VS,
VCC
VD2
17.5
Regulator drop voltage
VS > 3.3V
IVCC = –15mA
VS,
VCC
VD3
17.6
Line regulation
5.5V < VS < 18V
VCC
VCCline
0.1
0.2
%
A
17.7
Load regulation
5mA < IVCC < 50mA
VCC
VCCload
0.1
0.5
%
A
17.8
Power supply ripple
rejection
10Hz to 100kHz
CVCC = 10µF
VS = 14V, IVCC = –15mA
VCC
dB
D
17.9
Output current limitation VS > 5.5V
mA
A
µF
D
17.10 External load capacity
0.2 < ESR < 5 at
100kHz
for phase margin ≥ 60°
400
50
VCC
IVCClim
–240
–130
VCC
Cload
1.8
10
–85
ESR < 0.2 at 100kHz
for phase margin ≥ 30°
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
24
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3.7
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
17.11
VCC undervoltage
threshold
Referred to VCC
VS > 5.5V
VCC
VthunN
4.2
17.12
Hysteresis of
undervoltage threshold
Referred to VCC
VS > 5.5V
VCC
Vhysthun
250
17.13
Ramp-up time VS >
5.5V to VCC = 5V
CVCC = 2.2µF
Iload = –5mA at VCC
VCC
tVCC
130
Max.
Unit
Type*
4.8
V
A
mV
A
µs
A
300
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 3-10. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node1
THRec(max)
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
trx_pdf(2)
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4.
Atmel ATtiny87/ATtiny167 Microcontroller Block for Atmel ATA6616C/ATA6617C
4.1
Features
●
●
●
High performance, low power AVR® 8-bit microcontroller
Advanced RISC architecture
●
123 powerful instructions – most single clock cycle execution
●
32 8 general purpose working registers
●
Fully static operation
Non-volatile program and data memories
●
8Kbytes/16Kbytes of in-system programmable (ISP) program memory flash
●
512 bytes in-system programmable EEPROM
●
512 bytes internal SRAM
●
Programming lock for self-programming flash program and EEPROM data security
●
Low size LIN/UART software in-system programmable
●
●
●
26
Endurance: 100,000 write/erase cycles
Peripheral features
●
LIN 2.1 and 1.3 controller or 8-bit UART
●
8-bit asynchronous Timer/Counter0:
●
●
Endurance: 10,000 write/erase cycles
●
10-bit clock prescaler
●
1 output compare or 8-bit PWM channel
16-bit synchronous Timer/Counter1:
●
10-bit clock prescaler
●
External event counter
●
2 output compares units or 16-bit PWM channels each driving up to 4 output pins
●
Master/slave SPI serial interface,
●
Universal serial interface (USI) with start condition detector (master/slave SPI, TWI,...)
●
10-bit ADC:
●
11 Single ended channels
●
8 differential ADC channel pairs with programmable gain (8x or 20x)
●
On-chip analog comparator with selectable voltage reference
●
100µA ±10% current source (LIN node identification)
●
On-chip temperature sensor
●
Programmable watchdog timer with separate on-chip oscillator
Special microcontroller features
●
Dynamic clock switching (external/internal RC/watchdog clock) for power control, EMC reduction
●
DebugWIRE on-chip debug (OCD) system
●
Hardware in-system programmable (ISP) via SPI Port
●
External and internal interrupt sources
●
Interrupt and wake-up on pin change
●
Low power idle, ADC noise reduction, and power-down modes
●
Enhanced power-on reset circuit
●
Programmable brown-out detection circuit
●
Internal calibrated RC oscillator 8MHz
●
4MHz to 16MHz and 32KHz crystal/ceramic resonator oscillators
ATA6616C/ATA6617C [DATASHEET]
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●
●
I/O and Packages
●
16 programmable I/O lines
●
20-pin SOIC, 32-pad QFN and 20-pin TSSOP
Operating voltage:
●
●
2.7V to 5.5V for Atmel® ATtiny87/ATtiny167
Speed Grade:
●
0MHz to 8MHz at 2.7V to 5.5V (automotive temperature range: –40°C to +125°C)
●
0MHz to 16MHz at 4.5V to 5.5V (automotive temperature range: –40°C to +125°C)
4.2
Description
4.2.1
Comparison between Atmel ATtiny87 and Atmel ATtiny167
Atmel ATtiny87 and Atmel ATtiny167 are hardware and software compatible. They differ only in memory sizes as shown in
Table 4-1.
Table 4-1.
4.2.2
Memory Size Summary
Device
Flash
EEPROM
SRAM
Interrupt Vector size
ATtiny167
16KBytes
512Bytes
512Bytes
2-instruction-words / vector
ATtiny87
8KBytes
512Bytes
512Bytes
2-instruction-words / vector
Part Description
The Atmel ATtiny87/167 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture.
By executing powerful instructions in a single clock cycle, the Atmel ATtiny87/167 achieves throughputs approaching 1MIPS
per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The Atmel ATtiny87/167 provides the following features: 8K/16Kbyte of in-system programmable flash, 512bytes EEPROM,
512bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare
modes, one 8-bit high speed Timer/Counter, universal serial interface, a LIN controller, internal and external interrupts,
a 11-channel, 10-bit ADC, a programmable watchdog timer with internal oscillator, and three software selectable power
saving modes. The idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, analog comparator, and
interrupt system to continue functioning. The power-down mode saves the register contents, disabling all chip functions until
the next interrupt or hardware reset. The ADC noise reduction mode stops the CPU and all I/O modules except ADC, to
minimize switching noise during ADC conversions.
The device is manufactured using Atmel high density non-volatile memory technology. The on-chip ISP flash allows the
program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory
programmer or by an on-chip boot code running on the AVR core. The boot program can use any interface to download the
application program in the flash memory.
By combining an 8-bit RISC CPU with in-system self-programmable flash on a monolithic chip, the Atmel ATtiny87/167 is a
powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The Atmel ATtiny87/167 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
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4.2.3
Automotive Quality Grade
The Atmel® ATtiny87/167 have been developed and manufactured according to the most stringent requirements of the
international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive
characterization (temperature and voltage). The quality and reliability of the Atmel ATtiny87/167 have been verified during
regular product qualification as per AEC-Q100 grade 1.
As indicated in the ordering information paragraph, this document refers only to grade 1 products, for grade 0 products refer
to appendix A.
Table 4-2.
4.2.4
Temperature Grade Identification for Automotive Products
Temperature
Temperature
Identifier
Comments
–40°C/+125°C
Z
Grade 1
–40°C/+150°C
D
Grade 0
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR® microcontrollers
manufactured on the same process technology. Min. and Max values will be available after the device is characterized.
28
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4.2.5
Block Diagram
Figure 4-1. Block Diagram
GND
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits/
Clock
Generation
VCC
Power
Supervision
POR/BOD
and
RESET
debugWIRE
Flash
SRAM
Program
Logic
AVR CPU
EEPROM
AVCC
DATA BUS
AREF
Timer/
Counter-1
Timer/
Counter-0
SPI and USI
Analog
Comparator
A/D Conv.
Internal
Voltage
References
2
11
PORT B (8)
PORT A (8)
LIN/UART
RESET
XTAL[1; 2]
PB[0 to 7]
4.2.6
PA[0 to 7]
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
4.2.7
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code
examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors
include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C
compiler documentation for more details.
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4.3
AVR CPU Core
4.3.1
Overview
This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and
handle interrupts.
Figure 4-2. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status and
Control
32 x 8
General
Purpose
Registers
Control Lines
Indirect Addressing
Instruction
Decoder
Direct Addressing
Instruction
Register
ALU
Interrupt
Unit
Watchdog
Timer
A.D.C.
Analog
Comparator
I/O Module 1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
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In order to maximize performance and parallelism, the AVR® uses a harvard architecture – with separate memories and
buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions
to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This
allows single-cycle arithmetic logic unit (ALU) operation.
In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored
back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling
efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in
flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect
information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole
address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a
16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and
the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through
the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance
with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions.
The I/O memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5F.
4.3.2
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a
single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are
executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some
implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and
fractional format. See the “instruction set” section for a detailed description.
4.3.3
Status Register
The status register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the status register is
updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for
using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine and restored when returning from an
interrupt. This must be handled by software.
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4.3.3.1 SREG – AVR Status Register
The AVR® status register – SREG – is defined as:
Bit
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then
performed in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is
set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the
SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit
from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic. See the
“instruction set description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the
“Instruction set description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the “Instruction Set Description” for
detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed
information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed
information.
32
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4.3.4
General Purpose Register File
The register file is optimized for the AVR® enhanced RISC instruction set. In order to achieve the required performance and
flexibility, the following input/output schemes are supported by the register file:
● One 8-bit output operand and one 8-bit result input
●
●
●
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 4-3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-3. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle
instructions.
As shown in Figure 4-3, each register is also assigned a data memory address, mapping them directly into the first 32
locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the
file.
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4.3.4.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address
pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described
in Figure 4-4.
Figure 4-4. The X-, Y-, and Z-registers
15
X-register
7
XH
XL
0
7
R27 (0x1B)
15
Y-register
7
Z-register
7
R31 (0x1F)
0
R26 (0x1A)
YH
YL
0
7
R29 (0x1D)
15
0
0
0
R28 (0x1C)
ZH
ZL
0
7
0
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and
automatic decrement (see the instruction set reference for details).
4.3.5
Stack Pointer
The stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after
interrupts and subroutine calls. The stack pointer register always points to the top of the stack. Note that the stack is
implemented as growing from higher memory locations to lower memory locations. This implies that a stack PUSH command
decreases the stack pointer.
The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are located. This stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The stack pointer must be set to point above 0x60. The stack pointer is decremented by one when data is pushed onto the
stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the stack with
subroutine call or interrupt. The stack pointer is incremented by one when data is popped from the stack with the POP
instruction, and it is incremented by two when data is popped from the stack with return from subroutine RET or return from
interrupt RETI.
The AVR® stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only
SPL is needed. In this case, the SPH register will not be present
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4.3.5.1 SPH and SPL – Stack Pointer Register
Bit
Read/Write
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
4.3.6
ISRAM end (See Table 4-3 on page 38)
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR® CPU is driven by the CPU
clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast
access register file concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 4-5. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 4-6 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 4-6. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
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4.3.7
Reset and Interrupt Handling
The AVR® provides several different interrupt sources. These interrupts and the separate reset vector each have a separate
program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic
one together with the global interrupt enable bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. The complete
list of vectors is shown in Section 4.8 “Interrupts” on page 76. The list also determines the priority levels of the different
interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the
external interrupt request 0.
4.3.7.1 Interrupt behavior
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can
write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
The I-bit is automatically set when a return from interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these
interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine,
and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt
flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and
remembered until the global interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any
pending interrupt is served.
Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from
an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed
after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can
be used to avoid interrupts during the timed EEPROM write sequence.
36
ATA6616C/ATA6617C [DATASHEET]
9132J–AUTO–01/15
Assembly Code Example
in
cli
sbi
sbi
out
r16, SREG
; store SREG value
; disable interrupts during timed sequence
EECR, EEMPE ; start EEPROM write
EECR, EEPE
SREG, r16
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1
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