ATMEGA169A-MCHR

Atmel ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash DATASHEET SUMMARY Features • High performance, low power Atmel® AVR® 8-Bit Microcontroller • Advanced RISC architecture – 130 powerful instructions – most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 16MIPS throughput at16MHz (Atmel ATmega169A/169PA/649A/649P) – Up to 20 MIPS throughput at 20MHz (Atmel ATmega329A/329PA/3290A/3290PA/6490A/6490P) – On-chip 2-cycle multiplier • High endurance non-volatile memory segments – In-system self-programmable flash program memory • 16Kbytes (Atmel ATmega169A/ATmega169PA) • 32Kbytes (Atmel ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA) • 64Kbytes (Atmel ATmega649A/ATmega649P/ATmega6490A/ATmega6490P) – EEPROM • 512bytes (ATmega169A/ATmega169PA) • 1Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA) • 2Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P) – Internal SRAM • 1Kbytes (ATmega169A/ATmega169PA) • 2Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA) • 4Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P) – Write/erase cyles: 10,000 flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C (1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True read-while-write operation – Programming lock for software security • Atmel QTouch® library support – Capacitive touch buttons, sliders and wheels – Atmel QTouch and QMatrix acquisition – Up to 64 sense channels • JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan capabilities according to the JTAG standard – Extensive on-chip debug support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral features – 4 × 25 segment LCD driver (ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P) – 4 × 40 segment LCD driver (ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P) – Two 8-bit Timer/Counters with Separate Prescaler and Compare mode – One 16-bit Timer/Counter with Separate Prescaler, Compare mode, and Capture mode 8284FS–AVR–07/2014 – Real Time Counter with separate oscillator – Four PWM channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip oscillator – On-chip analog comparator – Interrupt and Wake-up on pin change • Special microcontroller features – Power-on reset and programmable Brown-out detection – Internal calibrated oscillator – External and internal interrupt sources – Five sleep modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and packages – 54/69 programmable I/O lines – 64/100-lead TQFP, 64-pad QFN/MLF, and 64-pad DRQFN • Speed Grade: – ATmega169A/169PA/649A/649P: • 0 - 16MHz @ 1.8 - 5.5V – ATmega3290A/3290PA/6490A/6490P: • 0 - 20MHz @ 1.8 - 5.5V • Temperature range: – -40°C to 85°C industrial • Ultra-low power consumption (picoPower® devices) – Active mode: • 1MHz, 1.8V: 215µA • 32kHz, 1.8V: 8µA (including oscillator) • 32kHz, 1.8V: 25µA (including oscillator and LCD) – Power-down mode: • 0.1µA at 1.8V – Power-save mode: • 0.6µA at 1.8V (Including 32kHz RTC) • 750nA at 1.8V ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 2 1. Pin configurations 1.1 Pinout - 64A (TQFP) and 64M1 (QFN/MLF) LCDCAP 1 (RXD/PCINT0) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (COM0) PA1 (COM1) PA2 (COM2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout Atmel ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P. 64 Figure 1-1. 48 PA3 (COM3) 47 PA4 (SEG0) INDEX CORNER (SCK/PCINT9) PB1 11 38 PC3 (SEG9) (MOSI/PCINT10) PB2 12 37 PC2 (SEG10) (MISO/PCINT11) PB3 13 36 PC1 (SEG11) (OC0A/PCINT12) PB4 14 35 PC0 (SEG12) (OC1A/PCINT13) PB5 15 34 PG1 (SEG13) (OC1B/PCINT14) PB6 16 33 PG0 (SEG14) (SEG15) PD7 32 39 PC4 (SEG8) (SEG16) PD6 31 10 (SEG17) PD5 30 (SS/PCINT8) PB0 29 40 PC5 (SEG7) (SEG18) PD4 9 28 (CLKO/PCINT7) PE7 (SEG19) PD3 41 PC6 (SEG6) 27 8 (SEG20) PD2 (DO/PCINT6) PE6 26 42 PC7 (SEG5) (INT0/SEG21) PD1 7 25 (DI/SDA/PCINT5) PE5 (ICP1/SEG22) PD0 43 PG2 (SEG4) 24 6 (TOSC1) XTAL1 (USCK/SCL/PCINT4) PE4 23 44 PA7 (SEG3) (TOSC2) XTAL2 5 22 (AIN1/PCINT3) PE3 GND 45 PA6 (SEG2) VCC 21 4 RESET/PG5 20 (XCK/AIN0/PCINT2) PE2 (T0/SEG23) PG4 19 46 PA5 (SEG1) (T1/SEG24) PG3 18 3 (OC2A/PCINT15) PB7 17 (TXD/PCINT1) PE1 ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 3 1.2 Pinout - 100A (TQFP) Figure 1-2. Pinout Atmel ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P. AVCC AGND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) DNC DNC PH7 (PCINT23/SEG36) PH6 (PCINT22/SEG37) PH5 (PCINT21/SEG38) PH4 (PCINT20/SEG39) DNC DNC GND VCC DNC PA0 (COM0) PA1 (COM1) PA2 (COM2) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 TQFP LCDCAP 1 75 PA3 (COM3) (RXD/PCINT0) PE0 2 74 PA4 (SEG0) 73 PA5 (SEG1) INDEX CORNER (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 72 PA6 (SEG2) (AIN1/PCINT3) PE3 5 71 PA7 (SEG3) (USCK/SCL/PCINT4) PE4 6 70 PG2 (SEG4) (DI/SDA/PCINT5) PE5 7 69 PC7 (SEG5) (DO/PCINT6) PE6 8 68 PC6 (SEG6) (CLKO/PCINT7) PE7 9 67 DNC VCC 10 66 PH3 (PCINT19/SEG7) GND 11 65 PH2 (PCINT18/SEG8) 45 46 47 48 49 50 (SEG23) PD3 (SEG22) PD4 (SEG21) PD5 (SEG20) PD6 (SEG19) PD7 PG0 (SEG18) 44 51 (SEG24) PD2 25 (INT0/SEG25) PD1 (OC1B/PCINT14) PB6 43 PG1 (SEG17) (ICP1/SEG26) PD0 52 42 24 DNC PC0 (SEG16) (OC1A/PCINT13) PB5 41 53 (PCINT30/SEG27) PJ6 23 40 PC1 (SEG15) (OC0A/PCINT12) PB4 (PCINT29/SEG28) PJ5 54 (PCINT28/SEG29) PJ4 22 39 PC2 (SEG14) (MISO/PCINT11) PB3 38 55 (PCINT27/SEG30) PJ3 21 37 PC3 (SEG13) (MOSI/PCINT10) PB2 (PCINT26/SEG31) PJ2 (SCK/PCINT9) PB1 56 36 PC4 (SEG12) 20 DNC 57 35 19 DNC PC5 (SEG11) (SS/PCINT8) PB0 (TOSC1) XTAL1 58 34 18 33 DNC DNC (TOSC2) XTAL2 59 32 DNC 17 GND 60 DNC 31 DNC 30 DNC 16 VCC 61 RESET/PG5 15 29 DNC DNC (T0/SEG32) PG4 62 28 14 (T1/SEG33) PG3 PH0 (PCINT16/SEG10) (PCINT25/SEG34) PJ1 27 PH1 (PCINT17/SEG9) 63 26 64 13 DNC 12 (OC2A/PCINT15) PB7 DNC (PCINT24/SEG35) PJ0 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 4 Pinout - 64MC (DRQFN) Pinout Atmel ATmega169A/ATmega169PA. A4 A22 B4 B19 A21 B5 B18 B6 A20 B17 A5 A6 A7 A19 B7 A34 B29 A33 B30 A31 B28 A32 B26 A30 B27 B3 A2 A3 A4 A22 B19 A21 B4 B18 B5 A20 B17 B6 A5 A6 A7 A19 B7 B16 A18 B8 A10 B9 A11 B10 A12 B11 A13 B12 A14 B13 A15 B14 A16 B15 A17 A9 B2 A8 A17 B15 B16 A18 A8 B21 A23 B20 A9 B3 A23 B20 B1 A10 B8 B21 B22 A24 B10 A11 B9 B2 A3 A1 A25 A13 B11 A12 B22 A24 A16 B14 A15 A25 B1 A2 Table 1-1. A26 A26 A1 B23 A27 B24 Bottom view A27 B23 A34 B30 A33 B29 A32 B28 A31 B27 A30 B26 A29 B25 A28 B24 Top view A28 B25 A29 Figure 1-3. B13 A14 B12 1.3 DRQFN-64 Pinout ATmega169A/ATmega169PA. A1 PE0 A9 PB7 A18 PG1 (SEG13) A26 PA2 (COM2) B1 VLCDCAP B8 PB6 B16 PG0 (SEG14) B23 PA3 (COM3) A2 PE1 A10 PG3 A19 PC0 (SEG12) A27 PA1 (COM1) B2 PE2 B9 PG4 B17 PC1 (SEG11) B24 PA0 (COM0) A3 PE3 A11 RESET A20 PC2 (SEG10) A28 VCC B3 PE4 B10 VCC B18 PC3 (SEG9) B25 GND A4 PE5 A12 GND A21 PC4 (SEG8) A29 PF7 B4 PE6 B11 XTAL2 (TOSC2) B19 PC5 (SEG7) B26 PF6 A5 PE7 A13 XTAL1 (TOSC1) A22 PC6 (SEG6) A30 PF5 B5 PB0 B12 PD0 (SEG22) B20 PC7 (SEG5) B27 PF4 A6 PB1 A14 PD1 (SEG21) A23 PG2 (SEG4) A31 PF3 B6 PB2 B13 PD2 (SEG20) B21 PA7 (SEG3) B28 PF2 A7 PB3 A15 PD3 (SEG19) A24 PA6 (SEG2) A32 PF1 B7 PB5 B14 PD4 (SEG18) B22 PA4 (SEG0) B29 PF0 A8 PB4 A16 PD5 (SEG17) A25 PA5 (SEG1) A33 AREF B15 PD7 (SEG15) B30 AVCC A17 PD6 (SEG16) A34 GND ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 5 2. Overview The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a low-power CMOS 8-bit microcontroller based on the Atmel®AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block diagram GND Block diagram. PF0 - PF7 VCC PA0 - PA7 DATA DIR. REG. PORTF DATA REGISTER PORTF PC0 - PC7 PORTA DRIVERS PORTF DRIVERS PORTC DRIVERS DATA DIR. REG. PORTA DATA REGISTER PORTA XTAL2 Figure 2-1. XTAL1 2.1 DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC AGND CALIB. OSC ADC INTERNAL OSCILLATOR AREF STACK POINTER WATCHDOG TIMER ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER BOUNDARYSCAN INSTRUCTION REGISTER TIMING AND CONTROL LCD CONTROLLER/ DRIVER TIMER/ COUNTERS GENERAL PURPOSE REGISTERS X PROGRAMMING LOGIC INSTRUCTION DECODER CONTROL LINES + - INTERRUPT UNIT ALU EEPROM STATUS REGISTER AVR CPU ANALOG COMPARATOR Z Y RESET DATA DIR. REG. PORTH DATA REGISTER PORTH PROGRAM COUNTER DATA DIR. REG. PORTJ DATA REGISTER PORTJ PORTH DRIVERS PORTJ DRIVERS PJ0 - PJ6 PH0 - PH7 OSCILLATOR JTAG TAP USART UNIVERSAL SERIAL INTERFACE DATA REGISTER PORTE DATA DIR. REG. PORTE PORTE DRIVERS PE0 - PE7 SPI DATA REGISTER PORTB DATA DIR. REG. PORTB PORTB DRIVERS PB0 - PB7 DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS PD0 - PD7 DATA REG. PORTG DATA DIR. REG. PORTG PORTG DRIVERS PG0 - PG4 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 6 single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P provides the following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K bytes EEPROM, 1K/2K/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD controller with internal contrast control, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching noise during ADC conversions. In Standby mode, the XTAL/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using the Atmel high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 7 2.2 Comparison between Atmel ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P Table 2-1. Differences between: ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P. Device Flash EEPROM RAM LCD Segments ATmega169A 16Kbyte 512Bytes 1Kbyte 4 × 25 ATmega169PA 16Kbyte 512Bytes 1Kbyte 4 × 25 ATmega329A 32Kbyte 1Kbyte 2Kbyte 4 × 25 ATmega329PA 32Kbyte 1Kbyte 2Kbyte 4 × 25 ATmega3290A 32Kbytes 1Kbyte 2Kbyte 4 × 40 ATmega3290PA 32Kbyte 1Kbyte 2Kbyte 4 × 40 ATmega649A 64Kbyte 2Kbyte 4Kbyte 4 × 25 ATmega649P 64Kbyte 2Kbyte 4Kbyte 4 × 25 ATmega6490A 64Kbyte 2Kbyte 4Kbyte 4 × 40 ATmega6490P 64Kbyte 2Kbyte 4Kbyte 4 × 40 ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 8 2.3 Pin descriptions The following section describes the I/O-pin special functions. 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7...PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 72. 2.3.4 Port B (PB7...PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 73. 2.3.5 Port C (PC7...PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 76. 2.3.6 Port D (PD7...PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 77. 2.3.7 Port E (PE7...PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 9 are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 79. 2.3.8 Port F (PF7...PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 2.3.9 Port G (PG5...PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 83. 2.3.10 Port H (PH7...PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega3290PA/6490P as listed on page 85. 2.3.11 Port J (PJ6...PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3290PA/6490P as listed on page 87. 2.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and reset characteristics” on page 332. Shorter pulses are not guaranteed to generate a reset. 2.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.14 XTAL2 Output from the inverting Oscillator amplifier. ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 10 2.3.15 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.16 AREF This is the analog reference pin for the A/D Converter. 2.3.17 LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Figure 24-2, if the LCD module is enabled and configured to use internal power. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value. ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 11 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. 1. Data retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 6. Capacitive touch sensing The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. 7. Register summary Note: Address Registers with bold type only available in Atmel ATmega3290A/3290PA/6490A/6490P. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) LCDDR19 Name SEG339 SEG338 SEG337 SEG336 SEG335 SEG334 SEG333 SEG332 236 (0xFE) LCDDR18 SEG331 SEG330 SEG329 SEG328 SEG327 SEG326 SEG325 SEG324 236 (0xFD) LCDDR17 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 236 (0xFC) LCDDR16 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 236 (0xFB) LCDDR15 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 236 (0xFA) LCDDR14 SEG239 SEG238 SEG237 SEG236 SEG235 SEG234 SEG233 SEG232 236 (0xF9) LCDDR13 SEG231 SEG230 SEG229 SEG228 SEG227 SEG226 SEG225 SEG224 236 (0xF8) LCDDR12 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 236 (0xF7) LCDDR11 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 236 (0xF6) LCDDR10 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 236 (0xF5) LCDDR09 SEG139 SEG138 SEG137 SEG136 SEG135 SEG134 SEG133 SEG132 236 ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 Page 12 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xF4) LCDDR08 Name SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 236 (0xF3) LCDDR07 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 236 (0xF2) LCDDR06 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 236 (0xF1) LCDDR05 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 236 (0xF0) LCDDR04 SEG039 SEG038 SEG037 SEG036 SEG035 SEG034 SEG033 SEG032 236 (0xEF) LCDDR03 SEG031 SEG030 SEG029 SEG028 SEG027 SEG026 SEG025 SEG024 236 (0xEE) LCDDR02 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 236 (0xED) LCDDR01 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG009 SEG008 236 (0xEC) LCDDR00 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 236 (0xEB) Reserved - - - - - - - - (0xEA) Reserved - - - - - - - - (0xE9) Reserved - - - - - - - - (0xE8) Reserved - - - - - - - - (0xE7) LCDCCR LCDDC2 LCDDC1 LCDDC0 LCDMDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 (0xE6) LCDFRR - LCDPS2 LCDPS1 LCDPS0 - LCDCD2 LCDCD1 LCDCD0 233 (0xE5) LCDCRB LCDCS LCD2B LCDMUX1 LCDMUX0 LCDPM3 LCDPM2 LCDPM1 LCDPM0 232 (0xE4) LCDCRA LCDEN LCDAB - LCDIF LCDIE LCDBD LCDCCD LCDBL 231 (0xE3) Reserved - - - - - - - - (0xE2) Reserved - - - - - - - - (0xE1) Reserved - - - - - - - - (0xE0) Reserved - - - - - - - - (0xDF) Reserved - - - - - - - - (0xDE) Reserved - - - - - - - - (0xDD) PORTJ - PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 93 (0xDC) DDRJ - DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 93 (0xDB) PINJ - PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 93 (0xDA) PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 93 (0xD9) DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 93 (0xD8) PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 93 (0xD7) Reserved - - - - - - - - (0xD6) Reserved - - - - - - - - (0xD5) Reserved - - - - - - - - (0xD4) Reserved - - - - - - - - (0xD3) Reserved - - - - - - - - (0xD2) Reserved - - - - - - - - (0xD1) Reserved - - - - - - - - (0xD0) Reserved - - - - - - - - (0xCF) Reserved - - - - - - - - (0xCE) Reserved - - - - - - - - (0xCD) Reserved - - - - - - - - (0xCC) Reserved - - - - - - - - (0xCB) Reserved - - - - - - - - (0xCA) Reserved - - - - - - - - (0xC9) Reserved - - - - - - - - (0xC8) Reserved - - - - - - - - (0xC7) Reserved - - - - - - - - (0xC6) UDR0 (0xC5) UBRR0H (0xC4) UBRR0L (0xC3) Reserved - - - - - - - - (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 189 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 188 187 USART0 Data Register 234 186 USART0 Baud Rate Register High 190 USART0 Baud Rate Register Low 190 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) Reserved - - - - - - - - (0xBC) Reserved - - - - - - - - (0xBB) Reserved - - - - - - - - (0xBA) USIDR (0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 198 198 USI Data Register 197 (0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC (0xB7) Reserved - - - - - - - - (0xB6) ASSR - - - EXCLK AS2 TCN2UB OCR2UB TCR2UB (0xB5) Reserved - - - - - - - - (0xB4) Reserved - - - - - - - - ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 153 13 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xB3) OCR2A Timer/Counter 2 Output Compare Register A 153 (0xB2) TCNT2 Timer/Counter2 153 (0xB1) Reserved - - - - - - - - (0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 (0xAF) Reserved - - - - - - - - 151 (0xAE) Reserved - - - - - - - - (0xAD) Reserved - - - - - - - - (0xAC) Reserved - - - - - - - - (0xAB) Reserved - - - - - - - - (0xAA) Reserved - - - - - - - - (0xA9) Reserved - - - - - - - - (0xA8) Reserved - - - - - - - - (0xA7) Reserved - - - - - - - - (0xA6) Reserved - - - - - - - - (0xA5) Reserved - - - - - - - - (0xA4) Reserved - - - - - - - - (0xA3) Reserved - - - - - - - - (0xA2) Reserved - - - - - - - - (0xA1) Reserved - - - - - - - - (0xA0) Reserved - - - - - - - - (0x9F) Reserved - - - - - - - - (0x9E) Reserved - - - - - - - - (0x9D) Reserved - - - - - - - - (0x9C) Reserved - - - - - - - - (0x9B) Reserved - - - - - - - - (0x9A) Reserved - - - - - - - - (0x99) Reserved - - - - - - - - (0x98) Reserved - - - - - - - - (0x97) Reserved - - - - - - - - (0x96) Reserved - - - - - - - - (0x95) Reserved - - - - - - - - (0x94) Reserved - - - - - - - - (0x93) Reserved - - - - - - - - (0x92) Reserved - - - - - - - - (0x91) Reserved - - - - - - - - (0x90) Reserved - - - - - - - - (0x8F) Reserved - - - - - - - - (0x8E) Reserved - - - - - - - - (0x8D) Reserved - - - - - - - - (0x8C) Reserved - - - - - - - - (0x8B) OCR1BH Timer/Counter1 Output Compare Register B High (0x8A) OCR1BL Timer/Counter1 Output Compare Register B Low 130 (0x89) OCR1AH Timer/Counter1 Output Compare Register A High 130 (0x88) OCR1AL Timer/Counter1 Output Compare Register A Low 130 (0x87) ICR1H Timer/Counter1 Input Capture Register High 131 (0x86) ICR1L Timer/Counter1 Input Capture Register Low 131 (0x85) TCNT1H Timer/Counter1 High 130 (0x84) TCNT1L (0x83) Reserved - - - 130 Timer/Counter1 Low - - 130 - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 129 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 128 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 126 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 203 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 220 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 216 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 202/219 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH ADC Data Register High 218 219 (0x78) ADCL (0x77) Reserved - - - ADC Data Register Low - - - - - 219 (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) PCMSK3 - PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 64 14 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x72) Reserved Name - - - - - - - - Page (0x71) Reserved - - - - - - - - (0x70) TIMSK2 - - - - - - OCIE2A TOIE2 154 (0x6F) TIMSK1 - - ICIE1 - - OCIE1B OCIE1A TOIE1 131 (0x6E) TIMSK0 - - - - - - OCIE0A TOIE0 137 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 64 (0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 64 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 64 (0x6A) Reserved - - - - - - - - (0x69) EICRA - - - - - - ISC01 ISC00 (0x68) Reserved - - - - - - - - (0x67) Reserved - - - - - - - - (0x66) OSCCAL (0x65) Reserved - - - - - - - - (0x64) PRR - - - PRLCD PRTIM1 PRSPI PSUSART0 PRADC (0x63) Reserved - - - - - - - - (0x62) Reserved - - - - - - - - (0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 38 (0x60) WDTCR - - - WDCE WDE WDP2 WDP1 WDP0 53 0x3F (0x5F) SREG I T H S V N Z C 15 0x3E (0x5E) SPH Stack Pointer High 0x3D (0x5D) SPL Stack Pointer Low 0x3C (0x5C) Reserved - - - - - - - - 0x3B (0x5B) Reserved - - - - - - - - 0x3A (0x5A) Reserved - - - - - - - - 0x39 (0x59) Reserved - - - - - - - - 0x38 (0x58) Reserved - - - - - - - - 0x37 (0x57) SPMCSR SPMIE RWWSB - RWWSRE BLBSET PGWRT PGERS SPMEN 289 0x36 (0x56) Reserved 61 Oscillator Calibration Register [CAL7...0] 38 46 17 17 0x35 (0x55) MCUCR JTD BODS BODSE PUD - - IVSEL IVCE 59/90/275 0x34 (0x54) MCUSR - - - JTRF WDRF BORF EXTRF PORF 53 0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE 45 0x32 (0x52) Reserved - - - - - - - - 0x31 (0x51) OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 242 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 202 0x2F (0x4F) Reserved - - - - - - - - 0x2E (0x4E) SPDR 0x2D (0x4D) SPSR SPIF WCOL - - SPI Data Register - - - SPI2X 165 164 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 163 0x2B (0x4B) GPIOR2 General Purpose I/O Register 0x2A (0x4A) GPIOR1 General Purpose I/O Register 0x29 (0x49) Reserved - - - 0x28 (0x48) Reserved - - - 0x27 (0x47) OCR0A Timer/Counter0 Output Compare A 0x26 (0x46) TCNT0 Timer/Counter0 0x25 (0x45) Reserved - - - - - - 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 135 0x23 (0x43) GTCCR TSM - - - - - PSR2 PSR10 138/155 - - - - - 29 29 - - - - - - - - - 138 137 - - EEPROM Address Register High 28 0x22 (0x42) EEARH 0x21 (0x41) EEARL EEPROM Address Register Low 28 0x20 (0x40) EEDR EEPROM Data Register 28 0x1F (0x3F) EECR 0x1E (0x3E) GPIOR0 - - - - 0x1D (0x3D) EIMSK PCIE PCIE2 PCIE1 PCIE0 0x1C (0x3C) EIFR PCIF3 PCIF2 PCIF1 0x1B (0x3B) Reserved - - - 0x1A (0x3A) Reserved - - 0x19 (0x39) Reserved - - 0x18 (0x38) Reserved - 0x17 (0x37) TIFR2 0x16 (0x36) EERIE EEMWE EEWE EERE 28 - - - INT0 62 PCIF0 - - - INTF0 63 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OCF2A TOV2 154 TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 131 0x15 (0x35) TIFR0 - - - - - - OCF0A TOV0 138 0x14 (0x34) PORTG - - - PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 92 0x13 (0x33) DDRG - - - DDG4 DDG3 DDG2 DDG1 DDG0 92 0x12 (0x32) PING - - PING5 PING4 PING3 PING2 PING1 PING0 92 General Purpose I/O Register 29 ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 15 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x11 (0x31) PORTF Name PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 92 0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 92 0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 92 0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 91 0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 92 0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 92 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 91 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 91 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 91 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 91 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 91 0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 91 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 90 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 90 0x03 (0x23) PINB 0x02 (0x22) PORTA PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 91 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 90 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 90 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 90 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY] 8284FS–AVR–07/2014 16 8. Instruction set summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 1 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr)