Atmel ATPL00B
FSK Power Line Communications SoC
DATASHEET
Features
Core
ADD8051C3A enhanced 8051 core
Speedups up to x5 vs. standard 8051 microcontroller
128Kbytes internal SRAM
In-circuit serial flash programming
Auto boot-loading program from serial flash
Media Access Control
Convolutional and block (FEC) channel coding, Viterbi decoding
Hardware CRC error detection and FEC error correction
By-pass mode to support earlier no-MAC FSK modem software
Modem
Power Line Carrier Modem for 50 and 60 Hz mains
Carrier Frequency: 132.5KHz
Baud rate Selectable: 600 to 4800 bps
Half Duplex communication
Receiver Sensitivity: Up to 44dBμVrms
Peripherals
Three 2-wire UARTs
Two SPI. SPI to serial flash and External RTC. Buffered SPI to external metering
IC
Programmable Watchdog
Quad dimmer in/out
Up to 20 I/O lines
Package
144-lead LQFP, 16 x 16 mm, pitch 0.4 mm
Pb-free and RoHS compliant
Typical Applications
Automated Meter Reading (AMR) & Advanced Meter Management (AMM)
Street lighting
Home Automation
43028A-ATPL - 9/12
Description
The ATPL00B is a Power Line Communications System on Chip that implements a
full PLC node using FSK modulations and includes a hardwired Medium Access
Controller (ADD1210). It has been developed to reduce the CPU computational load
in PLC systems. Thus, the microcontroller is free to be used in the applications tasks.
MAC functional capabilities of ATPL00B (performed in ADD1210 Medium Access
Controller) involve the construction of message packets, adding convolutional or FEC
(Forward Error Correction) codes to bytes and FCS (Frame Check Sequence) to
packets. In reception, the MAC provides frame detection and Viterbi decoding or FCS
and FEC correction.
ATPL00B MAC design is versatile and allows users to create a wide range of
datagram structures. The MAC shall be set in a bypass mode allowing direct
connection between the microcontroller and the modem to support old FSK software
that doesn‟t include the MAC.
ATPL00B PLC modem (ADD1310) is based on a Frequency-shift keying (FSK)
Modulation Scheme supporting Minimum Shift Frequency (MSK) in the C-Band with
carrier frequency of 132,5KHz. It shall work using a single power supply of 3.3V and
a few external components, supporting several Analog Front End (AFE)
configurations suitable for Home Automation purposes. It shall replace the traditional
analog PLC modem and can use the same software libraries or a simplified version if
the hardwired MAC is used. The PLC modem fits CENELEC C-band and EN50065-1
access rules, and has receiver sensitivity up to 44dBμVrms (158 μVrms).
ATPL00B core (ADD8051C3A) includes all features of the standard 8051, with an
average speed up to x5 and some additional features.
The microcontroller includes some specific peripherals as 4 input / 4 output dimmers
for power regulation (phase angle control), and also capable of generating PulseWidth Modulation (PWM) control.
A flash program loader allows downloading the microcontroller program in a standard
SPI serial flash memory and executing it from internal SRAM. In the start-up process,
the program is uploaded from serial flash to the internal 128Kbytes of SRAM before
starting the execution. After that, the free space in the serial flash shall be used to
store application data. ATPL00B includes an encryption engine for code protection.
Using a larger flash, several programs may be stored at the same time and the
microcontroller shall switch from one program to another. This feature could be used
to reprogram the SoC using PLC downloading.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
2
Table of Contents
1. Block Diagram.................................................................................... 6
2. Package and Pinout ........................................................................... 7
2.1
2.2
144-Lead LQFP Package Outline ..................................................................... 7
144-Lead LQFP Pinout ..................................................................................... 8
3. Pin Description ................................................................................. 10
4. Processor and Architecture .............................................................. 17
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
ADD8051C3A Microcontroller Description ...................................................... 17
Core Pinout Description .................................................................................. 18
Memory Organization ...................................................................................... 19
4.3.1
Program Memory .............................................................................. 20
4.3.2
Extended Addressing ........................................................................ 21
4.3.3
Data Memory .................................................................................... 25
4.3.4
SFR Registers .................................................................................. 26
Instruction Set ................................................................................................. 29
4.4.1
Program Status Word ....................................................................... 29
4.4.2
Addressing Modes ............................................................................ 29
4.4.3
Arithmetic Instructions....................................................................... 30
4.4.4
Logical Instructions ........................................................................... 31
4.4.5
Data Transfer Instructions................................................................. 33
4.4.6
Boolean Instructions ......................................................................... 34
4.4.7
Jump Instructions .............................................................................. 35
CPU Timing ..................................................................................................... 37
4.5.1
Reset
........................................................................................... 38
4.5.2
Power Saving Modes ........................................................................ 40
4.5.3
Idle Mode .......................................................................................... 40
4.5.4
Power-Down Mode ........................................................................... 40
Interrupts ......................................................................................................... 41
4.6.1
Interrupt Enabling ............................................................................. 41
4.6.2
Interrupt Priorities ............................................................................. 41
4.6.3
Interrupt Handling ............................................................................. 44
I/O Ports .......................................................................................................... 45
4.7.1
I/O Configurations ............................................................................. 46
4.7.2
Read-Modify-Write Feature............................................................... 47
4.7.3
Accessing External Memories ........................................................... 47
Debug Mode.................................................................................................... 48
5. Timers ............................................................................................ 49
5.1
5.2
5.3
Timer 0 and Timer 1 ........................................................................................ 49
5.1.1
Timer Mode 0 .................................................................................... 50
5.1.2
Timer Mode 1 .................................................................................... 51
5.1.3
Timer Mode 2 .................................................................................... 51
5.1.4
Timer Mode 3 .................................................................................... 51
Timer 2 ............................................................................................................ 52
5.2.2
Capture mode ................................................................................... 53
5.2.3
Auto-Reload mode ............................................................................ 53
5.2.4
Clock-Out mode ................................................................................ 54
5.2.5
Baud rate Generator mode ............................................................... 55
Watchdog (timer 3).......................................................................................... 56
6. Standard Serial Interfaces ................................................................ 58
6.1
6.2
Serial Port modes............................................................................................ 58
6.1.1
Mode 0 (shift register mode) ............................................................. 58
6.1.2
Mode 1 (8-bit UART) ......................................................................... 59
6.1.3
Modes 2 and 3 (9-bit UART) ............................................................. 59
Serial Port Timers (Timers 11, 12 and 14) ...................................................... 60
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
3
7. Serial Peripheral Interfaces SPI0 and SPI1 ...................................... 64
7.1
7.2
7.3
SPI description ................................................................................................ 64
7.1.2
SPI clock phase, polarity and operation ............................................ 66
7.1.3
SPI0 write collision ............................................................................ 68
SPI Modes ...................................................................................................... 68
SPI1 buffer operation ...................................................................................... 70
8. Boot Loader ..................................................................................... 72
8.1
8.2
8.3
Pin Description ................................................................................................ 73
Flash Programming ......................................................................................... 74
8.2.1
In-System programming.................................................................... 74
8.2.2
SPI Flash programming .................................................................... 74
System startup ................................................................................................ 76
8.3.1
Encrypted firmware requirements ..................................................... 77
8.3.2
Supported Devices ........................................................................... 77
8.3.2.1
Serial Number Device ..................................................... 77
9. Dimmer Peripheral ........................................................................... 78
9.1
9.2
Configuration Registers ................................................................................... 79
9.1.1
DIM_CTRL register ........................................................................... 80
9.1.2
INP_ST register ................................................................................ 81
9.1.3
OUT_ST register ............................................................................... 82
9.1.4
OUT_REF registers .......................................................................... 83
9.1.5
POLARITY register ........................................................................... 84
9.1.6
D_CONF register .............................................................................. 85
9.1.7
V_SWC register ................................................................................ 86
9.1.8
PWM_PER register ........................................................................... 87
9.1.9
INP_SOURCE register...................................................................... 88
External Circuits .............................................................................................. 89
10. Media Access Layer ......................................................................... 92
10.1
10.2
10.3
10.4
10.5
Packet Encapsulation...................................................................................... 92
MAC Architecture ............................................................................................ 94
MAC Configuration Registers .......................................................................... 94
10.3.1 CTRL register ................................................................................... 95
10.3.2 FLAGS1 register ............................................................................... 97
10.3.3 FLAGS2 register ............................................................................... 99
10.3.4 DATA register ................................................................................. 101
10.3.5 TH_PREAM register ....................................................................... 102
10.3.6 TH_HEADER register ..................................................................... 103
10.3.7 BAUDRATE register ....................................................................... 104
10.3.8 TRACK register ............................................................................... 105
10.3.9 PREAM register .............................................................................. 106
10.3.10 CTRL2 register ............................................................................... 107
10.3.11 BC register ...................................................................................... 108
10.3.12 MODE1 to MODE4 registers........................................................... 109
10.3.13 VTB_BE_HARD register ................................................................. 110
10.3.14 VTB_BE_SOFT registers ................................................................ 111
10.3.15 FEC_BER register .......................................................................... 112
Operation modes........................................................................................... 113
10.4.2 BYPASS mode ............................................................................... 113
10.4.3 WHD mode ..................................................................................... 113
10.4.4 BYTE mode .................................................................................... 114
10.4.5 FEC mode....................................................................................... 114
10.4.6 VTB mode ....................................................................................... 114
10.4.7 FCS mode....................................................................................... 114
10.4.8 NULL mode..................................................................................... 114
Operation Procedures ................................................................................... 114
10.5.1 STOP cycle ..................................................................................... 114
10.5.2 WHD mode operation procedure .................................................... 114
10.5.3 Transmission procedure ................................................................. 116
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
4
10.5.4
Reception procedure....................................................................... 118
11. PLC Modem ................................................................................... 119
11.1
11.2
11.3
Frequency coding.......................................................................................... 120
Modem Transmission and Reception ............................................................ 121
11.2.1 Transmission characteristics ........................................................... 121
11.2.2 Reception characteristics ................................................................ 122
PLC Modem Configuration registers ............................................................. 124
11.3.1 GAIN register .................................................................................. 125
11.3.2 CONTROL2 register ....................................................................... 126
11.3.3 CONFIG register ............................................................................. 127
11.3.4 GFSK_ADDR register ..................................................................... 128
11.3.5 GFSK_DX registers ........................................................................ 129
11.3.6 COMP register ................................................................................ 130
11.3.7 KNX_EN register ............................................................................ 131
11.3.8 CD_ENABLE register...................................................................... 132
11.3.9 CD_DECISION_TIME register ........................................................ 133
11.3.10 CD_DECISION_ERROR register ................................................... 134
11.3.11 TXRX_CTL register......................................................................... 135
11.3.12 Ri registers...................................................................................... 136
12. Electrical Characteristics ................................................................ 137
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Absolute Maximum Ratings .......................................................................... 137
Recommended Operating Conditions ........................................................... 138
DC Characteristics ........................................................................................ 139
12.3.2 V-I curves........................................................................................ 140
Power Consumption ...................................................................................... 143
Thermal Data ................................................................................................ 143
Oscillator ....................................................................................................... 144
Power on ....................................................................................................... 146
13. Mechanical Characteristics ............................................................ 147
14. Recommended mounting conditions .............................................. 148
14.1
14.2
Conditions of Standard Reflow ...................................................................... 148
Manual Soldering .......................................................................................... 149
15. Ordering Information ...................................................................... 150
16. Revision History ............................................................................. 151
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
5
1.
Block Diagram
Figure 1-1. ATPL00B 144-pin Block Diagram
DEBUG
D_INIT
RSTA
Reset
Interface
11.059.200Hz
CLKA
VDD
RESET
DEBUG
Clock
Power
Management
LDO_PD
VDEO
Clock
Interface
CLKB
VSSO
8051C3A Core
IDATA
INT1
TDI
TDO
TCK
TRST
TMS
JTAG
Bscan
128KB SRAM
CODE
SRAM
XDATA
SRAM
P1.7
P3(1,2), P3(3:5)
P4(0:7)
P5(0:5)
GENERAL
PURPOSE I/O
TRIAC_(3:0)
VNR
INTA(3:0)
INTB(3:0)
INTC(3:0)
INTD(3:0)
DIMMER
PERIPHERAL
M
U
X
MEDIUM
ACCESS
CONTROL
Vref1
Vref2
EMIT(12:0)
ENABLE
DC_COMP
D_IN
D_NIN
REC(8:1)
VIN
VRH
VRL
/PROG
BOOT
LOADER
SECURED
SSN
SPI0
MISO, MOSI,
CLK, SS
SPI1
MISO1, MOSI1,
CLK1, SS1
UART0
Rx0, Tx0
UART1
Rx1, Tx1
UART2
Rx2, Tx2
TIMER0
T0
TIMER1
T1
T2
TIMER2
PLC
MODEM
AVD
T2EX
T11, T12, T14
WATCHDOG
/EWDG
AVS
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
6
2.
Package and Pinout
2.1
144-Lead LQFP Package Outline
Figure 2-1. Orientation of the 144-Lead Package
108
73
109
72
144
37
1
36
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
7
2.2
144-Lead LQFP Pinout
Table 2-1.
ATPL00B 144-Lead LQFP pinout
PinNo
Pin Name
I/O
I(mA)
Res
HY
PinNo
Pin Name
I/O
I(mA)
Res
HY
1
P3_3/INT1
I/O
±5
PU
-
39
P5_4/RXD1/INTA0
I/O
±5
PU
-
2
VCC
P
-
-
-
40
P4_7/T2EX/INTA3
I/O
±5
PU
-
I/O
±5
PU
-
3
GND
P
-
-
-
41
P4_6/T2/INTA2
4
GND
P
-
-
-
42
P1_7/SSN
I/O
±5
PU
-
5
GND
P
-
-
-
43
VCC
P
-
-
-
6
TDI
I
±5
PU
-
44
GND
P
-
-
-
7
TDO
O
±5
-
-
45
EMIT_0
O
±X
-
-
8
TCK
I
±5
-
-
46
EMIT_1
O
±X
-
-
9
TMS
I
±5
PU
-
47
EMIT_2
O
±X
-
-
10
TRST
I
±5
PU
-
48
VCC
P
-
-
-
11
D_INIT
I
±5
PD
Y
49
GND
P
-
-
-
12
RSTA
I
±5
PD
Y
50
EMIT_3
O
±X
-
-
13
/PROG
I
±5
PU
Y
51
EMIT_4
O
±X
-
-
14
SECURED
I
±5
PD
Y
52
EMIT_5
O
±X
-
-
15
/EWDG
I
±5
PD
Y
53
EMIT_6
O
±X
-
-
16
DEBUG
I
±5
PD
Y
54
VCC
P
-
-
-
17
VCC
P
-
-
-
55
GND
P
-
-
-
18
CLKEB
I/O
-
-
-
56
EMIT_7
O
±X
-
-
19
GND
P
-
-
-
57
EMIT_8
O
±X
-
-
20
CLKEA
I
-
-
-
58
EMIT_9
O
±X
-
-
21
VCC
P
-
-
-
59
EMIT_10
O
±X
-
-
22
GND
P
-
-
-
60
VCC
P
-
-
-
23
GND
P
-
-
-
61
GND
P
-
-
-
24
VDE0
P
-
-
-
62
EMIT_11
O
±X
-
-
25
VDE0
P
-
-
-
63
EMIT_12
O
±X
-
-
26
VSS0
P
-
-
-
64
VCC
P
-
-
-
27
LDO_PD
I
65
GND
P
-
-
-
28
VDD
P
-
-
-
66
P3_1/TXD0
I/O
±5
PU
-
29
GND
P
-
-
-
67
P3_0/RXD0
I/O
±5
PU
-
30
VCC
P
-
-
-
68
P4_5/MISO1/INTB3
I/O
±5
PU
-
31
Vref1
I
-
-
-
69
P4_4/MOSI1/INTB2
I/O
±5
PU
-
32
Vref2
I
-
-
-
70
P4_3/SPICLK1/INTB1
I/O
±5
PU
-
33
VNR
I
±5
-
Y
71
P4_2/SS1/INTB0
I/O
±5
PU
-
34
TRIAC_3
O
±5
-
-
72
P4_1/TXD2
I/O
±5
PU
-
35
TRIAC_2
O
±5
-
-
73
P4_0/RXD2
I/O
±5
PU
-
36
TRIAC_1
O
±5
-
-
74
VCC
P
-
-
-
37
TRIAC_0
O
±5
-
-
75
GND
P
-
-
-
38
P5_5/TXD1/INTA1
I/O
±5
PU
-
76
INTC3
I
±5
-
-
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
8
Table 2-1.
ATPL00B 144-Lead LQFP pinout (Continued)
PinNo
Pin Name
I/O
I(mA)
Res
HY
PinNo
Pin Name
I/O
I(mA)
Res
HY
77
INTC2
I
±5
-
-
112
NC
-
-
-
-
78
INTC1
I
±5
-
-
113
GND
P
-
-
-
79
INTC0
I
±5
-
-
114
DC_COMP
O
±10
-
-
80
NC
-
-
-
-
115
VCC
P
-
-
-
81
NC
-
-
-
-
116
ENABLE
O
±10
-
-
82
NC
-
-
-
-
117
GND
P
-
-
-
83
NC
-
-
-
-
118
DNIN
I
±5
-
-
84
NC
-
-
-
-
119
DIN
I
±5
-
-
85
NC
-
-
-
-
120
REC_1
O
±5
-
-
86
NC
-
-
-
-
121
REC_2
O
±5
-
-
87
NC
-
-
-
-
122
REC_3
O
±5
-
-
88
NC
-
-
-
-
123
REC_4
O
±5
-
-
89
VDD
P
-
-
-
124
REC_5
O
±5
-
-
90
VCC
P
-
-
-
125
REC_6
O
±5
-
-
91
GND
P
-
-
-
126
REC_7
O
±5
-
-
92
NC
-
-
-
-
127
REC_8
O
±5
-
-
93
NC
-
-
-
-
128
VCC
P
-
-
-
94
NC
-
-
-
-
129
GND
P
-
-
-
95
NC
-
-
-
-
130
VRL
I
(**)
-
-
96
NC
-
-
-
-
131
VIN
I
(**)
-
-
97
NC
-
-
-
-
132
VRH
I
(**)
-
-
98
NC
-
-
-
-
133
AVD1
P
-
-
-
99
NC
-
-
-
-
134
AVS1
P
-
-
-
100
NC
-
-
-
-
135
AVD2
P
-
-
-
101
NC
-
-
-
-
136
AVS2
P
-
-
-
102
NC
-
-
-
-
137
VCC
P
-
-
-
103
VCC
P
-
-
-
138
GND
P
-
-
-
104
GND
P
-
-
-
139
P5_3/MISO0
I/O
±5
PU
-
105
INTD3
I
±5
-
-
140
P5_2/MOSI0
I/O
±5
PU
-
106
INTD2
I
±5
-
-
141
P5_1/SPICLK0
I/O
±5
PU
-
107
INTD1
I
±5
-
-
142
P5_0/SS0
I/O
±5
PU
-
108
INTD0
I
±5
-
-
143
P3_5/T1
I/O
±5
PU
-
109
NC
-
-
-
-
144
P3_4/T0
I/O
±5
PU
-
110
NC
-
-
-
-
111
NC
-
-
-
-
Notes:
1.
Mandatory to be tied down
I/O=pin direction:
I=input, O=Output, P=Power
I(mA)=nominal current:
+=source, -=sink, X=fixed by external resistor
RES=pin pullup/pulldown resistor: PU=pullup, PD=pulldown
;
HY=Input Hysteresis
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
9
3.
Pin Description
Table 3-1.
Pin Description List
Pin Number
Pin Name
Type
Comments
Microcontroller port 3.3 / External Interrupt 1
When configured as P3.3, this pin is a pseudobidirectional microcontroller I/O port
When configured as INT1, this pin is the 8051C3A
microcontroller external interrupt 1
Internal configuration: 33kΩ typ. pull-up resistor
1
P3.3/INT1
I/O
2, 17, 21, 30, 43,
48, 54, 60, 64,
74, 90, 103, 115,
128, 137
VCC
Power
3.3v digital supply. Digital power supply must be decoupled by external
capacitors
3, 4, 5, 19, 22,
23, 29, 44, 49,
55, 61, 65, 75,
91, 104, 113,
117, 129, 138
GND
Power
Digital ground
6
TDI(1)
Input
(1)
Output
8
TCK
(1)
Input
9
TMS(1)
Input
7
10
TDO
TRST(1)
Input
11
D_INIT
Input
12
RSTA
Input
13
/PROG
Input
Test Data In
Internal configuration: 33kΩ typ. pull-up resistor
Test Data out
Test Clock
Test Mode Select
Internal configuration: 33kΩ typ. pull-up resistor
Test Reset
Internal configuration: 33kΩ typ. pull-up resistor
Initialization Signal
During power-on, D_INIT should be released before
asynchronous reset signal RSTA, in order to ensure
proper system start up. Not minimum time is required
between both releases, ∆t>0
D_INIT is active high
Internal configuration: 33kΩ typ. pull-down resistor
Asynchronous reset
RSTA is a digital input pin used to perform a hardware
reset of the ASIC
RSTA is active high
Internal configuration: 33kΩ typ. pull-down resistor
SPI Flash programming pin
/PROG digital input is read during power up and sets
the system into “execution” mode or “serial flash
programming” mode
„0‟: Serial flash programming mode
„1‟: Execution mode (normal mode)
Internal configuration: 33kΩ typ. pull-up resistor
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
10
Table 3-1.
Pin Description List (Continued)
Pin Number
14
Pin Name
SECURED
Type
Input
Comments
Encryption enable
SECURED digital input enables encrypted firmware
storage and execution when the board configuration
supports it
„0‟: Encrypted storage/execution disabled
„1‟: Encrypted storage/execution enabled
Internal configuration: 33kΩ typ. pull-down resistor
Watchdog enable
15
/EWDG
Input
/EWDG digital input enables watchdog timer. This pin is
internally connected to the /EW signal of the
ADD8051C3A microcontroller
„0‟: Watchdog timer enabled
„1‟: Watchdog timer disabled
Internal configuration: 33kΩ typ. pull-down resistor
Debug mode enable
16
DEBUG
Input
DEBUG digital input is internally connected to DBG
signal of the ADD8051C3A microcontroller, and it is
intended to implement software debugging tools
„0‟: Debug mode disabled
„1‟: Debug mode enabled
Internal configuration: 33kΩ typ. pull-down resistor
External clock reference
18
CLKEB(2)
I/O
20
CLKEA(2)
Input
24, 25
VDEO
Power
26
VSSO
Power
27
LDO_PD
Power
CLKEB must be connected to one terminal of a crystal
(when a crystal is being used) or to one terminal of a
compatible oscillator (when a compatible oscillator is
being used)
External clock reference
CLKEA must be connected to one terminal of a crystal
(when a crystal is being used) or tied to ground if a
compatible oscillator is being used
LDO 3.3v power supply
LDO ground
LDO Power-down. This digital input is used to put the internal linear
regulator into power down mode
„0‟: Power down mode disabled
28,89
VDD
Power
31
Vref1
Input
„1‟: Power down mode enabled
LDO Power output
A capacitor in the range 0.1µF - 10µF must be connected to each pin
Voltage reference 1. Tie to Vcc with a Rpu = 4.7kΩ
32
Vref2
Input
Voltage reference 2. Tie to GND with a Rpd = 4.7kΩ
Zero-crossing detection signal
33
VNR
Input
This input detects the zero-crossing of the mains
voltage, needed to properly determine switching times
Depending on whether an isolated or a non-isolated
power supply is being used, isolation of this pin should
be taken into account in the circuitry design
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
11
Table 3-1.
Pin Description List (Continued)
Pin Number
Pin Name
Type
34, 35, 36, 37
TRIAC(3:0)
Output
38
39
40
41
42
P5.5/TxD1/INTA1
P5.4/RxD1/INTA0
P4.7/T2EX/INTA3
P4.6/T2/INTA2
P1.7/SSN
I/O
I/O
I/O
I/O
I/O
Comments
TRIAC outputs
These four pins are outputs to control home automation
devices by the ATPL00B dimmer peripheral. TRIAC
outputs can be configured to work as phase angle
controllers or as PWM controllers
Microcontroller port 5.5 / Standard Serial Port 1 Tx / Dimmer switch 1
When configured as P5.5, this pin is a pseudobidirectional microcontroller I/O port
When configured as TxD1, this pin is the digital output
of the asynchronous standard serial port 1
When configured as INTA1, this pin is the input to
dimmer peripheral signal INTERR(1)
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 5.4 / Standard Serial Port 1 Rx / Dimmer switch 0
When configured as P5.4, this pin is a pseudobidirectional microcontroller I/O port
When configured as RxD1, this pin is the digital input of
the asynchronous standard serial port 1
When configured as INTA0, this pin is the input to
dimmer peripheral signal INTERR(0)
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 4.7 / T2EX / Dimmer switch 3
When configured as P4.7, this pin is a pseudobidirectional microcontroller I/O port
When configured as T2EX, this pin is the Timer/Counter
2 capture/reload trigger described in Timer2 section
When configured as INTA3, this pin is the input to
dimmer peripheral signal INTERR(3)
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 4.6 / T2 / Dimmer switch 2
When configured as P4.6, this pin is a pseudobidirectional microcontroller I/O port
When configured as T2, this pin works as the external
T2 pin described in Timer2 section
When configured as INTA2, this pin is the input to
dimmer peripheral signal INTERR(2)
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 1.7 / Silicon Serial Number
When configured as P1.7, this pin is a pseudobidirectional microcontroller I/O port
This pin is the digital input used to read a Serial number
if a valid SSN device is being used. This Serial Number
is used for encryption purposes. Precaution should be
taken if used as generic control port since it searches
for a Silicon Serial Number device at start-up and could
put out undesirable transient values
Internal configuration: 33kΩ typ. pull-up resistor
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
12
Table 3-1.
Pin Description List (Continued)
Pin Number
Pin Name
Type
45
EMIT.0
Output
46, 47, 50, 51,
52, 53, 56, 57,
58, 59, 62, 63
EMIT(1:12)
Output
Comments
Tx/Rx control output pin
This output pin is used by the system to adapt the
external Analog-Front-end either in transmission or in
reception, thus improving the electrical behavior
PLC transmission ports(3)
Microcontroller port 3.1 / Standard Serial Port 0 Tx
66
67
68
69
70
P3.1/TxD0
P3.0/RxD0
P4.5/MISO1/INTB3
P4.4/MOSI1/INTB2
P4.3/SPICLK1/INTB1
I/O
I/O
I/O
I/O
I/O
When configured as P3.1, this pin is a pseudobidirectional microcontroller I/O port
When configured as TxD0, this pin is the digital output
of the asynchronous standard serial port 0
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 3.0 / Standard Serial Port 0 Rx
When configured as P3.0, this pin is a pseudobidirectional microcontroller I/O port
When configured as RxD0, this pin is the digital input of
the asynchronous standard serial port 0
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 4.5 / SPI1 Master In Slave Out / Dimmer switch 3
When configured as P4.5, this pin is a pseudobidirectional microcontroller I/O port
When configured as MISO1, this pin is the SPI1 Master
In Slave Out
When configured as INTB3, this pin is the input to
dimmer peripheral signal INTERR(3)
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 4.4 / SPI1 Master Out Slave In / Dimmer switch 2
When configured as P4.2, this pin is a pseudobidirectional microcontroller I/O port
When configured as MOSI1, this pin is the SPI1 Master
Out Slave In
When configured as INTB2, this pin is the input to
dimmer peripheral signal INTERR(2)
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 4.3 / SPI1 Clock / Dimmer switch1
When configured as P4.3, this pin is a pseudobidirectional microcontroller I/O port
When configured as SPICLK1, this pin is the SPI1 clock
signal
When configured as INTB1, this pin is the input to
dimmer peripheral signal INTERR(1)
Internal configuration: 33kΩ typ. pull-up resistor
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
13
Table 3-1.
Pin Description List (Continued)
Pin Number
71
Pin Name
P4.2/SS1/INTB0
Type
I/O
73
P4.0/RxD2
I/O
76, 77, 78, 79
INTC(3:0)
I/O
80, 81, 82, 83,
84, 85, 86, 87,
88, 92, 93, 94,
95, 96, 97, 98,
99, 100, 101,
102, 109, 110,
111, 112
Comments
Microcontroller port 4.2 / SPI1 Slave Select / Dimmer switch 0
When configured as P4.2, this pin is a pseudobidirectional microcontroller I/O port
When configured as SS1, this pin is the SPI1 Slave
Select. Active low
When configured as INTB0, this pin is the input to
dimmer peripheral signal INTERR(0)
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 4.0 / Standard Serial Port 2 Rx
When configured as P4.0, this pin is a pseudobidirectional microcontroller I/O port
When configured as RxD2, this pin is the digital input of
the asynchronous standard serial port 2
Internal configuration: 33kΩ typ. pull-up resistor
Dimmer switches
• These pins can be configured as inputs to dimmer
peripheral signals INTERR(3:0)
No Connect
NC
-
Dimmer switches
105, 106, 107,
108
INTD(3:0)
I/O
114
DC_COMP
Output
116
ENABLE
Output
118
DNIN
Input
119
DIN
Input
• These pins can be configured as inputs to dimmer
peripheral signals INTERR(3:0)
External comparator DC compensation
This output controls the direct current compensation of
the external comparator. This pin is connected only if an
external comparator is being used. Otherwise, this pin
must be left unconnected
External comparator enable
Output pin to enable external comparator. This pin is
connected only if an external comparator is being used.
Otherwise, this pin must be left unconnected
External comparator inverted output signal
This pin is the input for the external comparator inverted
output signal. This pin is connected only if an external
comparator is being used. Otherwise, this pin must be
tied to ground
External comparator output signal
This pin is the input for the external comparator output
signal. This pin is connected only if an external
comparator is being used. Otherwise, this pin must be
tied to ground
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
14
Table 3-1.
Pin Description List (Continued)
Pin Number
Pin Name
Type
Comments
External comparator threshold loop
120, 121, 122,
123, 124, 125,
126, 127
REC(1:8)
Output
130
VRL
Input
These outputs are used to set the voltage threshold in
the external comparator. These pins are connected only
if an external comparator is being used. Otherwise,
these pins must be left unconnected
Analog input low voltage reference
131
VIN
Input
Direct-analog input voltage
132
VRH
Input
Analog input high voltage reference
133, 135
AVD1, AVD2
Power
3.3v analog power
134, 136
AVS1, AVS2
Power
Analog ground
Microcontroller port 5.3 / SPI0 Master In Slave Out
139
140
141
142
143
144
P5.3/MISO0
P5.2/MOSI0
P5.1/SPICLK0
P5.0/SS0
P3.5/T1
P3.4/T0
I/O
I/O
I/O
I/O
I/O
I/O
When configured as P5.3, this pin is a pseudobidirectional microcontroller I/O port
When configured as MISO0, this pin is the SPI0 Master
In Slave Out
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 5.2 / SPI0 Master Out Slave In
When configured as P5.2, this pin is a pseudobidirectional microcontroller I/O port
When configured as MOSI0, this pin is the SPI0 Master
Out Slave In
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 5.1 / SPI0 Clock
When configured as 54.1, this pin is a pseudobidirectional microcontroller I/O port
When configured as SPICLK0, this pin is the SPI0 clock
signal
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 5.0 / SPI0 Slave Select
When configured as P5.0, this pin is a pseudobidirectional microcontroller I/O port
When configured as SS0, this pin is the SPI0 Slave
Select. Active low
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 3.5 / Timer 1 interrupt signal
When configured as P3.5, this pin is a pseudobidirectional microcontroller I/O port
When configured as T1, this pin works as the external
T1 pin described in Timer1 section
Internal configuration: 33kΩ typ. pull-up resistor
Microcontroller port 3.4 / Timer 0 interrupt signal
When configured as P3.4, this pin is a pseudobidirectional microcontroller I/O port
When configured as T0, this pin works as the external
T0 pin described in Timer0 section
Internal configuration: 33kΩ typ. pull-up resistor
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
15
Notes:
1. This pin is part of the JTAG Boundary Scan interface and is only used for boundary scan purposes
2. The crystal should be located as close as possible to CLKEA and CLKEB pins. Recommended value for Cx is 18pF.
This value may depend on the specific crystal characteristics
CLKEB
CLKEA
Xtal
Cx
Cx
Different configurations allowed depending on external topology and net behavior
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
16
4.
Processor and Architecture
4.1
ADD8051C3A Microcontroller Description
The following document provides a detailed description of the ADD8051C3A architecture and its hardware.
ADD8051C3A is fully compatible with any 8051 legacy microcontroller, however there are some hardware differences
that deserve to be taken into account.
CPU speed has been improved. The machine cycle has been reduced from 12 to 3 clock cycles, and all the instructions
are executed in 1 or 2 machine cycles. Programs are executed a minimum of four times faster than in a standard-8051architecture device, achieving x5 speedup for most programs.
A 128KBytes SRAM is embedded on chip. Program memory and External Data (XDATA) memory share this 128Kbytes
SRAM. The lower 64Kbytes are always dedicated to store program memory, while upper 64Kbytes are configurable to
allocate different program and XDATA memory size configurations, depending on bank switching page size (See 4.3).
This document includes a detailed description of registers and peripherals. Some of these items are upgraded versions
of the original 8051 microcontroller circuitry, while others are a simplified version.
Figure 4-1. ADD8051C3A microcontroller block diagram
EXTERNAL
INTERRUPTS
UART 0
UART 1
UART 2
COUNTER
INPUTS
MISO(0,1)
MOSI(0,1) SPICLK(0,1) /SS(0,1)
WATCHDOG
SERIAL
INTERFACE
SPI
TIMER 2
TIMER 1
INTERRUPT
CONTROL
TIMER 0
CPU
CLOCK
CONTROL
CLK
Note:
USER I/O PORTS
XPROGRAM AND XDATA
ACCESS
DATA
@
P1
P3
P4
256B RAM
(IDATA)
XDATA MAPPED
PERIPHERALS
P5
This chapter describes the architecture from the microcontroller point of view. Thus, “on-chip SRAM” is referred
to as “external memory” since “external” instructions like MOVX are necessary to access this memory
device
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
17
4.2
Core Pinout Description
Figure 4-2. ADD8051C3A core pinout diagram
XDATA
IDATA
CLK
SRST
PSEN
ARST
EW
ADD8051C3A
CORE
HIRQ
DBG
DATA
ADDRESS
P1
P2
P3
P4
SRST_OUT
RELOAD
HI
Table 4-1.
Core pinout description
Pin
I/O
Description
CLK
I
Clock input.
ARST
I
Asynchronous reset.
SRST
I
SRST
Must be held active one clock cycle to ensure proper power-on. External signal D_INIT is
connected to this core input.
/EW
I
Watchdog enable
Low level active.
External signal/EWDG is connected to this core input.
HIRQ
I
Hard idle request
High level active.
When asserted, the microcontroller finishes the instruction in execution and goes to a special
hard idle state. In hard idle state the CPU is stopped while peripheral circuits still run, CPU
restarts only after HIRQ deassertion.
DBG
I
Debug mode enable
High level active.
PSEN
O
Program Store Enable
Read strobe to program memory.
DATA
I/O
Data bus
16-bit bidirectional port to access program and/or data memories.
ADDRESS
O
Address bus
Output port to access program memory and XDATA.
SRST_OUT
O
Watchdog timer reset signal.
RELOAD
O
Program reload control signal
Software or watchdog activated.
Force program reload from a serial storage device to a parallel SRAM.
HI
O
Hard idle flag,
This flag is set to „1‟ when the CPU is in hard idle state.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
18
I/O Ports.
8-bit pseudo bidirectional I/O ports with pull-up resistors. These ports are by default in pseudobidirectional configuration. Configured in this way, port pins that have 1s written to them are
pulled high by the internal pull-ups, and in that state can be used as inputs. When a bit in a Port
register has a 0 to 1 transition the related pin is driven high using transistor during 1 clock
cycle, then the transistor is switched off and the pull-up resistor keeps the logic level.
Ports P3, P4 and P5 can be also configured as push-pull mode ports. In push-pull mode the
pin is always in output mode and logic 1 is always high driven (see 4.7.1).
Some pins of P3, P4 and P5 also serve the functions of various special features of the
microcontroller:
PORTS: P1, P3, P4,
P5 (*)
I/O
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
RxD (serial port 0 input)
TxD (serial port 0 output)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR(external data memory write strobe)
RD (external data memory read strobe)
RxD (serial port 2 input)
TxD (serial port 2 output)
SS1 (slave select input)
SPICLK1 (SPI1 clock input/output)
MOSI1 (master out / slave in data)
MISO1 (master in / slave out data
T2 (timer 2 input/output)
T2EX (timer 2 external input)
SS0 (slave select input)
SPICLK0 (SPI0 clock input/output)
MOSI0 (master out / slave in data)
MISO0 (master in / slave out data)
RxD (serial port 1 input)
TxD (serial port 1 output)
(*) each bit of ports 1, 3, 4 and 5 is composed of three lines: data output, data input and output
enable (low level active)
4.3
Memory Organization
ADD8051C3A has separate logical address spaces for program and data memory, as shown in Figure 4-3. The logical
separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be
quickly stored and manipulated by an 8-bit CPU. Nevertheless, 16-bit data memory addresses can also be generated
through the DPTR (Data Pointer Registers).
Program Memory and XDATA Memory are combined in a single 128Kbytes SRAM and accessed by the same bus
using internal RD and PSEN signals functions.
Program memory must only be read. Writing in Program Memory could lead to unexpected results and must be
avoided. There is a block of 64kbytes of base program memory, which can be increased by extended program
pages.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
19
XDATA occupies a separate address space from Program Memory. Up to 64kbytes of XDATA can be
addressed in the Data Memory space. The CPU generates the internal “read” and “write” signals, RD and WR,
needed during XDATA Memory accesses.
Additionally to these 128 Kbytes of SRAM, there are 384 bytes of internal data memory (IDATA) in the ADD8051C3A
core. This is explained in more detail in 4.3.3 section.
Figure 4-3. 128KB SRAM, XDATA and Program Memory
XDATA increases downwards
XDATA physical address =
(1FFFF - logical address)
XDATA
128Kbytes
SRAM
Program Memory
Program Memory
increases upwards
0x00000
The program must be uploaded to the SRAM after power up. The source of program must be a non volatile storage unit
(i.e. serial flash). A specific module (boot loader peripheral) has been designed to control the booting of the system after
power up. The boot loader module can also be used to program the non volatile storage unit (serial flash) using a serial
link. The non volatile storage unit must be connected to P5 port pins used for the SPI0 link (see Table 4-1). The serial
link to the boot loader shares pins with the microcontroller Serial Port 0. For more information see boot loader section in
8
4.3.1
Program Memory
After reset, the CPU begins execution from location 0000H and stack pointer (SP) value is set to 07H.
Interrupt Handling
A fixed location in Program Memory is assigned to each interrupt. The interrupt causes the CPU to jump to that
location, where it begins executing the service routine.
Example: External Interrupt 0, is assigned to location 0003H. If External Interrupt 0 is going to be used, its
service routine must begin at location 0003H. If the interrupt is not going to be used, its service location is
available as general purpose Program Memory.
The interrupt service locations are spaced at 8-byte intervals beginning at 0x0003 (i.e.0x0003 for External
Interrupt0, 0x000B for Timer0, etc.).
If an interrupt service routine is short enough, it can reside entirely within that 8-byte interval. Longer service
routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.
Program Memory addresses are always 17 bits wide, even though the actual amount of Program Memory used
may be less than 64kbytes.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
20
P0 and P2 ports are no longer used to access external memories, but Special Function Registers (SFR) P0 and P2
are still functional.
P2 register is used to generate the high order address byte when executing MOVX A,@Ri or MOVX
@Ri,A.
P0 register is the program address control register and it is used to specify the size of extended program
pages and to control bank switching.
4.3.2
Extended Addressing
ATPL00B combines program code and data in a single 128KB SRAM.
ADDRESS to access program is generated as a function of P0(7:6), P0(5:0) and PC(15:0).
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
P0
SX1
SX0
P05
P04
P03
P02
P01
P00
SX(1:0): Size of extended program pages and common program space
SX(1:0)
Extended
Common
“11”
0KB
64KB
“10”
8KB
56KB
“01”
16KB
48KB
“00”
32KB
32KB
P0(5:0): Extended program page number
Allowing different configurations as the one shown in Figure 4-4
Figure 4-4. SRAM Extended Addressing. 48KB common memory + 3x16KB extended program pages
0x0000
xdata
logical
address
0x01FFFF
XDATA
0x7FFF
PAGE 2
0x014000
0x013FFF
128KBytes
SRAM
PAGE 1
0x010000
0x00FFFF
PAGE 0
0x00C000
0x00BFFF
PROGRAM
MEMORY
0x000000
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
21
Common and extended memory sizes vary depending on the value in P0(7:6), as shown above. According to these size
values, the core knows when the PC is pointing to an address located in common memory and when it is pointing to an
address located in extended memory. When PC is pointing to an address in extended memory, then P0(5:0) indicates
the extended page number and the physical address is automatically calculated. Some examples are shown below.
Example:
SX(1:0)=”00” (common memory size = 32KB)
PC=0x7F23 (PC pointing to an address in common memory space)
P0(5:0)= don‟t care
LOGIC ADDRESS=0x7F23, common memory space
PHYSICAL ADDRESS=0x7F23 (common memory space P0(5:0) is ignored)
Figure 4-5. Extended Addressing example 1
PAGE 2
0x014000
0x013FFF
PAGE 1
0x010000
0x00FFFF
0x00FFFF
PAGE 0
PAGE 0
0x00C000
0x00C000
0x00BFFF
0x00BFFF
Physical Address = 0x7F23
Common
Program
Common
Program
0x000000
0x000000
PC=0x7F23
Logical Address = 0x7F23,
(commom memory space)
Physical Address = PC = 0x7F23
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
22
Example:
SX(1:0)=”00” (common memory size = 32KB)
PC=0x9F5A (PC pointing to an address in extended memory)
P0(5:0)= 0x00 (extended page 0)
LOGIC ADDRESS=0x1F5A, extended page 0
PHYSICAL ADDRESS=0x9F5A
Figure 4-6. Extended Addressing example 2
PAGE 2
0x014000
0x013FFF
PAGE 1
0x010000
0x00FFFF
0x00FFFF
PAGE 0
Physical Address = 0x9F5A
PAGE 0
0x00C000
0x00C000
0x00BFFF
0x00BFFF
Common
Program
Common
Program
0x000000
0x000000
PC=0x9F5A
Logical Address = 0x1F5A,
(extended page 0)
Physical Address = PC+(EPN*SEP)=
PC+(0*0x8000) = 0x9F5A
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
23
Example:
SX(1:0)=”00” (common memory size = 32KB)
PC=0x9F5A (PC pointing to an address in extended memory)
P0(5:0)= 0x01 (extended page 1)
LOGIC ADDRESS=0x1F5A, extended page 1
PHYSICAL ADDRESS=0x11F5A
Figure 4-7. Extended Addressing example 3
PAGE 2
0x014000
0x013FFF
PAGE 1
Physical Address = 0x11F5A
0x010000
0x00FFFF
0x013FFF
PAGE 0
PAGE 1
0x00C000
0x010000
0x00BFFF
0x00BFFF
Common
Program
Common
Program
0x000000
0x000000
Thus
if PC < SCS then
else
where
PC=0x9F5A
Logical Address = 0x1F5A,
(extended page 1)
Physical Address = PC+(EPN*SEP)=
PC+(1*0x8000) = 0x11F5A
Physical Address = PC
Physical Address = PC+(EPN*SEP)
SCS= Size of Common Space;
EPN=Extended Page Number;
SEP= Size of Extended Pages(defined by SX(1:0) value).
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
24
4.3.3
Data Memory
Figure 4-8 shows the internal and external Logical Data Memory spaces available to the microcontroller user.
Figure 4-8. Data Memory Space
PROGRAM
DATA
External
Data
Memory
(XDATA)
External
Program
Memory
IDATA
0xFF
0xFF
No Bit–Addressable
Spaces
0xE0
0x80
0xFF
indirect
IDATA
Upper
128
0x80
0x7F
0x7F
Bank
Select
Bits in
PSW
Lower
128
0x2F
0x20
direct
IDATA
SFRs
...
ACC
...
0xFF
0xB0
Port 3
...
0x80
direct &
indirect
IDATA
0xA0
Port 2
0x90
Port 1
0x80
Port 0
...
0x00
Bit – Addressable Space
(Bit Addresses 0 – 7F)
0x1F
11
Special
Function
Registers
Ports
PSW
Timer
Registers
Stack Pointer
Accumulator
Control Bits
(Etc)
(Addresses that end in 0 or 8
are also bit-addressable.)
0x18
0x17
10
0x10
0x0F
01
0x08
0x07
4 Banks of 8
Registers R0 – R7
RESET STACK POINTER
00
0x00
Logical addressing of the Internal Data Memory is mapped as shown in Figure 4-8. The internal IDATA memory space
has a total size of 384 bytes and is divided into three blocks, which are generally referred to as the Lower 128 bytes, the
Upper 128 bytes and SFR space (128 bytes size).
Internal Data Memory addresses are always one byte wide, which implies an address space of only 256 bytes. A simple
trick is used to accommodate the 384 bytes of IDATA using 8 bit addresses: direct addresses higher than 7FH access
SFR memory space, whereas indirect addresses higher than 7FH access the Upper 128 bytes of IDATA. Thus, Figure
4-8 shows the Upper 128 bytes and SFR space occupying the same block of addresses, 80H through FFH, although
they are physically separate entities.
Atmel ATPL00B [datasheet]
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In the Lower 128 bytes of IDATA, the lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call
out these registers as R0 through R7. Two bits in the Program Status Word (PSW) select which register bank is in use.
This allows more efficient use of code space, since register instructions are shorter than instructions that use direct
addressing.
The next 16 bytes above the register banks form a block of bit-addressable memory space. The 80C51 instruction set
includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these
instructions. The bit addresses in this area are 00H through 7FH.
Summarizing, the Lower 128 bytes are accessed independently of the addressing mode (direct or indirect addressing).
The Upper 128 bytes can be accessed only by indirect addressing, whereas SRF space is accessed only by direct
addressing.
Table 4-2 gives a look at the Special Function Register (SFR) space. SFRs include the Port registers, timers, peripheral
controls, etc. These registers can only be accessed by direct addressing. Sixteen addresses in SFR space are both
byte and bit addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. ADD8051C3A includes
the same 21 SFRs included in the legacy 8051C plus additional SFRs to implement the extended features.
The CPU generates the RD (P3.7) and WR (P3.6) signals needed during SRAM accesses, as shown below.
4.3.4
SFR Registers
Table 4-2 shows a map of the internal memory area called the Special Function Register (SFR) space. The entries in
bold are registers not included in the standard architecture of the 8051, these entries are specific for the ADD8051C3A.
Blank entries are not implemented on the chip. User software should not write to these unimplemented locations. Read
accesses to these addresses will return random data
Table 4-2.
Special Function Registers (specific ADD8051C3A registers in bold)
@(Hex)
@(Hex)
F8
F0
T3
B
CONF
FF
F7
E8
EF
E0
ACC
SPSTAT
SPCTL
SPDAT
SPSTAT1
SPCTL1
D8
SPDAT10
SPDAT11
SPDAT12
SPDAT13
SPDAT14
SPDAT15
D0
PSW
C8
T2CON
C0
P4
B8
IP
B0
P3
A8
IE
A0
P2
IE2
AUX1
AUX2
98
SCON
SBUF
SCON1
SBUF1
90
P1
IP2HL
88
TCON
TMOD
TL0
TL1
80
P0
SP
DPL
DPH
E7
SPDAT16
SPDAT17
DF
D7
T2MOD
RCAP2L
RCAP2H
TL2
TH2
CF
P5
C7
BF
IPH
B7
AF
A7
P3M
P4M
P5M
9F
SCON2
SBUF2
T1NP
97
TH0
TH1
TPR
T1NC
8F
PCON
87
Atmel ATPL00B [datasheet]
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The functions of some SFRs are described in the text below, while others are described with their related peripherals.
Accumulator (address: E0H)
ACC is the Accumulator register. Note that mnemonics for accumulator specific instructions usually
refer to the Accumulator simply as A.
B Register (address: F0H)
The B register is used during multiply and divide operations. For other instructions it can be treated
as another scratch pad register.
PSW register (address: D0H)
The PSW register contains program status information as detailed below.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
CY: Carry flag
AC: Auxiliary carry flag
F0: General purpose flag
RS(1:0): Register bank select control bits
OV: Overflow flag
F1: User definable flag
P: Parity flag
Stack Pointer (address: 81H)
8 bit stack pointer that is initialized to internal memory of 07H. The user program can initialize it at
any internal RAM location ranging from 07H to FFH.
Auxiliary 1
The AUX1 register includes the data pointer selection bit, the software reset control and the switch to
enable wake-up from power-down using external interrupts.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
AUX1
--
--
SRST
GF2
WUPD
0
--
DPS
--: Reserved bits
SRST: Software reset
GF2: General purpose flag
WUPD: When set, enables external interrupts driven wake-up from power down
0: fixed „0‟
DPS: Data pointer selector, selects between DPTR0 and DPTR1
P0, P1, P2, P3, P4, P5 registers
P1, P3, P4 and P5 are the SFR registers of Ports 1, 3, 4 and 5 respectively.
Writing a one/zero to a bit in these registers causes the corresponding port output pin to switch
high/low. When a port bit is used as an input the corresponding port SFR must be set to „1‟.
Ports 3, 4 and 5 are pseudo bidirectional by default, and can be configured to push-pull or pseudo
bidirectional using SFRs P3M, P4M and P5M respectively, as follows: when P4M(i) is set, P4(i) is
configured as push-pull.
Atmel ATPL00B [datasheet]
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P0 and P2 ports are no longer used to address program and external data. P0 SFR takes control of
extended addressing and program banking and P2 SFR is used when MOVX @Ri instructions are
executed (in this case, P2 SFR content is used as most significant address byte).
Data Pointer
The Data Pointer Register (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended
function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent
8-bit registers. The same entry accesses two different data pointers (DPTR0, DPTR1), user software
can switch between them using the data pointer selection bit in AUX1.
Figure 4-9. DPTR selection scheme
AUX1.DPS
DPH(1)
DPH(0)
DPTR
OUTPUT
DPTR
INPUT
DPL(1)
DPL(0)
Serial Data Buffers
The Serial Buffers have actually two separate registers, a transmit buffer and a receive buffer. When
data is moved to SBUF, it goes to the transmit buffer and is held for serial transmission. (Moving a
byte to SBUF is what initiates the transmission.) When data is moved from SBUF, it comes from the
receive buffer.
Timer Registers
Register pairs (TH0, TL0), (TH1, TL1) and (TH2, TL2) are the 16-bit Counting registers for
Timer/Counters 0, 1 and 2, respectively.
T3 is the 8-bit counting register of the watchdog timer, see 5.3 for detailed behavior description.
CONF Register
CONF register includes specific configuration features for the flash loader and Standard Serial
Interface.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CONF
--
--
--
--
--
RLD
RLT3
BAUD2
--: Reserved bits
RLD: When set, it forces program reload from SPI flash
RLT3: When set, it forces program reload from SPI flash when watchdog timeout occurs
BAUD2: doubles USART baud rates when set
Control Registers
Special Function Registers IP, IPH, IP2HL, IE, IE2, TMOD, TCON, T2CON, SCONj, SPSTATj and
PCON contain control and status bits for the interrupt system, the Timer/Counters, the serial ports
and the serial peripheral interfaces
Atmel ATPL00B [datasheet]
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4.4
Instruction Set
The instruction set provides a variety of fast addressing modes for accessing the internal RAM to facilitate byte
operations on small data structures. The instruction set provides extensive support for one-bit variables as a separate
data type, allowing direct bit manipulation in control and logic systems that require boolean processing.
4.4.1
Program Status Word
The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. The PSW, shown
in 4.3.4, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register
bank select bits, the Overflow flag, a Parity bit, and two user-definable status flags.
The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the “Accumulator” for
a number in Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown in Figure 4-8. A number of instructions
refer to these RAM locations as R0 through R7. The selection of which of the four is being referred to is made on the
basis of the RS0 and RS1 at execution time.
The Parity bit reflects the number of 1s in the Accumulator: P = 1 if the Accumulator contains an odd number of 1s, and
P = 0 if the Accumulator contains an even number of 1s. Thus the number of 1s in the Accumulator plus P is always
even. Two bits in the PSW are uncommitted and may be used as general purpose status flags.
4.4.2
Addressing Modes
Direct Addressing
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal Data
RAM and SFRs can be directly addressed.
Indirect Addressing
In indirect addressing the instruction specifies a register which contains the address of the operand. Both
internal and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be either R0 / R1 of the selected register bank or the Stack
Pointer. The address register for 16-bit addresses can only be the 16-bit “data pointer” register, DPTR.
Register Instructions
The register banks, containing registers R0 through R7, can be accessed by certain instructions which
carry a 3-bit register specification within the opcode of the instruction. Instructions that access the
registers this way are code efficient, since this mode eliminates an address byte. When the instruction is
executed, one of the eight registers in the selected bank is accessed. One of four banks is selected at
execution time by the two bank select bits in the PSW.
Register-Specific Instructions
Some instructions are specific to a certain register. For example, some instructions always operate on the
Accumulator, or Data Pointer, etc., so no address byte is needed to point to it. The opcode itself does that.
Instructions that refer to the Accumulator as A assemble as accumulator specific opcodes.
Immediate Constants
The value of a constant can follow the opcode in Program Memory.
For example:
MOV A, 64H
loads the Accumulator with the number 64H.
Atmel ATPL00B [datasheet]
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Indexed Addressing
Only program Memory can be accessed with indexed addressing, and it can only be read. This addressing
mode is intended for reading look-up tables in Program Memory. A 16-bit base register (either DPTR or
the Program Counter) points to the base of the table, and the Accumulator is set up with the table entry
number.
The address of the table entry in Program Memory is formed by adding the Accumulator data to the base
pointer.
Another type of indexed addressing is used in the “case jump” instruction. In this case the destination
address of a jump instruction is computed as the sum of the base pointer and the Accumulator data.
4.4.3
Arithmetic Instructions
The menu of arithmetic instructions is listed in Table 4-3, which indicates the addressing modes that can be used with
each instruction to access the operand. For example, the ADD A, instruction can be written as:
ADD
A, 6EH
(direct addressing)
ADD
A, @R1
(indirect addressing)
ADD
A, R6
(register addressing)
ADD
A, #206
(immediate constant)
The execution times listed in Table 4-3 assume 3 clock cycles per machine cycle (mc), using a 10MHz clock 1 mc is
executed in 0.3us. All the arithmetic instructions execute in 1mc except the Multiply and Divide instructions, which take
2mc.
Note that any byte in the internal Data Memory space can be incremented without going through the Accumulator.
One of the INC instructions operates on the 16-bit Data Pointer. The Data Pointer is used to generate 16-bit addresses
for external memory, so being able to increment it in one 16-bit operation is a useful feature.
The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the 16-bit product into the
concatenated B and Accumulator registers.
The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8-bit quotient in the
Accumulator, and the 8-bit remainder in the B register. Oddly enough, DIV AB finds less use in arithmetic “divide”
routines than in radix conversions and programmable shift operations. In shift operations, dividing a number by 2^n
shifts its n bits to the right. Using DIV AB to perform the division completes the shift in 2mc and leaves the B register
holding the bits that were shifted out.
The DA A instruction is for BCD arithmetic operations. In BCD arithmetic, ADD and ADDC instructions should always be
followed by a DA A operation, to ensure that the result is also in BCD. Note that DA A will not convert a binary number
to BCD. The DA A operation produces a meaningful result only as the second step in the addition of two BCD bytes.
Atmel ATPL00B [datasheet]
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Table 4-3. Arithmetic Instructions
ADDRESSING MODES
MNEMONIC
EXECUTION
OPERATION
DIR
IND
REG
IMM
TIMES (mc)
ADD A,
A = A +
X
X
X
X
1
ADD A,
A = A + + C
X
X
X
X
1
SUBB A,
A = A – – C
X
X
X
X
1
INC A
A=A+1
INC
= + 1
INC DPTR
DPTR = DPTR + 1
Data Pointer only
1
DEC A
A=A–1
Accumulator only
1
DEC
= – 1
MUL AB
B*A = B x A
Accumulator only
X
X
X
X
1
X
1
X
1
ACC and B only
2
ACC and B only
2
Accumulator only
1
A = Int[A/B]
DIV AB
B = Mod[A/B]
DA A
4.4.4
Decimal Adjust
Logical Instructions
Table 4-4 shows the list of logical instructions. The instructions that perform Boolean operations (AND, OR, Exclusive
OR, CPL) on bytes perform the operation on a bit-by-bit basis. That is, if the Accumulator contains 00110101B and byte
contains 01010011B, then:
ANL A,
will leave the Accumulator holding 00010001B.
The addressing modes that can be used to access the operand are listed in Table 4-4.
The ANL A, instruction may take any of the forms:
ANL
A,6FH
(direct addressing)
ANL
A,@R0
(indirect addressing)
ANL
A,R5
(register addressing)
ANL
A,#42H
(immediate constant)
All of the logical instructions execute in 1mc (0.3us using a 10MHz clock).
Atmel ATPL00B [datasheet]
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Table 4-4. Logical Instructions
ADDRESSING MODES
MNEMONIC
EXECUTION
OPERATION
DIR
IND
REG
IMM
TIME (mc)
X
X
X
1
ANL A,
A = A.AND.
X
ANL ,A
= .AND.A
X
1
ANL ,#data
= .AND.#data
X
1
ORL A,
A = A.OR.
X
ORL ,A
= .OR.A
X
1
ORL ,#data
= .OR.#data
X
1
XRL A,
A = A.XOR.
X
XRL ,A
= .XOR.A
X
1
XRL ,#data
= .XOR.#data
X
1
CLR A
A = 00H
Accumulator only
1
CPL A
A = .NOT.A
Accumulator only
1
RL A
Rotate ACC Left 1 bit
Accumulator only
1
RLC A
Rotate Left through Carry
Accumulator only
1
RR A
Rotate ACC Right 1 bit
Accumulator only
1
RRC A
Rotate Right through Carry
Accumulator only
1
SWAP A
Swap Nibbles in A
Accumulator only
1
X
X
X
X
X
X
1
1
Note that Boolean operations can be performed on any byte in the internal Data Memory space without going through
the Accumulator. The XRL , #data instruction, for example, offers a quick and easy way to invert port bits, as in
XRL P1, #0FFH.
If the operation is in response to an interrupt, not using the Accumulator saves time and effort to push it onto the stack
in the service routine.
The Rotate instructions (RL, A, RLC A, etc.) shift the Accumulator 1 bit to the left or right. For a left rotation, the MSB
rolls into the LSB position. For a right rotation, the LSB rolls into the MSB position.
The SWAP A instruction interchanges the high and low nibbles within the Accumulator. This is a useful operation in
BCD manipulations.
Atmel ATPL00B [datasheet]
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4.4.5
Data Transfer Instructions
Internal RAM
Table 4-5 shows the menu of instructions that are available for moving data around within the internal memory spaces,
and the addressing modes that can be used with each one. All of these instructions are executed in 1 mc.
Table 4-5. Data Transfer Instructions that Access Internal Data Memory Space
EXE
CUTI
ON
ADDRESSING MODES
MNEMONIC
OPERATION
DIR
IND
REG
IMM
TIME
(mc)
X
1
MOV A,
A =
X
X
X
MOV ,A
= A
X
X
X
MOV ,
=
X
X
X
MOV DPTR,#data16
DPTR = 16-bit immediate constant
PUSH
INC SP:MOV“@SP”,
X
1
POP
MOV ,“@SP”:DEC SP
X
1
XCH A,
ACC and exchange data
X
XCHD A,@Ri
ACC and @Ri exchange low nibbles
X
1
X
1
X
1
X
1
X
1
The MOV , instruction allows data to be transferred between any two internal RAM or SFR locations
without going through the Accumulator. Remember, the upper 128 bytes of IDATA can be accessed only by indirect
addressing, and SFR space only by direct addressing.
Note that in any 80C51 device, the stack resides in on-chip RAM, and grows upwards. The PUSH instruction first
increments the Stack Pointer (SP), then copies the byte into the stack. PUSH and POP use only direct addressing to
identify the byte being saved or restored, but the stack itself is accessed by indirect addressing using the SP register.
This means the stack can go into the Upper 128 bytes of RAM, if they are implemented, but not into SFR space.
The Data Transfer instructions include a 16-bit MOV that can be used to initialize the Data Pointer (DPTR) for look-up
tables in Program Memory, or for 16-bit external Data Memory accesses.
The XCH A, instruction causes the Accumulator and addressed byte to exchange data. The XCHD A, @Ri
instruction is similar, but only the low nibbles are involved in the exchange.
External RAM (from microcontroller point of view)
Table 4-6 shows a list of the Data Transfer instructions that access external Data Memory. Only indirect addressing can
be used. The choice is whether to use a one-byte address, @Ri, where Ri can be either R0 or R1 of the selected
register bank, or a two-byte address, @DPTR. All of these instructions execute in 2 mc.
Note that in all external Data RAM accesses, the Accumulator is always either the destination or source of the data.
The read and write strobes to external RAM are activated only during the execution of a MOVX instruction.
Atmel ATPL00B [datasheet]
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Table 4-6. Data Transfer Instructions that access External Data Memory Space
ADDRESS
MNEMONIC
OPERATION
EXECUTION TIME (mc)
8 bits
MOVX A,@Ri
Read external RAM @Ri
2
8 bits
MOVX @Ri,A
Write external RAM @ Ri
2
16 bits
MOVX A,@DPTR
Read external RAM @ DPTR
2
16 bits
MOVX @DPTR,A
Write external RAM @ DPTR
2
WIDTH
Code Constants
Table 4-7 shows the two instructions that are available for reading code constants in Program Memory. Since these
instructions access only Program Memory, the code constants can only be read, not updated.
The mnemonic is MOVC for “move constant”. The first MOVC instruction in Table 4-7 can accommodate a table of up to
256 entries numbered 0 through 255. The number of the desired entry is loaded into the Accumulator, and the Data
Pointer is set up to point to the beginning of the table. Then, MOVC A,@A+DPTR copies the desired table entry into the
Accumulator.
The other MOVC instruction works the same way, excepting that the Program Counter (PC) is used as the base
address: MOVC A,@A+PC
Table 4-7. Code Constants Read Instructions
4.4.6
MNEMONIC
OPERATION
EXECUTION TIME (mc)
MOVC A,@A+DPTR
Read program memory at (A + DPTR)
2
MOVC A,@A+PC
Read program memory at (A + PC)
2
Boolean Instructions
80C51 devices contain a complete Boolean (single-bit) processor. The internal RAM contains 128 addressable bits, and
the SFR space can support up to 128 addressable bits as well. All of the port lines are bit-addressable, and each one
can be treated as a separate single-bit port. The instructions that access these bits are not just conditional branches,
but a complete menu of move, set, clear, complement, OR, and AND instructions. These kinds of bit operations are not
easily obtained in other architectures with any amount of byte-oriented software. The instruction set for the Boolean
processor is shown in Table 4-8. All bit accesses are by direct addressing.
Bit addresses 00H through 7FH are in the Lower 128, and bit addresses 80H through FFH are in SFR space.
The Carry bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instructions that refer to
the Carry bit as C assemble as Carry-specific instructions (CLR C, etc.). The Carry bit also has a direct address, since it
resides in the PSW register, which is bit-addressable.
Note that the Boolean instruction set includes ANL and ORL operations, but not the XRL (Exclusive OR) operation.
There is a series of bit-test instructions which execute a jump if the addressed bit is set (JC, JB, JBC) or if the
addressed bit is not set (JNC, JNB). JBC executes the jump if the addressed bit is set, and also clears the bit. Thus a
flag can be tested and cleared in one operation. All the PSW bits are directly addressable, so the Parity bit, or the
general purpose flags, for example, is also available to the bit-test instructions.
Atmel ATPL00B [datasheet]
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Table 4-8. Boolean Instructions
MNEMONIC
OPERATION
EXECUTION TIME (mc)
ANL C,bit
C = C.AND.bit
1
ANL C,/bit
C = C.AND..NOT.bit
1
ORL C,bit
C = C.OR.bit
1
ORL C,/bit
C = C.OR..NOT.bit
1
MOV C,bit
C = bit
1
MOV bit,C
bit = C
1
CLR C
C=0
1
CLR bit
bit = 0
1
SETB C
C=1
1
SETB bit
bit = 1
1
CPL C
C = .NOT.C
1
CPL bit
bit = .NOT.bit
1
JC rel
Jump if C = 1
2
JNC rel
Jump if C = 0
2
JB bit,rel
Jump if bit = 1
2
JNB bit,rel
Jump if bit = 0
2
JBC bit,rel
Jump if bit = 1; CLR bit
2
Relative Offset
The destination address for these jumps is specified to the assembler by a label or by an actual address in Program
memory. However, the destination address assembles to a relative offset byte. This is a signed (two‟s complement)
offset byte which is added to the PC in two‟s complement arithmetic if the jump is executed. The range of the jump is
therefore –128 to +127 Program Memory bytes relative to the first byte following the instruction.
4.4.7
Jump Instructions
Table 4-9 shows the list of unconditional jumps and the execution time associated.
The table lists SJMP, LJMP, and AJMP, which differ in the format of the destination address. JMP is a generic
mnemonic which can be used if the programmer does not care which way the jump is encoded.
The SJMP instruction encodes the destination address as a relative offset, as described above. The instruction is 2
bytes long, consisting of the opcode and the relative offset byte. The jump distance is limited to a range of –128 to +127
bytes relative to the instruction following the SJMP.
The LJMP instruction encodes the destination address as a 16-bit constant. The instruction is 3 bytes long, consisting of
the opcode and two address bytes. The destination address can be anywhere in the 64k Program Memory space.
Atmel ATPL00B [datasheet]
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The AJMP instruction encodes the destination address as an 11-bit constant. The instruction is 2 bytes long, consisting
of the opcode, which itself contains 3 of the 11 address bits, followed by another byte containing the low 8 bits of the
destination address. When the instruction is executed, these 11 bits replace the low 11 bits in the PC. The high 5 bits
stay the same. Hence the destination has to be within the same 2k block as the instruction following the AJMP.
The JMP @A+DPTR instruction supports case jumps. The destination address is computed at execution time as the
sum of the 16-bit DPTR register and the Accumulator. Typically, DPTR is set up with the address of a jump table.
Table 4-9 shows two “CALL addr” instructions LCALL and ACALL, which differ in the format in which the subroutine
address is given to the CPU. CALL is a generic mnemonic which can be used if the programmer does not care which
way the address is encoded.
The LCALL instruction uses the 16-bit address format, and the subroutine can be anywhere in the 64k Program Memory
space.
The ACALL instruction uses the 11-bit format, and the subroutine must be in the same 2k block as the instruction
following the ACALL.
Subroutines should end with a RET instruction, which returns execution to the instruction following the CALL.
RETI is used to return from an interrupt service routine. The only difference between RET and RETI is that RETI tells
the interrupt control system that the interrupt in progress is done. If there is no interrupt in progress at the time RETI is
executed, then the RETI is functionally identical to RET.
Table 4-10 shows the list of conditional jumps available to the microcontroller user. All of these jumps specify the
destination address by the relative offset method, and so are limited to a jump distance of –128 to +127 bytes from the
instruction following the conditional jump instruction.
There is no Zero bit in the PSW. The JZ and JNZ instructions test the Accumulator data for that condition.
The DJNZ instruction (Decrement and Jump if Not Zero) is for loop control.
The CJNE instruction (Compare and Jump if Not Equal) can also be used for loop control. Two bytes are specified in
the operand field of the instruction. The jump is executed only if the two bytes are not equal. Another application of this
instruction is in “greater than, less than” comparisons. The two bytes in the operand field are taken as unsigned
integers. If the first is less than the second, then the Carry bit is set (1). If the first is greater than or equal to the second,
then the Carry bit is cleared.
Table 4-9. Unconditional Jump instructions
MNEMONIC
OPERATION
EXECUTION TIME (mc)
(S)JMP addr
Jump to addr
2
(L)JMP addr
Jump to addr
2
(A)JMP addr
Jump to addr
2
JMP @A+DPTR
Jump to A + DPTR
2
(A,L)CALL addr
Call subroutine at addr
2
RET
Return from subroutine
2
RETI
Return from interrupt
2
NOP
No operation
1
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
36
Table 4-10. Conditional Jump instructions
ADDRESSING MODES
MNEMONIC
DIR
4.5
EXECUTION
OPERATION
IND
REG
IMM
TIME(mc)
JZ rel
Jump if A = 0
2
JNZ rel
Jump if A /= 0
2
DJNZ ,rel
Decrement and jump if not
zero
X
CJNE A,,rel
Jump if A /=
X
CJNE
,#data,rel
Jump if /= #data
X
2
X
X
X
2
2
CPU Timing
Execution time is divided into machine cycles. A machine cycle consists of a sequence of 3 states, numbered S1
through S3. Each state time lasts for one clock period. Thus a machine cycle takes 3 clock periods (or near 0.27 s if the
clock frequency is 11.059.200Hz).
Figure 4-10 shows fetch/execute sequences for various kinds of instructions; while an instruction is being executed
code bytes for the next instruction are fetched. Normally three program fetches are generated during each machine
cycle, even if the next instruction to be executed doesn‟t require it. If the instruction doesn‟t need the three code bytes,
the CPU simply ignores the extra fetches, and the Program Fetch Counter is not incremented.
All the instructions, except MOVX, have the same fetch/execute sequence.
The MOVX instructions take two machine cycles to execute. During a MOVX instruction only one fetch is generated, S1
in machine cycle 1. This is the only time program fetches are skipped. The fetch/execute sequence for MOVX
instructions is shown in Figure 4-10b and Figure 4-10c.
The fetch/execute sequences are the same whether the Program Memory is internal or external to the chip. Execution
times do not depend on whether the Program Memory is internal or external.
Figure 4-10 shows the signals and timing involved in program fetches when the Program Memory is external. If
Program Memory is external, then the Program Memory read strobe PSEN is normally activated („0‟) three times per
machine cycle, as shown in Figure 4-10a. If an access to external Data Memory occurs, as shown in Figure 4-10b and
15c, five PSENs are skipped, because the address and data bus are being used for the Data Memory access.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
37
Figure 4-10. Bus timing in 8051C3A
S1
S2
S3
S1
S2
S3
S1
S2
S3
wri
dec
exe
wri
dec
exe
wri
dec
exe
wri
dec
ADD
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
PC+7
PC+8
PC+9
PC+..
DATA
OPC
OPC+1
OPC+2
OPC+3
OPC+4
OPC+5
OPC+6
OPC+7
OPC+8
OPC+9
OPC+..
S1
S2
S3
PC+2
PC+3
PC+4
PC+..
OPC+2
OPC+3
OPC+4
OPC+..
CLOCK
CPU
state
PSEN
RD
WR
(a) Program execution without
S1
S2
S3
S1
S2
MOVX
S3
CLOCK
PSEN
RD
WR
ADD
PC
PC+1
XX
DATA
OPC
OPC+1
ZZ
READ ADD
ZZ
READ DATA
(b) Program execution with
S1
S2
S3
S1
S2
ZZ
a read MOVX
S3
S1
S2
S3
PC+2
PC+3
PC+4
PC+..
OPC+2
OPC+3
OPC+4
OPC+..
CLOCK
PSEN
RD
WR
ADD
PC
PC+1
XX
DATA
OPC
OPC+1
ZZ
WRITE ADD
WRITE DATA
(c) Program execution with
4.5.1
ZZ
a write MOVX
Reset
ATPL00B can be reset in different ways, listed and explained below
External reset. The external reset input signal is RSTA which is an asynchronous reset. Every time RSTA
signal is asserted, the boot loader is triggered (thus, microcontroller is halted, target program from the serial
flash is uploaded to the internal SRAM, and then microcontroller is released to begin program execution). In
power-on, D_INIT must be set before RSTA in order to ensure proper system start up.
Software reset AUX1(5) = AUX1.SRST. This field in AUX1 SFR forces the microcontroller to start program
execution from PC=0, and all the SFRs are initialized to their reset default values. This reset doesn‟t affect the
boot loader reload.
Software reset CONF(2) = CONF.RLD. This field is directly connected to boot loader reload input. Every
time the microcontroller sets this field, the boot loader is triggered.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
38
Watchdog reset /EWDG signal and CONF(1)=CONF.RLT3.
CONF.RLT3 = „0‟ : After a watchdog timeout, microcontroller starts execution from PC=0, but boot
loader is not triggered.
CONF.RLT3 = „1‟ : After a watchdog timeout, if field RLT3 in CONF SFR is „1', boot loader is triggered.
The microcontroller keeps track of the start-up point in the AUX2 register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
AUX2
--
--
--
--
--
ST2
ST1
ST0
--: Reserved bits
ST(2:0): Start-up flags
“000”:Asynchronous external reset
“001”:Software reset by writing AUX1(5)=‟1‟
“010”:Watchdog T3 timeout
“100”:Asynchronous external reset
SFR values after a reset are shown in Table 4-11. The internal RAM is not affected. Port registers are initialized to FFH
to keep port pins in pull-up state.
Table 4-11. SFRs Reset values
SFR
Address
Reset
Value
SFR
Address
Reset
Value
SFR
Address
Reset Value
P0
SP
DPL
DPH
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
TPR
T1NC
P1
IP2HL
SCON2
SBUF2
T1NP
SCON
SBUF
SCON1
80H
81H
82H
83H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
90H
91H
94H
95H
96H
98H
99H
9AH
11111111
00000111
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00111111
00000000
11111111
xxxx0000
00000000
00000000
00000000
00000000
00000000
00000000
SBUF1
P3M
P4M
P5M
P2
IE2
AUX1
AUX2
IE
P3
IPH
IP
P4
P5
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
PSW
9BH
9CH
9DH
9EH
A0H
A1H
A2H
A3H
A8H
B0H
B7H
B8H
C0H
C4H
C8H
C9H
CAH
CBH
CCH
CDH
D0H
00000000
00000000
00000000
00000000
11111111
xxxxxx00
00000000
xxxxxbbb
00000000
11111111
00000000
00000000
11111111
11111111
00000000
xx001100
00000000
00000000
00000000
00000000
00000000
SPDAT10
SPDAT11
SPDAT12
SPDAT13
SPDAT14
SPDAT15
SPDAT16
SPDAT17
ACC
SPSTAT
SPCTL
SPDAT
SPSTAT1
SPCTL1
B
CONF
T3
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
E0H
E1H
E2H
E3H
E4H
E5H
F0H
F1H
FFH
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
000xxxxx
00000100
00000000
000xx000
00000100
00000000
00000000
00000000
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
39
4.5.2
Power Saving Modes
ADD8051C3A has two power-saving modes, Idle and Power Down.
In the Idle mode (IDL = 1), the CPU is stopped but the peripheral circuits continue running.
In Power Down (PD = 1), the CPU and the peripheral circuits are stopped, except external interrupts hardware that can
be configured to run when in power down mode.
The Idle and Power Down Modes are activated by setting bits in Special Function Register PCON. If 1s are written to
PD and IDL at the same time, PD takes precedence. When watchdog is enabled power down modes are automatically
disabled.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
PCON
SMOD
--
--
WLE
GF1
GF0
PD
IDL
4.5.3
SMOD: Double baud rate bit when timer 1 is used as time generator and serial port is in
modes 1, 2 or 3
--: Reserved bits
WLE: Watchdog load enable. It must be set by software to enable T3 reload. It is reset by
hardware after 13 machine cycles
GF1: General purpose flag bit, user programmable
GF0: General purpose flag bit, user programmable
PD: Sets power-down mode
IDL: Sets idle mode
Idle Mode
Setting PCON(0), CPU is stopped but peripheral circuits (Interrupts, Timers, Standard Serial Interface and Serial
Peripheral Interface functions) continue running. The CPU status is entirely preserved; Stack Pointer, Program Counter,
Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins hold the logical
states they had at the time Idle was activated. PSEN holds at logic high level.
There are two ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON(0) to be cleared by hardware, terminating the Idle mode.
The interrupt will be served, and following RETI, the next instruction to be executed will be the one following
the instruction that put the device into Idle.
Reset signal. The signal at the RSTA pin redefines all the SFR values to their reset values and then the IDL bit
is cleared. At this time, and with three clock cycle delay, the CPU restart program execution with program
counter at initial value 0x0000, RAM content remains unchanged.
4.5.4
Power-Down Mode
An instruction that sets PCON(1) causes that to be the last instruction executed before going into the Power Down
mode. In the Power Down mode all functions are stopped, except external interrupts hardware. The contents of the onchip RAM and Special Function Registers are maintained. The port pins output the values held by their respective
SFRs. The PSEN output is held low.
There are two ways to exit Power Down mode.
Hardware reset. Hardware reset redefines all the SFRs.
External interrupt. External interrupts must be configured for low level activation.When they are enabled a low
level at their inputs will cause a microcontroller restart and a jump to the corresponding interruption routine. As
in idle mode, the interrupt will be served, and following RETI, the next instruction to be executed will be the
one following the instruction that put the device into power down.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
40
4.6
Interrupts
The microcontroller has 10 user interrupt sources:
2 external interrupts.
3 timer interrupts.
3 serial port interrupts.
2 standard serial peripheral interrupts.
Interrupt priorities are user selectable to a priority level ranging from “000” to “011” (higher value correspond to higher
priority level).
4.6.1
Interrupt Enabling
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the SFRs named IE and IE2
(Interrupt Enable). The IE register also contains a global disable bit, which can be cleared to disable all interrupts at
once.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
IE
EA
ET2
ESPI
ES
ET1
EX1
ET0
EX0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
IE2
--
--
--
--
ESPI1
ES2
--
ES1
4.6.2
EA: „1‟ enables all interrupts; „0‟ disables all interrupts
ET2: „1‟ enables timer 2 interrupt; „0‟ disables timer 2 interrupt
ESPI: „1‟ enables serial peripheral interface0 interrupt; „0‟ disables serial peripheral
interface0 interrupt
ES: „1‟ enables serial port 0 interrupt; „0‟ disables serial port0 interrupt
ET1: „1‟ enables timer 1 interrupt; „0‟ disables timer 1 interrupt
EX1: „1‟ enables external interrupt 1; „0‟ disables external interrupt 1
ET0: „1‟ enables timer 0 interrupt; „0‟ disables timer 0 interrupt
EX0: „1‟ enables external interrupt 0; „0‟ disables external interrupt 0
--: Reserved bit
ESPI1: „1‟ enables serial peripheral interface1 interrupt; „0‟ disables serial peripheral
interface1 interrupt.
ES2: „1‟ enables serial port 2 interrupt; „0‟ disables serial port2 interrupt
ES1: „1‟ enables serial port 1 interrupt; „0‟ disables serial port1 interrupt
Interrupt Priorities
Each interrupt source can also be individually programmed to four priority levels by setting or clearing two bits in the
SFRs named IP, IPH and IP2HL (Interrupt Priority). Figure 4-11 shows how the IE, IE2, IP, IPH and IP2HL registers and
the polling sequence work to determine the interrupt to be served. The IP, IPH, IP2HL and IE2 registers contain a
number of unimplemented bits, these bits are reserved and user software should not write to these positions.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
41
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
IP
--
PT2
PSPI
PS0
PT1
PX1
PT0
PX0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
IPH
--
PT2H
PSPIH
PS0H
PT1H
PX1H
PT0H
PX0H
-- : Reserved bit
[IPH(6),IP(6)] : PT2 defines timer 2 interrupt priority level
[IPH(5),IP(5)] : PSPI defines serial peripheral interface SPI0 interrupt priority level
[IPH(4),IP(4)] : PS0 defines serial port 0 interrupt priority level
[IPH(3),IP(3)] : PT1 defines timer 1 interrupt priority level
[IPH(2),IP(2)] : PX1 defines external interrupt 1 priority level
[IPH(1),IP(1)] : PT0 defines timer 0 interrupt priority level
[IPH(0),IP(0)] : PX0 defines external interrupt 0 priority level
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
IP2HL
PSPI1_1
PSPI1_0
PS2_1
PS2_0
--
--
PS1_1
PS1_0
IP2HL(7:6) : PSPI1 defines serial peripheral port 1 SPI1 priority level
IP2HL(5:4) : PS2 defines serial port 2 priority level
-- : Reserved bit
IP2HL(1:0) : PS1 defines serial port 1 priority level
A low-priority interrupt can only be interrupted by a higher priority interrupt (but neither by another low-priority nor an
equal-priority interrupt).
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority is served. If
interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which
request is served. Thus within each priority level there is a second priority structure determined by the polling sequence
as follows:
0.
1.
2.
3.
4.
5.
6.
7.
9.
10.
IE0
TF0
IE1
TF1
RI+TI
SPI0
TF2+EXF2
RI1+TI1
RI2+TI2
SPI1
(highest priority)
(lowest priority)
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
42
When in operation mode, all the interrupt flags are latched into the interrupt control system during state 2 of every
machine cycle. The samples are polled during the following machine cycle. If the flag for an enabled interrupt is found to
be set („1‟), the interrupt system generates an LCALL to the appropriate location in Program Memory, unless some
other condition blocks the interrupt. Several conditions can block an interrupt, for example when an interrupt of equal or
higher priority level is already in progress.
The hardware-generated LCALL causes the value in the Program Counter to be pushed into the stack, and reloads the
PC with the beginning address of the service routine. As previously noted the service routine for each interrupt begins at
a fixed location.
Only the Program Counter is automatically pushed onto the stack, not the PSW or any other register.
Having only the PC automatically saved it is a programmer task to save other registers if necessary
Figure 4-11. Interrupt Priorities diagram
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
43
4.6.3
Interrupt Handling
External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and
IT1 in Register TCON. When external interrupts are transition-activated the INTx pin must show a high level in one
cycle and a low level in the next cycle to generate the interrupt, so that an input high or low should hold for at least 1
machine cycle to ensure sampling. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. The
flags are cleared by hardware when the service routine is vectored only if the interrupts are transition-activated. When
the interrupts are level-activated the interrupt flags are controlled by the external source, so that the external source has
to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.
The response time is always more than 3 machine cycles and less than 7 machine cycles depending on program
execution and interrupt status (see Figure 4-12).
Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover. The flags are cleared by the
on-chip hardware when the service routines are vectored.
Timer 2 interrupts (TF2 and EXF2) are user configurable, and depending on configuration flags will be cleared by
hardware or by user software.
Serial Ports Interrupts are generated by the logical OR of RI and TI. They must be cleared by software.
SPI interrupts must be cleared by software.
Figure 4-12. Interrupt Handling
S2 S3 S1 …. S3
interrupt
latching
interrupt
polling
S1 …. S3 S1 …. S3 S1 …. S3 S1
hardware LCALL
to interrupt code
interrupt code
2nd interrupt polling
executed when previous polling is blocked
All of the bits that generate interrupts can be set or cleared by software. That is, interrupts can be generated or pending
interrupts can be canceled by software. Each of these interrupt sources can be individually enabled or disabled by
setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
The interrupt flags are sampled at every machine cycle. The samples are polled during the following machine cycle. If
one of the flags was in a set condition at the preceding cycle, the polling cycle will find it and the interrupt system will
generate an LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any
of the following conditions:
Condition 1. An interrupt of equal or higher priority level is already in progress.
Condition 2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress.
Condition 3. The instruction in progress is RETI or any write to the IE or IP registers.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
44
Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures
that the instruction in progress will be completed before vectoring to any service routine. Condition 3 ensures that if the
instruction in progress is RETI or any access to IE or IP, then at least one more instruction will be executed before any
interrupt is vectored to.
The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at the
previous machine cycle. The polling cycle/LCALL sequence is illustrated in Figure 4-12.
The hardware-generated LCALL executes a program jump to fixed program entries as shown below:
Table 4-12. Fixed Program entries
Source
Vector
Address
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI0+TI0
0023H
SPI0
002BH
TF2+EXF2
0033H
RI1+TI1
003BH
RI2+TI2
004BH
SPI1
0053H
Execution proceeds from that location until the RETI instruction is encountered then the interrupted program continues
from where it left off.
4.7
I/O Ports
The ports P1, P3, P4 and P5 in the ADD8051C3A are bidirectional. Each port consists of a register (Special Function
Registers P1, P3, P4, P5), an output driver, and an input buffer.
Pins in ports 3, 4 and 5 are multifunctional. They are port pins and also serve as input or output for the microcontroller
peripherals:
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
45
Table 4-13. P3, P4, P5 ports Alternate Functions
Pin
Note:
4.7.1
Alternate Function
P3.0
RxD (serial port 0 input)
P3.1
TxD (serial port 0 output)
P3.2
INT0 (external interrupt 0)
P3.3
INT1 (external interrupt 1)
P3.4
T0 (timer 0 external input)
P3.5
T1 (timer 1 external input)
P3.6
WR(external data memory write strobe)
P3.7
RD (external data memory read strobe)
P4.0
RxD (serial port 2 input)
P4.1
TxD (serial port 2 output)
P4.2
SS1 (SPI1 slave select input)
P4.3
SPICLK1 (SPI1 clock input/output)
P4.4
MOSI1 (SPI1 master out / slave in data)
P4.5
MISO1 (SPI1 master in / slave out data
P4.6
T2 (timer 2 input/output)
P4.7
T2EX (timer 2 external input)
P5.0
SS (SPI0 slave select input)
P5.1
SPICLK (SPI0 clock input/output)
P5.2
MOSI (SPI0 master output / slave input data)
P5.3
MISO (SPI0 master input / slave output data)
P5.4
RxD (serial port 1 input)
P5.5
TxD (serial port 1 output)
To use an Alternate Function the corresponding bit (or bits) in the SFR must contain a 1.
I/O Configurations
Figure 4-13 and Figure 4-14 show a functional diagram of bit register and I/O buffer in each of the four ports. The level
of the port pin is placed on the internal bus and instructions can read the port pin value or the SFR register value.
If a bit in a register with AOF (Alternate Output Function) contains a 1, then the output level is controlled by the signal
labeled “Alternate Output function”.
Figure 4-13. Pins with AOF structure
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
46
Figure 4-14. Pins without AOF structure
OE
register
read
write
data
D
Q
Pj.i
PIN
Pj.i
REG.
write
clock
CLK Q
pin
read
Pseudo-bidirectional mode
Ports 1, 3, 4 and 5 have internal pull-ups. Each I/O line can be independently used as an input or an output. To be used
as an input, the port bit register must contain a „1‟; When an SFR port bit is set to „1‟ the PMOS port driver is turned on
one clock cycle and then is turned off. Then, the pin is pulled high by a weak internal pull-up, and can be pulled low by
an external source. In the ADD8051C3A included in ATPL00B, the pull-up consists of 33Kohm resistors.
P1, P3, P4 and P5 registers are set to FFH by default (configured as inputs).
Push-Pull mode
Ports 3, 4 and 5 can be configured as Push-Pull output ports using P3M, P4M and P5M SFRs respectively.
Setting a bit in these SFRs to `1‟ configures the corresponding port as Push-Pull mode.
Setting a bit in these SFRs to „0‟ configures the corresponding port as Pseudo-bidirectional.
P3M, P4M and P5M are set to 00H by default (configured in Pseudo-bidirectional mode).
4.7.2
Read-Modify-Write Feature
Some instructions that read a port read the register and others read the pin. Only the read-modify-write instruction read
the register. The instructions that read the register rather than the pin are the ones that read a value, possibly change it,
and then rewrite it to the register. When the destination operand is a port, or a port bit, these instructions read the
register rather than the pin: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ, MOV PX.Y,C, CLR PX.Y, SET PX.Y. The last
three instructions are bit modify instructions. They read the port byte, all 8 bits, modify the target bit, then the modified
byte is written to the register.
The-modify-write instructions are directed to the register to avoid a possible misinterpretation of the voltage level at the
pin. When a port register is set to „1‟ to using the pin as input an external source can be pulling the pin to „0‟, if we need
to know the configuration of the port we need to read the register and to know the state of the external source we need
to read the pin.
4.7.3
Accessing External Memories
Accesses to external memory are of two types: accesses to external program code and accesses to external program
data. Both share ports ADDRESS and DATA buses. Accesses to external program code use signal PSEN (program
store enable) as the read strobe. Accesses to external program data use RD(P3.7) or WR(P3.6) to strobe the memory.
Fetches from external program memory always use a 16-bit logical address, fetches to external data can use 16-bit or
8-bit logical address.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
47
4.8
Debug Mode
Debug mode is active when DBG pin is set to „1‟. Debug mode is intended to implement software debugging tools.
As stated in Table 2-1, DEBUG digital input is internally connected to DBG signal of the ADD8051C3A microcontroller
When in debug mode, a program can modify its own code. Thus, user should not work in debug mode unless explicitly
stated otherwise.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
48
5.
Timers
The ADD8051C3A has a full set of timers, listed below:
Two 16-bit configurable Timers/Counters: Timer 0 and Timer 1 that can be configured as timers or event
counters.
Three 8-bit auto reload counters Timers 11, 12 and 14, used as baud rate generators for uarts 0, 1 and 2
respectively (see Standard Serial Interfaces section).
One 8-bit, with 18-bit preescaler, watchdog timer: Timer 3 (see Watchdog (timer 3) section).
One 16-bit Timer/Counter Timer 2 with capture reload hardware (see 5.2)
5.1
Timer 0 and Timer 1
Timers 0 and 1 have 2-bit preescalers. These preescalers can be programmed to slow down count rate. The reset value
set the preescaler values to the slowest count rate and the real count rate of the timers is the same than the timers in an
“8051 legacy” microcontroller (12 clock cycles per machine cycle).
TPR, TMOD and TCON registers described below are involved in timer 0 and timer 1 management.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
TPR
--
--
T1P1
T1P0
T01P1
T01P0
T0P1
T0P0
--: Reserved bit
T1P(1:0): Rollover value for T1 preescaler when T1 is in modes 0, 1, 2 and 3
T01P(1:0): Rollover value for TH0 preescaler when T0 is in mode 3
T0P(1:0): Rollover value for T0 preescaler when T0 is in modes 0, 1, and 2, and for TL0
preescaler when T0 is in mode 3
When T0 or T1 are in the timer function, the registers are incremented every 1, 2, 3 or 4 machine cycles. Since a
machine cycle consists of 3 oscillator periods, the count rate is 1/3, 1/6, 1/9 or 1/12 of the oscillator frequency.
In the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input
pin, T0(P3.4) or T1(P3.5). When in counter function, the external input is sampled once every machine cycle. When the
samples show a high in one cycle and a low in the next cycle (1-to-0 transition), the count is incremented. The register
value is updated during the cycle following the one in which the transition was detected, the maximum count rate is 1/2
of the machine cycle frequency.
Either the timer or counter function is selected by control bit C/T in the Special Function Register TMOD where T0 and
T1 have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD.
TIMER 1
TIMER 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
GATE:
„1‟: Enables gate control. Device count is enabled only when both „INTi‟ pin and
“TCON.TRi” are high.
„0‟: Disables gate control. Device count is enabled when “TCON.TRi” is high.
C/T:
„1‟: Counter operation mode. Input from Ti input pin
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
49
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
5.1.1
„0‟: Timer operation mode. Input from internal clock system
M(1:0): Operation modes
“00”: Mode 0: 8048 13bit timer, TLi used as 5 bit preescaler
“01”: Mode 1: 16 bit timer/counter composed by concatenated THi and TLi
“10”: Mode 2: 8 bit with auto reload (TLi 0)
(2)
MISO
P5.3
(1)
MOSI
P5.2
(1)
SPICLK
P5.1
slave
out
in
in
(1)
comment
SPI0 disabled, P5(3:0)
are used as port pins
1
master
in
out
out
P5.0
(1)
0
slave
out
in
in
slave not needing SS
P5.0
(1)
1
master
in
H
H
master not needing SS
1.
function as port or as alternate output function
2.
the MSTR bit changes to „0‟ automatically when SS becomes low in input mode and SSIG is 0
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
69
7.3
SPI1 buffer operation
SPI1 is a byte buffered serial peripheral interface. Data transfers have a selectable additional number of bytes ranging
from 0 to 7, SPSTAT1(2:0) is used to select the number of additional bytes. The buffer is composed of the registers
SPDAT10 to SPDAT17. The content of SPDAT10 is the first to be transferred.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
SPCTL1
SSIG
SPEN
DORD
MSTR
CPOL
CPHA
PSC1
PSC0
SSIG: /SS1 slave select ignore, if set to '1' MSTR decides whether the device is a master
or a slave and /SS1 pin can be used as port pin; if set to '0' and MSTR is set to '1' then
the /SS1 pin decides whether the device is a master or a slave
SPEN: SPI1 enabled '1' or disabled '0', when the SPI1 is disabled the SPI1 pins can be
used as general I/O pins
DORD: SPI1 data order
'1' - the LSB of the data byte is transmitted first
'0' - the MSB of the data byte is transmitted first
MSTR: master '1' / slave '0' mode select. See SSIG field
CPOL: SPI1 clock polarity
'1' – SPICLK1 is high when idle, the leading edge of SPICLK1 is the falling edge and
the trailing edge is the rising edge
'0' – SPICLK1 is low when idle, the leading edge of SPICLK1 is the rising edge and
the trailing edge is the falling edge
CPHA: SPI1 clock phase select
'1' - data is driven on the leading edge of SPICLK1 and is sampled on the trailing
edge
'0' - the first data bit is on the MOSI1/MISO1 line before the first SPICLK1 leading
edge, data is sampled on the leading edge of SPICLK1 and driven on the trailing
edge of SPICLK1
PSC(1:0): SPI1 clock rate select, determines master clock output. 8 different baud rates
can be selected using PSC2[SPSTAT1(5)] & PSC(1:0)[SPCTL1(1:0)]
When working as slave, PSC(2:0) value is not taken into account, nevertheless this value
must be different from “000”
PSC(2:0)
clock rate
“000”
fosc/4
“001”
fosc/16
“010”
fosc/64
“011”
fosc/128
“100”
fosc/256
“101”
fosc/512
“110”
fosc/1024
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
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Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
SPSTAT1
SPIF
WCOL
PSC2
--
--
N2
N1
N0
--: Reserved bit
SPIF: SPI1 transfer completion flag. When ESPI1 (IE2.3) bit and EA (IE.7) bit are '1' and
a SPI1 transfer finishes then the SPIF bit is set by hardware and an interrupt is
generated. SPIF will also be set when SPI1 is in master mode with SSIG(SPCTL1.7)='0'
and /SS(slave select) pin is driven low
WCOL: SPI1 write collision flag. The WCOL bit is set by hardware when SPDAT is written
during a data transfer. WCOL flag is cleared in software by writing '0' to this bit.
PSC2: SPI1 master clock rate select msb
N(2:0): Number of additional bytes to transfer in SPI1
The data bytes to be transferred must be written in order. Transfer will start when SPDAT1N is written if
N=SPSTAT(2:0).
A write collision will occur if any SPDAT1N (with N 90
0
10ms
20ms
In case that PWM mode is selected, these four registers are used to adjust the duty cycle. In this case, each one
must contain a value between 0 and 255 (0xFF). When 255 (0xFF), PWM output is always VDD.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
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9.1.5
POLARITY register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
POLARITY
IN_POL3
IN_POL2
IN_POL1
IN_POL0
OUT_POL3
OUT_POL2
OUT_POL1
OUT_POL0
Name:
POLARITY
Address:
0xFEA7
Reset:
“11111111”
IN_POL3:
This bit sets the polarity of D3 field in INP_ST register
„0‟: The bit D3 will be equal to „1‟ when the switch connected to INTERR3 input is OFF,
and equal to „0‟ when the switch is ON
„1‟: The bit D3 will be equal to „0‟ when the switch connected to INTERR3 input is OFF,
and equal to „1‟ when the switch is ON
IN_POL2:
This bit sets the polarity of D2 field in INP_ST register
„0‟: The bit D2 will be equal to „1‟ when the switch connected to INTERR2 input is OFF,
and equal to „0‟ when the switch is ON
„1‟: The bit D2 will be equal to „0‟ when the switch connected to INTERR2 input is OFF,
and equal to „1‟ when the switch is ON
IN_POL1:
This bit sets the polarity of D1 field in INP_ST register
„0‟: The bit D1 will be equal to „1‟ when the switch connected to INTERR1 input is OFF,
and equal to „0‟ when the switch is ON
„1‟: The bit D1 will be equal to „0‟ when the switch connected to INTERR1 input is OFF,
and equal to „1‟ when the switch is ON
IN_POL0:
This bit sets the polarity of D0 field in INP_ST register
„0‟: The bit D0 will be equal to „1‟ when the switch connected to INTERR0 input is OFF,
and equal to „0‟ when the switch is ON
„1‟: The bit D0 will be equal to „0‟ when the switch connected to INTERR0 input is OFF,
and equal to „1‟ when the switch is ON
OUT_POL3: This bit sets if the triac connected to TRIAC3 output is firing whether with “chip ground” or
VDD
„0‟: The triac is firing with VDD
„1‟: The triac is firing with chip ground
OUT_POL2: This bit sets if the triac connected to TRIAC2 output is firing whether with “chip ground” or
VDD
„0‟: The triac is firing with VDD
„1‟: The triac is firing with chip ground
OUT_POL1: This bit sets if the triac connected to TRIAC1 output is firing whether with “chip ground” or
VDD
„0‟: The triac is firing with VDD
„1‟: The triac is firing with chip ground
OUT_POL0: This bit sets if the triac connected to TRIAC0 output is firing whether with “chip ground” or
VDD
„0‟: The triac is firing with VDD
„1‟: The triac is firing with chip ground
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
84
9.1.6
D_CONF register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
D_CONF
OPTO3
OPTO2
OPTO1
OPTO0
SPF3
SPF2
SPF1
SPF0
Name:
D_CONF
Address:
0xFEA8
Reset:
“11111111”
This register selects the switches detector type and the triacs firing type
OPTO3:
This bit sets if the switch connected to INTERR3 input is being detected by means of an
optocoupler or a Zener diode
„0‟: Zener diode detection
„1‟: Optocoupler detection
OPTO2:
This bit sets if the switch connected to INTERR2 input is being detected by means of an
optocoupler or a Zener diode
„0‟: Zener diode detection
„1‟: Optocoupler detection
OPTO1:
This bit sets if the switch connected to INTERR1 input is being detected by means of an
optocoupler or a Zener diode
„0‟: Zener diode detection
„1‟: Optocoupler detection
OPTO0:
This bit sets if the switch connected to INTERR0 input is being detected by means of an
optocoupler or a Zener diode
„0‟: Zener diode detection
„1‟: Optocoupler detection
SPF3:
This bit sets if the load connected to TRIAC3 output is firing whether with a simple pulse or
a pulse train.
„0‟: Pulse train firing
‟1‟: Simple pulse firing
SPF2:
This bit sets if the load connected to TRIAC2 output is firing whether with a simple pulse or
a pulse train.
„0‟: Pulse train firing
‟1‟: Simple pulse firing
SPF1:
This bit sets if the load connected to TRIAC1 output is firing whether with a simple pulse or
a pulse train.
„0‟: Pulse train firing
‟1‟: Simple pulse firing
SPF0:
This bit sets if the load connected to TRIAC0 output
whether with a simple pulse or a pulse train.
„0‟: Pulse train firing
‟1‟: Simple pulse firing
Figure 9-4.
is firing
Simple pulse vs. Pulse train
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
85
9.1.7
V_SWC register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
V_SWC
HVI3
HVI2
HVI1
HVI0
PWM3
PWM2
PWM1
PWM0
Name:
V_SWC
Address:
0XFEA9
Reset:
“11111111”
This register selects the voltage switches type (AC alternating-current high voltage switch or DC direct-current low
voltage switch) and activates the PWM (Pulse Width Modulation) control.
HVI3:
Selects the switch type (AC switch or DC switch) that is connected to INTERR3 (internal
logic acts in different way depending on the switch type)
„0‟: DC switch is connected
‟1‟: AC switch is connected
HVI2:
Selects the switch type (AC switch or DC switch) that is connected to INTERR2 (internal
logic acts in different way depending on the switch type)
„0‟: DC switch is connected
‟1‟: AC switch is connected
HVI1:
Selects the switch type (AC switch or DC switch) that is connected to INTERR1 (internal
logic acts in different way depending on the switch type)
„0‟: DC switch is connected
‟1‟: AC switch is connected
HVI0:
Selects the switch type (AC switch or DC switch) that is connected to INTERR0 (internal
logic acts in different way depending on the switch type)
„0‟: DC switch is connected
‟1‟: AC switch is connected
PWM3:
Sets the behavior of TRIAC3 output mode
PWM2:
PWM1:
PWM0:
„0‟: PWM output
‟1‟: Phase angle control output
Sets the behavior of TRIAC2 output mode
„0‟: PWM output
‟1‟: Phase angle control output
Sets the behavior of TRIAC1 output mode
„0‟: PWM output
‟1‟: Phase angle control output
Sets the behavior of TRIAC0 output mode
„0‟: PWM output
‟1‟: Phase angle control output
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
86
9.1.8
PWM_PER register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
PWM_PER
D7
D6
D5
D4
D3
D2
D1
D0
Name:
PWM_PER
Address:
0xFEAA
Reset:
“00000000”
This register is used to adjust the period of the PWM control
D(7:0):
Values can be between 0 and 255 (0xFF).
The smaller the value, the greater the frequency
PWM FREQUENCY =
KHz
Where n=D(7:0) value
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
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9.1.9
INP_SOURCE register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
INP_SOURCE
--
--
--
--
--
D2
D1
D0
Name:
INP_SOURCE
Address:
0xFEAB
Reset:
“00000000”
--:
Reserved bit
D(2:0):
This register controls the multiplexor that selects the input to INTERR(3:0) (dimmer
switches). See Figure 9-5
D(2:0)
INTERR(3:0) input
“000” (default)
“1111”
“001”
“010”
“011”
“100”
INTA(3:0)
“101”
INTB(3:0)
“110”
“111”
INTC(3:0)
INTD(3:0)
Comment
INTC(3:0) in “Hi-Z”
INTC(3:0) in “Hi-Z”
“1111”
Microcontroller must not write a '0' in
these ports when they are being used as
switch inputs
Figure 9-5. INTERR input mux
DIMMER
PERIPHERAL
VNR
“1111”
TRIAC(3:0)
0-3
INTA
4
INTB
INTC
5
INTD
7
INTERR(3:0)
6
INP_SOURCE(2:0)
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
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9.2
External Circuits
Some external components are necessary to control the loads connected to the ATPL00B. The external circuitry must
be different depending if the integrated circuit GND pin is connected to power line Neutral or not. Examples of external
circuit configurations are described below:
Figure 9-6. Phase Control with “non-isolated” connection
P
TRIAC
ATPL00B
SoC
P
VNR
GND
VNR pin is used to detect the power line wave zero crossing. If the chip ground is not connected to the power line (N)
an optocoupler must be used in the detection circuit as shown in Figure 9-7.
Figure 9-7. Phase Control with ground connection
Vcc
TRIAC
P
ATPL00B
SoC
N
P
VNR
GND
N
To connect a mains switch to the integrated circuit, an optocoupled connection is the preferred option (see Figure 9-8).
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
89
Figure 9-8. Mains switch connection
Vcc
ATPL00B
SoC
P
Switch Input
GND
N
Nevertheless, It‟s also possible to use a Zener diode to detect the switch too (see Figure 9-9).
Figure 9-9. Switch detection circuit using a Zener diode
ATPL00B
SoC
P
Switch Input
GND
N
Figure 9-10 shows how to connect a low voltage switch to the integrated circuit.
Figure 9-10. Direct current switch (Low Voltage switch)
VCC
VCC
ATPL00B
SoC
Switch Input
GND
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
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Notes:
1.
This pin is part of the JTAG Boundary Scan interface and is only used for boundary scan purposes
2.
See supported devices section 8.3.2
3.
The crystal should be located as close as possible to CLKEA and CLKEB pins. Recommended value for Cx is
18pF. This value may depend on the specific crystal characteristics
CLKEB
CLKEA
Xtal
Cx
4.
Cx
Different configurations allowed depending on external topology and net behavior
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
91
10.
Media Access Layer
In power line communication (PLC) systems, medium access control (MAC) tasks require a high percent of the CPU
available computational time. To reduce the computational load of the integrated MCU (8051C3A Core) the ATPL00B
accelerates the execution of critical tasks by means of additional specific hardware units such as ADD1210 hardwired
MAC unit
MAC functional capabilities involve the construction of message packets and the management of correction and error
detection mechanisms.
The ATPL00B MAC is compatible with EHS and KONNEX. Moreover, its design is very versatile and allows the
construction of a wide range of datagram structures with the only constrain of hardware correction and detection codes.
10.1
Packet Encapsulation
Depending on enabled error correction and detection mechanisms, MAC can encapsulate packets following different
configurations:
Figure 10-1. Packet Encapsulation diagram
2 Bytes
2 Bytes
variable
PREAMBLE
HEADER
PAYLOAD
8bits
2 bits
POST
8bits
DATA1 DATA2
8bits
6 bits
DATA1
FEC1
8bits
DATAN
8bits
8bits
8bits
DATAN
FCSh
FCSi
6 bits
8bits
6 bits
8bits
6 bits
FECN
FCSh
FECh
FCSi
FCSi
16 x (N + 2) bits
VITERBI (DATA 1, DATA 2, … DATA N, FCSh, FCSi)
8bits
8bits
HEADER H
HEADER L
8bits
6 bits
8bits
HEADER H
FEC
HEADER L
6 bits
FEC
A standard packet encapsulation has the following structure
Figure 10-2. Datagram structure
2 byte
2 byte
variable
2 bit
PREAMBLE
HEADER
PAYLOAD
POSTAMBLE
Preamble: two bytes long, containing 0xAAAA for bit synchronization. The preamble size is configurable by a
field in CTRL register 10.3.1
Header: two bytes long. It defines the type of datagram. ATPL00B supports FEC (Forward Error Correction)
shielded and unshielded headers. In shielded headers, each byte of the header field is protected by a FEC
field as shown below:
Unshielded header:
8-bit
8-bit
Header MSB
Header LSB
Shielded header:
8-bit
6-bit
8-bit
6-bit
Header MSB
FEC
Header LSB
FEC
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
92
Payload: This part of the message contains the data block. It also includes optional error correction
information. ATPL00B supports Block Coding (FEC) and Convolutional Coding and a Frame Check Sequence
(FCS) algorithm which is performed on the packet in order to detect additional errors
The hardware-implemented FEC, with 8 bit of data and 6 bit of protection, is capable of correcting a 3 bit error
burst in a 14 bit block. The generator polynomial is:
The Viterbi algorithm is implemented with a constraint length (K) of 5, the code generator polynomials in octal
are 27 and 31 and the decision method is soft-decision.
Figure 10-3. Viterbi Encoder scheme
First output
+
Input
1
1
Z
-1
0
1
Z
1
-1
0
Z
1
-1
0
Z
-1
1
1
Second output
+
A 16 bit interleaving block, implemented with a 4x4 square matrix, improves the Viterbi performance.
A 2-byte long FCS helps to detect errors that could not be corrected by the FEC algorithm. The polynomial
used to compute FCS is:
In order to ensure proper error detection by the FCS, a maximum of 64 data bytes should be sent by frame.
According to the correction mechanism selected, the MAC generates different types of payload structures:
Payload without protection, length=8*(n+2) bits
8-bit
DATA1
DATA2
DATA4
DATA5
…
DATAn
8-bit
8-bit
FCSh
FCSl
Payload with FEC protection, length=14*(n+2) bits
8-bit
6-bit
DATA1
FEC1
DATA3
…
DATAn
FECn
8-bit
6-bit
8-bit
6-bit
FCSh
FECh
FCSl
FECl
Payload with Viterbi protection, length=16*(n+2) bits
Viterbi (DATA1, DATA2, …, DATAn, FCSh, FCSl)
Postamble: This field is two bit long to allow full reception of significant data. Both bits are the complement of
the last bit of the message.
Atmel ATPL00B [datasheet]
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10.2
MAC Architecture
The interface between the MCU and the MAC is achieved by addressing it as external data RAM. There are fifteen
configuration registers in the MAC accessible to the MCU, mapped from 0xFE00 to 0xFE0E.
The tasks to perform and the MAC operation are controlled by the configuration registers settings, which are read by the
MAC control logic. The MAC emitter-receiver logic sends or receives serial data through the modem, MSb first, at the
selected baud rate.
Interrupt 0, located at INT0 internal port (P3.2), is triggered by the MAC whenever a new data byte is received. It can be
configured to be triggered also in transmission (default value: INT0 is not triggered in transmission).
10.3
MAC Configuration Registers
Table 10-1. MAC Configuration registers address maps
Address
Register name
Reset Value (hex)
0xFE00
CTRL
0x4E
0xFE01
FLAGS1
0x10
0xFE02
FLAGS2
0x00
0xFE03
DATA
0x00
0xFE04
TH_PREAM
0x3F
0xFE05
TH_HEADER
0x00
0xFE06
BAUDRATE
0x02
0xFE07
TRACK
0x04
0xFE08
PREAM
0x02
0xFE09
CTRL2
0x00
0xFE0A
BC
0xFF
0xFE0B
MODE1
0x0C
0xFE0C
MODE2
0x0C
0xFE0D
MODE3
0x0C
0xFE0E
MODE4
0x0C
0xFE44
VTB_BE_HARD
0x00
0xFE45
VTB_BE_SOFTH
0x00
0xFE46
VTB_BE_SOFTL
0x00
0xFE47
FEC_BER
0x00
By default, reception mode has a baud rate of 2400 bps, the MAC computes the FEC and FCS fields, the TX interrupt is
disabled and the header is unshielded. No preamble length restriction is needed in the header detection process.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
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10.3.1 CTRL register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CTRL
A1
A0
BYTE
WHD
FCS
FEC
TXRX
STOP
Name:
CTRL
Address:
0xFE00
Reset:
“01001110”
The CTRL register holds mode operation bits and special purpose bits. Mode operation bits control the MAC behavior.
The MCU has full access to this register.
Note: See description of BYTE, WHD, FEC, VTB and FCS modes in Operating modes section (10.4)
A(1:0):
Preamble Size.
Bits A1 and A0 determine how many 0xA‟s must precede the header field in order to consider
the data sequence as a valid packet in reception. As the preamble size increases, the number
of “false packets” received will decrease. The preamble is not protected against burst noise
and a single bit error in this field will cause a packet loss.
“00”: Preamble=0xA
“01”: Preamble=0xAA
“10”: Preamble=0xAAA
“11”: Preamble=0xAAAA
Note: This only concerns the reception of packets.
Note: This field is not taken into account if ZERO_A field in FLAGS1 register (see 10.3.2) is
enabled
BYTE:
Byte mode.
This bit controls the BYTE mode operation when BYP and WHD bits are clear. In this mode,
bytes are sent or received without protection mechanism.
„0‟: BYTE mode disabled
„1‟: BYTE mode enabled
WHD:
Write Headers mode
This bit controls the Write Headers mode operation when BYP bit is clear. In this mode, the
MCU configures the desired values of the four programmable headers. The hardware will only
detect those packets whose headers coincide with one of the header models stored.
„0‟: Write Headers mode disabled
„1‟: Write Headers mode enabled
FCS:
Frame Check Sequence operation
When this bit is set and BYTE (with ADV bit set, see CTR2 register in 10.3.10), FEC or VTB
modes are also set, the FCS mode operation is active and the FCS field computation is
assumed by the MAC. Clear this bit if FCS is not used or the FCS field computation is done by
the MCU.
„0‟: FCS operation disabled
„1‟: FCS operation enabled
FEC:
Forward Error Correction operation
If this bit is set and BYP, WHD, BYTE and VTB bits are clear, the FEC field computation is
assumed by the MAC. Clear this bit if the packet doesn‟t have FEC protection or the FEC field
computation is done by the MCU.
Atmel ATPL00B [datasheet]
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TXRX:
„0‟: FEC operation disabled
‟1‟: FEC operation enabled
Transmission/Reception mode
This bit selects if data is being transmitted/received to/from the modem
„0‟: Transmission mode
‟1‟: Reception mode
STOP:
This bit resets the MAC logic circuitry and aborts the current reception or transmission
process. A “STOP cycle” (STOP bit must be set and then cleared) has to be issued by the
MCU every time a packet reception or transmission is finished or being aborted. The STOP
cycle doesn‟t reset the configuration registers.
„0‟: MAC is in normal operation mode
‟1‟: MAC is in reset state
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10.3.2 FLAGS1 register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
FLAGS1
BYP
--
--
ZER0_A
NMDR
RxFEC
RX
TX
Name:
FLAGS1
Address:
0xFE01
Reset:
“00010000”
This register holds a mode operation bit, some special purpose bits and the RX and TX flags to control the transmission
and reception processes. The MCU has full access to this register.
--:
Reserved bit
BYP:
Bypass mode
When this mode is enabled, the MAC logic is disabled and the MCU takes full control of the
PLC modem
„0‟: Bypass mode disabled
„1‟: Bypass mode enabled
ZER0_A:
Errors allowed in preamble
This field selects whether erroneous bits are allowed in preamble reception or not
„0‟: No errors are allowed in preamble reception. A(1:0) field (see CTRL register in 10.3.1)
sets the number of 0xA‟s expected to be received. If there is any erroneous bit in this
preamble reception, the frame will be discarded.
„1‟: Errors are allowed in preamble reception. The frame will be discarded only if the
erroneous bits received in preamble exceed a threshold (see TH_PREAM register in
10.3.5).
NMDR:
No more data required
This bit should be set by the MCU after the last byte of the payload is being sent or received
through the DATA register. In FCS mode it would mean that the next field to be processed by
the MAC is the FCS field.
Setting the NMDR bit is only required in the following situations:
a) Message transmissions with TX interrupt enabled.
RxFEC:
b) Message receptions in FCS mode with Viterbi algorithm disabled.
„0‟: NMDR deasserted
„1‟: NMDR asserted
Receive FEC fields
If this bit is set, FEC fields are also delivered by the MAC to the MCU by means of DATA
register. If this bit is clear, the MAC delivers to the MCU only the data bytes. See DATA
register section and “Operation Modes” chapter for more information about how the FEC bits
are made accessible to the MCU.
„0‟: Only data bytes are read by the MCU
‟1‟: Both data and FEC are read by the MCU
Atmel ATPL00B [datasheet]
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RX:
Reception flag
This flag is set by the MAC when a new byte is received, which automatically generates an
external interrupt (INT0) that alerts the MCU. The RX flag should be cleared by the MCU after
the DATA register value has been read
Rx bit is also set to „1‟ in transmission every time a FCS-field byte is sent. Thus, the MAC
alerts the MCU to read and store the value of the FCS (sent by the MAC), which is later
needed to receive and validate the correspondent ACK
TX:
Transmission flag
The MCU has to set this flag after writing a new byte in the DATA register for transmission.
The MAC will clear this bit when it is ready to accept more data. The MCU should only write
into the DATA register when the TX bit is clear.
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10.3.3 FLAGS2 register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
FLAGS2
HDEC
HD_SH
TH_MODE
END_TX
HD1
HD0
EFCS
EFEC
Name:
FLAGS2
Address:
0xFE02
Reset:
“00000000”
This register holds three configuration bits and five read-only information bits (FLAGS2(4:0)).
HDEC:
Header decoding mode
When the MAC is configured to receive unshielded headers (HD_SH=‟0‟), this bit selects the
way the errors are calculated when a header is received.
„0‟: Soft decision. In soft decision there are eight levels of decision. A “strong 0” is
represented with a value of “0”, while a “strong 1” is represented with a value of “7”. The
rest of values are intermediate, so “3” is used to represent a “weak 0” and “4” represents
a “weak 1”. Soft decision calculates the error in one bit received as the distance in
decision levels between the value received (a value between “0” and “7” ) and the
corrected one (“0” or “7”).
„1‟: Hard decision. In hard decision there are only two decision levels. If the received
value is different than the corrected one, the error value taken is “7”. Otherwise, the error
value taken is “0”.
HD_SH:
Shielded header
When this bit is set, shielded header packets are in use. A shielded header packet means that
the header is protected by FEC fields. Shielded headers are not compatible with EHSKONNEX.
This bit is only taken into account in headers reception. This bit does not affect transmission.
„0‟: Shielded headers disable
„1‟: Shielded headers enable
TH_MODE: Header threshold mode
When the MAC is configured to receive unshielded headers (HD_SH=‟0‟), this bit configures
how the header detection thresholds are used.
„0‟: Errors found in preamble and errors found in header are not accumulated. Threshold
for errors in preamble is stored in TH_PREAM register (see 10.3.5) while threshold for
errors in header is stored in TH_HEADER register (see 10.3.6).
„1‟: Errors found in preamble and errors found in header are accumulated. The threshold
for this addition is stored in TH_HEADER register.
END_TX:
End of transmission flag
This flag is set by the MAC when the current transmission finishes. A STOP cycle clears this
bit.
„0‟: Transmission in curse
„1‟: End of transmission
Atmel ATPL00B [datasheet]
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HD(1:0):
Header number
When the MAC detects one of the programmed header values in the incoming data sequence,
and once the first byte following the header has been received, the MAC triggers the external
interruption. The data byte will be stored in DATA register, and the header type will be stored
in HD(1:0). That is, the MAC doesn‟t send the header bytes to the MCU through DATA
register.
“00”: Header 1 (default value = 0x9B58)
“01”: Header 2 (default value = 0xE958)
“10”: Header 3 (default value = 0x24E7)
“11”: Header 4 (default value = 0xA5D8)
EFCS:
FCS error flag
This flag is set if an error in the FCS field is detected in the incoming packet.
„0‟: No error detected
‟1‟: Error detected
EFEC:
FEC error flag
This flag is set if an error in the FEC field is detected in the incoming packet.
„0‟: No error detected
‟1‟: Error detected
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10.3.4 DATA register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Name:
DATA
Address:
0xFE03
Reset:
“00000000”
In default mode, DATA register holds the byte value to be sent in transmission or the last received byte in reception.
This register is also used to program the header values (see WHD mode section for more details). The MCU has full
access to this register.
In some operation modes, the FEC field is also transmitted by means of DATA register. As the FEC field is 6-bit long, it
is stored in the 6 lsb (less significant bits) in DATA register according to one of the configurations below.
DATA register in FEC mode
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
DATA
--
--
FEC5
FEC4
FEC3
FEC2
FEC1
FEC0
In FEC mode, when RxFEC=‟1‟, the MAC also transfers the FEC field to the MCU in reception (if RxFEC=‟0‟,
only data bytes will be transferred), and this is done according to configuration shown above
DATA register in NULL mode (see 10.4.8)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
DATA
--
--
/FEC5
/FEC4
/FEC3
/FEC2
/FEC1
/FEC0
On the other hand, when MAC is in NULL mode (that is, the MAC does not manage the FEC field), the MCU
must manage FEC fields following the configuration shown above. Due to not-MAC intervention, the MCU will
receive the FEC inverted, so the FEC must be also written inverted in the DATA register by the MCU when
transmitting.
Atmel ATPL00B [datasheet]
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10.3.5 TH_PREAM register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
TH_PREAM
--
--
D5
D4
D3
D2
D1
D0
Name:
TH_PREAM
Address:
0xFE04
Reset:
“00111111”
Preamble threshold register
D(5:0):
Preamble threshold.
This field stores an upper threshold for errors detected in preamble when receiving unshielded
headers (header without FEC, HD_SH=‟0‟). If this threshold is exceeded, the frame will be
discarded.
Note: This register is taken into account only if TH_MODE=‟0‟.
Note: This register is taken into account only if ZERO_A=‟1‟.
Atmel ATPL00B [datasheet]
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10.3.6 TH_HEADER register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
TH_HEADER
D7
D6
D5
D4
D3
D2
D1
D0
Name:
TH_HEADER
Address:
0xFE05
Reset:
“00000000”
Header threshold register
D(7:0):
Preamble threshold.
This register stores an upper threshold for errors detected in the header, when receiving
unshielded headers (HD_SH=‟0‟). The received header is compared with the four headers
stored in memory and error value is calculated. If the error value is equal or below the value in
TH_HEADER, the header is taken as valid.
If this threshold is exceeded, the frame will be discarded.
Note: If TH_MODE field in FLAGS2 register is set, TH_HEADER register stores the threshold
for errors found in header + errors found in preamble.
Atmel ATPL00B [datasheet]
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10.3.7 BAUDRATE register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
BAUDRATE
--
--
--
--
--
--
BR1
BR0
Name:
BAUDRATE
Address:
0xFE06
Reset:
“00000010”
The MCU can configure the baud rate of the system by writing to the BAUDRATE register. The MCU has full access to
this register.
BR(1:0):
This field sets the baud rate.
“00”: 600 bps
“01”: 1200 bps
“10”: 2400 bps
“11”: 4800 bps
Atmel ATPL00B [datasheet]
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10.3.8 TRACK register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
TRACK
--
D6
D5
D4
D3
D2
D1
D0
Name:
TRACK
Address:
0xFE07
Reset:
“00000100”
This register is used for internal debug. Reset value is the suitable for correct operation.
This register must not be modified, unless otherwise stated.
Atmel ATPL00B [datasheet]
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10.3.9 PREAM register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
PREAM
--
D6
D5
D4
D3
D2
D1
D0
Name:
PREAM
Address:
0xFE08
Reset:
“00000010”
This register is used for internal debug. Reset value is the suitable one for correct operation.
This register must not be modified, unless otherwise stated.
Atmel ATPL00B [datasheet]
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10.3.10 CTRL2 register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CTRL2
--
--
--
--
TXIE
--
ADV
VTB
Name:
CTRL2
Address:
0xFE09
Reset:
“00000000”
This register holds configuration bits that control new features of the ATPL00B that are not backwards compatible.
--:
Reserved bit
TXIE:
This bit enables the transmission interrupt INT0 in operation modes that are not WHD
„0‟: TX interrupt disabled
„1‟: TX interrupt enabled
ADV:
Advanced mode
Changes the behavior of BYTE and FCS operation mode bits, allowing the combined BYTE +
FCS mode. This mode is not backward compatible
„0‟: Advanced mode disabled
„1‟: Advanced mode enabled
VTB:
VTB mode
Activate VTB mode when BYP, WHD and BYTE bits are clear
„0‟: VTB mode disabled
„1‟: VTB mode enabled
Atmel ATPL00B [datasheet]
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10.3.11 BC register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
BC
D7
D6
D5
D4
D3
D2
D1
D0
Name:
BC
Address:
0xFE0A
Reset:
“11111111”
D(7:0):
The BC register must be configured by the MCU in a reception process when Viterbi mode
is enabled.
The BC register holds the byte count parameter, that is, the total number of bytes protected by
the Viterbi algorithm. Once the MCU knows the total length of the frame that is receiving, it
must configure the BC register, which means this register must be dynamically updated with
every received frame.
When Viterbi algorithm enabled, the byte count parameter must be decoded before the
execution of the flushing stage. As a consequence, the optimum position of the byte count
parameter is the closest to the header section. The MCU has full access to this register.
Atmel ATPL00B [datasheet]
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10.3.12 MODE1 to MODE4 registers
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
MODE4
--
--
--
VTBi
FECi
FCSi
BYTEi
ENi
Name:
MODE1 – MODE4
Address:
0xFE0B - 0xFE0E
Reset:
“00001100”, 00001100”, 00001100”, 00001100”.
MODEi registers allow associating a MAC operation mode in reception to each of the four programmable headers
stored in memory. This way, if mode-i (where i=1,2,3,4) is enabled (ENi=‟1‟), when the MAC receives the header-i, it
automatically processes this frame according to the operation mode defined by MODEi.
VTBi, FECi,FCSi and BYTEi fields work in the same way as the corresponding fields in the general configuration: VTB,
FEC, FCS and BYTE respectively.
These registers are only applicable to frame reception. Transmission mode is still controlled by the general
configuration bits (VTB, FEC, FCS, BYTE).
Atmel ATPL00B [datasheet]
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10.3.13 VTB_BE_HARD register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
VTB_BE_HARD
D7
D6
D5
D4
D3
D2
D1
D0
Name:
VTB_BE_HARD
Address:
0xFE44
Reset:
“00000000”
D(7:0):
Stores the number of errors accumulated in the last received frame using Viterbi hard.
The register holds the value until the next frame is completely received, and then the value is
updated.
Note: The value in this register is only correct if the message has been correctly received
(successful CRC check).
Atmel ATPL00B [datasheet]
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10.3.14 VTB_BE_SOFT registers
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
VTB_BE_SOFTH
D15
D14
D13
D12
D11
D10
D9
D8
VTB_BE_SOFTL
D7
D6
D5
D4
D3
D2
D1
D0
Name:
VTB_BE_SOFTH – VTB_BE_SOFTL
Address:
0xFE45 - 0xFE46
Reset:
“00000000”, “00000000”
D(15:0):
Stores the number of errors accumulated in the last received frame using Viterbi soft.
The register holds the value until the next frame is completely received, and then the value is
updated.
Note: The value in this register is correct only if the message has been correctly received
(successful CRC check).
Atmel ATPL00B [datasheet]
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10.3.15 FEC_BER register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
FEC_BER
D7
D6
D5
D4
D3
D2
D1
D0
Name:
FEC_BER
Address:
0xFE47
Reset:
“00000000”
D(7:0):
Stores the number of errors accumulated in a frame reception using Forward Error
Correction.
Atmel ATPL00B [datasheet]
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10.4
Operation modes
The different operation modes are summarized in Table 10-2
Table 10-2. MAC Operation modes
[BYP, WHD, BYTE]
000
001
01X
1XX
0X0
NULL
BYTE
WHD
BYPASS
X01
VTB
BYTE
WHD
BYPASS
X11
VTB + FCS
BYTE
WHD
BYPASS
100
FEC
BYTE
WHD
BYPASS
110
FEC + FCS
BYTE
WHD
BYPASS
[FEC, FCS, VTB]
As mentioned before, if bit ADV is set, a special mode BYTE+FCS is available. This mode is selected when BYTE and
FCS bits are set and BYP and WHD bits are cleared.
10.4.2 BYPASS mode
In BYPASS mode, the MCU takes control of the ATPL00B modem. The MAC circuitry is disabled and the MAC layer
has to be fully implemented by software.
The following table shows the connections between the MCU and the modem in bypass mode operation:
Table 10-3. MCU-modem connection in bypass mode
MCU
Modem
P1.0
CD
P1.2
TxRx
P1.1
TxD
P3.2
RxD
10.4.3 WHD mode
In WHD mode it is possible to change the value of the programmable headers.
The MAC detects how many headers have been programmed and uses them to look for valid incoming packets during
reception. Up to four headers can be programmed in this mode. See WHD mode operation procedure in 10.5.2for
detailed information.
Atmel ATPL00B [datasheet]
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10.4.4 BYTE mode
In BYTE mode, the MAC logic transfers data to and from the modem in byte format. Thus, transferred bytes do not have
protection field. This mode should be used by the MCU to send PREAMBLE and HEADER fields in EHS-KONNEX
compatible packets.
10.4.5 FEC mode
FEC is one of the two available error correction mechanisms. In this mode, the MAC appends a FEC field to each data
byte during transmission and checks its value during reception.
10.4.6 VTB mode
The second error correction mechanism is VTB. In VTB mode, the MAC uses convolutional encoding to encode data
bytes during transmission. During reception, the data bytes are decoded applying the Viterbi algorithm if VTB mode is
chosen.
10.4.7 FCS mode
In FCS mode, a FCS field is appended to the packet during transmission, and checked afterwards during reception.
This mode has to be used together with any of the following modes: BYTE (with ADV set), FEC or VTB.
10.4.8 NULL mode
In NULL mode, the MAC logic assumes that FEC fields are being used in the data packet but computed by the MCU. As
a consequence, each data byte is followed by a FEC field, and only the 6 bits of the DATA register that holds the FEC
field are processed.
10.5
Operation Procedures
This section describes the different operation procedures that the MCU has to take in order to handle with the MAC
hardware. Except for the STOP cycle which is common to all modes, the rest of procedures are mode dependent.
10.5.1 STOP cycle
A MAC STOP cycle resets the MAC logic circuitry and it can also abort the current transmission or reception process.
The MCU must generate a STOP cycle every time a packet transmission or reception is completed or aborted.
10.5.2 WHD mode operation procedure
The WHD mode operation procedure allows the MCU to change the default values of the programmable headers.
The default number of programmable headers involved in the header detection process is 4. However, if a header
programming procedure takes place, this number will be equal to the number of programmed headers.
The four header values are stored in an eight byte stack area. The value of FLAGS2[HD[1:0]] is used by the MAC logic
to point into the stack to the header that is being received in the incoming message.
In WHD mode there is no data sent to the modem, but the CTRL[TXRX] bit has to be cleared anyway. Additionally, the
TX interrupt is disabled independently of the CTR2[TXIE] bit value.
Atmel ATPL00B [datasheet]
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Example:
Header programming procedure
An example of the header programming procedure is provided in this section. The purpose is to change the header
values the following way:
Default values
HD[1:0] HEADER
00
0x9B58
01
0xE958
10
0x24E7
11
0xA5D8
Target values
HD[1:0] HEADER
00
0x0102
01
0x0304
10
0x0506
11
0x0708
The procedure to program these values is shown in Figure 10-4 Note that the shadowed headers would not be involved
in the header detection process.
Figure 10-4. WHD procedure example
MAC STOP cycle
WHD mode ON
(CONTROL[WHD] = 1)
TX mode
(CONTROL[TXRX] = 0)
DATA = 08
Set TX flag
DATA = 07
Set TX flag
DATA = 06
Set TX flag
DATA = 05
Set TX flag
DATA = 04
Set TX flag
DATA = 03
Set TX flag
DATA = 02
Set TX flag
DATA = 01
Set TX flag
HD[1:0] HEADER
00
0x0708
01
0x9B58
10
0xE958
11
0x24E7
HD[1:0] HEADER
00
0x0506
01
0x0708
10
0xE958
11
0x24E7
HD[1:0] HEADER
00
0x0304
01
0x0506
10
0x0708
11
0x24E7
HD[1:0] HEADER
00
0x0102
01
0x0304
10
0x0506
11
0x0708
RX mode
(CONTROL[TXRX] = 1)
WHD mode OFF
(CONTROL[WHD] = 0)
MAC STOP cycle
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10.5.3 Transmission procedure
To send a PLC message, the MCU must follow the transmission procedure outlined in Figure 10-5. The described
procedure is independent of the selected operation mode and can be executed with TX interrupt enabled or disabled.
The carrier detect signal (P10) must be checked by the MCU before executing the transmission procedure.
Figure 10-5. Transmission procedure flowchart
MAC STOP cycle
Select operation
mode
TX mode
TX interrupt
enabled?
false
More data to
send?
true
More data to
send?
false
false
Wait until
END_TX = 0
Set NMDR bit
Wait until TX = 0
Exit interrupt routine
or do other tasks
RX mode
Change operation
mode
RX procedure
Clear NMDR bit
Write data in
DATA register
RX mode
END_TX
Set TX flag
TX
Interrupt INT0
Interrupt type
RX
false
FCSh
received?
true
Read FCSh from
DATA register
Read FCSl from
DATA register
Clear RX flag
Exit interrupt routine
At the beginning of the procedure, the MCU must configure the MAC in transmission mode and select the desired
operation mode.
The decision „More data to send?‟ returns FALSE when there are no more bytes to send in modes without FCS. When
FCS is used, the next byte is the highest byte of the FCS field.
The process „Change operation mode‟ is optional. When used, it is possible to change the operation mode to compose
messages with a complex structure. For example, in a EHS-KONNEX message, the preamble and header fields are
sent in BYTE mode without protection and the rest of the message in FEC + FCS mode.
Atmel ATPL00B [datasheet]
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During transmission, there are three types of INT0 interrupts: TX, RX and END_TX. Interrupts of type TX and END_TX
are only active when bit CTR2[TXIE] is set. RX type interrupt is active when CTRL[FCS] is set. The TX type interrupt
alerts the MCU whenever the MAC is ready to accept a new byte to be sent. The RX type interrupt, in transmission
mode, is used to pass the FCS value from the MAC to the MCU. Finally, the END_TX type interrupt indicates that the
last bit of the POSTAMBLE field was sent to the modem, that is, the message is finished.
To know what type of INT0 interrupt has occurred, the MCU has to check the CTRL[TXRX] bit and flags FLAGS1[RX]
and FLAGS2[END_TX]. Then, by following the algorithm shown in Figure 10-6, it can determine the appropriate
interrupt handler.
Figure 10-6. Interrupt type detection
INT0 interrupt
TXRX?
1
Reception mode
0
Transmission mode
END_TX?
RX interrupt
1
0
RX?
0
END_TX interrupt
1
RX interrupt
TX interrupt
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10.5.4 Reception procedure
After configuring the system in reception mode, the MAC looks for a valid header in the incoming data sequence. When
a valid header is detected, the following byte received is left in the DATA register, bits HD[1:0] are set according to the
header detected and MAC raises the INT0 interrupt to alert the MCU.
Figure 10-7. Reception procedure flowchart
INT0 interrupt
MAC STOP cycle
New
message?
Select operation
mode
false
true
Read HD[1:0]
RX mode
Read data from
DATA register
Do other tasks
FEC mode?
false
true
Check EFEC flag
Clear RX flag
FCS mode?
false
Last byte?
false
TX or RX procedure
true
Last byte
before FCS?
true
Set NMDR flag
false
Last byte?
true
Exit interrupt routine
Check EFCS flag
Exit interrupt routine
TX or RX procedure
For each processed byte, an interrupt alerts the MCU. If the FLAGS1[RxFEC] bit is set, then FEC fields are also passed
to the MCU via the interrupt method. If the message includes error protection and/or detection mechanism, the MAC
hardware uses the flags FLAGS2[EFEC] and FLAG2[EFCS] to inform about the computation results. However, it is a
MCU decision to abort the reception process or not. The reception of the message can be aborted anytime by issuing a
STOP cycle.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
118
11.
PLC Modem
The ATPL00B is a Power Line Communications System on Chip. It includes an enhanced 8051 microcontroller (IP core
ADD8051C3A), a Media Access Controller (MAC) (IP core ADD1210) and a PLC Modem circuit for the EHS/KNX
Power Line medium specifications (IP core ADD1310).
The ATPL00B is a multi Baud rate device, which can work at 600 bauds, 1200 bauds, 2400 bauds or 4800 bauds.
ATPL00B PLC modem works at a 132.5 kHz carrier frequency.
The PLC modem can be controlled using the hardwired MAC ADD1210 or it can be controlled by the microcontroller
ADD8051C3A, nonetheless when the microcontroller takes control the MAC is still used, but in a bypass mode.
Figure 11-1. PLC Modem diagram
VSENSE
ENABLE
PSENSE
PLC
MODEM
DIN
EMIT(12:0)
DNIN
REC(8:1)
VIN
VRH
DC_COMP
VRL
D
S
AV
AV
The modem has a set of configuration registers (listed in Table 11-5) which are mapped in the external data space of
the microcontroller. Many bits in these registers are not user definable, and the user must not write to these bits.
In order to have direct access from the microcontroller to the modem, its control signals (TX,RX,TX/RX,CD) are
connected to microcontroller ports. The port P3.2 has a double function. When the MAC is in full operation mode, P3.2
is used to interrupt the microcontroller when a new byte, or a new byte+FEC is received. When the MAC is in bypass
mode the reception output of the modem, RX, is connected to P3.2
Table 11-1. MUC-MAC connection
MAC
MCU
bypass
Full operation
P3.2
Rx
Rx Interrupt
P1.0
CD
CD
P1.1
Tx
--
P1.2
TxRx
--
When the MAC is used in full operation mode all the modem control signals (TX,RX,TX/RX,CD) are connected only to
the MAC.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
119
11.1
Frequency coding
Logic symbol „1‟ is sent using a frequency value slightly below Fcarrier while the upper side is used to represent the
logic symbol „0‟, according to:
•
F(“1”) = Fcarrier - baud rate/2
•
F(“0”) = Fcarrier + baud rate /2
Besides there is another option, where you can choose (frequency deviation=0.5):
•
F(“1”) = Fcarrier - baud rate/4
•
F(“0”) = Fcarrier + baud rate/4
Exact frequencies for every baud rate can be found in 0.
Note: 0.5 deviation value is not allowed when working at Baud Rate = 600. See Table 11-2 for suitable values.
Table 11-2. Allowed deviation values by baud rate
Baud rate
F (Hz)
Deviation
600(1)
-600
-1
1200
600
1200
0.5
1
2400(2)
1200
2400(2)
0.5
1
4800
2400
4800
0.5
1
Note:
1.Deviation value = 0.5 not allowed
Note:
2.Default value
A couple of modems have been implemented inside ATPL00B (each one with Tx and Rx capabilities), so we can select
between them to establish different values or frequency deviation for transmission and reception (See DEV_TX and
DEV_RX fields in CONFIG register).
This allows the device to be configured to comply with KONNEX requirements, setting a deviation value = 1 for
reception and a deviation value = 0.5 for transmission.
Table 11-3. Allowed Tx-Rx deviation values
Tx
(1)
Note:
0.5
Rx
(1)
0.5
0.5
1
1
1
1. If a reception deviation value = 0.5 is selected, same transmission deviation value = 0.5 must be selected as
well. In this case, only baud rate=2400bauds can be used
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
120
Table 11-4. Modem mark and space frequencies
Carrier
frequency
(KHz)
Exact frequency
(Hz)
Baud rate
600
1200
132,5
2400
4800
11.2
Deviation
"1"
"0"
--
--
--
1
132200
132800
0,5
132200
132800
1
131900
133100
0,5
131900
133100
1
131300
133700
0,5
131300
133700
1
130100
134900
Modem Transmission and Reception
11.2.1 Transmission characteristics
ATPL00B PLC Modem implements a direct transmission configuration, where the transmitted signal is generated by
means of a resistor array. The value of the resistors determines the intensity that will be injected to the power line, and
then the signal level. This low-cost and low-consumption configuration is intended for Home Automation purposes. An
example of a possible application diagram is shown in Figure 11-2
Figure 11-2. Example of an emission circuit using a resistor array
Note: PLC modem also works properly with direct coupling, allowing final user to save transformer costs and reducing
design size.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
121
Figure 11-3. Direct coupling without transformer
11.2.2 Reception characteristics
The receiving characteristics, input sensitivity and input impedance, are greatly influenced by the receiving circuitry.
ATPL00B provides a Low-Cost Direct-Analog input stage using VIN, VRH and VRL inputs, allowing to save costs in
external circuitry and providing robust performance.
Figure 11-4. Low Cost reception circuit
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
122
Note: ATPL00B also provides a High-Performance External-Comparator reception interface that allows the user to work
with external comparator circuitry when looking for an extremely-high-temperature-environment working system. Please
contact Atmel for further information.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
123
11.3
PLC Modem Configuration registers
The modem has a set of configuration registers which are mapped in the external data space of the microcontroller and
allow the user to set main working characteristics.
Table 11-5. MODEM Registers map
Address
Register name
0xFE14
GAIN
0xFE15
Reset
Value
(hex)
Address
Register name
Reset
Value
(hex)
0x40
0xFE49
CD_DECISION_TIME
0x20
CONTROL2
0x80
0xFE4A
CD_DECISION_ERROR
0x0F
0xFE17
CONFIG
0x06
0xFE4B
TXRX_CTL
0x00
0xFE18
GFSK_ADDR
0x00
0xFE4C
R1
0x60
0xFE19
GFSK_D3
0x00
0xFE4D
R2
0x60
0xFE1A
GFSK_D2
0x00
0xFE4E
R3
0x60
0xFE1B
GFSK_D1
0x00
0xFE4F
R4
0x60
0xFE1C
GFSK_D0
0x00
0xFE50
R5
0xFF
0xFE1F
COMP
0x04
0xFE51
R6
0xFF
0xFE40
KNX_EN
0x57
0xFE52
R7
0xFF
0xFE48
CD_ENABLE
0x01
0xFE53
R8
0xFF
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
124
11.3.1 GAIN register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
GAIN
G7
G6
G5
G4
G3
G2
G1
G0
Name:
GAIN
Address:
0xFE14
Reset:
“01000000”
This register controls the Amplitude of the emitted PLC signal
G(7:0):
Controls the Amplitude of the emitted PLC signal. Square output waveform is selected when
the value is above 0x7B in order to minimize distortion
Values from 0x00 to 0x7B: Sine output waveform. The amplitude(*) varies according to:
Where Vcc is the voltage supplied to the output analog stage (which varies depending on
its configuration)
Values from 0x7C to 0xFF: Square output waveform. Any value above 0x7C will be
automatically stored as 0x7C.
Note: Amplitude values depend on the net impedance. The net impedance varies constantly.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
125
11.3.2 CONTROL2 register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CONTROL2
C_PD
--
--
--
--
--
--
STOP_MODEM
Name:
CONTROL2
Address:
0xFE15
Reset:
“10000000”
C_PD:
Internal Comparator Power Down
„0‟: Normal state
„1‟: Power down state
STOP_MODEM:
PLC Modem power down
„0‟: Normal state
„1‟: Power down state
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
126
11.3.3 CONFIG register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CONFIG
KNX
DEV_RX
DEV_TX
--
--
EOP_EN
--
GFSK_EN
Name:
CONFIG
Address:
0xFE17
Reset:
“00000110”
KNX:
KONNEX normative
If KNX=‟0‟, KONNEX normative is not complied, but a more solid transmission is achieved
(the more A‟s you add to the preamble, the better it works)
In order to comply KONNEX normative (*), this bit must be set.
„0‟: KONNEX normative not compliant
„1‟: KONNEX normative compliant
(*) In order to comply with KONNEX normative, the following values must be used:
Baud rate = 2400 bauds
CONFIG(KNX) = „1‟
CONFIG(DEV_TX) = „1‟ (frequency deviation = 0.5)
CONFIG(DEV_RX) = „0‟ (frequency deviation = 1)
KNX_EN register = 0x77
DEV_RX:
Deviation value in reception
DEV_RX=‟0‟ is the normal mode of transmission which has a deviation value of 1. In case the
user wants to work with a deviation value of 0.5, this bit must be set.
„0‟: Frequency deviation=1
„1‟: Frequency deviation=0.5
Note: Frequency deviation=0.5 can only be used when working at 2400 bauds. Nevertheless,
it is recommended to work with a frequency value deviation=1.
DEV_TX:
Deviation value in transmission
DEV_TX=‟0‟ is the normal mode of transmission which has a deviation value of 1. In case the
user wants to work with a deviation value of 0.5, this bit must be set.
„0‟: Frequency deviation=1
„1‟: Frequency deviation=0.5
EOP_EN:
Emission Output Pins Enable
Enables the emission outputs (EMIT(1:12) pins).
0 - Transmission outputs enabled
1 - Transmission outputs disabled
Note: This bit must be cleared (EOP_EN=‟0‟) before starting transmission in order to protect
external circuitry.
GFSK_EN: Gaussian output filter
If set, configures the ADD1310 to use the Gaussian output filter, that smoothes pulses to limit
its spectral width.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
127
11.3.4 GFSK_ADDR register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
GFSK_ADDR
--
A6
A5
A4
A3
A2
A1
A0
Name:
GFSK_ADDR
Address:
0xFE18
Reset:
“00000000”
--:
Reserved bit
A(6:0):
This field contains 7 bits to address the table where Gaussian Filter predefined values are
written in memory.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
128
11.3.5 GFSK_DX registers
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
GFSK_D3
--
--
--
--
D27
D26
D25
D24
GFSK_D2
D23
D22
D21
D20
D19
D18
D17
D16
GFSK_D1
D15
D14
D13
D12
D11
D10
D9
D8
GFSK_D0
D7
D6
D5
D4
D3
D2
D1
D0
Name:
GFSK_D3 – GFSK_D0
Address:
0xFE19 – 0xFE1C
Reset:
“00000000”, “00000000”, “00000000”, “00000000”.
--:
Reserved bit
D(27:0):
The 28-bit value from the table address pointed by GFSK_ADDR register is stored in four
registers named GFSK_D3 to GFSK_D0.
It is also possible to write a desired data in these registers, and it will be automatically kept in
the memory ADDRESS read from GFSK_ADDR register once the new data has been written.
This is useful in case of changing the baud rate and a new table must be saved in memory
before applying the filter.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
129
11.3.6 COMP register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
COMP
--
--
--
--
--
--
--
CCLK_IDLE
Name:
COMP
Address:
0xFE1F
Reset:
“00000100”
--:
Reserved bit
CCLK_IDLE: Converter Clock Idle
Set the state of the clock that drives the external comparator (ENABLE pin)
„0‟:External Comparator clock enabled
„1‟: External Comparator clock disabled
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
130
11.3.7 KNX_EN register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
KNX_EN
--
D6
D5
D4
D3
D2
D1
D0
Name:
KNX_EN
Address:
0xFE40
Reset:
“01010111”
Note: This register is used to comply with KONNEX normative.
If a KONNEX normative compliant modem is required, D5 bit field must be set, thus KNX_EN=0x77 and
values described in CONFIG register section must be used.
Else, default value (KNX_EN=0x57) is recommended.
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
131
11.3.8 CD_ENABLE register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CD_ENABLE
--
--
--
--
--
--
--
EN
Name:
CD_ENABLE
Address:
0xFE48
Reset:
“00000001”
This register is used to enable/disable the automatic carrier detection
--:
Reserved bit
EN:
Automatic Carrier Detection enable
„0‟: Carrier Detection depends on the value stored in THRESHOLD registers. If the level
read is below the value stored in THRESHOLD registers, then carrier presence is taken
as positive. If the level read is above the value stored in THRESHOLD registers, then we
assume there is no carrier presence.
„1‟: Carrier Detection is detected automatically
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
132
11.3.9 CD_DECISION_TIME register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CD_DECISION_TIME
D7
D6
D5
D4
D3
D2
D1
D0
Name:
CD_DECISION_TIME
Address:
0xFE49
Reset:
“00100000”
D(7:0):
The number stored in this register is multiplied by (2^16/fclk) in order to know how long is
the period (in seconds) between consecutive runs of the carrier detector decision algorithm
when in automatic carrier detection mode ( CD_ENABLE(0)=‟1‟ ).
Default value = 0x20 = 32
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
133
11.3.10 CD_DECISION_ERROR register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
CD_DECISION_ERROR
--
D6
D5
D4
D3
D2
D1
D0
Name:
CD_DECISION_ERROR
Address:
0xFE4A
Reset:
“00001111”
--:
Reserved bit
D(6:0):
This register sets the number of errors allowed before taking a decision in the automatic
carrier detection algorithm.
It is used only in automatic mode (CD_ENABLE(0)=‟1‟ ).
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
134
11.3.11 TXRX_CTL register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
TXRX_CTL
--
--
--
--
--
VALUE
HARD
POL
Name:
TXRX_CTL
Address:
0xFE4B
Reset:
“00000000”
--:
Reserved bit
VALUE:
This bit is writable by the user, and will be the output in the EMIT0 pin when HARD=‟0‟.
HARD:
Selects the signal to be output by EMIT0.
POL:
„0‟: EMIT0 outputs the bit value stored in VALUE field
„1‟: EMIT0 outputs the internal signal TXRX, with the polarity designated by POL
Polarity of EMIT0 when TXRX internal signal is selected as output (HARD=‟1‟)
„0‟: „0‟ is output in transmission, „1‟ is output in reception
„1‟: 1‟ is output in transmission, „0‟ is output in reception
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
135
11.3.12 Ri registers
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
B it 0
R1
D7
D6
D5
D4
D3
D2
D1
D0
R2
D7
D6
D5
D4
D3
D2
D1
D0
R3
D7
D6
D5
D4
D3
D2
D1
D0
R4
D7
D6
D5
D4
D3
D2
D1
D0
R5
D7
D6
D5
D4
D3
D2
D1
D0
R6
D7
D6
D5
D4
D3
D2
D1
D0
R7
D7
D6
D5
D4
D3
D2
D1
D0
R8
D7
D6
D5
D4
D3
D2
D1
D0
Name:
R1 - R8
Address:
0xFE4C – 0xFE53
Reset:
R1:0x60
R2:0x60
R3:0x60
R4:0x60
R5:0xFF
R6:0xFF
R7:0xFF
R8:0xFF
The value in these registers strongly depends on the external configuration. ATMEL provides values to be
used according with the design recommended in the ATMEL Reference Design.
Please contact ATMEL if other external configurations are going to be used.
Recommended
register value
R1
0x00
R2
0x00
R3
0x00
R4
0x00
R5
0xFF
R6
0xFF
R7
0xFF
R8
0xF8
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
136
12.
Electrical Characteristics
12.1
Absolute Maximum Ratings
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions given in the Recommended Operating Conditions section. Exposure to the Absolute
Maximum Conditions for extended periods may affect device reliability.
(VSS = 0 V)
Table 12-1. ATPL00B Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VCC
-0.5 to 4.0
V
Input Voltage
VI
-0.5 to VCC+0.5( 4.0V)
V
Output Voltage
VO
-0.5 to VCC+0.5( 0
Not minimum time is required between both releases, t > 0, so a simple RC circuit is enough to satisfy this
requirement.
Figure 12-7. Example circuit
3.3v
C
D_INIT
R1
3.3v
C
RSTA
R2 > R1
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
146
13.
Mechanical Characteristics
Figure 13-1. 144-lead LQFP Package Mechanical Drawing
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
147
14.
Recommended mounting conditions
14.1
Conditions of Standard Reflow
Table 14-1. Conditions of standard Reflow
Items
Contents
Method
IR(Infrared Reflow)/Convection
Times
2
Before unpacking
Please use within 2 years after
production
From unpacking to second reflow
Within 8 days
In case over period of floor life
Baking with 125ºC +/- 3ºC for 24hrs
+2hrs/-0hrs is required. Then please
use within 8 days. (please remember
baking is up to 2 times)
Floor Life
Floor Life Condition
Between 5ºC and 30ºC and also below 70%RH required. (It is preferred lower
humidity in the required temp range.)
Figure 14-1. Temperature Profile
Temperature
260ºC
255ºC
Liquidous
Temperature
170-190ºC
RT
b
c
a
Note:
d
e
d‟
Time
H rank: 260ºC Max
a: Average ramp-up rate:
1ºC/s to 4ºC/s
b: Preheat & Soak:
170ºC to 190ºC, 60s to 180s
c: Average ramp-up rate:
1ºC/s to 4ºC
d: Peak temperature:
260ºC Max, up to 255ºC within 10s
d‟: Liquidous temperature:
Up to 230ºC within 40s or
Up to 225ºC within 60s or
Up to 220ºC within 80s
e: Cooling: Natural cooling or forced cooling
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
148
14.2
Manual Soldering
Table 14-2. Conditions of Manual Soldering
Items
Contents
Before unpacking
Please use within 2 years after production
From unpacking to Manual Soldering
Within 2 years after production (No control required for
moisture adsorption because it is partial heating)
Floor life
Floor life
condition
Solder
Condition
Between 5 C and 30 C and also below 70%RH required. (It is preferred lower humidity in the required
temp range.)
Temperature of soldering iron: Max 400 C, Time: Within 5 seconds/pin
*Be careful for touching package body with iron
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
149
15.
Ordering Information
Table 15-1. Atmel ATPL00B Ordering Codes
Atmel Ordering Code
Package
Package Type
Temperature Range
ATPL00B-AZU-Y
144 LQFP
Pb-Free
Industrial (-40ºC to 85º)
A T P L 0 0 B - A Z U - Y x x
Atmel Designator
Customer marking
AT=Atmel
Product Family
PL=Power Line Communications
Device Designator
Device Revision
Shipping Carrier Option
Y = Tray
Package Device Grade or
Wafer/Die Thickness
U = Lead free (Pb-free)
Industrial temperature range
(-40°C to +85°C)
Package Option
AZ
= 144LQFP
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
150
16.
Revision History
Doc. Rev.
Date
A
09/27/2012
Comments
Initial Release
Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12
151
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